Checklist Form - Global Semiconductor Alliance · Web viewThis document contains a summary of the PDK, including relevant contact information, foundry process documents, and electronic

Version 4.0 | July 29, 2013

GSA Analog / Mixed SignalProcess Design KitQuality Checklist

PDK QUALITY CHECKLIST

1. Foundry and Support Contact Information

Foundry & Process Information

Foundry Name __________________________________________

Process Name __________________________________________

PDK Name & Version ______________________________________

PDK Date __________________________________________

PDK Checklist Revision ____________________________________

PDK Support Contact (Specify how PDK users should contact foundry for questions & issues; customize this section as needed.)

Name __________________________________________

Phone __________________________________________

Email or URL__________________________________________

Insert Your Company Logo Here

ANALOG / MIXED-SIGNAL / RF PDK QUALITY CHECKLIST

Checklist FormVersion 4.0


2. Foundry Process Documents Document

Information Document Number & Title Section Revision DateBonding Pad RulesChip Finishing

InstructionsDesign Layout RulesDesign Manual (PDK

Devices)PDK Device Cross

SectionsElectrical ParametersElectrical Rules

CheckingElectromigration

Parameters (current density)ESD GuidelinesInterconnect

SpecificationLatchup RulesLayer MapMapping between

process modules & PDK devicesMask ProcurementMatching ModelsNoise ModelPcell DocumentationProcess Control Monitor

(PCM)Programmable

Electrical Rules Checking (PERC)RF Parameters/ModelingSafe Operating Area

(SOA)SPICE Model ChecklistSPICE Model LibraryTapeout Instructions


(Rows can be added as needed. No rows should be removed, however. Use N/A if not applicable.)

3. EDA Tools Supported and Verified for Use with this PDK

Type Vendor and Tool VersionSupport

LevelSchematicSimulation ControlCircuit Simulator (A)Circuit Simulator (B)Circuit Simulator (C)Circuit Simulator (D)Layout EditorDRC Checker (A)DRC Checker (B)DRC Checker used by

Foundry for T/O SignoffLVS Checker (A)LVS Checker (B)Parasitic Extractor (A)Parasitic Extractor (B)Analysis ToolsPlace&Route (if

supported by the PDK)PERC Checker

(Programmable ERC)

Key to Support Level:Full - PDK is fully qualified and supported with this toolPartial - PDK can be used with this tool, but it is not fully qualifiedBy Request - PDK files to support this tool will be provided upon request.

Reference Design Flow:Do you have a reference design flow?___________________What kind (Analog/Mixed-Signal/RF): __________________With which Vendor(s)________________________________

4. PDK Details

Option Data VersionPDK Standard e.g. iPDK, OPDK, CDS OA

PDK,e.g. 2.0


Database e.g. OpenAccess, cdb, falcon,

e.g. Data model 4

Schematic Symbols e.g. Si2 OA SymbolsCDF e.g. iCDF, DDF, Skill,Callbacks e.g. Tcl, Skill,Layout Technology

Filee.g. oaTechDB, CDS OA techfile,

PCell Language e.g. python, Skill,DRC runset e.g. xh018-PVS, e.g. 4.0.1DRC language e.g. openDFM, IPILO,LVS runsetLVS languagePEX runsetPEX languageAntenna runsetAntenna languageERC runsetERC languagePERC runsetPERC languageInputs to PDK Build e.g. OPS, InternalPDK Build

Methodologye.g. Manual, Automated via tool x,

(Rows can be added as needed. No rows should be removed, however. Use N/A if not applicable.)


5. PDK Device Tables & Tests PerformedD

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Tool(s) used for simulation testing: _________________________________Tool(s) used for DRC testing: ______________________________________ Tool(s) used for LVS testing: _______________________________________Tool(s) used for parasitic extraction testing:___________________________Tool(s) used for post-layout simulation testing: ________________________

Comments12345 GSA ANALOG / MIXED SIGNAL / RF


Users GuideVersion 4.0


What is the GSA Analog / Mixed Signal / RF PDK Checklist?

The GSA Analog / Mixed Signal / RF Process Design Kit (PDK) Checklist is a document completed by the PDK developer and delivered with each new release of an Analog / Mixed signal / RF PDK.

This document contains a summary of the PDK, including relevant contact information, foundry process documents, and electronic design automation (EDA) tools supported. It includes details of the PDK such as the database used by the EDA software, language the PDK's PCells are written in, and standards followed such as IPL (iPDK) or Si2 (OPDK). It also includes a device list with the deliverables and tests performed for each device. The Analog / Mixed Signal /RF PDK Checklist references the GSA Mixed Signal / RF SPICE Model Checklist for modeling details.

This document serves as a combination ingredients list and “nutrition facts label” for an Analog / Mixed signal / RF PDK. This document helps you obtain a better understanding of the source data, completeness and quality of the PDK before using it to design ICs or to modify it to fit into your in-house design flow.

The following diagram is an abstract of a typical analog / mixed signal process from a foundry and a design flow from an EDA vendor interacting with a typical PDK. Each blue area represents a “front-end kit” (e.g. foundry deliverable for a process or PDK still under development) used by a circuit designer. The green areas represent a “back-end kit” used by a layout designer, which completes the PDK. Together they provide a design environment for analog / mixed signal design. The Analog / Mixed Signal PDK Checklist summarizes what you have and where to find additional information.


Figure 1 Understanding PDK Standardization

EDA Vendor Y PluginEDA Vendor X Plugin EDA Vendor Z Plugin

TCL Parser

eDRM

Pcell/regress

DRCspec

LVSspec

PEXspec

Techfiles

Techfiles


Understanding and Using the Sections of the PDK Checklist

Section 1 – Foundry and Support Contact Information

This section describes how to contact the foundry if questions arise relating to the PDK.

Foundry Name – name of foundry company and fab location (or number if relevant).

Process Name – process code and modifiers that uniquely define the process and all process options that could affect the model or differentiate the model from another process derivative.

PDK Name & Version - name of PDK and version that uniquely defines this PDK release.

PDK Date - date of PDK release PDK Checklist Revision - Indicates revision of the PDK checklist document

itself (in case you may need to revise just the PDK document, but the PDK itself didn't change).

PDK Support Contact – how to contact the foundry if questions arise relating to the PDK. It may contain a Web site URL, name, phone, fax and/or e-mail. Customize this section as needed.

Section 2 - Foundry Process Documents

This section includes references to: (1) foundry documents used to create the PDK or needed to design with the PDK; (2) documents describing the source of data used in the PDK; or (3) the methodology and tradeoffs used to obtain PDK data. Each foundry has a different method of naming and bundling these documents into single or multiple subject documents.

Document Number & Title – identifier that is used to link the document and the process, and its derivatives.

Section – describes which volume or section (used when foundries put many of the documents described in this section into a single manual).

Revision – many foundries use a version numbering system (0.X for pre-production, 1.X for risk production and 2.X for full production) of a model or document.

Date – release date of the document or data file.

Description of Document Information (listed in alphabetical order):

Bonding Pad Rules – document (if separate or if in a single design manual, which section) that addresses rules and guidelines for layout pad structures supported by the foundry.

Chip Finishing Instructions – document (if separate or if in a single design manual, which section) that addresses requirements by the foundry for special layout structures, die seal, etc. to be included in the chip database prior to tapeout.


Design Layout Rules – document (if separate or if in a single design manual, which section) that addresses the layout geometry rules for the process. This document (or a separate document) may include the electrical rules or process control monitor (PCM) specification for the process and the design rule checking (DRC)/layout vs. schematic (LVS)/layout parameter extraction (LPE) runset that interprets and verifies the latest design rules (often a separate foundry document).

Design Manual (PDK Devices) – name of a document that includes the design layout rules, layer map, DRC, LVS, LPE and parasitic runsets.

Device Cross Sections – document (if separate or if in a single design manual, which section) that includes cross-section drawings for each PDK device.

Electrical Parameters – document (if separate or if in a single design manual, which section) that defines the key device electrical parameters for design.

Electrical Rules Checking - document (if separate or if in a single design manual, which section) that defines rules that check for electrical connections in the circuit that are considered dangerous. These may include checks for unconnected inputs or shorted outputs, ESD issues, voltage dependent rules, etc.

Electromigration parameters - document (if separate or if in a single design manual, which section) that defines parameters such as current density that are used during the layout implementation to reduce electromigration damage during operation of the chip.

Electrostatic Discharge (ESD) Guidelines – guidelines that define the appropriate structures to be used to achieve various levels of ESD tolerance.

Interconnect Specification – document (if separate or if in a single design manual, which section) that defines interconnect parameters such as resistance and capacitance used by parasitic extraction.

Latchup Rules – document (if separate or if in a single design manual, which section) that addresses rules to prevent circuit latchup.

Layer Map – document (if separate or if in a single design manual, which section) that addresses GDSII layers, colors and stipple patterns used to describe the layout for the layout editor, DRC, LVS and parasitic extraction tools.

Mask Procurement – document (if separate or if in a single design manual, which section) that addresses requirements for mask making, including the relationship between drawn PDK layers and the masks.

Matching Models – document (if separate or if in a single design manual, which section) that addresses local process variation and mismatch (LPVM) issues.

Noise Model – document (if separate or if in a single design manual, which section) that addresses noise model issues.

Pcell Documentation - document (if separate or if in a single design manual, which section) that describes the interface of the Pcells.

Process Control Monitor (PCM) – PCM parameters provided by the foundry to define the acceptable process corners for wafer acceptance.


RF Parameters/Modeling – document (if separate or if in a single design manual, which section) that addresses RF parameters and modeling issues.

Safe Operating Area (SOA) – document (if separate or if in a single design manual, which section) that addresses the voltage and current conditions over which the PDK device can be expected to operate without self-damage.

SPICE Model Checklist – reference to the GSA Mixed-Signal/RF SPICE Model Checklist(s) that describe(s) the details of the SPICE models used in the PDK.

SPICE Model Library – all model files (.lib or separate model cards). Tapeout Instructions - document (if separate or if in a single design

manual, which section) that describes the procedures for taping out chips designed in this PDK.

Section 3 - EDA Tools Supported and Verified for Use with the PDK

This section states the EDA tools supported and verified for use with the PDK. Other tool versions may or may not operate correctly with the PDK. The Checklist assumes that the EDA tools operate the same on all hardware platforms if the software version has the same version number. A single PDK can support multiple circuit simulators, DRC/LVS packages or other multiple tools. If multiple simulators or other tools have the same level of PDK support (e.g. signoff), they may share an entry and column in the device tables.

Type – foundry name for the class of the EDA tool (e.g. schematic capture, circuit simulator, RF simulator, DRC/LVS verification program).

Vendor and Tool - known product name for the EDA tool (e.g. Agilent ADS, Cadence Spectre, Simucad SmartSpice, Synopsys HSPICE).

Version – many EDA vendors use a version numbering system for their products and product platforms.

Support Level – Specify the level of support provided for this tool; Use the Keywords (Full, Partial, By Request) as defined in the key below the table. Include additional notes below if necessary.

Reference Design Flow: A reference design is an example design flow based on a set of EDA vendor tools and the foundry PDK. It demonstrates the design stages from schematic/netlist to GDS. The design can be silicon proven or not. If the foundry has a reference design flow for this PDK, then that can be noted below the EDA tools table.

Section 4 – PDK Details

This section describes the details of a PDK. PDKs can be made for a wide range of EDA software. EDA software that is based on the OpenAccess database needs more detailed information, as OpenAccess allows a variety of methods for one task. For example, PCells can be written in any possible language. Use this table to indicate what PDK standards are being followed, along with the data language or type for each PDK element.


PDK Standard - Note the PDK standard being followed such as iPDK (from IPL) or OpenPDK (from Si2).

Database – database used by EDA software (e.g. CDB, OpenAccess, Milkyway).

Schematic Symbols –symbols used to create schematics. (note that Si2 OA Symbols are the standard for both iPDK and OpenPDK)

CDF – language of the component description format used to describe pcell parameters. (e.g. iCDF, DDF, Skill)

Callbacks – language the PDK device callbacks are written in (e.g. Skill, TCL, Perl, Amble).

Spice Models – language that the spice models are written in. Layout Technology File – language that the layout tech file is written in.

(e.g. oaTechDB, Skill) PCell Language – language the PDK’s PCells are written in (e.g. Skill,

Python, Perl, Tcl, Amble). DRC Runset - executable file used by the DRC software program that

contains absolute (and sometimes recommended) widths, spacing, overlaps and other rules.

DRC language – language the DRC rules are written in (may be specific tool language or a standard such as OpenDFM).

LVS Runset - executable file used by the LVS software program that extracts the intended PDK devices and their parameters to compare with schematic netlists. This is sometimes referred to as the layout parameter extraction runset and is sometimes confused with the layout parasitic extraction runset.

LVS language – language the LVS rules are written in (may be specific tool language or a standard such as OpenDFM).

PEX (Parasitic Extraction) Runset - executable file used by the parasitic extraction software program that extracts parasitic capacitance, resistance and/or inductance from circuit layout. This is sometimes referred to as the layout parasitic extraction runset, and is sometimes confused with the layout parameter extraction runset used by the LVS program.

PEX language – language the parasitic extraction rules are written in (may be specific tool language or a standard such as OpenDFM).

Antenna runset - executable file used to check for antenna violations that could potentially cause yield and reliability problems during manufacturing.

Antenna language - language the antenna rules are written in (may be specific tool language or a standard such as OpenDFM)

PERC runset - executable file used to check for programmable ERC rules such as for ESD or voltage dependent rules.

PERC language - language the PERC rules are written in (may be specific tool language or a standard such as open DFM).

Inputs to PDK Build - If using an automated system for building the PDK, use this field to document the input format (e.g. OPS, Internal)

PDK Build Methodology – Indicate here what methodology is followed for building the PDK, such as automated method using tool x; in-house automation system; manual creation; etc.


Section 5 - PDK Device Tables & Tests Performed

The device tables are designed to quickly give you an overview of the devices that are supported in the PDK, and are sorted by the following device types:

Device Type Device ExamplesMOS NMOS/PMOS LV/HV, LVth/HVth, thick oxide, floating gateBJT NPN/PNP, LV/HV, lateral, verticalDiodes N+/PW, P+/NW, ZenerCapacitors Poly-poly, MIM, MOS, MOM, tunnel, hi-QResistors N-diff, p-diff, n-well, poly0, poly1, polyn, fuse, metalInductors Standard, differentialVaractors MOS, junction, hyperabruptOther Other foundry-defined devices not in the categories

above

Device types are not standardized in the Checklist because of the wide variety of definitions for these devices. The columns in the PDK device table help you to judge the completeness of the PDK and to understand how the PDK devices have been qualified with the EDA. List the tool(s) used for testing in the space provided below the PDK Device Table. The meanings of the columns are as follows:

Device Type – see table above. Device Name – foundry-defined unique name that invokes the schematic

symbol and model card. Model Name – foundry-defined unique name of the SPICE model that is

called when the device is simulated. This name is used in the SPICE netlist to refer to the device.

Comment – a reference to a comment field to be found after the PDK device table. Comments can be used for explanations, exceptions or limits of the device. (note: either remove this statement or make clearer)

Terminals – defines the number of terminals on the device. Symbol (Schematic Symbol) – if this box is checked, a schematic symbol

exists with all terminals, is on grid, and matches EDIF 2 0 0 standards. Sim-Net (SPICE netlist for circuit simulator A, B, C or D, as listed in the EDA

tools section of the Checklist – if this box is checked, the SPICE netlist for circuit simulator A, B, C or D was generated when the schematic symbol was invoked.

LVS Net – if this box is checked, the extracted netlist successfully matched a schematic for that symbol.

SDL Net – if this box is checked, the schematic-driven layout directives were generated when the schematic symbol was invoked.

Layout – if this box is checked, a foundry-supplied layout for the device is included in the PDK, either as a Pcell or a fixed layout cell.

Schematic Sim-Test (simulation test for simulator A, B, C or D, as listed in the EDA tools section of the Checklist) – if this box is checked, the schematic


symbol has been tested to invoke the SPICE model with correct parameters over the range of PCELL parameters. The model simulates and produces verified simulation results for the specified simulator.

DRC Test – if this box is checked, all the layer and device layout rules have been implemented in the DRC rule deck and verified with a test structure.

LVS Test – if this box is checked, a layout parameter netlist was extracted and successfully compared with the schematic symbol.

PCell Test – if this box is checked, an array of PCELLS over the range of the PCELL limits was instantiated and passed DRC.

Parasitic Extract Test )Post-layout simulation test with parasitic extraction for simulator A, B, C or D, as listed in the EDA tools section of the Checklist) - If this box is checked, the device was extracted from layout using the parasitic extraction runset and the simulation test passed.

Post-Layout Sim Test (Post-layout simulation test for simulator A, B, C or D, as listed in the EDA tools section of the Checklist) - If this box is checked, the intentional device was extracted from layout using the layout parameter extraction runset and the simulation test passed.


PDK Checklist Feedback

Please send feedback on the usability and clarity of the GSA Analog / Mixed Signal / RF PDK Checklist and/or Users Guide to the GSA Working Group Manager ([email protected]; 972-489-0248)

AcknowledgementsGSA wishes to acknowledge the contributions of the following people for their significant contribution and effort to develop and review the GSA Analog / Mixed Signal / RF PDK Checklist.

Marcia McReynolds, Microsemi Jim Culp, IBMAbhijit Gupta, SanDisk Mohamed Youssef, Mentor GraphicsAparna Dey, Cadence Linda Fosler, Mentor GraphicsJingwen Yuan, Synopsys John Stabenow, CadenceJohn Laughlin, GlobalFoundries Tom Quan, TSMCJoerg Doblaski, X-Fab Thomas Moerth, AMSSri Saripalle, GlobalFoundries Karen Bartleson, SynopsysQi Wang, Cadence Harrison Beasley, GSAMany reviewers

Revision History

Mixed-Signal/RF PDK Checklist (Version 1.0)

March 2004 – initial release


April 2006 Included references to the GSA Mixed-Signal/RF SPICE Model Checklist

adopted in August 2005 and referenced specific models per device with model name

Removed redundant fields: SPICE Model Type, 1/f Noise, HF Noise and Stat Mod

Expanded the definition of sim-test to include parameter extracted and parasitic extracted simulations

Expanded definitions of foundry contacts, foundry documents and EDA tools Added revision history


December 2008 Added “PDK Details” section to account for OpenAccess-based PDKs


mailto:[email protected]


July 2013 Updated PDK Details table to include support for new IPL/Si2 standards. This

table also serves as a vehicle to highlight what the standards are. This table is expanded to include all the PDK elements listed in the diagram above.

Expanded the list of Foundry Process Documents Moved runset documentation from the Foundry Process Documents table to

the PDK Details table. In EDA Tools table, removed Version Date and added Support Level. Also

added place for documenting if a reference design flow is available. Added line in EDA Tools table for foundry to specify which DRC tool they use

for signoff. Added place for PDK name & version on front page & for revision control of

the checklist itself.

Important Disclosures

Copyright© 2013 by GSA. All rights reserved. GSA grants a worldwide license to all PDK developers to add data, contact information and company logo to a copy of the GSA Analog / Mixed Signal / RF PDK Checklist and distribute it to their partners, prospects and customers; however, all references to GSA, including GSA logo and GSA references may not be altered in any way. GSA makes no claims to the accuracy of the data entered on a GSA Analog / Mixed Signal / RF PDK Checklist.