Circuits à capacités commutées et microsystèmes

Circuits à capacités commutées et microsystèmes

Nicolas Delorme, [email protected] Cyril Condemine, [email protected]

Marc Belleville, [email protected]

Circuits à capacités commutées et microsystèmes N. Delorme, Club EEA 2005 2

2005 Outline

• Introduction

• State-of-the-art in capacitance sensing

• Sensor interfaces at LETI

• NEMS-induced (r)evolutions

• Concluding remarks


2005 Microsystem?

• Sensor/Actuator with interface IC• A/D, D/A conversion• Digital processing• Communication• Energy management• Security management

…in a small volume!

Actu

ato

rsS

en

sors

An

ten

ne

An

ten

ne

Sen

sor/a

ctuato

rIn

terfa

ce

AD

C/D

AC

Non-volatilememory

Digitalprocessing

Powermanagement

RF

Security management

Energy sources

an

ten

na

an

ten

na


2005 Our lab methodology

• « Top-down » approach

Analog Digital

Mixed-signal +MEMS and E source

Linear & non-linear Control theory tools

Analytical models

Circuit Signal & noise parameters

Testability

Adjustments

Test methodology

High-level modelling Identification

Compensator optimization (e.g. Matlab)

Feedback

Building blocks specifications

Electrical engineering Behavioral (VHDL-AMS, Verilog-A)

RTL / Gate-level (VHDL, Verilog) Transistor-level (Eldo, Spice)

(e.g. ADMS)

Systems engineering

Test engineering

IC technology

Test equipment


2005 Context

• Why low-power?– Handheld, Autonomous sensor nodes…– Environment protection– Available energy sources

• Batteries• Energy scavenging

10 nW

100 nW

1W

10 W

100 W

1 mW

10 mW

100 mW

1 W

10 W

100 W

GSM

MP3 player, Palm

Miniature FM receiver

Ear implant

Bluetooth Transceiver

10 nW

100 nW

1W

10 W

100 W

1 mW

10 mW

100 mW

1 W

10 W

100 W

10 nW

100 nW

1W

10 W

100 W

1 mW

10 mW

100 mW

1 W

10 W

100 W

DesktopP

Laptop P

GSM

RFID tag

Digital wristwatch

Standby

Crystal oscillator 32 kHz


2005 Outline

• Introduction






2005 Review of circuit techniques (1/3)

• After Wu et. Al., JSSC, May 2004• Power?

SC=Switched-Capacitor

CT=Continuous-TIme



• After Yazdi et. Al. « Precision readout circuits for capacitive microaccelerometers », IEEE 2004

AC bridge

Transimpedance amp.

Switched-cap

Switched-cap+CDS



• Power?• Ease of implementation?• Choice in prospect of co-integration


2005 Outline

• Introduction






2005 Our lab approach

• Sigma-delta-based– Low bandwidth / high resolution– High performance with

modest analog– Well suited to capacitive MEMS

• MEMS embedded in circuit architecture– Lower power– Lower noise


2005 Open-loop interfaces

• RFID pressure sensor– 0.6 m/3.3V CMOS– Full on-chip digital filter (decimator)

• Extrapolation to Vdd=1v, 130nm:– 30W ~500nW (V210, C6)

capacitive sensor interface+ADC

12bits @BW=100Hz

2mA @3.3V (RFID)

150A @3.3V ()

10A @3.3V (Digital)

Digital filterRFID Test

Se

nsor

An

ten

na


2005 Readout

• Power reduction?

After Temes et. Al., ISCAS’98

refref


2005 performance w.r.t. opamp BW & SR

• 2nd-order simulation,sampling T=1.5e-7s (F=6.4MHz)

SNDR (dB)

Opamp slew rate (x107V/s)

Opamp settling time (x10-8 s)

Optimization margins in opamp bias currents


2005 Interface power optimization

• Time-dependant power & noise control– Made possible by event knowledge

sampling instants



• Step further = Passive

Continuous-time 2nd-order ADC (voltage input)

9bits @ BW=40KHz

15A @ 3.3V (measured, core)

Active area

IntegratedR&C

?

R

R

R R

R R

C C

C C

CLK

Block diagram

Performance summary• See also TI, ISSCC’04 (switched-cap)

In+

In-

out



• Passive applied to capacitive sensor interface

Interface+ADC core

Test caps

Continuous-time 2nd-order capacitive sensor interface+ADC

Core<Pad opening!

14bits @ BW=100Hz

1A @ 3.3V (expected)

Expected performance summary


2005 Closed-loop acceleration measurement• Dynamic range: +/-2g & +/-10g• Résolution (SNR+THD) = 15 bits over [0-100Hz]

After C. Condemine et. Al., ISSCC’05


2005 Readout & actuation

• Front end: LETI patentBack end after Temes et. Al., ISCAS’98


2005 Readout & actuation


2005 Closed-loop controller

• 32-bit controller coefficients• Fully programmable• Coefficient design carried out with Laboratoire d’Automatique de Grenoble (LAG)


2005 Summary

• 15-bit SNR @50Hzclosed-loop capacitive accelerometer, 0.35m CMOS

• Better than 16-bit linearity• Extensive use of LP

techniques:– Analog current reduction– Analog activity windows– Digital gated clock– Digital level adaptation

• All @3.3V, Iana=150A, Idig=0.65A

• Digital @2.1V, Analog windowed Power 2

smux tmux vmux

Level adaptation

Digital compensator SPI link

Clock generation

Digital compensator


2005 Our lab roadmap

• Capacitive sensor interface performance

FOM 4kT DR2

BW× ×Power

-----------------------------------------

*( )

=(*) ref. Sansen W.

ST/lis3l02d

1e-05

0.0001

0.001

0.01

0.1

1

10

100

1000

10000

1996 1997 1998 1999 2000 2001 2002 2003 2004 2005

Fig

ure

of M

erit

Year

Commercial circuits

Research circuits

ST/lis2l01

ADXL202

VTIST/lis2l02a

ADXL150

ST/lis3l02a

Kulah (Michigan)

Yazdi (Michigan)

Lang (kaiserslautern)

Lemkin (Berkeley)

LETI

Analog outputDigital output

2006

Brigati (Pavia)


2005 Outline

• Introduction






2005 XG « thin SOI » accelerometers

(Transparent retiré intentionnellement)


2005 Application to MIMOSA accelerometer

• Use of a LETI-designed SC circuit (readout+ADC)(in short: coarse but fast comparison of sensor charge to a reference charge + error reduction by integration)

• Top-level Simulink model:


2005 Simulation setup – Sensor model

• 2nd-order differential eq. with:– Feedback non-linearities– Non-linear damping

l m

L m

N u m b e r o f t e e t h : n

N u m b e r o f t e e t h : n N u m b e r o f t e e t h : n

N u m b e r o f t e e t h : n

Vread=0.1V

Vread=0V


2005 Simulation setup – Electronics model

• Electronic imperfections:– kT/C noise– OTA noise & non-linearity– Comparator offset


2005 Simulation setup – existing electronics

• Switched-cap Sigma-delta based• Problems to expect:

– Low C0 & C (reliable small caps difficult to integrate)– Low pull-in voltage

Low signal

subject to glitches(only if high mechanical Fc)


2005 Results

• Without Casimir forces• C0=7.2fF, C=70aF/g• All integrated caps=100fF• Readout voltage=200mV• Input=40g@67Hz• Noise floor=-70dB@BW=100Hz• SNR=33dB@BW=100Hz• THD=-30dB


2005 Results

• Circuit parameter variations around nominal

0.0001

0.001

0.01

1e-16 1e-14 1e-12 1e-10 1e-08 1e-06 0.0001 0.01 1 100

Inpu

t-re

ferr

ed n

oise

(V

rms)

Parameter Value (Ccfbcm (F), Cfbsd (F), gmotad (A/V), idotad (normalized w.r.t. nominal))

vmux_vs_ccfbcm.datvmux_vs_cfbsd.dat

vmux_vs_gmotad.datvmux_vs_idotad.dat

+ Previous Matlab simulation

Unrealistic integrated capacitance zone

Higher power

+ +


2005 Capacitive resonant cantilever (1/2)

• Cantilever, 40µmx0.8µmx0.6µm• Capacitive detection, Cs=40aF,

Cp=0.2fF, Cpa=40fF, Ls=700H, Rs=80MCmax=40aF

• Motional current: few nA

After Verd et. Al., IEEE J. MEMS, June 2005


2005 Capacitive resonant cantilever (2/2)

• Readout circuit: motional current integrated on parasitic capacitance

After Verd et. Al., IEEE J. MEMS, June 2005


2005 Concluding remarks

• Several approaches possible for capacitance sensing• readout well suited to low power with high resolution

– Passive approach benefits?– Other than sigma-delta also good LP candidates

• Choice between SC and CT depends on Cs0 and Cparasitic

• A lot to gain from co-integrated NEMS (low Cs0 and Cparasitic) AC bridge preferred?

• New « active » detection principles would relax noise constraints (higher signal)– Transistor detection– Tunnel effect– …

Thank you for your attention

Documents

Circuits à capacités commutées et microsystèmes