Circuits and MOS Small-Signal Models Prof. Ali M. Niknejad Prof. …rfic.eecs.berkeley.edu/105/pdf/module3-3_SSM.pdf · – 2) Substitute the small-signal model of the MOSFET and

Department of EECS University of California, Berkeley

EECS 105 Spring 2017, Module 3

Prof. Ali M. Niknejad Prof. Rikky Muller

Circuits and MOS Small-Signal Models

EE 105 Spring 2017 Prof. A. M. Niknejad Prof. Rikky Muller

2

Announcements

l  HW 7 is last HW before Midterm l  Next HW will be posted before Spring Break and

due Friday after Spring Break (2 weeks to complete)

l  Next week: Midterm Review (Tuesday), Midterm (Thursday)

l  Syllabus after Spring Break will be updated

University of California, Berkeley


3

A Simple Circuit: An MOS Amplifier


DSI

GSV

vgs

DR DDV

vGS =VGS + vgs

ov

Input signal

Output signal

Supply “Rail”


4

Selecting the Output Bias Point l  The bias voltage VGS is selected so that the output is

mid-rail (between VDD and ground) l  For gain, the transistor is biased in saturation l  Constraint on the DC drain current:

l  All the resistor current flows into transistor:

l  Must ensure that this gives a self-consistent solution (transistor is biased in saturation)


DD o DD DSR

D D

V V V VIR R− −

= =

,R DS satI I=

DS GS TV V V> −


5

Finding the Input Bias Voltage l  Ignoring the output impedance

l  Typical numbers: W = 40 µm, L = 2 µm, RD = 25kΩ, µnCox = 100 µA/V2, VTn = 1 V, VDD = 5 V


2,

1 ( )2DS sat n ox GS Tn

WI C V VLµ= −

2,

1 ( )2 2D

DDR DS sat n ox GS Tn

D

V WI I C V VR L

µ= = = −

22

5V µA 1100µA 20 100 ( 1)50k V 2 GSV= = ⋅ ⋅ −

Ω

.1= (VGS −1V )2 VGS =1.32V VGS −VT = .32V <VDS = 2.5Vü


6

Applying the Small-Signal Voltage


Approach I. Just use vGS in the equation for the total drain current iD and find vo

vGS =VGS + vgs

ˆ coss sv v tω=

vO =VDD − RDiDS =VDD − RDµnCoxWL12(VGS + vgs −VT )

2

Note: Neglecting charge storage effects. Ignoring device output impedance.


7

Solving for the Output Voltage vO


vO =VDD − RDiDS =VDD − RDµnCoxWL12(VGS + vgs −VT )

2

vO =VDD − RDiDS =VDD − RDµnCoxWL12(VGS −VT )

2 1+vgs

VGS −VT

⎛

⎝⎜⎜

⎞

⎠⎟⎟

2

DSI

vO =VDD − RDIDS 1+vgs

VGS −VT

⎛

⎝⎜⎜

⎞

⎠⎟⎟

2

2DDV


8

Small-Signal Case l  Linearize the output voltage for the s.s. case l  Expand (1 + x)2 = 1 + 2x + x2 … last term can be

dropped when x << 1


Neglect

vO ≈VDD − RDIDS 1+2vgs

VGS −VT

⎛

⎝⎜⎜

⎞

⎠⎟⎟

1+2vgs

VGS −VT

⎛

⎝⎜⎜

⎞

⎠⎟⎟

2

=1+2vgs

VGS −VT+

vgsVGS −VT

⎛

⎝⎜⎜

⎞

⎠⎟⎟

2


9

Linearized Output Voltage For this case, the total output voltage is: The small-signal output voltage:


vO ≈VDD − IDRDS 1+2vgs

VGS −VT

⎛

⎝⎜⎜

⎞

⎠⎟⎟

vO ≈ (VDD − IDRDS )−2IDRDSvgsVGS −VT

=VDD2−VDDvgsVGS −VT

“DC” Small-signal output

vo ≈ −2IDRDSvgsVGS −VT

= −VDDvgsVGS −VT

Avvgs

Voltage gain


10

Plot of Output Waveform (Gain!)


Numbers: VDD / (VGS – VT) = 5/ 0.32 = 16

output

input

mV


11

There is a Better Way! l  What’s missing: didn’t include device output

impedance or charge storage effects (must solve non-linear differential equations…)

l  Approach II: Solve problem in two steps. –  1) DC voltages and currents (ignore small signals

sources): set bias point of the MOSFET ... we had to do this to pick VGS already

–  2) Substitute the small-signal model of the MOSFET and the small-signal models of the other circuit elements …

l  This constitutes small-signal analysis



12

Total Small Signal Current


( )DS DS dsi t I i= +

DS DSds gs ds

gs ds

i ii v vv v∂ ∂

= +∂ ∂

1ds m gs ds

o

i g v vr

= +

Transconductance Conductance


13

Changing One Variable at a Time


Assumption: VDS > VDS,SAT = VGS – VTn (square law)

GSV

/DSI k

3VDSV =1VTV =

Square Law Saturation

Region

Linear Triode Region

Slope of Tangent: Incremental current increase


14

The Transconductance gm


Defined as the change in drain current due to a change in the gate-source voltage, with everything else constant

, ,

( )(1 )GS DS GS DS

D Dm ox GS T DS

GS GSV V V V

i i Wg C V V Vv v L

µ λΔ ∂

= = = − +Δ ∂

2, ( ) (1 )

2ox

DS sat GS T DSCWI V V V

Lµ

λ= − +

( )m ox GS TWg C V VL

µ= −

0≈

2 2DSm ox ox DS

ox

IW Wg C C IWL LCL

µ µµ

= =

2( )

DSm

GS T

IgV V

=−

Gate Bias

Drain Current Bias

Drain Current Bias and Gate Bias


15

Output Resistance ro


Defined as the inverse of the change in drain current due to a change in the drain-source voltage, with everything else constant

Non-Zero Slope

DSVδ

DSIδ

IDS / K

VDS (V )


16

Evaluating ro


1

,GS DS

Do

DS V V

irv

−⎛ ⎞∂⎜ ⎟=⎜ ⎟∂⎝ ⎠

2( ) (1 )2ox

D GS T DSCWi V V V

Lµ

λ= − +

02

1

( )2ox

GS T

r CW V VLµ

λ=

−

01

DS

rIλ

≈


17

Three-Terminal Small-Signal Model


ids = gmvgs +

1ro

vds


18

P-Channel MOSFET


Everything is flipped around compared to an NMOS. Currents are negative of NMOS.


19

Square-Law PMOS Characteristics


/DSI k

VDS (V)

VGS = −2V

VGS = −3V

VGS = −4V

VGS = −1V


20

Right Side Up!


VSG = 2V

VSG = 3V

VSG = 4V

VSG = 1V

ISD / k

VSD (V)


21

Small-Signal PMOS Model



22

What we’re ignoring for now…

l  The fourth terminal of the MOSFET is the body of the transistor… it can act like a second gate, or “back gate”

l  The junctions of the transistor form pn-junction diodes with body, this introduces parasitic capacitance

l  Modern transistors are very short channel lengths, and there are many “short channel” effects that we’re ignoring, most prominently velocity saturation

l  Subthreshold conduction l  Capacitance!


Documents

Circuits and MOS Small-Signal Models Prof. Ali M. Niknejad Prof. …rfic.eecs.berkeley.edu/105/pdf/module3-3_SSM.pdf · – 2) Substitute the small-signal model of the MOSFET and