Circuits Intégrés Analogiques - 2012/2013 - Chapter 9 08 ...nouet/homepage/pdf_files/CIA1213CH9.pdfCircuits Intégrés Analogiques - 2012/2013 - Chapter 9 08/01/2013 5 Plan • Introduction

Circuits Intégrés Analogiques - 2012/2013 - Chapter 9 08/01/2013

1

M2 EEA – Systèmes MicroélectroniquesPolytech’montpellier – ERII 4

Analog Integrated Circuits

Chapter IXMiller Operational Transconductance Amplifier:

Dynamic performances

Pascal Nouet / 2012-2013

[email protected]

http://www2.lirmm.fr/~nouet/homepage/lecture_ressources.html

Introduction

• Miller OTA is a two-stage amplifier with high output impedance

• Dynamic performances– Slew-Rate (SR)

– Cut-off frequency / bandwidth (fc)

– Unity-gain frequency (fu)

– Gain-Bandwidth product (GBW)

V+ V-

Ibias1

Vdd Vdd

Ibias2

Vout

1

11

out

mv g

gA −≅

2

22

out

mv g

gA −≅

Plan

• Introduction

• Two stage amplifier Dynamic Performances– Cut-off frequency and poles

– AC simulations

– Dominant pole and slew-rate– Stability and compensation

• From Miller OTA to Miller OPAMP

• Other amplifiers

3Pole due to the first stage output

MOS circuits exhibit a lot of capacitances…

V- V+T1 T2

Vdd

T3 T4

Vout

T12

V- V+T1 T2

Vdd

T3 T4

VoutV- V+

T1 T2

Vdd

T3 T4

Vout

T12

V- V+T1 T2

Vdd

T3 T4

Vout

T12

V- V+T1 T2

Vdd

T3 T4

VoutV- V+

T1 T2

Vdd

T3 T4

Vout

T12

1212 32

ings CC ⋅=

24, dd CC

1212 % 10 ingd CC ⋅=

121212 LWCC oxpin ⋅⋅=

4

p1

1

gg

g

ggg

gA

4ds2ds

2m

1out4ds2ds

2m1v τ+

⋅+

−=++

−=

πττ

2

1

10 142

122 =⇒+

≅ cdsds

inv fgg

CA

Pole due to the first stage output

• Simplified approach– Calculation of the load

capacitance of the first stage Miller effect must be taken

into account

pC

Ag invout 10

1221 ≅⇒

5

V- V+

Ibias

T1 T2

Vdd

T3 T4

Vout

T7

Ibias7

T12

T13

Ibias13

Vout

Vbias

V- V+

Ibias

T1 T2

Vdd

T3 T4

VoutV- V+

Ibias

T1 T2

Vdd

T3 T4

Vout

T7

Ibias7

T12

T13

Ibias13

Vout

Vbias

Plan

• Introduction


– AC simulations




6


2

Studied OTA

T8

T5T11

T9

R

Ibias/10

T6T10

V- V+T1 T2

Vdd

T3 T4

T7

Ibias7

T12

T13

Ibias13

Vout

Vref

CfT16

Vout1

4ds2ds

1m1v gg

gA

+−≅

1312

122

dsds

mv gg

gA

+−≅

7

8

59000

70500

57600

DC simulation

1st stage gain

Total gain

DC gain: impact of an output load

• Rout = 10MΩ, 1MΩ et 100kΩ

'1312

1312'

outdsds

outdsdsvv ggg

gggAA

++++⋅=

9 10AC response

-40 dB/décade

-20 dB/décade

1er pôle

2ème pôle

Two stage OTA: ac response analysis

• Phase diagram (without compensation)– 1st pole : 23900 Hz

– 2bd pole : 19,2 MHz

– 180° phase shift: 67,6 MHz

11Two stage OTA: ac response analysis

• Theoretical analysis of 1st pole due to capacitances

0:m2 0:m4 0:m12

– cdtot 178.5f 188.1f

– cgs 655.3f

– cgd 83.27f

pFC

pFCAA

total

gdvv

92,19

9,18227 1222

=

=⋅⇒−=

kHzfµsgg

Cc

dsds

total 4,2421

51,6 142

≅=⇒=+

=πτ

τ

12


3

Two stage OTA: ac response analysis

• Diagramme de gain (AOP non compensé)– DC gain: 59566 (95,5 dB )

– Unity-gain frequency: 153 MHz gain @ phase shift equal to -180° > 0 dB

13 Two stage OTA: impact of an output capacitance

• Gain diagram 2nd pole is shifted

Cout = 1fF, 100fF, 10pF et 1nF

outc

out

dsds

out

Cf

C

gg

C

⋅=⇒=

+≅

−

− πτ

210.4

10.4

6

261312

2

Two stage OTA: impact of an output capacitance

Cout = 1fF, 100fF, 10pF et 1nF

Plan

• Introduction


– AC simulations




16

Poles of an amplifier

• Simplified model– One stage one pole

– First stage pole is a dominant pole (Miller effect)

– A two stage amplifier should be stable

• Simulated behavior, some other poles exist (current source for example)– Phase shift increases above 180° @ high frequencies

– A two stage amplifier is not naturally stable

17 18AC response

-20 dB/décade

1er pôle

2ème pôle

fu=153MHz

f=68MHz φ=-180°


4

Dominant pole adjustment

• 1st pole can be shift down in low frequencies by adding Cf in parallel with Cgd12

V- V+T1 T2

Vdd

T3 T4

T7

Ibias7

T12

T13

Ibias13

Vout

Vbias

Cf

Vout1

19

pFCHzfna

CA

ggf

gg

C

CAC

CC

fc

fv

dsdsc

dsds

total

fvtotal

gdf

5500.2.227

10.6,3500..

.2.2

1

6

1

2

421

42

2

12

==⇒=

+==

+=⇒

⋅=⇒

>>

−

π

ππτ

τ

20Cf = 100fF 1pF 5pF 10pF

fc=519Hz

Other dynamic performances

• Gain-BandWidth product

• Unity-gain frequency– Circuits behave as a 1st order

• Slew-rate Maximum swing of the voltage output

21

MHz8,31pF5.2

V/mA1GBWV/mA1g.n.a

C.2

gGBW

C.2.A

ggA

gg

gfAAGBW

f

2m

f2v

4ds2ds2v

4ds2ds

2m1c2v1v

=π

=⇒=

π=⇒

π+

+==

m2

f

2mu C.2

gGBWf

π==

f

bias

max

f

C

I

dt

)C(dV.R.S ==

OTA dynamic performances: Slew-Rate

SR = 29,1 V/µs

22


• Let’s calculate the SR with Cf=5pF

• Impact of W/L of T1 and T2

doubling SR without changing fu et Ibias

V- V+T1 T2

Vdd

T3 T4

T7

Ibias7

T12

T13

Ibias13

Vout

Vbias

Cf

Vout1

23

µs/V20pF5

µA100.R.S

C

I

dt

)C(dV.R.S

f

bias

max

f

==

==

11 T

'

T

1eff1eff

1eff

bias2m2m

f

2mu

ff L

W

4

1

L

W

2

'VV

'V

I.2

2

g'g

C.

'gf

2

C'C =⇒=⇒==⇒

π=⇒=⇒


SR = 57,2 V/µs

pFCL

W

L

Wf 5.2et 23,5

494

2

2

1

1 =≅==

24


5

Plan

• Introduction


– AC simulations




25 26Cf = 100fF 1pF 5pF 10pF

fc=519Hz

fu=33MHz

f=33MHz φ=-180°

gm2.vinVout

r1

Cc

C1gm12.vout1 r2 C2

Vout1

2-stage OTA: frequency responseanalysis

V- V+T1 T2

Vdd

T3 T4

T7

Ibias7

T12

T13

Ibias13

Vout

Vbias

Cf

Vout1

12

13122

13122

12421

421

////

//

gdfc

loaddd

loaddsds

gsdd

dsds

CCC

CCCC

gggr

CCCC

ggr

+⇒

++⇒

⇒

++⇒

⇒

27 282-stage OTA: frequencyresponse analysis

( )

( )

( )

12

22

1

122

112

11111

12

1

...

),(...

mc

c

outout

outoutcoutout

outm

outinoutoutoutcoutout

inm

gpC

pCCr

vv

vvpCvpCr

vvg

vvfvvvpCvpCr

vvg

−

++=⇒

−++=−

=⇒−++=−

gm2.vinVout

r1

Cc

C1gm12.vout1 r2 C2

Vout1

gm2.vinVout

r1

Cc

C1gm12.vout1 r2 C2

Vout1

( ) ( )( )cc

cmcc

CCCCCCrrb

CrrgCCrCCra

122121

21121122

++=++++=

212

21212

1

1

bpap

gpC

rgrg

v

v m

cmm

in

out

++

−⋅⋅=

gm2.vinVout

r1

Cc

C1gm12.vout1 r2 C2

Vout1

292-stage OTA: frequencyresponse analysis

• Increasing Cc

– fz and fp1 are shifted down accordingly

• Increase of gm12

silicon cost, power consumption

( )

c

12mz

21

12m2p

c212m11p

C2

gf

CC2

gf

Crgr2

1f

⋅π−

=

+⋅π=

⋅π=

gm2.vinVout

r1

Cc

C1gm12.vout1 r2 C2

Vout1

gm2.vinVout

r1

Cc

C1gm12.vout1 r2 C2

Vout1

ω+

ω+=++

++

−⋅⋅

=

2p1p

2

212m

c212m12m

in

out

p1

p1bpap1

bpap1

g

pC1rgrg

v

v

2-stage OTA: frequencyresponse analysis

gm2.vinVout

r1

Cc

C1gm12.vout1 r2 C2

Vout1

• Solution: adding a serial resistance– 1st and 2nd poles doesn’t move a lot

– Additional 3rd pole @ higher frequencies

– Zero is changed:

Zero can be placed

to compensate 2nd pole (unreliable)

just after the unity gain frequency (reliable)

Rs

( )smcz RgC

f−⋅

−=1212

1π

30


6

2-stage OTA: zero positioning

• 1st method

• Step 1: – First simulation with

random Cf0 (5pF) and Rs=0

– Choice of a phase margin extract fu

measure Av(fu)

• Step 2:– Calculation of Cf= Cf0.Av(fu)

– Zero positionning @ fu+20% Rs calculation

31

V- V+T1 T2

Vdd

T3 T4

T7

Ibias7

T12

T13

Ibias13

Vout

Vbias

Cf

Vout1

Rs

32CC=5pF and RS=0

fu=10,7MHz φ=-125°

fu=10,7MHz

AV=2,6 (8,3dB)

CC=13pF

fc=520Hz

33

fu=21MHz

AV=-0,46dB

CC=13pF and RS=0

fu=21MHz φ=-180°

( )Ω≈+

⋅π=⇒

=−⋅π

−=

1020g

1

Cf2

1R

MHz12Rg1C2

1f

12mczs

s12mcz

fc=200Hz

34

fc=200Hz

CC=13pF and RS=1020Ω

fu = 10,3 MHz

Phase margin73°

180° phase-shift frequency

77,6 MHz

Gain margin20,2dB

35CC=13pF and RS=1020Ω2-stage OTA: zero positioning

• 2nd method:– Choice of unity-gain frequency:

• Example: GBW=18MHz

– Calculation of the capacitance:

– Zero positionning

• fu + 20% : 22MHz

( ) Ω≈+⋅

=⇒=−⋅

−= 18201

21

2212

1

1212 mczs

smcz gCf

RMHzRgC

fππ

MHz18fu =

pFf

gC

u

mf 8,8

22 ≈=

π

36


7

Phase margin100° @ 18,4MHz

Gain margin23,3dB @ 282MHz

37CC=8.8pF and RS=1820Ω2-stage OTA: zero positioning

• In any case resistor maybe replaced by a MOST in the linear regime V- V+

T1 T2

Vdd

T3 T4

T7

Ibias7

T12

T13

Ibias13

Vout

Vbias

13pFT16

Vout1

w=16µ

L=1µ

38

effox

ds

effoxds

dsds

dseffoxds

VL

WµC

r

VL

WµC

V

Ig

VVL

WµCI

1=

==

=

δδ

39

fu = 25,8 MHz

Phase margin32°

180° phase shift frequency

47,4 MHz

Gain margin5,68dB

CC=5pF and T16

(30µm/0.8µm) Plan

• Introduction


– AC simulations




40

Ldsds

mvL Ggg

gAG

++−≅⇒

1312

122

From 2-stage OTA to Miller OPAMP

T8

T5T11

T9

R

Ibias/10

T6T10

V- V+T1 T2

Vdd

T3 T4

T7

Ibias7

T12

T13

Ibias13

Vout

Vbias

CfT16

Vout1 T14

Vout

T15

pACgg

gA

vfdsds

mv

242

11 ++

−≅

1312

122

dsds

mv gg

gA

+−≅ Lmdsds

mv Gggg

gA

+++≅

151514

153

41Plan

• Introduction


– AC simulations




42


8

2-stage OTA with PMOS differentialpair

43

M4

Vdd=+3,3V

M5M10

M12

M1

M11

M3

M2Vin- Vin+ M9

M7

M6

M8CC

Vout

A single-stage OTA

V1 V2T1 T2

Vdd

T4T8

T7

IpVp

T8

T5 T6

T9

CL

Vout

« Folded-cascode » OPAMP

Ib1

V- V+

Ib2

T1 T2

Vdd

T11

T3

T12

T4

T13

T8

VB2

T7

T10T9

T5 T6

VB1

CL

Vout

« Folded-cascode » OPAMP

Documents

Circuits Intégrés Analogiques - 2012/2013 - Chapter 9 08 ...nouet/homepage/pdf_files/CIA1213CH9.pdfCircuits Intégrés Analogiques - 2012/2013 - Chapter 9 08/01/2013 5 Plan • Introduction