CISC RISC and Post RISC Mark Becker and Abdul Ahmad v2(2)

8/6/2019 CISC RISC and Post RISC Mark Becker and Abdul Ahmad v2(2)

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CISC, RISC and Post RISCCISC, RISC and Post RISCBy Mark Becker and Abdul AhmadBy Mark Becker and Abdul Ahmad

Complex Instruction Set

Computers (CISC):

CISC

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Definition: A complex instruction set computer

(CISC, pronounced like "sisk") is a microprocessorinstruction set architecture (ISA) in which eachinstruction can execute several low-leveloperations, such as a load from memory, an

arithmetic operation, and a memory store, all in asingle instruction. The term was retroactivelycoined in contrast to reduced instruction setcomputer (RISC).

CISC

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History: In the late 1950s, faced with the need torationalize it's computer product lines, IBM instituted aresearch program having the objective of creating a range

of software compatible computers that would also captureits existing software investments. The result, introducedon April 7, 1964 was the System/360, the firstcommercially available microprogrammed computerarchitecture (latter to become known as complexinstruction set computer, or CISC architecture). Thesuccess of System/360 resulted in CISC architecturesdominating computer, and later microprocessor, designfor two decades.

CISC

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History (cont):

However, the ability to incorporate any instruction which

could be microprogrammed turned out to be a mixedblessing. During the mid-1970s, improved performancemeasurement tools demonstrated that the execution ofmost application programs on CISC-based systems wasdominated by a few simple instructions, and the complex

ones were seldom used.

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History (cont):

As a result, in October 1975 the project was initiated at IBM's WatsonResearch Center which, four years later gave birth to a 32-bit RISC

microprocessor named for the building in which it was developed.

CISC

In the immortal words of Joel Birnbaum,the first leader of the 801 project and laterdesigner of the PA-RISC architecture:

Engineers had guessed that computersneeded numerous complex instructions inorder to work efficiently. It was a badguess. That kind of design producedmachines that were not only ornate, butbaroque - even rococo.

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CISC, RISC and Post RISCCISC, RISC and Post RISC

CISC

By Mark Becker and Abdul AhmadBy Mark Becker and Abdul Ahmad

Benefits:Directly supported high-level programming constructs combined intosingle instructions.

The compact nature of such instruction sets resulted in smaller programsizes and fewer calls to main memory which meant good programmingproductivity.

Many designs achieved the aim of higher throughput at lower cost andalso allowed high-level language constructs to be expressed by fewer

instructions. 7


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CISC, RISC and Post RISCCISC, RISC and Post RISC

CISC

By Mark Becker and Abdul AhmadBy Mark Becker and Abdul Ahmad

Problems:Low-end versions of complex architectures (i.e. using less hardware) could leadto situations where it was possible to improve performance by not using a

complex instruction (such as a procedure call or enter instruction), but insteadusing a sequence of simpler instructions.

The invention of Pipelining made CISC less efficient because the CISC instructioncould not be broken up into smaller parts that could be run simultaneously.

When memory became less expensive, it became less important to create

instruction sets that called main memory fewer times. 8


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Reduced Instruction Set

Computers (RISC):

RISC

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The Microprocessor

Revolution Technology in microprocessor has led to new inventions, such as digitaldevices such as digital camera, wristwatches, cellular phone, personal computersand non digital device such as automobile are more intelligent. Their performancehas improved by a factor of 10,000 in the 37 years since its birth in 1971! Has anyother invention, so useful already at birth, undergone a similar improvement?

As we already know that the development of microprocessor has been doublingevery 18 month!

This increase partly was influenced with the introduction of Reduced Instruction SetComputers (RISC). The instruction set is the hardware "language" in which thesoftware tells the processor what to do. Surprisingly, reducing the size of theinstruction set -- eliminating certain instructions based upon a careful quantitativeanalysis, and requiring these seldom-used instructions to be emulated in software --can lead to higher performance, for several reasons:

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The Microprocessor (continued)

Performance can be accelerated since there are more space in the chipwith commonly used instruction.

Optimization is easier.

It allows microprocessors to use techniques that was restricted to thelargest computers.

It simplifies translation from the high-level language in which peopleprogram into the instruction set that the hardware understands, resultingin a more efficient program.

RISC creation was preceded the hardware design, a more quantitativeapproach to computer architecture. Previously, many computer designprojects guided by intuition that lead to disappointing results.

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The History of RISC

Three research project conducted by IBM, the Berkeley RISC processor,and the Stanford MIPS processor contributed in RISC early development.

It attracted enormous interest because of claims of a performanceadvantage of anywhere from two to five times.

IBM project was the first to start in the late 70s but was the last tobecome public. The IBM machine was designed as a minicomputer madefrom hundreds of chips, while the university projects were both

microprocessors.

John Cocke is considered to be the father of the 801 design. Inrecognition of his contribution he received both the Turing award, thehighest award in computer science and engineering, and the PresidentialMedal of Technology.

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The History of RISC

In 1980, David A. Patterson and his colleagues at the University ofCalifornia at Berkeley, sponsored by the Department of Defense

Advanced Research Projects Agency(DARPA), began the project that wasto give this approach its name. They built two machines, called RISC-Iand RISC-II. Because the IBM project was not widely known ordiscussed, the role played by the Berkeley group in promoting the RISCapproach was critical to the acceptance of the technology.

In 1981, John L. Hennessy and his colleagues at Stanford published adescription of the Stanford MIPS machine, also developed under DARPAsponsorship. Both university projects were interested in designing asimple machine that could be built as a microchip within the universityenvironment. All three early RISC machines had similar "reduced"languages.

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The History of RISC

Importantly, the Berkeley and Stanford projects fit within the DARPAVLSI Program that developed the concept of the multichip wafer, which

allowed multiple integrated circuit designs to share a single siliconfabrication run, dramatically reducing costs.

In 1986 the computer industry began to announce commercialprocessors based on the technology explored by the three RISC researchprojects.

In 1987 Sun Microsystems began delivering machines based on theSPARC architecture, a derivative of the Berkeley RISC-II machine. It wasSun's success with RISC-based workstations that convinced theremaining skeptics that RISC was significant commercially. In particular,RISC advocates used Sun's success to get RISC restarted at IBM. IBM

announced a new RISC architecture in 1990.

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The History of RISC

Intel's microprocessors are used in the popular IBM PC, and hence arethe most widely used microprocessors, but they predate RISC. RISC

microprocessors have been the standard-bearers of performance, so Intelhas embraced ideas from RISC and followed the quantitative approach.Thus both the ideas and the competition from RISC has benefited allcomputer users, since RISC has raised the performance target for theentire industry. With the announcement that Hewlett-Packard and Intel

will move to a common instruction set in 1997, the end of the non-RISCarchitectures draws near.

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RISC

Advantages:

Can run several instructions simultaneously

Shorter Instructions - Breaking the complex instructioninto several short simpler instructions

Minimize latency effect between instructions

Multiple hardware pieces can interact in one clock cycle

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Post RISCIntroduction:

The current generation of processors introduces an exciting new era of

high performance processors. These processors uniformly showdramatic increases in performance of a scale that has not been seensince the late 1980s when RISC processors first became available. Thechanges that spurred the performance gains of RISC were clearbecause they were changes in instruction set architecture (ISA). Thechanges that are spurring the performance gains of recent processors,

however, are more subtle. While there are some changes that impactthe ISA such as the Intel MMX and Sun VIS instructions, theperformance gains are mostly due to features that are decidedly notRISC. These new features referred as Post-RISC.

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Post RISCPost-RISC Characteristics:

The most significant Post-

RISC changes are to theimplementation of thearchitecture. SuperscalarRISC processors relied on

the compiler to orderinstructions for maximumperformance and hardwarechecked the legality ofmultiple simultaneous

instruction issue. 19


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Post-RISC processors are

much more aggressive atissuing instructions usinghardware to dynamicallyperform the instruction

reordering. The newprocessors find moreparallelism by executinginstructions out of programorder.

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Out-of-order execution is not a new concept in computing

(it existed twenty years ago on IBM and CDC computers)but it is innovative for single-chip implementations. Theresult is a RISC ISA with an execution core that is similarto a dataflow implementation. However, these processors

still adhere to most of the RISC concepts. For example, theexecution units of these processors are optimized tocomplete most instructions in a single cycle.

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Post RISCPost-RISC Pipeline:

The Post-RISC Pipeline consists of three connected three

connected components: (1) Fetch/Decode section, (2)Execution Units, and (3) Retire Units. Between each ofthese components, there is a flexible queue of instructions.The Instruction Reorder Buffer connects the Fetch/Decode

components and the Execution Units. The CompletedInstruction Buffer connects the Execution units to theRetire Unit.

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Wikipedia - Complex instruction set computerhttp://en.wikipedia.org/wiki/Complex_instruction_set_computer

A Brief History of RISC (circa 2001)http://www.aallison.com/history.htm

Reduced Instruction Set Computers (RISC):Academic/Industrial Interplay Drives Computer Performance Forwardhttp://www.cs.washington.edu/homes/lazowska/cra/risc.html

Beyond RISC - The Post-RISC Architecturehttp://www.cse.msu.edu/~enbody/postrisc/postrisc2.htm

Computer Architecture and Organization: An Integrated ApproachBy Miles J. Murdocca and Vincent P. HeuringISBN: 978-0-471-73388-1http://www.wiley.com/WileyCDA/WileyTitle/productCd-0471733881.html

References

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CISC RISC and Post RISC Mark Becker and Abdul Ahmad v2(2)