C.K.K.Yang and E.H.ChenPresented by :

Pedram Payandehnia 810187200Supervisor : Professor Fakhraei

ADC-Based Serial I/O ReceiversCICC 2009

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Class presentation for the course: “Custom Implementation of DSP Systems” All the materials are copy rights of their respective authors as listed in references.

Serial Link Applications[1] Processor-to-memory

RDRAM (1.6Gbps), XDR DRAM (7.2Gbps) XDR2 DRAM (12.8Gbps)

Processor-to-peripheral PCIe(2.5, 5, 8Gbps), Infiniband(10Gbps), USB3 (4.8Gbps)

Processor-to-processor Intel QPI (6.4Gbps), AMD Hypertransport(6.4Gbps)

Storage SATA (6Gbps), FibreChannel (20Gbps)

Networks LAN: Ethernet (1, 10Gbps) WAN: SONET (2.5, 10, 40Gbps) Backplane Routers: (2.5 –12.5Gbps)

IEEE 802.3xx

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Introduction[1]

Design Challenges Finite Bandwidth => Frequency

dependent attenuation => ISI Reflection Crosstalk Jitter in Transmitter and

Receiver

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Simple Transmitter[2]

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Simple Receiver[2]

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ADC based Receiver – Introduction[31]

The common design approach has used CT or DT, FFE and DFE

A common trend in digital communications has been the increasing use of digital signal processing.

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ADC based Receiver - Introduction[31]

Benefits : The digital signal representation enables

greater flexibility and more powerful signal processing techniques to achieve lower

BER.Ease of programmability Extensibility for different channel

characteristics, and robustness to process variations.

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ADC based Receiver – Introduction[31]

Challenges face the adoption of ADC-based receivers for SerDes applications:These applications have substantially higher data

sampling rates that are nearing 20Gb/s per channel. The required sampling rates for such a data bandwidth can be within an order of magnitude of the fT of the underlying CMOS technology.

Furthermore, a large number of SerDes channels are often integrated along with application-specific signal processing. Thus, the power dissipation per channel is typically heavily constrained.

Given these challenges, the adoption of ADC-based frontends is still debated .

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ADC Specification- ADC Resolution[31]

The number of conversion levels depends on the linkcharacteristics. Copper Ethernet and DSL applications canrequire up to 10bits. EDC and SerDes applications can require up to 6bits.

backplane channel with >22dB of attenuation at the Nyquist frequency.More than 5bits of resolution is needed to achieve a reasonable BER and can still be quite far from an ideal equalizer (shown as a quantization-error-free mixed-mode DFE with the same noise condition). Performance approaches the ideal for a low attenuation channel.

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ADC Specification- Power Dissipation[31]

For an IC with Tb/s of aggregate bandwidth and >10Gb/s/channel links, the power requirement is less than a few hundred mW/link to maintain a reasonable total I/O power. As a result, energy per bit for a link cannot exceed 10’s of pJ/bit. For the ADC, the figure-of-merit (FoM) corresponds to <0.5pJ/step.

Flash: FoM of 8.5 [17], 2 [15] and 0.7pJ/step [5] in 250nm, 90nms and 65nm.

Pipeline: FoM of 2[11], 2.4[10], and 0.6pJ/step[6] in 130nm, 90nm, and 65nm.

SAR: rates. The sampling speed of each interleaving path is typically a few hundred MHz [12][19][21] thus a high degree of interleaving is needed. However, due to the lower input capacitance, up to 24GS/s [12] has been demonstrated using 160-way interleaving.

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Design Tradeoffs & Power Considerations- ADC Architecture[31]

Flash : o By employing a large offset tuning range one can

implement a loop-unrolled DFE [18].

Pipeline : o More highly interleaved designs using pipelined ADC

can reach a higher number of bits for the same input capacitance.

o The reference levels are not fully programmable and hence cannot be used for a loop-unrolled architecture.

o Enables an option of integrating a low tap-weight DFE at each stage [19].

SAR : May be in near future by EHSAN !!

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Design Tradeoffs & Power Considerations- Low Jitter Clock Generation[31]

Low jitter multiple phase clocks are another substantial source of power dissipation. The noise specification of the frontend directly determines the power dissipation of the on-chip clock generation oscillator.

The clocking cost of the sampling frontends alone can cost >5pJ/bit if not carefully designed and laid out.

While the clocks for the interleaving S/H are the noise critical signals, the total clock capacitance can be substantially higher. The ADC architecture can impact the total clock loading. Some architectures such as SAR and pipelined ADC tradeoff input capacitance with clock capacitance. Even more significant is the digital signal processing following the ADC. As seen in the next section, the digital data deserializer, filters, and timing recovery all require a large number of clocked elements.

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Design Tradeoffs & Power Considerations- Timing Recovery[31]

Fig. 11 illustrates a separate path for timing recovery. An edge-sampling phase detector can be used to determine whether the sampling edge is early or late. An extra clock signal samples the data transition information. The transition information also depends on the data decisions and hence the transition samples are typically delayed until the data decisions are made.

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Design Tradeoffs & Power Considerations- Timing Recovery[31]

Drawbacks : 1. With ISI, the phase information has a poor distribution.2. The binary data are decided after a long latency which

dramatically reduce the bandwidth of the loop and incur larger jitter and less phase tracking.

Two improvements are possible: 1. By providing additional filtered for the CDR path. The filter can

be designed to roughly cancel the ISI.2. Additionally, an auxiliary data receiver (in gray in Fig. 11). A data decision can be made with very low latency. While this decision has poor BER, since the CDR loop is severely low-pass

filtered, a BER of 10-6 is sufficient to provide phase locking [24].

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Design Tradeoffs & Power Considerations- Timing Recovery[31]

Second approach of data-driven timing recovery [5][25][26][27] only based on data samples.

The implementation is often simplified by assuming a symmetric and short memory channel so that the timing-recovery filter is small. A few specific data pattern can also be used to determine the desired early/late information without implementing complex filtering [23][26].

Similar to the edge-sampling CDRs, the tracking bandwidth can be limited by the long decision latency.

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Design Tradeoffs & Power Considerations- Timing Recovery[31]

Both transition sampling and data sampling approaches may not sample signals at the peak of pulse response since the response depends on the channel characteristics. As shown in Fig. 14, the lock point may be shifted from the ideal position. In some implementation, an auxiliary control loop has been proposed to shift the sampling phase by either using an explicit eye monitor [28], or by detecting the SNR of the received signal [29] or by the BER [13].

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Design Tradeoffs & Power Considerations- Digital Signal Processing[31]

Up to 65-nm CMOS process, the digital processing occupies a substantial portion of the total power.

For efficient digital signal processing, the digital clock rate is typically <1/10 of the link data rate.

A digital DFE alone with relatively few taps (<5) can be very power efficient especially when using a selection-based architecture similar to mixed-mode loop-unrolling (100mw)

An interleaved multiply-add implementation of a 4-tap FFE with a DFE can consume considerably more power

such as ~700mW in [6]. To extract the signal under very low SNR, an FFE followed by a maximum-likelihood sequence detector (MLSD) such as a Viterbi decoder has been demonstrated. However, the power dissipation of ~2W [7] is too high to be realistic for a multi-channel link.

Technology scaling has been shown [30] to lead to limited analog power scaling but leads to power scaling of digital processing. More complex FIR and DFE approaches are more likely in the 45-nm CMOS technology node and MLSD approaches are not likely until the 32-nm CMOS technology node.

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Conclusion[31]

In the near term, simpler digital techniques supplemented with some analog pre-filtering will be the ADC-based receiver architecture with reasonably power of a few tens of pJ/bit.

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References

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[1] Prof. Palermo, Texas A&M, “ECEN 689: Special Topics in High-Speed Links Circuit & Systems”, Lectures Notes

[2] John F. Bulzacchelli et.al, “A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS Technology”,JSSC 2006

[3] V. Balan, et al., “A 4.8-6.4-Gb/s Serial Link for BackplaneApplications Using Decision Feedback Equalization,” JSSC, Sept2005, pp. 1957-1967328 11-2-6

Authorized licensed use limited to: University of Tehran. Downloaded on April 27,2010 at 07:12:15 UTC from IEEE Xplore. Restrictions apply.

[4] K.-L.J. Wong, et al., "A 5-mW 6-Gb/s Quarter-Rate SamplingReceiver With a 2-Tap DFE Using Soft Decisions", JSSC, Apr2007, pp. 881-8[3] Y-S. Sahn, et al., "A 2.2Gbps CMOS look-ahead DFE receiver for multidrop channel with pin-to-pin time skew compensation,”2003 CICC, pp

[5] V. Stojanovic, et al., “Adaptive equalization and data recovery ina dual-mode (PAM2/4) serial link transceiver”, 2004 VLSI Symp.,pp 348-51

[6] M. Harwood, et al., “A 12.5Gb/s SerDes in 65nm CMOS Using aBaud-Rate ADC with Digital Receiver Equalization and ClockRecovery”, 2007 ISSCC, pp. 436-7

[7] J. Cao, et al., “A 500mW Digital Calibrated AFE in 65nm CMOS for 10Gb/s Serial Links over Backplane and Multimode Fiber”,2009 ISSCC, 21.7, pp 370-1

[8] O. E. Agazzi, et al., “A 90 nm CMOS DSP MLSD Transceiver With Integrated AFE for Electronic Dispersion Compensation ofMultimode Optical Fibers at 10 Gb/s,” JSSC, Dec. 2008, pp.2939-57

[9] “Will ADCs Overtake Binary Frontends in Backplane Signaling?” SE.3, 2009 ISSCC

[10] K. Poulton, et al., “A 20 GS/s 8 b ADC with a 1 MB memory in 0.18 μm CMOS”, 2003 ISSCC, pp 318-9

[11] A. Nazemi, et al., “A 10.3GS/s 6bit (5.1 ENOB at Nyquist) time-interleaved/pipelined ADC using open-loop amplifiers and digital calibration in 90nm CMOS”, 2008 VLSI Symp, pp. 18-9

[12] A. Varzaghani and C.-K. K. Yang, “A 4.8 GS/s 5-bit ADC-Based Receiver with Embedded DFE for Signal Equalization,” JSSC,March 2009 pp. 901 - 915

[12] P. Schvan, et al., “A 24GS/s 6b ADC in 90nm CMOS,” 2008 ISSCC, pp.544-5

[13] E.H Chen, et al., “Adaptation of CDR and Full Scale Range of ADC-Based SerDes Receiver”, 2009 VLSI Symp.

[14] S. Kasturia, H. J. Winters, “Techniques for High-Speed Implementation of Non-Linear Cancellation,” IEEE JSAC, Jun. 1991 pp. 711-7

[15] S. Park, et al., “A 3.5 GS/s 5-b Flash ADC in 90 nm CMOS,” 2006 CICC, pp. 489-92

References

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[16] S. Galal, B. Razavi, “40-Gb/s amplifier and ESD protection circuit in 0.18-μm CMOS technology”, JSSC, Dec. 2004, pp. 2389-96

[17] C.-K.K. Yang, et al., “A serial-link transceiver based on 8-GSamples/s A/D and D/A converters in 0.25-μm CMOS,” JSSC, Nov. 2001, pp.1684-92

[18] B. S. Leibowitz, et al., “A 7.5Gb/s 10-Tap DFE Receiver with First Tap Partial Response, Spectrally Gated Adaptation, and 2nd-Order Data-Filtered CDR,” 2007 ISSCC, pp. 228-9

[19] A. Varzaghani, C.K. Yang, “A 4-bit 6-GSa/s Time-Interleaved Pipelined A/D Converter with Embedded DFE for Serial-Link Receivers,” JSSC, April 2006, pp 935-44

[20] E. Alpman, et al., “A 1.1V 50mW 2.5GS/s 7b Time-Interleaved C-2C SAR ADC in 45nm LP Digital CMOS,” 2009 ISSCC, pp.76-7.

[21] Z. Cao, et al., “A 32mW 1.25GS/s 6b 2b/step SAR ADC in 0.13μm CMOS,” 2008 ISSCC, pp. 542-3

[22] E-H. Chen, et al., “Near-Optimal Equalizer and Timing Adaptation for I/O Links Using a BER-Based Metric,” JSSC,Sept. 2008, pp. 2144-56

[23] K.L. Wong, et al., “Edge and Data Adaptive Equalization of Serial-Link Transceivers“ JSSC, Sept. 2008, pp. 2157-69

[24] D. Sun, et al., “A 1 GHz CMOS analog front-end for a generalized PRML read channel,” JSSC, Nov. 2005 pp. 2275-85

[25] K. Mueller, M. Muller, “Timing Recovery in Digital Synchronous Data Receivers,” IEEE Trans. on Comm., May 1976 pp 516-31

[26] A. Emami-Neyestanak, et al., “CMOS transceiver with baud rate clock recovery for optical interconnects”, 2004 VLSI Symp, pp.

410-3

[27] F. Musa, A. Chan Carusone, “Modeling and Design of Multilevel Bang-bang CDRs in the Presence of ISI and Noise,’’ TCAS I, Oct. 2007 pp. 2137-47

[28] H. Noguchi, et al., “A 40Gb/s CDR with Adaptive Decision-Point control Using Eye-Opening Monitor Feedback”, 2008 ISSCC, 11.5, pp 228-9

[29] H.-M. Bae, et al., “An MLSE Receiver for Electronic Dispersion Compensation of OC192 Fiber Links,” JSSC, Nov. 2006 pp2541-55

[30] K. Bult, “The Effect of Technology Scaling on Power Dissipation in Analog

[31] C.K.K.Yang et.al “ADC-Based Serial I/O Receivers “ CICC 2009