Class D Power amplifier -----using ADS Song lin @utk June30

Class D Power amplifier-----using ADS

Song lin @utk June30

Outline

Why select Class D?Compare different deviceSimple Class D architectureLoad-pull to give out ZoutMatching and simulation results of ideal narrow band Class D PA Broad band matching

Why Class D?Class D PA works in the switching mode, with a square wave voltage and a half wave rectified sine wave of current. In its ideal switching mode,

when Vds<>0, Ids=0; when Ids<>0,Vds=0.

Class D PA can achieve very high frequency close to 100%. Although it is very nonlinear, we still can use the LINC technique to kill the IMD product.

Two kinds of Class D PA

Compare the device(I)

For high frequency, ----- the higher the betterFor high on/off switching speed,----- the shorter the betterFor high efficiency, the on-resistance of a switching device must be as low as possible to minimize the power dissipation in the switches during the positive half cycle.----- Rs is the smaller the better.For high Power output, ----- BV(beake down voltage)

the higher the betterFor high Gain, ----- the bigger the betterFor power dissipate,----- the small the better

maxf

mg

sdt

dsI

Compare the device(II)

Conclusion:

Also for the wide band application, we should chose the component whose Zout and Zin has very little variety in some frequency range.

I suggest to use the MRF282SR1.-----N-channel Enhancement-Mode Lateral MOSFETs

Basic Class D PA architecture

vout1

vds2

vds1

VD_FET1

Do not delete this port.




OutputPort

Sample Class DAmplifier

OutputBias Port

InputBias Port

InputPort

TF3TF2

T2=1.00T1=1.00

1

2

3

3

1-

T1

1-

T2

1

TF3TF1

T2=1.00T1=1.00

1

2

3

3

1-

T1

1-

T2

1SLCSLC1

C=1.750 pFL=20.0 nH

PortOutputNum=2

I_ProbeID_FET2

Statz_ModelGeneric_GaAsFet

Imelt=Trise=

I_ProbeID_FET1

PortOutBiasNum=4

PortInBiasNum=3

PortInputNum=1

CC3C=1.0 uF

GaAsFETFET2

Trise=Area=10

GaAsFETFET1

Trise=Area=10

CC4C=1.0 uF

Load Pull to give out Zout

vload

Vs_low Vs_high

Refer to the example design file: examples/RF_Board/LoadPull_prj/HB1Tone_LoadPull_eqns for details about how this simulation is run. Refer to the data display file"ReflectionCoefUtility" in the sameexample project for help in setting s11_rho and s11_center.

s11_rho is the radius and s11_center is thecenter of the circle.(But this is just a static drawing.)

One Tone Load Pull Simulation; output power and PAE found at each fundamental load impedance

Set Load and Source impedances atharmonic frequencies

Set these values:

Specify desired Fundamental Load Tuner coverage: s11_rho is the radius of the circle of reflection coefficients generated. However, the radius of the circle will be reduced if it would otherwise go outside the Smith Chart.s11_center is the center of the circle of generated reflection coefficientspts is the total number of reflection coefficients generatedZ0 is the system reference impedance

ClassDampX2

OutBiasInBias

OutputInput

VARSTIMULUS

Vlow=-2.7Vhigh=4.8RFfreq=850 MHzPavs=23 _dBm

EqnVar

P_1TonePORT1

Freq=RFfreqP=dbmtow(Pavs)Z=50 OhmNum=1

VARVAR3Z_s_fund=10

EqnVar

S1P_EqnS1S[1,1]=LoadTunerZ[1]=Z0

VARVAR2

Z_s_5 =10* Z0 + j*0Z_s_4 =10* Z0 + j*0Z_s_3 =10* Z0 + j*0Z_s_2 =10* Z0 + j*0Z_l_5 =10* Z0 + j*0Z_l_4 =10* Z0 + j*0Z_l_3 =10*Z0 + j*0Z_l_2 =10*Z0 + j*0

EqnVar

ParamSweepSweep1

PARAMETER SWEEP

VARImpedanceEquations

EqnVar

HarmonicBalanceHB1

Order[1]=9Freq[1]=RFfreq

HARMONIC BALANCE

I_ProbeIload

VARSweepEquations

Z0=50pts=100s11_center =-0.65 +j*0.0s11_rho =0.35

EqnVar

V_DCSRC1Vdc=Vhigh

V_DCSRC2Vdc=Vlow

LL2

R=L=1 uH

LL1

R=L=1 uH

I_ProbeIs_low I_Probe

Is_high

Statz_ModelFLC301XP

Imelt=Trise=

Narrow band input and output matching and simulation results

voad vout

Vs_low Vs_high

vin

Set these values:

ClassDampX2

OutBiasInBias

OutputInput

VARSTIMULUS

Vlow=-2.7Vhigh=4.8RFfreq=850 MHzPavs=14 _dBm

EqnVar

RR1R=50 Ohm

I_ProbeIs_high

I_ProbeIs_low

LL1

R=L=1 uH

LL2

R=L=1 uHV_DC

SRC2Vdc=Vlow

V_DCSRC1Vdc=Vhigh

I_ProbeIload

LL5

R=L=0.5 nH

LL3

R=L=1.2 nH

CC1C=21 pF

LL4

R=L=2.1 nH

OptionsOptions1

MaxWarnings=10GiveAllWarnings=yesI_AbsTol=1e-12 AI_RelTol=1e-6V_AbsTol=1e-6 VV_RelTol=1e-6TopologyCheck=yesTnom=25Temp=25

OPTIONS

CC2C=2.1 pFP_nTone

PORT1

P[1]=dbmtow(Pavs)Freq[1]=RFfreqZ=50 OhmNum=1

HarmonicBalanceHB1


HARMONIC BALANCE

ZinZin1Zin1=zin(S11,PortZ1)

Zin

N

TranTran1

MaxTimeStep=1 nsecStopTime=2 usec

TRANSIENT

VARSTIMULUS1

Max_IMD_order=7fspacing=1 MHz

EqnVar

Statz_ModelFLC301XP

Imelt=Trise=

0.5 1.0 1.5 2.00.0 2.5

-1.0

-0.5

0.0

0.5

1.0

-1.5

1.5

time, nsec

ts(v

in), V

0.5 1.0 1.5 2.00.0 2.5

-4

-2

0

2

4

-6

6

time, nsec

ts(v

oad)

, V

0.5 1.0 1.5 2.00.0 2.5

0

2

4

6

8

-2

10

time, nsec

ts(v

ds1)

, Vts

(ID

_FE

T1.

i), A

0.5 1.0 1.5 2.00.0 2.5

0

2

4

6

8

-2

10

time, nsec

ts(v

ds2)

, Vts

(ID

_FE

T2.

i), A

Wide band matching using coaxial


Zin

N

CC1C=3.0 pF

CC2C=24 pF

CC3C=1.1 pF

MLINTL1

L=675.0 milW=225.0 milSubst="MSub1"

MSUBMSub1

Rough=0 milTanD=0T=1.4 milHu=3.9e+034 milCond=1.0E+50Mur=1Er=2.5H=32 mil

MSub

S_ParamSP1

Step=50 MHzStop=0.6 GHzStart=0.03 GHz

S-PARAMETERS

TermTerm1

Z=50 OhmNum=1

TermTerm2

Z=50 OhmNum=2

freq30.00MHz80.00MHz130.0MHz180.0MHz230.0MHz280.0MHz330.0MHz380.0MHz430.0MHz480.0MHz530.0MHz580.0MHz600.0MHz

Zin112.879 + j1.50811.948 - j1.36210.330 - j1.8469.075 - j1.3208.380 - j0.3818.217 + j0.6128.497 + j1.4069.052 + j1.7669.545 + j1.5369.520 + j0.8578.775 + j0.2397.597 + j0.1177.105 + j0.224

A conventional design allows the coaxial transformer to transform the impedance to obtain a match the low end of the band, then add additional low-pass matching sections to lower the impedance at the upper band edge.

Using the MRF282S to simulate narrow band VMCD @300MHz

vout2 vload

Vs_low Vs_high

Specify desired Fundamental Load Tuner coverage: s11_rho is the radius of the circle of reflection coefficients generated. However, the radius of the circle will be reduced if it would otherwise go outside the Smith Chart.s11_center is the center of the circle of generated reflection coefficientspts is the total number of reflection coefficients generatedZ0 is the system reference impedance

Refer to the example design file: examples/RF_Board/LoadPull_prj/HB1Tone_LoadPull_eqns for details about how this simulation is run. Refer to the data display file"ReflectionCoefUtility" in the sameexample project for help in setting s11_rho and s11_center.

s11_rho is the radius and s11_center is thecenter of the circle.(But this is just a static drawing.)

One Tone Load Pull Simulation; output power and PAE found at each fundamental load impedance

Set Load and Source impedances atharmonic frequencies

Set these values:

ClassDampX2

OutBiasInBias

OutputInput

VARSTIMULUS

Vlow=3Vhigh=20RFfreq=300 MHzPavs=28 _dBm

EqnVar

HarmonicBalanceHB1


HARMONIC BALANCE

VARSweepEquations

Z0=50pts=100s11_center =-0.25 -j*0.03s11_rho =0.7

EqnVar

EqnMeas

FSL_TECH_INCLUDEFTI

FSL_TECH_INCLUDE

ParamSweepSweep1

PARAMETER SWEEP

VARImpedanceEquations

EqnVar

I_ProbeIload

VARVAR2

Z_s_5 =10* Z0 + j*0Z_s_4 =10* Z0 + j*0Z_s_3 =10* Z0 + j*0Z_s_2 =10* Z0 + j*0Z_s_fund =10 + j*0Z_l_5 =10* Z0 + j*0Z_l_4 =10* Z0 + j*0Z_l_3 =10*Z0 + j*0Z_l_2 =10*Z0 + j*0

EqnVar

V_DCSRC1Vdc=Vhigh

V_DCSRC2Vdc=Vlow

LL2

R=L=1 uH

LL1

R=L=1 uH

I_ProbeIs_low I_Probe

Is_high

CC1C=1.0 uF S1P_Eqn

S1S[1,1]=LoadTunerZ[1]=Z0

P_1TonePORT1

Freq=RFfreqP=dbmtow(Pavs)Z=Z_sNum=1

CC2C=1.0 uF

Push_pull structure

vout1

VD_FET1

vds2

vds1





OutputPort

Sample Class DAmplifier

OutputBias Port

InputBias Port

InputPort

SLCSLC1

C=14 pFL=20.0 nH

FSL_MRF_ROOT_MODELMRF1MODEL=MRF282S


TF3TF2

T2=1.00T1=1.00

1

2

3

3

1-

T1

1-

T2

1

TF3TF1

T2=1.00T1=1.00

1

2

3

3

1-

T1

1-

T2

1

PortOutputNum=2

I_ProbeID_FET2

I_ProbeID_FET1

PortOutBiasNum=4

PortInBiasNum=3

PortInputNum=1

CC3C=1.0 uF

CC4C=1.0 uF

Narrow band matching (input,

output)

Vs_high

vinvloadvout1

vds1

VD_FET1

Vs_low

vout

vds2


OutputBias Port

InputBias Port

InputPort

Set these values:

HarmonicBalanceHB1


HARMONIC BALANCE

V_DCSRC1Vdc=Vhigh

VARSTIMULUS

Vlow=5Vhigh=20RFfreq=300 MHzPavs=28 _dBm

EqnVar

LL4

R=L=6.4 nH

CC2C=36 pF

LL5

R=L=4.8 nH

LL3

R=L=8.7 nH

CC1C=30 pF

SLCSLC1

C=14 pFL=20 nH

OptionsOptions1

MaxWarnings=10GiveAllWarnings=yesI_AbsTol=1e-12 AI_RelTol=1e-6V_AbsTol=1e-6 VV_RelTol=1e-6TopologyCheck=yesTnom=25Temp=25

OPTIONS

P_nTonePORT1

P[1]=dbmtow(Pavs)Freq[1]=RFfreqZ=50 OhmNum=1


Zin

N

FSL_TECH_INCLUDEFTI

FSL_TECH_INCLUDE

LL1

R=L=1 uH

I_ProbeIs_high

V_DCSRC2Vdc=Vlow

LL2

R=L=1 uH

I_ProbeIs_low

I_ProbeIload

RR1R=50 Ohm

CC4C=1.0 uF

CC3C=1.0 uF

I_ProbeID_FET1

I_ProbeID_FET2

TF3TF1

T2=1.00T1=1.00

1

2

3

3

1-

T1

1-T2

1

TF3TF2

T2=1.00T1=1.00

1

2

3

31-

T1

1-T2

1



Narrow band simulation results

PAE78.833

Pdel_Watts36.194

Pdc45.112

Pdel_Watts/Pdc0.802

Eqn Pdel_dBm = 10*log10(Pdel_Watts)+30

Eqn Pavs_Watts=10**((28-30)/10)

Eqn Pdel_Watts=real(0.5*vout[1]*conj(Iload.i[1]))

Eqn PAE=100*(Pdel_Watts-Pavs_Watts)/Pdc

Eqn Is_h=exists("real(Is_high.i[0])")

Eqn Is_l=exists("real(Is_low.i[0])")

Eqn Vs_l=exists("real(Vs_low[0])")

Eqn Vs_h=exists("real(Vs_high[0])")

Eqn Pdc=Is_h*Vs_h +Is_l*Vs_l +1e-20

DC Power CalculationsThe exists() function checks to be surethe corresponding piece of data is in the dataset. If it is not, then the function returns 0.

Power Delivered and Power-AddedEfficiency Calculations

Pavs is the available source power, set onthe schematic, and passed into the datasetusing the Harmonic Balance controller.

1 2 3 4 5 60 7

0

10

20

30

40

-10

50

0

1

2

3

-1

4

time, nsec

ts(v

ds1

), V

ts(ID_FE

T1.i), A

1 2 3 4 5 60 7

0

10

20

30

40

-10

50

0

1

2

3

-1

4

time, nsec

ts(v

ds2

), V

ts(ID_FE

T2.i), A

Final schematic

vggvdd

Output

vd1

v2

v1

Reflect

Input

CC17C=1.5 pF

MSub

EqnVar

VARVAR2

ltout=2965 milltin=1630 milztout=45 Ohmztin=16 Ohmc2=2 pFc1=2783 pFr1=5 Ohm

Eqn

Var

LL12

R=L=0.35 nH

LL11

R=L=1.4304 nH

HARMONIC BALANCE

HarmonicBalanceHB2

Order[1]=3Freq[1]=0.3 GHz

HARMONIC BALANCE

I_P robeIout

I_P robeI_ds

EqnMeas

I_P robeI_P robe3



I_P robeI_P robe4

FSL_TECH_INCLUDEFTI

FSL_TECH_INCLUDE

VARVAR3

rs=15 Ohmls=19.5 nHcs=0.01 uF

EqnVar

I_P robeI_P robe2

I_P robeI_P robe1

Final simulation results(1)

RFfreq0.010000.030340.050690.071030.091380.111720.132070.152410.172760.193100.213450.233790.254140.274480.294830.315170.335520.355860.376210.396550.416900.437240.457590.477930.498280.518620.538970.55931

eta3.18477

19.1714926.6900733.8735738.0597340.5522152.8991561.1628863.5857865.0909069.3704071.5722474.1238973.8164771.2833972.0263276.8916476.9276375.8578578.1925980.0278379.8680479.4126580.3053782.4331183.1881381.6628280.91020

Pdc35.4236145.4257641.5319253.3718950.6750747.0099957.2424362.9260059.0168954.7549153.1365150.5148049.1444248.2410145.8544644.4901444.8106745.9219547.1437148.2536347.3848447.1146546.8049145.7738043.7890841.5784240.0780339.06156

Pdel_Watts1.128168.70879

11.0849018.0789619.2867919.0635930.2807638.4873537.5263535.6404736.8610136.1545736.4277635.6098132.6866132.0446134.4556635.3266735.7622137.7307737.9210637.6295537.1690236.7588236.0967034.5883132.7288531.60478

PAE-10.96363

8.1383814.6225524.4831028.1695229.8909244.1436353.1981755.0935155.9376259.9383361.6506463.9256463.4272360.3534360.7611965.7070866.0137465.2268067.8060869.4508769.2304368.7046469.3561570.9876271.1341169.1575368.07950

Gain-6.476232.399603.447305.571705.852555.801997.811618.853138.743328.519408.665658.581638.614348.515728.143748.057608.372668.481098.534318.767028.788878.755358.701868.653668.574718.389328.149327.99753

Final simulation results(2)

1 2 3 4 5 60 7

0

20

40

-20

60

-3

-2

-1

0

1

-4

2

time, nsec

ts(v

d1), V

ts(I_ds.i), A

eta73.76255

Pdc42.70324

Pdel_Watts31.49900

PAE62.02603

Gain7.98301

The problem remain:

1. The Class D PA need a resonator tank to pull out the fundamental signal, to filter out the third time signal, so I decide to divide the band into 3 parts, one from 30 to 88 MHz; 88MHz to 200MHz; 200MHz to 500MHz. We can separate the signals by filter bank.

2. For the real device, the Rs isn’t very small, so the efficiency can’t be so high. Because of the , the Vds and some overlap with Ids, it also kill some efficiency.

3. To achieve better performance at low frequency band, I have to increase the Vgg.

4. ADS is very hard to converge when simulation.

dst

Thank you!!!

Documents

Class D Power amplifier -----using ADS Song lin @utk June30