Class News - University of California, Berkeleykeutzer/classes/244fa2004/pdf/1-2-rtl-overview.pdfCourtesy Ravi Subramaniam demond and sync 8 Targeting an IC Implementation zSystem

1

EECS 244:Overview of

the IC Design Flow

Prof. Kurt KeutzerEECS

[email protected]

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Class News

Web page almost up – stay tuned!

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Important Class Dates

Project teams + topics (1 paragraph) due 9/13Full project proposals due 9/29Exam 1 Handed out 10/6Exam 1 collected at BEGINNING of class 10/11Preliminary project report due 11/1Exam 2 Handed out 11/3Exam 2 collected at BEGINNING of class 11/8

Final project presentations – between 12/6 and 12/8

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ApplicationMotivated by:

A bright ideaA market opportunity

An emerging market A high growth market

A technological breakthrough

For example - wireless telephony

5

Market Opportunity - World’s Cellular Subscribers

0

100

200

300

400

500

600

700

1993 1994 1995 1996 1997 1998 1999 2000 2001

Millions

Year

Digital

Analog

Source: Ericsson Radio Systems, Inc.

Will providea ubiquitousinfrastructurefor wirelessdata as well

as voice

6

SpecificationFunction, performance (power, delay, area), cost

A competitor’sIntegrated circuitData sheet

A napkinAn industry standard

For example, GSM standard for cellular telephony

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System Level Model: GSM SystemSystem model is organized into major components

A

D

digitaldownconv

900Mhz70Mhz

10.7Mhz

SH

SAW FILTER

RF IF

analog digital

digital receiver

40Ms/sec - 540ks/sec

MLSEViterbiEqlz.

270.8ks/secBB

phonebookphonebook

keypadintfc

protocolcontrol

de-intlViterbi

decoder

RPE-LTPspeechdecoder

speechquality

enhancement

voicerecognition

Courtesy Ravi Subramaniam

demondand sync

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Targeting an IC ImplementationSystem model is further refined to begin to think about physical implementation

A

D

digitaldownconv

900Mhz70Mhz

10.7Mhz

SH

SAW FILTER

RF IF

analog digital

digital receiver40Ms/sec - 540ks/sec

MLSEViterbiEqlz.

270.8ks/secBB

phonebookphonebook

keypadintfc

protocolcontrol

de-intlViterbi

decoder

RPE-LTPspeechdecoder

speechquality

enhancement

voicerecognition

Courtesy Ravi Subramaniam

demondand sync

DSP Core

uController

RAM

ASIC logic

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Mapping onto a system on a chip

RAM µCRAM

DSPCORE

ASICLOGIC

S/P

DMA

phonebook

protocol

keypadintfc

control

S/P

DMA

speechquality

enhancment

de-intl &decoder

voicerecognition

RPE-LTPspeech decoder

demodulatorand

synchronizerViterbi

equalizer

10

Full Wireless Phone Organization

C540

ARM7

11

A more complex design – SOC architecture

Courtesy Synopsys

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From specification to design entry

Design : specify and enter the design intent

Implement:refine the design through all phases

Verify:verify the correctness of design and implementation

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A more complex design – SOC architecture

Courtesy Synopsys

14

Current Practice: HDL at RTL Level

module foobar (q,clk,s,a,b);

input clk, s, a, b;

output q; reg q; reg d;

always @(a or b or s) // mux

begin

if( !s )

d = a;

else if( s )

d = b;

else

d = 'bx;

end // always @ (a or b or s)

always @(clk) // latch

begin

if( clk == 1 )

q = d;

else if( clk !== 0 )

q = 'bx;

end // always @ (clk)

endmodule

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An RTL description is always implicitly structural - the registers and their interconnectivity are defined

Thus the clock-to-clock behavior is defined

Only the control logic for the transfers is synthesized.

This approach can be enhanced:

Register inferencing

Automating resource allocation

+

+1

*RTL implies

b

c

a

d

e2

RTL level

a = b + c;d = a + 1;e = d * 2;

Behavioral implies

e = 2 * (b + c + 1)

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Verification




17

Design Verification

RTLSynthesis

HDL

netlist

logicoptimization

netlist

Library/modulegenerators

physicaldesign

layout

manualdesign

specification

Is the design

consistentwith the originalspecification?

Is what I think I wantwhat I really want?

18

Implementation Verification

RTLSynthesis

HDL

netlist

logicoptimization

netlist


physicaldesign

layout

manualdesign

Is the implementation

consistentwith the originaldesign intent?

Is what I implemented

what Iwanted?

a

b

s

q0

1

d

clk

a

b

s

q0

1

d

clk

19

Manufacture Verification (Test)

RTLSynthesis

HDL

netlist

logicoptimization

netlist


physicaldesign

layout

manualdesign

Is the manufactured

circuitconsistent

with the implemented

design?

Did theybuildwhat I

wanted?

a

b

s

q0

1

d

clk

a

b

s

q0

1

d

clk

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Formal verificationModel checking - prove properties relative to modelTheorem proving - prove properties of a circuit

Simulation Application of simulation stimulus to model of circuit

EmulationImplement a version of the circuit on emulator

Rapid prototyping Create a prototype of actual hardware

Approaches to Design Verification

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Simulationmodel

(HDL)

Simulationdriver

(vectors)

Simulationmonitor

(yes/no)

Software Simulation

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Types of software simulators

Circuit simulation Spice, Advice, Hspice Timemill + Ace, ADM

Event-driven gate/RTL/Behavioral simulationVerilog - VCS, NC-Verilog, Turbo-Verilog, Verilog-XLVHDL - VSS, MTI, Leapfrog

Cycle-based gate/RTL/Behavioral simulationVerilog - SpeedsimVHDL – Cyclone

Generic system-level simulation - SystemCDomain-specific simulation

SPW, COSSAP, Architecture-specific simulation

VAST, Axys, Lisatek

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Implementation




24

RTL Design Flow

RTLSynthesis

HDL

netlist

logicoptimization

netlist

Library

physicaldesign

layout

a

b

s

q0

1

d

clk

a

b

s

q0

1

d

clk

ModuleGenerators

ManualDesign

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Manual DesignPerformed at

Gate level (100 gates/week) /gate-level editorTransistor level (10 - 20 gates week)/tr level editor

Very expensive in design cost and design time -Used for:

AnalogLeaf cells - libraries, memory cellsDatapaths in high performance designs - DSP, microprocessor etc.

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Module Generators

Parameterized generators of actual physical layoutTypically used for:

Memories (word length, #words, # ports)Programmable logic arrays (PLA)Register files

Occasionally used for:MultipliersGeneral-purpose datapathDatapaths in high performance designs - DSP, microprocessors etc.

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Workhorse: RTL Synthesis Flow

RTLSynthesis

HDL

netlist

logicoptimization

netlist

Library

physicaldesign

layout

a

b

s

q0

1

d

clk

a

b

s

q0

1

d

clk

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Library

Contains for each cell:Functional information: cell = a *b * cTiming information: function of

input slewintrinsic delayoutput capacitance

non-linear models used in tabular approachPhysical footprint (area)Power characteristics

Wire-load models - function ofBlock sizeWiring

Library

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RTL Synthesis

module foobar (q,clk,s,a,b);input clk, s, a, b;output q; reg q; reg d;

always @(a or b or s) // mux

beginif(~s )

d = a;else if( s )

d = b;else

d = 'bx;end // always @ (a or b or s)

ab

s

q01

d

clk

RTLSynthesis

HDL

netlist

translate HDL source into netlist

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Logic Optimization

Perform a variety of transformations and optimizations

Structural graph transformationsBoolean transformationsMapping into a physical library

logicoptimization

netlist

netlist

pre-optimized smaller, fasterless power

Library

a

b

s

q0

1

d

clk

a

b

s

q0

1

d

clk

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Optimization Technologies

LOGIC EQUATIONS

TECHNOLOGY-INDEPENDENTOPTIMIZATION

FactoringCommonality Extraction

LIBRARYTECH-DEPENDENT OPTIMIZATION(MAPPING, TIMING)

OPTIMIZED LOGIC NETWORK

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Physical Design

Transform sequential circuit netlist into a physical circuit

place circuit componentsroute wirestransform into a mask

Or for FPGA’splace look-up tablesroute wires

physicaldesign

netlist

layout

netlist physical layout

Library

a

b

s

q0

1

d

clk

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Channeled and Channel lessRouting:

Channel based: Routing only in channels between gates (few metal layers: 2)

Channel less: Routing over gates(many metal layers: 3 - 6)

Often split in two steps:Global route:Find a coarse route depending on local routing densityDetailed route: Generate routing layout

Channel based Channel less

J. Christiansen,CERN - EP/MIC

[email protected]

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Channeled Gate Array

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Standard Cell Layout

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Channel less CellsArbitrary routing over cells

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Gordian Placement FlowJ. Kleinhaus, G. Sigl, F. Johannes, K. Antreich,GORDIAN: VLSI Placement by Quadratic

Programming and Slicing Optimization, IEEE Trans. on CAD, March, 1991, pp. 356 - 365

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a

b

s

q0

1

d

clk

Size and aspect ratio of core die

Netlist - >100K cells from library

Library, Netlist, and Aspect Ratio

39

Setting up Global Optimization

40

Resulting Layout

41

Partitioning

42

Layout after Min-cut

43

Final Placement

44

Slicing Tree

45

Other details - slotting constraints

Slotting constraints

A. E. Dunlop, B. W. Kernighan, A procedure for placement of standard-cell VLSI

circuits, IEEE Trans. on CAD, Vol. CAD-4, Jan , 1985, pp. 92- 98

46

Generating Final Placement

47

Standard Cell Layout

48

RoutingTo simplify routing problem, divide it into two phases

GlobalDetailed

Global routingDefine routing regionsAssign nets to regions

Detailed (Channel) routingRoute nets within each regionAssign nets to pins

49

Global Routing

Grid-Graph ModelChecker-Board Graph (also use slicing structure)

50

Channel Routing

Basic Terminology:

Fixed pin positions on top and bottom edges

Classical channel: no nets leave channel

Three-sided channel possible

channelpins

tracks end

via

trunk

net

1 1

1

branch

51

Maze Routing

Basic idea -- wave propagation method(Lee, 1961)

Breadth-first searchBack-tracing after finding the shortest pathguarantee to find the shortest path

4 3 2 3 4 5 6 7 8 9 10 11

3 2 1 2 3 4 5 6 7 8 9 10

2 1 A 1 5 6 7 8

3 2 1 2 6 7 8 9 10 11 12

4 3 2 3 12 13

5 4 3 4 14 B 13 14

6 5 13 14 14

7 6 7 11 12 13 14

8 7 8 9 10 11 12 13 14

9 8 9 10 11 12 13 14

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Followed by Two-Dimensional Compaction

X then Y 1D Compaction Y then X 1D Compaction

53

Placed and Routed Standard Cells

54

Another Final Placement

55

Re-visiting Verfication




56

Implementation Verification

RTLSynthesis

HDL

netlist

logicoptimization

netlist


physicaldesign

layout

manualdesign

Is the implementation

consistentwith the originaldesign intent?

Is what I implemented

what Iwanted?

a

b

s

q0

1

d

clk

a

b

s

q0

1

d

clk

57

Static Sign-off

RTLSynthesis

HDL

netlist

logicoptimization

netlist


physicaldesign

layout

manualdesign

a

b

s

q0

1

d

clk

a

b

s

q0

1

d

clk

ASICsignoff

Use static analysis techniques to verify:

functionality:• formal equivalence-checking techniques

and timing:• use static timing analysis

58

Manufacture Verification (Test)

RTLSynthesis

HDL

netlist

logicoptimization

netlist


physicaldesign

layout

manualdesign

Is the manufactured

circuitconsistent

with the implemented

design?

Did theybuildwhat I

wanted?

a

b

s

q0

1

d

clk

a

b

s

q0

1

d

clk

59

RAM µCRAM

DSPCORE

ASICLOGIC

S/P

DMA

Test Synthesis

Full-chip test requires:

JTAG 1149.1BIST

Partialscan

Full Scan

Fault simulationfor asynchronous

interfaces

60

Current Status of RTL Design FlowCurrent RTL design flow is able to produce

High speed microprocessors - e.g. Alpha, Pentium Pro > 1M gate-equivalents > 1GHz. (with intervention)System-on-a-chip/Systems on silicon

Integration of micro-p, DSP, memory and ASIC on a single die > 10M gate-equivalents >500MHz.

Rapid turnaround “Structured” ASICISSP-90 HIS from NEC~ 3M usable gates ~10 Mb SRAM; 10G SerDes

RTL Design flow now used for FPGA’s as wellRTL synthesis provided by independent vendors – e.g. Synplicity – as well as FPGA providers – e.g. XilinxPlace and route provided by FPGA vendors – e.g. Xilinx

Documents

Class News - University of California, Berkeleykeutzer/classes/244fa2004/pdf/1-2-rtl-overview.pdfCourtesy Ravi Subramaniam demond and sync 8 Targeting an IC Implementation zSystem