class.ece.uw.edu · Web viewAbstract 1. Introduction 1. Discussion of Project 1. Design Specification 1. Design Procedure 1. Software - uClinux 1. Software - Test Application 2

Table of ContentsAbstract............................................................................................................................................1

Introduction......................................................................................................................................1

Discussion of Project.......................................................................................................................1Design Specification............................................................................................................1Design Procedure.................................................................................................................1

Software - uClinux...................................................................................................1Software - Test Application.....................................................................................2Hardware..................................................................................................................2

System Description..............................................................................................................2Software Implementation.....................................................................................................3

uClinux.....................................................................................................................3Test Application.......................................................................................................4Bootloader................................................................................................................4Flash Driver.............................................................................................................5Linker Script............................................................................................................5

Hardware Implementation...................................................................................................5Instruction and Data Cache......................................................................................6Microblaze System Clock Speed.............................................................................6

Problems Encountered.....................................................................................................................6uClinux CVS Tree Divergence............................................................................................6Xilinx Platform Studio & EDK Upgrade.............................................................................6Long Kernel Image Download Time...................................................................................7BSB *.xbd Bugs...................................................................................................................7Creating a Group Workspace...............................................................................................7Departmental Windows Workstations.................................................................................8

Analysis of Errors............................................................................................................................8Clock Speed Mismatch........................................................................................................8Test Application Hangs........................................................................................................9

Test plan...........................................................................................................................................9uClinux.................................................................................................................................9Test Application...................................................................................................................9Hardware..............................................................................................................................9

Presentation, Discussion, and Analysis of Results..........................................................................9

Summary & Conclusion.................................................................................................................10

Appendix A: XPS Hardware Configuration Files.........................................................................11Full Flash Source / No Cache in Use.................................................................................11

LATS_TestBed.ucf................................................................................................11LATS_TestBed.mhs...............................................................................................13LATS_TestBed.mss...............................................................................................19

Limited Flash Source / I and D Cache in Use....................................................................21

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LATS_TestBed.ucf................................................................................................21LATS_TestBed.mhs...............................................................................................23LATS_TestBed.mss...............................................................................................29

Appendix B: Software Source.......................................................................................................31uClinux Kernel Configuration...........................................................................................31

No Cache Enabled: .config (uClinux-dist/linux-2.4.x/.config)..............................31Cache Enabled: .config (uClinux-dist/linux-2.4.x/.config)...................................38

Flash Source.......................................................................................................................45Flash.C...................................................................................................................45Flash.h....................................................................................................................63

Bootloader Source..............................................................................................................65Linker Source.....................................................................................................................74Test Application Source: by Jeremy Connor.....................................................................76

Appendix C: Project Setup Tutorial...............................................................................................78

Appendix D: Using Instruction and Data Cache Tutorial..............................................................79

Appendix E: Microblaze System Clock Speed-up Tutorial...........................................................81

Appendix F: Implementing uClinux with Custom Applications...................................................83

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Table of FiguresFigure 1 LATS System Architecture Diagram................................................................................3Figure 2 Bootloader Menu...............................................................................................................4Figure 3 Flash Code Reduction Source...........................................................................................5

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ABSTRACTThis lab report discusses the creation of a Microblaze softcore CPU-based system on a

NuHorizons Spartan-3 development board. This CPU runs an implementation of uClinux, custom-compiled for the Microblaze hardware environment. We employ and test functionality of not only the over-arching uClinux system, but also the uClinux bootloader, UART communication systems, CPU data and instruction cache, and SRAM and flash memory as both storage devices and as file systems. The end result is a functionally basic uClinux standalone system with many paths for future development.

INTRODUCTION This report goes through the inner workings of the Local Area Tracking System (LATS)

control unit and should serve as a sort of how-to to construct it from the ground up. It runs uClinux on a NuHorizons Spartan3-based FPGA Development Board, and the parts that work do so pretty well. To help someone reading this report replicate the work described, several detailed tutorials are included as appendices that should serve as nearly standalone documents to completely re-create the system.

The purpose of this project was twofold: one, to make a control system for the LATS, and two, to learn about FPGA development and the uClinux Linux distribution. We used the latest versions of uClinux available from the uclinux.org compiled on RedHat 8.0 & RedHat Enterprise Linux 3 systems, the aforementioned dev board, and Xilinx Project Studio 6.2 (with EDK 6.2) and included tools like iMPACT running on Windows 2000 & XP systems.

DISCUSSION OF PROJECT

Design SpecificationThe uClinux OS will control most peripherals on the NuHorizons Spartan 3 development

board, including LED’s, UART’s, LCD, Flash memory, SDRAM. The implementation of uClinux will be able to interact with other PCs via RS232, accepting input and providing output. The OS will also be able to add new input and output paths to the maximum capacity of the development board. The uClinux kernel and boot loader will be able to reside on the Flash memory, thus allowing the OS to boot from a local memory system (Flash) instead of relying on re-download of OS on power cycle.

The principal job of the OS will be to mediate the interaction of all the components in the system (including user interface, display, networking, and communication components) and to orchestrate safe handling of shared memory resources. This is critical to proper system operation.

Design Procedure

Software - uClinuxWhile investigating possible operating systems to control the LATS, several were

investigated but uClinux stood out for the same reasons Linux typically does: it’s free, open-source, and has a huge support network. Fortunately, uClinux was designed for us ahead of time, and the only changes made in it were those necessary for it to function with hardware. This

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included modifying the kernel configuration. Two example configurations can be found in the appendices.

Software - Test ApplicationDesign of the test application was very quick and straightforward – all that was needed

was a function to demonstrate some measure of hardware interaction while inside the uClinux system. Fortunately, a program like this already existed in Jeremy Connor’s Microblaze tutorial (see Appendix B: Software Source, Test Application Source: by Jeremy Connor). All that was necessary was to update the code to work within Xilinx EDK 6.2 and integrate it into the uClinux image.

HardwareThe hardware for this project was set up using the Base System Builder and then was

modified to meet our needs. These modifications came in the form of bug fixes, cache enabling, and processor speedup, all of which will be discussed in more detail later. For a detailed description of the hardware setup process using the BSB, see Appendix C: Project Setup Tutorial. Our first step was to set up the hardware project using the BSB. Then, we took the bootloader source that was provided in the mbvanilla_net distribution (see Appendix F: Implementing uClinux with Custom Applications) and modified it to work with our board configuration. This included changing base addresses of system components and integrating a new flash driver. The bootloader and new flash source can be found in the appendices, as also can found our project configuration files. These source files were compiled to work on the MicroblazeTM soft-core processor and function as our means to directing the processor to our kernel image. Thus, we can boot our image and run our applications.

System DescriptionThe system configuration for the LATS is similar to the diagram shown in Figure 1

below. The command and control center for the system is the uClinux OS, which runs on a Spartan 3 FPGA. This OS mediates the interaction between the rest of the system components, which include:

UI interface

VGA interface

Network Protocol

UWB communication interface (RF for now)

Math unit—for matrix manipulation

LCD

RS232 communication interface

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Figure 1 LATS System Architecture Diagram

Software Implementation

uClinuxThe LATS control unit runs uClinux (uclinux.org), a miniaturized version of Linux ported to

more than ten microcontroller architectures. No code modifications were necessary to make a functional system, though additional drivers had to be added and a few Xilinx libraries were required to compile. As such, the final code used for the uClinux system is identical to that which is available via CVS through uclinux.org; it has been customized only through compile options, described below.

The uClinux kernel options consisted of matching kernel options with what has been built in the hardware platform, described in the next section. Portions of the kernel options changed consisted of:

Processor Type and Features – CPU speed, cache, hardware math coprocessor abilities, core drivers

Memory Technology Devices, Flash Drivers – Support for RAM and ROM chips, AMD brand, ST brand

Memory Technology Devices, Mapping Drivers – CFI Flash Size 4MB

All other settings were left at their defaults. In distribution build options, only the test application was added; all others were left at their defaults. The uClinux image was built from this configuration to form the software system.

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Once the previously-discussed bootloader hands control to uClinux system in RAM (or copies the system from flash memory to RAM and then hands over control), uClinux boots and creates a ramdisk, expanding the filesystem built in a file called “romfs.img,” included in the uClinux image, inside. Once this is accomplished, the system prints the message of the day and presents a command prompt and awaits further instructions.

Test ApplicationThe test application is a direct copy of Jeremy Connor’s sample Microblaze test code

integrated into the uClinux image – this code is replicated in Appendix B: Software Source, section Test Application Source: by Jeremy Connor. The code consists of a simple button register read and resultant LED register write, where a while loop executes indefinitely watching for a button press which then causes an LED to blink, and is meant to be a simple uClinux hardware interaction test. The functions used to accomplish this are standard Microblaze function calls written by Xilinx for use with their FPGA cores.

BootloaderOnce the uClinux image has been downloaded to the target the bootloader can be used to

select the memory space from which to boot the kernel. When our bootloader is launched, the user sees the menu in Figure 2 in their Hypertermal window.

Figure 2 Bootloader Menu

The result of selecting each of these choices is self-explanatory. If the image download process has been followed as explained in the previous section, the kernel will currently reside at the beginning of SDRAM space (0x80000000). At this bootloader prompt, selecting 2 will set the program counter to address 0x80000000 and thus the uClinux kernel will boot. The user will notice that the image download time is quite long; therefore it is desirable to write a working kernel image to flash in order to avoid having to re-download the image every time the power is cycled. The bootloader is smart enough to prompt the user as to what order things must be done. For example, if 1 is entered before the flash has been erased and written to, the bootloader will inform the user that the Flash needs to be written to and erased first. The procedure to write and execute an image from flash is to enter 3 to erase the flash, 4 to copy the image from RAM to Flash, then 1 to execute the image. We are only dealing with 1 flash slot so, when prompted, the user must choose to operate on this slot. Currently, entering 5 does nothing and this option will be removed from the project for future use.

The bootloader code was taken from the mbvanilla distribution (see Appendix F: Implementing uClinux with Custom Applications, Introduction) and modified to work with our project. In fact, the only useful source code from mbvanilla was the bootloader.c since we had

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to get our own flash driver and make it all work with our hardware, which is different from the default mbvanilla hardware.

Flash DriverThe flash driver is responsible for all read/write/erase interaction with the flash chip. The

driver that came with the mbvanilla hardware project does not work for our flash chip. Therefore, we had to find another driver. Free driver source was obtained from the STMicroelectronics website (www.st.com). We used this source and integrated it into our project, removing unneeded code to save memory space. Because of the BRAM requirements for data and instruction caching (see sections Instruction and Data Cache and Appendix D: UsingInstruction and Data Cache Tutorial ), it was necessary to reduce code size as much as possible. The flash source is only necessary for reading and writing to flash. Once we have a working image in flash, we no longer need this driver code. Therefore, we used the following preprocessor directive structure in order to strip out any unnecessary flash driver code.

Figure 3 Flash Code Reduction Source

The USING_FLASH flag is defined or undefined in flash.h. The code size with flash source included is 0x28C1. When the flash source is compiled out, the code size is reduced to 0x1879. This is important because the BRAM allocation for MicroblazeTM source can only be 8KB, 16KB, or 32KB. Thus, by reducing our code size by just 0x1000 (4KB), we really reduce BRAM usage from 16KB down to 8KB and thus allow us the option of using instruction and data cache.

Linker ScriptWhen using the BSB, the source file TestApp\src\TestApp.c is created along with a linker

script, TestApp\src\TestAppLinkScr. This script designates where the different parts of the .elf file will be stored. It allows for a text, data, and stack section. The linker script that we used can be found in Appendix B: Software Source. When the XPS gives an error indicating that one section overlaps another or that the ilmb_cntlr is full, that means that the ilmb_cntlr space is too small. This file is useful for knowing how the source will be stored in the .elf.

Hardware ImplementationWe chose the NuHorizons, Spartan 3 FPGA development board for our project. This

board has the Spartan 3 FPGA and, as peripherals to the FPGA, has a 4MB flash chip, 8MB SDRAM chip, UART, JTAG, LCD, 8 LED’s, ADC, DAC, 3 push buttons, PS2 port, and 20 I/O pins. We used the Xilinx, XPS EDK software to configure the FPGA to work with all these peripherals except for the ADC, DAC, and PS2 port. The Base System Builder (BSB) was used to configure a default project to control all the hardware. The project was then modified to fix BSB setup bugs. See Appendix A: XPS Hardware Configuration Files for the hardware configuration source files. In order to use these source files to duplicate our project settings see Appendix C: Project Setup Tutorial.

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http://www.st.com/

Instruction and Data CacheDuring the uClinux boot process a calculation is performed in the kernel Calibration

Delay Loop which results in some number measured in BogoMips. A Google search to http://www.hyperdictionary.com/computing/bogomips yields the explanation, “A BogoMips is an unscientific measurement of processor speed made by the Linux kernel when it boots, to calibrate an internal busy-loop.” Although is a pseudo measure of processor speed, we like to pay attention to it to get some idea of how fast things are running when we boot uClinux. With our first successful uClinux boot with no caching enable, and at 50MHz processor speed, we were running at 1.92 BogoMips. When we successfully enabled the Instruction (I) and Data (D) Cache we increased to 24.49 BogoMips. This was a significant and very noticeable speedup. Of course, with the entry of D and I caching came the exit of a lot of BRAM which was needed for storing the bootloader source code (see Appendix D: Using Instruction and Data Cache Tutorial). It was therefore necessary to decrease the bootloader and flash driver code size, as was explained previously (see the Flash Driver section). As suggested by the speedup figures, it is very much worthwhile to minimize other source code so that there is room to enable caching. After reducing the code size and enabling cache, the user MUST go into Project->Add/Edit Cores->Peripherals and change the ilmb_cntlr and dlmb_cntlr space to go from 0x00000000 to 0x00001FFF. Otherwise, you will over map your BRAM and get very frustrated.

Microblaze System Clock SpeedFirst of all, it is a good idea to get everything working with the 50 MHz clock first, which

we did. After that, it was our goal to optimize and speed everything up as fast as possible. We attempted to speed up our system clock from the default of 50 MHz to 80 MHz. We were successful in speeding up the clock and we were able to boot the kernel at 39.62 BogoMips from the SDRAM. We did have some interesting issues come up with trying to boot the image from Flash. This issue will be discussed in the Problems Encountered section. A full tutorial on increasing clock speed can be found in Appendix E: Microblaze System Clock Speed-up Tutorial.

PROBLEMS ENCOUNTERED

uClinux CVS Tree DivergenceFor one reason or another, both kernel and distribution uClinux code trees would, with

regular update, quickly deviate from what the most up to date copy should be – even when using the CVS prune option to delete files purged from the repository. Two freshly-pruned CVS trees residing on different computers had only partially-overlapping sets of libraries included, as a small example. Deleting the trees and re-downloading them solved the problem (of course, other problems resulted from the fact that code had been updated), but required much more time to complete than a simple CVS update took.

Xilinx Platform Studio & EDK UpgradeMoving from version 6.1 to 6.2 of both XPS and the EDK partway through the quarter

caused several delays. While having versions to match John Williams’s mbvanilla_net example hardware platform was beneficial in some ways, heavy modification were required to that example anyway to make things function with our NuHorizons board, so the upgrade wasn’t

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http://www.hyperdictionary.com/dictionary/busy-loop

http://www.hyperdictionary.com/dictionary/boots

http://www.hyperdictionary.com/dictionary/kernel

http://www.hyperdictionary.com/dictionary/Linux

http://www.hyperdictionary.com/dictionary/processor

http://www.hyperdictionary.com/computing/bogomips

entirely essential. Upgrading XPS necessitated a revision of Jeremy Connor’s Microblaze tutorial, and upgrading the EDK changed FPGA core versions, causing problems. The psychological aspect of the upgrade had an impact as well – true progress was impeded for some time while the class held its breath waiting for the software to arrive and be installed.

Long Kernel Image Download TimeUnfortunately, this is just the way it is. It usually took about 20 minutes or so for our

image to download to the SDRAM. I’m not really sure why it takes so long, but this is really good motivation for getting the flash to work and storing your image there so you only have to download once!

BSB *.xbd BugsThe Base System Builder (BSB) is very useful insetting up default XPS projects that are

able to control all the development board peripherals. The *.xbd file that is used by the BSB is a complimentary file provided by the development board manufacturer. Since they are the ones who designed the board, they know best where all pins should be configured to make things work. However, it is a monumental mistake to assume that they have actually tested their file to make sure that everything works. In our case, we found that a couple of the SDRAM pins were not connected and, therefore, we were not able to interact with the SDRAM until we figured that out and fixed the problem.

The BSB should set most of what you need up here and everything should work fine. However, we have noticed a problem with the BSB file and, since I don’t know if the NuHorizons folks have fixed this error yet, this is worth mentioning.

Assuming you asked BSB to set up SDRAM, go to Project->Add/Edit Cores->Ports and make sure that SDRAM_DQM is in your port list. This is important, as the SDRAM will not work without it! If it is not there, go to the explorer window on the right, select it and add it to your port list.

Now, go to your *.ucf file and make sure the following lines are in there somewhere:Net SDRAM_4Mx16_SDRAM_DQM<1> LOC=P15;Net SDRAM_4Mx16_SDRAM_DQM<0> LOC=P40;

If they’re not there, you need to add them. These pins are for the digital clock manager, which is VERY IMPORTANT!

Creating a Group WorkspaceBuilding a server for the class to do their work had been done already, but the matter of

configuring it suitably took too long. Unfortunately, creation of the ideal environment – one which could interact with the department’s resources to make everything really useful – threatened to absorb a sizable portion of the quarter, and the current isolated form was what resulted. The primary problem encountered with departmental interaction was the task of using Kerberos-authenticated user logins, and using the department’s LDAP records to get groups associated with each user. From there, it would have been easy to set proper permissions for all files, restrict those allowed to log in to those in the class group, and use this system for future

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classes. Departmental home directories (the 500MB available to each student) would have been accessible as well. Kerberos tickets were working, and once a user had a Kerberos ticket LDAP searches were possible, but login was impossible because, even though LDAP was listed first in authentication priority, the EE590 server did not perform an LDAP lookup when authenticating a username and password. Local accounts were created to deal with this, but using a home directory served from the department was not possible with this solution in place.

Outside of authentication and access issues, the current group server’s disk space is inadequate. One complete CVS tree requires over 1GB of space, and we barely have room for one on the current server. For true uClinux development to occur, each student requires his or her own copy, with custom kernel configurations and integrated code in various stages of progression. There must also be space for a master copy of the code tree; since they diverge, this centrally-accessible master would be deleted and re-created periodically for all students to pull from.

Departmental Windows WorkstationsTwo problems resulted from using Windows workstations managed by the department.

Firstly, a new workstation management utility employed by the department, DeepFreeze, would periodically restore the hard disk to a freshly-installed state, obliterating our work in the process. Fortunately, this was rectified early in the quarter.

Secondly, the amount of low-level hardware control required by the Xilinx development tools proved too low for a user of access level “User”, or too low for Windows XP itself. Without Administrator-level control, a user could not launch iMPACT (it crashes) to download a compiled hardware platform to their development board. All students in the ee590 LDAP group were given Administrator access on the three 590 PCs to solve this problem. This solved the FPGA development problem, but further issues arose – and still persist – when trying to download a uClinux image to the development board. The communication link from PC to dev board via the parallel JTAG, while using XMD to download the uClinux image, masquerades as a network connection. As a result, Windows XP firewall blocks the connection; fortunately the block is only for incoming data so the image can be sent out, but this block could contribute to the very low transfer speeds (~900 baud) experienced.

ANALYSIS OF ERRORS

Clock Speed MismatchThe only real error that we are still experiencing from the hardware side of things is that

fact that we have not been able to consistently get the flash chip to operate at the increased system clock speed of 80 MHz. All is well at 50 MHz, but it is possible that the flash chip is simply not able to operate that fast. The first time we tried to run it at that (80 MHz) speed, everything worked, although it didn’t seem like things should because we forgot to increase the clock speed setting in the flash and SDRAM core parameters. This means that the clock was operating at 80 MHz but the flash and SDRAM chips though they were operating at 50 MHz. It is possible for these chips to function at times with this mismatch, but it certainly is not reliable and, sure enough, it does not always work. The next step to fixing this will be to find the manufacturer specification on the flash chip to find out what the maximum clock speed is.

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Test Application HangsBeing based on a while(1) loop, it’s no surprise that the test application indefinitely runs,

but its lack of responsiveness is still unfortunate. The fact that its execution doesn’t cause a kernel panic or other such serious error, and can be killed using Ctrl+C, means that the code inside is viable for a uClinux environment. The plan to continue pursuing this problem is to disassemble the test application into its core parts, and verify that each Xilinx function call works as it should while printing debug messages to the uClinux console. One possible reason for the hang is a power struggle over the UART; because uClinux is constantly occupying it for its shell, the UART output commands probably clash with uClinux.

TEST PLAN

uClinuxTesting uClinux’s functionality consists of a straightforward verification of the filesystem

and responsiveness. After selecting the appropriate option from the bootloader, the system should boot through a suite of standard startup routines, expand the filesystem, print the uClinux logo, and present a console for interaction with the system. Typing alphanumeric characters should result in them being echoed back to you – this verifies basic UART input/output functionality of the system. Using Linux cd and ls commands, verify the presence of those applications compiled into the uClinux image in the /bin directory. Type ps -ef at the command prompt to ensure Linux processes are running and the system is active.

Test ApplicationOnce the uClinux system is booted to a command prompt, execute /bin/foo – the test

application. In an ideal world, it should turn an LED on and off and print to the screen via the UART in response to a button on the NuHorizons development board. Additionally, it should observe all usual program politeness: should not crash the system, exit with Ctrl+C, and respond to the “kill” command.

HardwareWe download the hardware configuration bit stream to the target and run some diagnostic

code to make sure everything is working. This includes reading and writing to the SDRAM and Flash, printing to the LCD, writing text to the UART which appears in a HyperTerminal session, and making the 8 LED’s blink. The diagnostics source can be found in Appendix B: Software Source.

PRESENTATION, DISCUSSION, AND ANALYSIS OF RESULTSAs our current system stands, a basic uClinux kernel and distribution will function well

on a custom-built FPGA hardware implementation based on John Williams’s (http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux/) example mbvanilla_net platform (Appendix F: Implementing uClinux with Custom Applications, Introduction). The hardware includes a Microblaze CPU, cache, flash memory capabilities and runs uClinux with high speed and responsiveness. Of course, there’s still a lot to do.

We successfully implemented a hardware configuration that boots uClinux and allows user interaction via a HyperTerminal session. The uClinux kernel runs of either flash or

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http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux/

SDRAM, as we desired. We are also able to control all peripherals from the MicroblazeTM side and continue to work on making uClinux control everything, effectively bypassing all MicroblazeTM code.

The next step from the hardware aspect will be to continue to work on increasing the system clock for better performance. Now that uClinux works, there still remains the issue of making it into a custom embedded system. The first direction to head is to improve hardware interaction and control through the exploration of Microblaze code to interact with hardware and, if needed, the implementation of drivers. Once basic hardware control can be established, the next step is to integrate this system with each core and system necessary to fully realize the LATS: networking, communication, display, and alternative methods of input. From this basic tool set, the control program can then be written to oversee data acquisition, processing, and display subsystems to accomplish the goals the LATS was originally created to accomplish.

SUMMARY & CONCLUSIONAfter a standard progression of research, investigation, design, prototyping, and

debugging, the FPGA hardware and basic uClinux operating system work together. While the project is still some distance to completion, much has already been accomplished in creating a starting ground for future students to build on. Hopefully, with the information contained in this document, students will be able to quickly learn from the discussed mistakes and problems, quickly come up to speed with uClinux and hardware platform design, and build more exciting projects out of this base framework. Much learning on the part of the authors has occurred not only in the technical aspects of design but also project management on a scale never previously experienced.

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APPENDIX A: XPS HARDWARE CONFIGURATION FILES

Full Flash Source / No Cache in Use

LATS_TestBed.ucfNet sys_clk PERIOD = 20000 ps;Net RS232_RX LOC=P87;Net RS232_TX LOC=P85;Net LEDs_8Bit_GPIO_d_out<0> LOC=P161;Net LEDs_8Bit_GPIO_d_out<1> LOC=P162;Net LEDs_8Bit_GPIO_d_out<2> LOC=P165;Net LEDs_8Bit_GPIO_d_out<3> LOC=P166;Net LEDs_8Bit_GPIO_d_out<4> LOC=P167;Net LEDs_8Bit_GPIO_d_out<5> LOC=P168;Net LEDs_8Bit_GPIO_d_out<6> LOC=P169;Net LEDs_8Bit_GPIO_d_out<7> LOC=P171;Net Push_Buttons_2Bit_GPIO_in<0> LOC=P64;Net Push_Buttons_2Bit_GPIO_in<1> LOC=P62;Net LCDDISPLAY_12Bit_GPIO_d_out<11> LOC=P152;Net LCDDISPLAY_12Bit_GPIO_d_out<10> LOC=P150;Net LCDDISPLAY_12Bit_GPIO_d_out<9> LOC=P149;Net LCDDISPLAY_12Bit_GPIO_d_out<8> LOC=P148;Net LCDDISPLAY_12Bit_GPIO_d_out<7> LOC=P147;Net LCDDISPLAY_12Bit_GPIO_d_out<6> LOC=P146;Net LCDDISPLAY_12Bit_GPIO_d_out<5> LOC=P144;Net LCDDISPLAY_12Bit_GPIO_d_out<4> LOC=P143;Net LCDDISPLAY_12Bit_GPIO_d_out<3> LOC=P156;Net LCDDISPLAY_12Bit_GPIO_d_out<2> LOC=P154;Net LCDDISPLAY_12Bit_GPIO_d_out<1> LOC=P155;Net LCDDISPLAY_12Bit_GPIO_d_out<0> LOC=P141;Net SDRAM_4Mx16_SDRAM_DQ<15> LOC=P4;Net SDRAM_4Mx16_SDRAM_DQ<14> LOC=P5;Net SDRAM_4Mx16_SDRAM_DQ<13> LOC=P7;Net SDRAM_4Mx16_SDRAM_DQ<12> LOC=P9;Net SDRAM_4Mx16_SDRAM_DQ<11> LOC=P10;Net SDRAM_4Mx16_SDRAM_DQ<10> LOC=P11;Net SDRAM_4Mx16_SDRAM_DQ<9> LOC=P12;Net SDRAM_4Mx16_SDRAM_DQ<8> LOC=P13;Net SDRAM_4Mx16_SDRAM_DQ<7> LOC=P39;Net SDRAM_4Mx16_SDRAM_DQ<6> LOC=P37;Net SDRAM_4Mx16_SDRAM_DQ<5> LOC=P36;Net SDRAM_4Mx16_SDRAM_DQ<4> LOC=P35;Net SDRAM_4Mx16_SDRAM_DQ<3> LOC=P26;Net SDRAM_4Mx16_SDRAM_DQ<2> LOC=P24;Net SDRAM_4Mx16_SDRAM_DQ<1> LOC=P22;Net SDRAM_4Mx16_SDRAM_DQ<0> LOC=P21;Net SDRAM_4Mx16_SDRAM_Addr<11> LOC=P29;Net SDRAM_4Mx16_SDRAM_Addr<10> LOC=P31;Net SDRAM_4Mx16_SDRAM_Addr<9> LOC=P33;Net SDRAM_4Mx16_SDRAM_Addr<8> LOC=P34;Net SDRAM_4Mx16_SDRAM_Addr<7> LOC=P57;Net SDRAM_4Mx16_SDRAM_Addr<6> LOC=P50;Net SDRAM_4Mx16_SDRAM_Addr<5> LOC=P48;Net SDRAM_4Mx16_SDRAM_Addr<4> LOC=P46;

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Net SDRAM_4Mx16_SDRAM_Addr<3> LOC=P45;Net SDRAM_4Mx16_SDRAM_Addr<2> LOC=P44;Net SDRAM_4Mx16_SDRAM_Addr<1> LOC=P28;Net SDRAM_4Mx16_SDRAM_Addr<0> LOC=P27;Net SDRAM_4Mx16_SDRAM_WEn LOC=P16;Net SDRAM_4Mx16_SDRAM_CKE LOC=P43;Net SDRAM_4Mx16_SDRAM_CSn LOC=P20;Net SDRAM_4Mx16_SDRAM_CASn LOC=P18;Net SDRAM_4Mx16_SDRAM_RASn LOC=P19;Net SDRAM_4Mx16_SDRAM_Clk LOC=P42;Net SDRAM_4Mx16_SDRAM_BankAddr<1> LOC=P61;Net SDRAM_4Mx16_SDRAM_BankAddr<0> LOC=P58;Net SDRAM_4Mx16_SDRAM_DQM<1> LOC=P15;Net SDRAM_4Mx16_SDRAM_DQM<0> LOC=P40;Net FLASH_Mem_A<31> LOC=P175;Net FLASH_Mem_A<30> LOC=P93;Net FLASH_Mem_A<29> LOC=P113;Net FLASH_Mem_A<28> LOC=P111;Net FLASH_Mem_A<27> LOC=P114;Net FLASH_Mem_A<26> LOC=P115;Net FLASH_Mem_A<25> LOC=P116;Net FLASH_Mem_A<24> LOC=P117;Net FLASH_Mem_A<23> LOC=P119;Net FLASH_Mem_A<22> LOC=P131;Net FLASH_Mem_A<21> LOC=P132;Net FLASH_Mem_A<20> LOC=P133;Net FLASH_Mem_A<19> LOC=P135;Net FLASH_Mem_A<18> LOC=P137;Net FLASH_Mem_A<17> LOC=P138;Net FLASH_Mem_A<16> LOC=P139;Net FLASH_Mem_A<15> LOC=P140;Net FLASH_Mem_A<14> LOC=P109;Net FLASH_Mem_A<13> LOC=P120;Net FLASH_Mem_A<12> LOC=P122;Net FLASH_Mem_A<11> LOC=P130;Net FLASH_Mem_A<10> LOC=P128;Net FLASH_Mem_DQ<7> LOC=P96;Net FLASH_Mem_DQ<6> LOC=P97;Net FLASH_Mem_DQ<5> LOC=P100;Net FLASH_Mem_DQ<4> LOC=P101;Net FLASH_Mem_DQ<3> LOC=P102;Net FLASH_Mem_DQ<2> LOC=P106;Net FLASH_Mem_DQ<1> LOC=P107;Net FLASH_Mem_DQ<0> LOC=P108;Net FLASH_Mem_WEN LOC=P126;Net FLASH_Mem_OEN LOC=P95;Net FLASH_Mem_CEN LOC=P94;Net FLASH_Mem_RPN LOC=P125;Net sys_clk LOC=P80;Net sys_rst LOC=P63;

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LATS_TestBed.mhs# ############################################################################### Created by Base System Builder Wizard for Xilinx EDK 6.2 Build EDK_Gm.11# Wed Nov 10 11:37:34 2004# Target Board: Nu Horizons Spartan-III 400 Evaluation Board Rev 1# Family: spartan3# Device: XC3S400# Package: PQ208# Speed Grade: -4# Processor: Microblaze# System clock frequency: 50 MHz# Debug interface: On-Chip HW Debug Module# Data Cache: 8192 Byte# Instruction Cache: 8192 Byte# On Chip Memory : 8 KB# Total Off Chip Memory : 12 MB# - SDRAM_4Mx16 = 8 MB# - FLASH_4Mx8 = 4 MB# ##############################################################################

PARAMETER VERSION = 2.1.0

PORT RS232_TX = RS232_TX, DIR = OUT PORT RS232_RX = RS232_RX, DIR = IN PORT LEDs_8Bit_GPIO_d_out = LEDs_8Bit_GPIO_d_out, VEC = [0:7], DIR = OUT PORT Push_Buttons_2Bit_GPIO_in = Push_Buttons_2Bit_GPIO_in, VEC = [0:1], DIR = IN PORT LCDDISPLAY_12Bit_GPIO_d_out = LCDDISPLAY_12Bit_GPIO_d_out, VEC = [0:11], DIR = OUT PORT SDRAM_4Mx16_SDRAM_DQ = SDRAM_4Mx16_SDRAM_DQ, VEC = [0:15], DIR = INOUT PORT SDRAM_4Mx16_SDRAM_DQM = SDRAM_4Mx16_SDRAM_DQM, VEC = [0:1], DIR = OUT PORT SDRAM_4Mx16_SDRAM_RASn = SDRAM_4Mx16_SDRAM_RASn, DIR = OUT PORT SDRAM_4Mx16_SDRAM_WEn = SDRAM_4Mx16_SDRAM_WEn, DIR = OUT PORT SDRAM_4Mx16_SDRAM_Addr = SDRAM_4Mx16_SDRAM_Addr, VEC = [0:11], DIR = OUT PORT SDRAM_4Mx16_SDRAM_BankAddr = SDRAM_4Mx16_SDRAM_BankAddr, VEC = [0:1], DIR = OUT PORT SDRAM_4Mx16_SDRAM_CASn = SDRAM_4Mx16_SDRAM_CASn, DIR = OUT PORT SDRAM_4Mx16_SDRAM_CKE = SDRAM_4Mx16_SDRAM_CKE, DIR = OUT PORT SDRAM_4Mx16_SDRAM_CSn = SDRAM_4Mx16_SDRAM_CSn, DIR = OUT PORT SDRAM_4Mx16_SDRAM_Clk = SDRAM_4Mx16_SDRAM_Clk, DIR = OUT PORT FLASH_Mem_WEN = FLASH_Mem_WEN, DIR = OUT PORT FLASH_Mem_RPN = FLASH_Mem_RPN, DIR = OUT PORT FLASH_Mem_OEN = FLASH_Mem_OEN, DIR = OUT PORT FLASH_Mem_DQ = FLASH_Mem_DQ, VEC = [0:7], DIR = INOUT PORT FLASH_Mem_A = FLASH_Mem_A, VEC = [0:31], DIR = OUT PORT FLASH_Mem_CEN = FLASH_Mem_CEN, DIR = OUT PORT timer_interrupt = timer_interrupt, DIR = OUT, SIGIS = INTERRUPT, SENSITIVITY = LEVEL_HIGH PORT sys_rst = sys_rst_s, DIR = IN PORT sys_clk = sys_clk_s, DIR = IN, SIGIS = CLK

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BEGIN microblaze PARAMETER INSTANCE = microblaze_0 PARAMETER HW_VER = 2.10.a PARAMETER C_DEBUG_ENABLED = 1 PARAMETER C_NUMBER_OF_PC_BRK = 2 PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 1 PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 1 PARAMETER C_USE_BARREL = 1 PARAMETER C_USE_DIV = 1 PARAMETER C_USE_MSR_INSTR = 1 PARAMETER C_ICACHE_BASEADDR = 0x80000000 PARAMETER C_ICACHE_HIGHADDR = 0x807FFFFF PARAMETER C_USE_ICACHE = 0 PARAMETER C_ADDR_TAG_BITS = 10 PARAMETER C_CACHE_BYTE_SIZE = 8192 PARAMETER C_DCACHE_BASEADDR = 0x80000000 PARAMETER C_DCACHE_HIGHADDR = 0x807FFFFF PARAMETER C_USE_DCACHE = 0 PARAMETER C_DCACHE_ADDR_TAG = 10 PARAMETER C_DCACHE_BYTE_SIZE = 8192 BUS_INTERFACE DLMB = dlmb BUS_INTERFACE ILMB = ilmb BUS_INTERFACE DOPB = mb_opb BUS_INTERFACE IOPB = mb_opb PORT DBG_UPDATE = DBG_UPDATE_s PORT CLK = sys_clk_s PORT DBG_TDI = DBG_TDI_s PORT DBG_CLK = DBG_CLK_s PORT DBG_CAPTURE = DBG_CAPTURE_s PORT DBG_TDO = DBG_TDO_s PORT DBG_REG_EN = DBG_REG_EN_s PORT INTERRUPT = interruptEND

BEGIN opb_v20 PARAMETER INSTANCE = mb_opb PARAMETER HW_VER = 1.10.b PARAMETER C_EXT_RESET_HIGH = 0 PORT OPB_Clk = sys_clk_s PORT SYS_Rst = sys_rst_sEND

BEGIN opb_mdm PARAMETER INSTANCE = debug_module PARAMETER HW_VER = 2.00.a PARAMETER C_MB_DBG_PORTS = 1 PARAMETER C_USE_UART = 1 PARAMETER C_UART_WIDTH = 8 PARAMETER C_BASEADDR = 0xFFFF7000 PARAMETER C_HIGHADDR = 0xFFFF70FF BUS_INTERFACE SOPB = mb_opb PORT DBG_CAPTURE_0 = DBG_CAPTURE_s PORT DBG_UPDATE_0 = DBG_UPDATE_s PORT DBG_CLK_0 = DBG_CLK_s PORT DBG_TDO_0 = DBG_TDO_s PORT DBG_TDI_0 = DBG_TDI_s

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PORT OPB_Clk = sys_clk_s PORT DBG_REG_EN_0 = DBG_REG_EN_sEND

BEGIN lmb_v10 PARAMETER INSTANCE = ilmb PARAMETER HW_VER = 1.00.a PARAMETER C_EXT_RESET_HIGH = 0 PORT LMB_Clk = sys_clk_s PORT SYS_Rst = sys_rst_sEND

BEGIN lmb_v10 PARAMETER INSTANCE = dlmb PARAMETER HW_VER = 1.00.a PARAMETER C_EXT_RESET_HIGH = 0 PORT LMB_Clk = sys_clk_s PORT SYS_Rst = sys_rst_sEND

BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE = dlmb_cntlr PARAMETER HW_VER = 1.00.b PARAMETER C_MASK = 0x80000000 PARAMETER C_BASEADDR = 0x00000000 PARAMETER C_HIGHADDR = 0x00007FFF BUS_INTERFACE SLMB = dlmb BUS_INTERFACE BRAM_PORT = dlmb_portEND

BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE = ilmb_cntlr PARAMETER HW_VER = 1.00.b PARAMETER C_MASK = 0x80000000 PARAMETER C_BASEADDR = 0x00000000 PARAMETER C_HIGHADDR = 0x00007FFF BUS_INTERFACE SLMB = ilmb BUS_INTERFACE BRAM_PORT = ilmb_portEND

BEGIN bram_block PARAMETER INSTANCE = lmb_bram PARAMETER HW_VER = 1.00.a PARAMETER C_PORT_AWIDTH = 12 BUS_INTERFACE PORTA = ilmb_port BUS_INTERFACE PORTB = dlmb_portEND

BEGIN opb_uartlite PARAMETER INSTANCE = RS232 PARAMETER HW_VER = 1.00.b PARAMETER C_BAUDRATE = 57600 PARAMETER C_DATA_BITS = 8 PARAMETER C_ODD_PARITY = 0 PARAMETER C_USE_PARITY = 0 PARAMETER C_CLK_FREQ = 50000000 PARAMETER C_BASEADDR = 0xFFFF2000

15

PARAMETER C_HIGHADDR = 0xFFFF20FF BUS_INTERFACE SOPB = mb_opb PORT TX = RS232_TX PORT RX = RS232_RX PORT Interrupt = RS232_Interrupt PORT OPB_Clk = sys_clk_sEND

BEGIN opb_gpio PARAMETER INSTANCE = LEDs_8Bit PARAMETER HW_VER = 3.01.a PARAMETER C_GPIO_WIDTH = 8 PARAMETER C_IS_DUAL = 0 PARAMETER C_IS_BIDIR = 0 PARAMETER C_ALL_INPUTS = 0 PARAMETER C_BASEADDR = 0xFFFF5000 PARAMETER C_HIGHADDR = 0xFFFF51FF BUS_INTERFACE SOPB = mb_opb PORT GPIO_d_out = LEDs_8Bit_GPIO_d_out PORT OPB_Clk = sys_clk_sEND

BEGIN opb_gpio PARAMETER INSTANCE = Push_Buttons_2Bit PARAMETER HW_VER = 3.01.a PARAMETER C_GPIO_WIDTH = 2 PARAMETER C_IS_DUAL = 0 PARAMETER C_IS_BIDIR = 0 PARAMETER C_ALL_INPUTS = 1 PARAMETER C_BASEADDR = 0xFFFF5200 PARAMETER C_HIGHADDR = 0xFFFF53FF BUS_INTERFACE SOPB = mb_opb PORT OPB_Clk = sys_clk_s PORT GPIO_in = Push_Buttons_2Bit_GPIO_inEND

BEGIN opb_gpio PARAMETER INSTANCE = LCDDISPLAY_12Bit PARAMETER HW_VER = 3.01.a PARAMETER C_GPIO_WIDTH = 12 PARAMETER C_IS_DUAL = 0 PARAMETER C_IS_BIDIR = 0 PARAMETER C_ALL_INPUTS = 0 PARAMETER C_BASEADDR = 0xFFFF5400 PARAMETER C_HIGHADDR = 0xFFFF55FF BUS_INTERFACE SOPB = mb_opb PORT OPB_Clk = sys_clk_s PORT GPIO_d_out = LCDDISPLAY_12Bit_GPIO_d_outEND

BEGIN opb_sdram PARAMETER INSTANCE = SDRAM_4Mx16 PARAMETER HW_VER = 1.00.d PARAMETER C_INCLUDE_HIGHSPEED_PIPE = 1 PARAMETER C_SDRAM_CAS_LAT = 2 PARAMETER C_SDRAM_TRAS = 44000 PARAMETER C_SDRAM_TRC = 66000

16

PARAMETER C_SDRAM_TRCD = 20000 PARAMETER C_SDRAM_TREF = 64 PARAMETER C_SDRAM_TRFC = 66000 PARAMETER C_SDRAM_TRP = 20000 PARAMETER C_SDRAM_TRRD = 15000 PARAMETER C_SDRAM_TCCD = 1 PARAMETER C_SDRAM_COL_AWIDTH = 8 PARAMETER C_SDRAM_BANK_AWIDTH = 2 PARAMETER C_SDRAM_AWIDTH = 12 PARAMETER C_SDRAM_DWIDTH = 16 PARAMETER C_OPB_CLK_PERIOD_PS = 20000 PARAMETER C_BASEADDR = 0x80000000 PARAMETER C_HIGHADDR = 0x807FFFFF BUS_INTERFACE SOPB = mb_opb PORT SDRAM_DQ = SDRAM_4Mx16_SDRAM_DQ PORT SDRAM_DQM = SDRAM_4Mx16_SDRAM_DQM PORT SDRAM_RASn = SDRAM_4Mx16_SDRAM_RASn PORT SDRAM_WEn = SDRAM_4Mx16_SDRAM_WEn PORT OPB_Clk = sys_clk_s PORT SDRAM_CLK_in = sys_clk_s PORT SDRAM_Addr = SDRAM_4Mx16_SDRAM_Addr PORT SDRAM_BankAddr = SDRAM_4Mx16_SDRAM_BankAddr PORT SDRAM_CASn = SDRAM_4Mx16_SDRAM_CASn PORT SDRAM_CKE = SDRAM_4Mx16_SDRAM_CKE PORT SDRAM_CSn = SDRAM_4Mx16_SDRAM_CSn PORT SDRAM_Clk = SDRAM_4Mx16_SDRAM_ClkEND

BEGIN opb_emc PARAMETER INSTANCE = FLASH PARAMETER HW_VER = 1.00.d PARAMETER C_DEV_MIR_ENABLE = 0 PARAMETER C_NUM_BANKS_MEM = 1 PARAMETER C_READ_ADDR_TO_OUT_SLOW_PS_0 = 150000 PARAMETER C_WRITE_ADDR_TO_OUT_SLOW_PS_0 = 55000 PARAMETER C_WRITE_MIN_PULSE_WIDTH_PS_0 = 70000 PARAMETER C_READ_ADDR_TO_OUT_FAST_PS_0 = 150000 PARAMETER C_WRITE_ADDR_TO_OUT_FAST_PS_0 = 55000 PARAMETER C_READ_RECOVERY_BEFORE_WRITE_PS_0 = 15000 PARAMETER C_WRITE_RECOVERY_BEFORE_READ_PS_0 = 35000 PARAMETER C_OPB_CLK_PERIOD_PS = 20000 PARAMETER C_BASEADDR = 0xFFFF0000 PARAMETER C_HIGHADDR = 0xFFFF01FF PARAMETER C_MEM0_BASEADDR = 0x81400000 PARAMETER C_MEM0_HIGHADDR = 0x817fffff PARAMETER C_MEM_WIDTH = 8 BUS_INTERFACE SOPB = mb_opb PORT Mem_WEN = FLASH_Mem_WEN PORT Mem_RPN = FLASH_Mem_RPN PORT Mem_OEN = FLASH_Mem_OEN PORT Mem_DQ = FLASH_Mem_DQ PORT OPB_Clk = sys_clk_s PORT Mem_A = FLASH_Mem_A PORT Mem_CEN = FLASH_Mem_CENEND

BEGIN opb_timer

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PARAMETER INSTANCE = opb_timer_0 PARAMETER HW_VER = 1.00.b PARAMETER C_BASEADDR = 0xffff1000 PARAMETER C_HIGHADDR = 0xffff10ff BUS_INTERFACE SOPB = mb_opb PORT OPB_Clk = sys_clk_s PORT Interrupt = timer_interruptEND

BEGIN opb_intc PARAMETER INSTANCE = opb_intc_0 PARAMETER HW_VER = 1.00.c PARAMETER C_BASEADDR = 0xFFFF3000 PARAMETER C_HIGHADDR = 0xFFFF30FF BUS_INTERFACE SOPB = mb_opb PORT Irq = interrupt PORT Intr = RS232_Interrupt & timer_interrupt PORT OPB_Clk = sys_clk_sEND

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LATS_TestBed.mss


BEGIN OS PARAMETER OS_NAME = standalone PARAMETER OS_VER = 1.00.a PARAMETER PROC_INSTANCE = microblaze_0 PARAMETER STDIN = RS232 PARAMETER STDOUT = RS232END

BEGIN PROCESSOR PARAMETER DRIVER_NAME = cpu PARAMETER DRIVER_VER = 1.00.a PARAMETER HW_INSTANCE = microblaze_0 PARAMETER COMPILER = mb-gcc PARAMETER ARCHIVER = mb-ar PARAMETER XMDSTUB_PERIPHERAL = debug_moduleEND

BEGIN DRIVER PARAMETER DRIVER_NAME = generic PARAMETER DRIVER_VER = 1.00.a PARAMETER HW_INSTANCE = mb_opbEND

BEGIN DRIVER PARAMETER DRIVER_NAME = uartlite PARAMETER DRIVER_VER = 1.00.b PARAMETER HW_INSTANCE = debug_moduleEND

BEGIN DRIVER PARAMETER DRIVER_NAME = bram PARAMETER DRIVER_VER = 1.00.a PARAMETER HW_INSTANCE = dlmb_cntlrEND

BEGIN DRIVER PARAMETER DRIVER_NAME = bram PARAMETER DRIVER_VER = 1.00.a PARAMETER HW_INSTANCE = ilmb_cntlrEND

BEGIN DRIVER PARAMETER DRIVER_NAME = uartlite PARAMETER DRIVER_VER = 1.00.b PARAMETER HW_INSTANCE = RS232END

BEGIN DRIVER

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PARAMETER DRIVER_NAME = gpio PARAMETER DRIVER_VER = 2.00.a PARAMETER HW_INSTANCE = LEDs_8BitEND

BEGIN DRIVER PARAMETER DRIVER_NAME = gpio PARAMETER DRIVER_VER = 2.00.a PARAMETER HW_INSTANCE = Push_Buttons_2BitEND

BEGIN DRIVER PARAMETER DRIVER_NAME = gpio PARAMETER DRIVER_VER = 2.00.a PARAMETER HW_INSTANCE = LCDDISPLAY_12BitEND

BEGIN DRIVER PARAMETER DRIVER_NAME = sdram PARAMETER DRIVER_VER = 1.00.a PARAMETER HW_INSTANCE = SDRAM_4Mx16END

BEGIN DRIVER PARAMETER DRIVER_NAME = emc PARAMETER DRIVER_VER = 1.00.a PARAMETER HW_INSTANCE = FLASHEND

BEGIN DRIVER PARAMETER DRIVER_NAME = tmrctr PARAMETER DRIVER_VER = 1.00.b PARAMETER HW_INSTANCE = opb_timer_0END

BEGIN DRIVER PARAMETER DRIVER_NAME = intc PARAMETER DRIVER_VER = 1.00.c PARAMETER HW_INSTANCE = opb_intc_0END

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Limited Flash Source / I and D Cache in Use

LATS_TestBed.ucfNet sys_clk PERIOD = 20000 ps;Net RS232_RX LOC=P87;Net RS232_TX LOC=P85;Net LEDs_8Bit_GPIO_d_out<0> LOC=P161;Net LEDs_8Bit_GPIO_d_out<1> LOC=P162;Net LEDs_8Bit_GPIO_d_out<2> LOC=P165;Net LEDs_8Bit_GPIO_d_out<3> LOC=P166;Net LEDs_8Bit_GPIO_d_out<4> LOC=P167;Net LEDs_8Bit_GPIO_d_out<5> LOC=P168;Net LEDs_8Bit_GPIO_d_out<6> LOC=P169;Net LEDs_8Bit_GPIO_d_out<7> LOC=P171;Net Push_Buttons_2Bit_GPIO_in<0> LOC=P64;Net Push_Buttons_2Bit_GPIO_in<1> LOC=P62;Net LCDDISPLAY_12Bit_GPIO_d_out<11> LOC=P152;Net LCDDISPLAY_12Bit_GPIO_d_out<10> LOC=P150;Net LCDDISPLAY_12Bit_GPIO_d_out<9> LOC=P149;Net LCDDISPLAY_12Bit_GPIO_d_out<8> LOC=P148;Net LCDDISPLAY_12Bit_GPIO_d_out<7> LOC=P147;Net LCDDISPLAY_12Bit_GPIO_d_out<6> LOC=P146;Net LCDDISPLAY_12Bit_GPIO_d_out<5> LOC=P144;Net LCDDISPLAY_12Bit_GPIO_d_out<4> LOC=P143;Net LCDDISPLAY_12Bit_GPIO_d_out<3> LOC=P156;Net LCDDISPLAY_12Bit_GPIO_d_out<2> LOC=P154;Net LCDDISPLAY_12Bit_GPIO_d_out<1> LOC=P155;Net LCDDISPLAY_12Bit_GPIO_d_out<0> LOC=P141;Net SDRAM_4Mx16_SDRAM_DQ<15> LOC=P4;Net SDRAM_4Mx16_SDRAM_DQ<14> LOC=P5;Net SDRAM_4Mx16_SDRAM_DQ<13> LOC=P7;Net SDRAM_4Mx16_SDRAM_DQ<12> LOC=P9;Net SDRAM_4Mx16_SDRAM_DQ<11> LOC=P10;Net SDRAM_4Mx16_SDRAM_DQ<10> LOC=P11;Net SDRAM_4Mx16_SDRAM_DQ<9> LOC=P12;Net SDRAM_4Mx16_SDRAM_DQ<8> LOC=P13;Net SDRAM_4Mx16_SDRAM_DQ<7> LOC=P39;Net SDRAM_4Mx16_SDRAM_DQ<6> LOC=P37;Net SDRAM_4Mx16_SDRAM_DQ<5> LOC=P36;Net SDRAM_4Mx16_SDRAM_DQ<4> LOC=P35;Net SDRAM_4Mx16_SDRAM_DQ<3> LOC=P26;Net SDRAM_4Mx16_SDRAM_DQ<2> LOC=P24;Net SDRAM_4Mx16_SDRAM_DQ<1> LOC=P22;Net SDRAM_4Mx16_SDRAM_DQ<0> LOC=P21;Net SDRAM_4Mx16_SDRAM_Addr<11> LOC=P29;Net SDRAM_4Mx16_SDRAM_Addr<10> LOC=P31;Net SDRAM_4Mx16_SDRAM_Addr<9> LOC=P33;Net SDRAM_4Mx16_SDRAM_Addr<8> LOC=P34;Net SDRAM_4Mx16_SDRAM_Addr<7> LOC=P57;Net SDRAM_4Mx16_SDRAM_Addr<6> LOC=P50;Net SDRAM_4Mx16_SDRAM_Addr<5> LOC=P48;Net SDRAM_4Mx16_SDRAM_Addr<4> LOC=P46;Net SDRAM_4Mx16_SDRAM_Addr<3> LOC=P45;Net SDRAM_4Mx16_SDRAM_Addr<2> LOC=P44;Net SDRAM_4Mx16_SDRAM_Addr<1> LOC=P28;

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Net SDRAM_4Mx16_SDRAM_Addr<0> LOC=P27;Net SDRAM_4Mx16_SDRAM_WEn LOC=P16;Net SDRAM_4Mx16_SDRAM_CKE LOC=P43;Net SDRAM_4Mx16_SDRAM_CSn LOC=P20;Net SDRAM_4Mx16_SDRAM_CASn LOC=P18;Net SDRAM_4Mx16_SDRAM_RASn LOC=P19;Net SDRAM_4Mx16_SDRAM_Clk LOC=P42;Net SDRAM_4Mx16_SDRAM_BankAddr<1> LOC=P61;Net SDRAM_4Mx16_SDRAM_BankAddr<0> LOC=P58;Net SDRAM_4Mx16_SDRAM_DQM<1> LOC=P15;Net SDRAM_4Mx16_SDRAM_DQM<0> LOC=P40;Net FLASH_Mem_A<31> LOC=P175;Net FLASH_Mem_A<30> LOC=P93;Net FLASH_Mem_A<29> LOC=P113;Net FLASH_Mem_A<28> LOC=P111;Net FLASH_Mem_A<27> LOC=P114;Net FLASH_Mem_A<26> LOC=P115;Net FLASH_Mem_A<25> LOC=P116;Net FLASH_Mem_A<24> LOC=P117;Net FLASH_Mem_A<23> LOC=P119;Net FLASH_Mem_A<22> LOC=P131;Net FLASH_Mem_A<21> LOC=P132;Net FLASH_Mem_A<20> LOC=P133;Net FLASH_Mem_A<19> LOC=P135;Net FLASH_Mem_A<18> LOC=P137;Net FLASH_Mem_A<17> LOC=P138;Net FLASH_Mem_A<16> LOC=P139;Net FLASH_Mem_A<15> LOC=P140;Net FLASH_Mem_A<14> LOC=P109;Net FLASH_Mem_A<13> LOC=P120;Net FLASH_Mem_A<12> LOC=P122;Net FLASH_Mem_A<11> LOC=P130;Net FLASH_Mem_A<10> LOC=P128;Net FLASH_Mem_DQ<7> LOC=P96;Net FLASH_Mem_DQ<6> LOC=P97;Net FLASH_Mem_DQ<5> LOC=P100;Net FLASH_Mem_DQ<4> LOC=P101;Net FLASH_Mem_DQ<3> LOC=P102;Net FLASH_Mem_DQ<2> LOC=P106;Net FLASH_Mem_DQ<1> LOC=P107;Net FLASH_Mem_DQ<0> LOC=P108;Net FLASH_Mem_WEN LOC=P126;Net FLASH_Mem_OEN LOC=P95;Net FLASH_Mem_CEN LOC=P94;Net FLASH_Mem_RPN LOC=P125;Net sys_clk LOC=P80; // pll clock is 80, main clk is 79Net sys_rst LOC=P63;

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LATS_TestBed.mhs# ############################################################################### Created by Base System Builder Wizard for Xilinx EDK 6.2 Build EDK_Gm.11# Wed Nov 10 11:37:34 2004# Target Board: Nu Horizons Spartan-III 400 Evaluation Board Rev 1# Family: spartan3# Device: XC3S400# Package: PQ208# Speed Grade: -4# Processor: Microblaze# System clock frequency: 50 MHz# Debug interface: On-Chip HW Debug Module# Data Cache: 8192 Byte# Instruction Cache: 8192 Byte# On Chip Memory : 8 KB# Total Off Chip Memory : 12 MB# - SDRAM_4Mx16 = 8 MB# - FLASH_4Mx8 = 4 MB# ##############################################################################


PORT RS232_TX = RS232_TX, DIR = OUT PORT RS232_RX = RS232_RX, DIR = IN PORT LEDs_8Bit_GPIO_d_out = LEDs_8Bit_GPIO_d_out, VEC = [0:7], DIR = OUT PORT Push_Buttons_2Bit_GPIO_in = Push_Buttons_2Bit_GPIO_in, VEC = [0:1], DIR = IN PORT LCDDISPLAY_12Bit_GPIO_d_out = LCDDISPLAY_12Bit_GPIO_d_out, VEC = [0:11], DIR = OUT PORT SDRAM_4Mx16_SDRAM_DQ = SDRAM_4Mx16_SDRAM_DQ, VEC = [0:15], DIR = INOUT PORT SDRAM_4Mx16_SDRAM_DQM = SDRAM_4Mx16_SDRAM_DQM, VEC = [0:1], DIR = OUT PORT SDRAM_4Mx16_SDRAM_RASn = SDRAM_4Mx16_SDRAM_RASn, DIR = OUT PORT SDRAM_4Mx16_SDRAM_WEn = SDRAM_4Mx16_SDRAM_WEn, DIR = OUT PORT SDRAM_4Mx16_SDRAM_Addr = SDRAM_4Mx16_SDRAM_Addr, VEC = [0:11], DIR = OUT PORT SDRAM_4Mx16_SDRAM_BankAddr = SDRAM_4Mx16_SDRAM_BankAddr, VEC = [0:1], DIR = OUT PORT SDRAM_4Mx16_SDRAM_CASn = SDRAM_4Mx16_SDRAM_CASn, DIR = OUT PORT SDRAM_4Mx16_SDRAM_CKE = SDRAM_4Mx16_SDRAM_CKE, DIR = OUT PORT SDRAM_4Mx16_SDRAM_CSn = SDRAM_4Mx16_SDRAM_CSn, DIR = OUT PORT SDRAM_4Mx16_SDRAM_Clk = SDRAM_4Mx16_SDRAM_Clk, DIR = OUT PORT FLASH_Mem_WEN = FLASH_Mem_WEN, DIR = OUT PORT FLASH_Mem_RPN = FLASH_Mem_RPN, DIR = OUT PORT FLASH_Mem_OEN = FLASH_Mem_OEN, DIR = OUT PORT FLASH_Mem_DQ = FLASH_Mem_DQ, VEC = [0:7], DIR = INOUT PORT FLASH_Mem_A = FLASH_Mem_A, VEC = [0:31], DIR = OUT PORT FLASH_Mem_CEN = FLASH_Mem_CEN, DIR = OUT PORT timer_interrupt = timer_interrupt, DIR = OUT, SIGIS = INTERRUPT, SENSITIVITY = LEVEL_HIGH PORT sys_rst = sys_rst_s, DIR = IN PORT sys_clk = sys_clk_s, DIR = IN, SIGIS = CLK

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BEGIN microblaze PARAMETER INSTANCE = microblaze_0 PARAMETER HW_VER = 2.10.a PARAMETER C_DEBUG_ENABLED = 1 PARAMETER C_NUMBER_OF_PC_BRK = 2 PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 1 PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 1 PARAMETER C_USE_BARREL = 1 PARAMETER C_USE_DIV = 1 PARAMETER C_USE_MSR_INSTR = 1 PARAMETER C_ICACHE_BASEADDR = 0x80000000 PARAMETER C_ICACHE_HIGHADDR = 0x807FFFFF PARAMETER C_USE_ICACHE = 1 PARAMETER C_ADDR_TAG_BITS = 10 PARAMETER C_CACHE_BYTE_SIZE = 8192 PARAMETER C_DCACHE_BASEADDR = 0x80000000 PARAMETER C_DCACHE_HIGHADDR = 0x807FFFFF PARAMETER C_USE_DCACHE = 1 PARAMETER C_DCACHE_ADDR_TAG = 10 PARAMETER C_DCACHE_BYTE_SIZE = 8192 BUS_INTERFACE DLMB = dlmb BUS_INTERFACE ILMB = ilmb BUS_INTERFACE DOPB = mb_opb BUS_INTERFACE IOPB = mb_opb PORT DBG_UPDATE = DBG_UPDATE_s PORT CLK = sys_clk_s PORT DBG_TDI = DBG_TDI_s PORT DBG_CLK = DBG_CLK_s PORT DBG_CAPTURE = DBG_CAPTURE_s PORT DBG_TDO = DBG_TDO_s PORT DBG_REG_EN = DBG_REG_EN_s PORT INTERRUPT = interruptEND

BEGIN opb_v20 PARAMETER INSTANCE = mb_opb PARAMETER HW_VER = 1.10.b PARAMETER C_EXT_RESET_HIGH = 0 PORT OPB_Clk = sys_clk_s PORT SYS_Rst = sys_rst_sEND

BEGIN opb_mdm PARAMETER INSTANCE = debug_module PARAMETER HW_VER = 2.00.a PARAMETER C_MB_DBG_PORTS = 1 PARAMETER C_USE_UART = 1 PARAMETER C_UART_WIDTH = 8 PARAMETER C_BASEADDR = 0xFFFF7000 PARAMETER C_HIGHADDR = 0xFFFF70FF BUS_INTERFACE SOPB = mb_opb PORT DBG_CAPTURE_0 = DBG_CAPTURE_s PORT DBG_UPDATE_0 = DBG_UPDATE_s PORT DBG_CLK_0 = DBG_CLK_s PORT DBG_TDO_0 = DBG_TDO_s PORT DBG_TDI_0 = DBG_TDI_s

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PORT OPB_Clk = sys_clk_s PORT DBG_REG_EN_0 = DBG_REG_EN_sEND

BEGIN lmb_v10 PARAMETER INSTANCE = ilmb PARAMETER HW_VER = 1.00.a PARAMETER C_EXT_RESET_HIGH = 0 PORT LMB_Clk = sys_clk_s PORT SYS_Rst = sys_rst_sEND

BEGIN lmb_v10 PARAMETER INSTANCE = dlmb PARAMETER HW_VER = 1.00.a PARAMETER C_EXT_RESET_HIGH = 0 PORT LMB_Clk = sys_clk_s PORT SYS_Rst = sys_rst_sEND

BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE = dlmb_cntlr PARAMETER HW_VER = 1.00.b PARAMETER C_MASK = 0x80000000 PARAMETER C_BASEADDR = 0x00000000 PARAMETER C_HIGHADDR = 0x00001FFF BUS_INTERFACE SLMB = dlmb BUS_INTERFACE BRAM_PORT = dlmb_portEND

BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE = ilmb_cntlr PARAMETER HW_VER = 1.00.b PARAMETER C_MASK = 0x80000000 PARAMETER C_BASEADDR = 0x00000000 PARAMETER C_HIGHADDR = 0x00001FFF BUS_INTERFACE SLMB = ilmb BUS_INTERFACE BRAM_PORT = ilmb_portEND

BEGIN bram_block PARAMETER INSTANCE = lmb_bram PARAMETER HW_VER = 1.00.a PARAMETER C_PORT_AWIDTH = 12 BUS_INTERFACE PORTA = ilmb_port BUS_INTERFACE PORTB = dlmb_portEND

BEGIN opb_uartlite PARAMETER INSTANCE = RS232 PARAMETER HW_VER = 1.00.b PARAMETER C_BAUDRATE = 57600 PARAMETER C_DATA_BITS = 8 PARAMETER C_ODD_PARITY = 0 PARAMETER C_USE_PARITY = 0 PARAMETER C_CLK_FREQ = 50000000 PARAMETER C_BASEADDR = 0xFFFF2000

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PARAMETER C_HIGHADDR = 0xFFFF20FF BUS_INTERFACE SOPB = mb_opb PORT TX = RS232_TX PORT RX = RS232_RX PORT Interrupt = RS232_Interrupt PORT OPB_Clk = sys_clk_sEND

BEGIN opb_gpio PARAMETER INSTANCE = LEDs_8Bit PARAMETER HW_VER = 3.01.a PARAMETER C_GPIO_WIDTH = 8 PARAMETER C_IS_DUAL = 0 PARAMETER C_IS_BIDIR = 0 PARAMETER C_ALL_INPUTS = 0 PARAMETER C_BASEADDR = 0xFFFF5000 PARAMETER C_HIGHADDR = 0xFFFF51FF BUS_INTERFACE SOPB = mb_opb PORT GPIO_d_out = LEDs_8Bit_GPIO_d_out PORT OPB_Clk = sys_clk_sEND

BEGIN opb_gpio PARAMETER INSTANCE = Push_Buttons_2Bit PARAMETER HW_VER = 3.01.a PARAMETER C_GPIO_WIDTH = 2 PARAMETER C_IS_DUAL = 0 PARAMETER C_IS_BIDIR = 0 PARAMETER C_ALL_INPUTS = 1 PARAMETER C_BASEADDR = 0xFFFF5200 PARAMETER C_HIGHADDR = 0xFFFF53FF BUS_INTERFACE SOPB = mb_opb PORT OPB_Clk = sys_clk_s PORT GPIO_in = Push_Buttons_2Bit_GPIO_inEND

BEGIN opb_gpio PARAMETER INSTANCE = LCDDISPLAY_12Bit PARAMETER HW_VER = 3.01.a PARAMETER C_GPIO_WIDTH = 12 PARAMETER C_IS_DUAL = 0 PARAMETER C_IS_BIDIR = 0 PARAMETER C_ALL_INPUTS = 0 PARAMETER C_BASEADDR = 0xFFFF5400 PARAMETER C_HIGHADDR = 0xFFFF55FF BUS_INTERFACE SOPB = mb_opb PORT OPB_Clk = sys_clk_s PORT GPIO_d_out = LCDDISPLAY_12Bit_GPIO_d_outEND

BEGIN opb_sdram PARAMETER INSTANCE = SDRAM_4Mx16 PARAMETER HW_VER = 1.00.d PARAMETER C_INCLUDE_HIGHSPEED_PIPE = 1 PARAMETER C_SDRAM_CAS_LAT = 2 PARAMETER C_SDRAM_TRAS = 44000 PARAMETER C_SDRAM_TRC = 66000

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PARAMETER C_SDRAM_TRCD = 20000 PARAMETER C_SDRAM_TREF = 64 PARAMETER C_SDRAM_TRFC = 66000 PARAMETER C_SDRAM_TRP = 20000 PARAMETER C_SDRAM_TRRD = 15000 PARAMETER C_SDRAM_TCCD = 1 PARAMETER C_SDRAM_COL_AWIDTH = 8 PARAMETER C_SDRAM_BANK_AWIDTH = 2 PARAMETER C_SDRAM_AWIDTH = 12 PARAMETER C_SDRAM_DWIDTH = 16 PARAMETER C_OPB_CLK_PERIOD_PS = 12500 PARAMETER C_BASEADDR = 0x80000000 PARAMETER C_HIGHADDR = 0x807FFFFF BUS_INTERFACE SOPB = mb_opb PORT SDRAM_DQ = SDRAM_4Mx16_SDRAM_DQ PORT SDRAM_DQM = SDRAM_4Mx16_SDRAM_DQM PORT SDRAM_RASn = SDRAM_4Mx16_SDRAM_RASn PORT SDRAM_WEn = SDRAM_4Mx16_SDRAM_WEn PORT OPB_Clk = sys_clk_s PORT SDRAM_CLK_in = sys_clk_s PORT SDRAM_Addr = SDRAM_4Mx16_SDRAM_Addr PORT SDRAM_BankAddr = SDRAM_4Mx16_SDRAM_BankAddr PORT SDRAM_CASn = SDRAM_4Mx16_SDRAM_CASn PORT SDRAM_CKE = SDRAM_4Mx16_SDRAM_CKE PORT SDRAM_CSn = SDRAM_4Mx16_SDRAM_CSn PORT SDRAM_Clk = SDRAM_4Mx16_SDRAM_ClkEND

BEGIN opb_emc PARAMETER INSTANCE = FLASH PARAMETER HW_VER = 1.00.d PARAMETER C_DEV_MIR_ENABLE = 0 PARAMETER C_NUM_BANKS_MEM = 1 PARAMETER C_READ_ADDR_TO_OUT_SLOW_PS_0 = 150000 PARAMETER C_WRITE_ADDR_TO_OUT_SLOW_PS_0 = 55000 PARAMETER C_WRITE_MIN_PULSE_WIDTH_PS_0 = 70000 PARAMETER C_READ_ADDR_TO_OUT_FAST_PS_0 = 150000 PARAMETER C_WRITE_ADDR_TO_OUT_FAST_PS_0 = 55000 PARAMETER C_READ_RECOVERY_BEFORE_WRITE_PS_0 = 15000 PARAMETER C_WRITE_RECOVERY_BEFORE_READ_PS_0 = 35000 PARAMETER C_OPB_CLK_PERIOD_PS = 12500 PARAMETER C_BASEADDR = 0xFFFF0000 PARAMETER C_HIGHADDR = 0xFFFF01FF PARAMETER C_MEM0_BASEADDR = 0x81400000 PARAMETER C_MEM0_HIGHADDR = 0x817fffff PARAMETER C_MEM_WIDTH = 8 BUS_INTERFACE SOPB = mb_opb PORT Mem_WEN = FLASH_Mem_WEN PORT Mem_RPN = FLASH_Mem_RPN PORT Mem_OEN = FLASH_Mem_OEN PORT Mem_DQ = FLASH_Mem_DQ PORT OPB_Clk = sys_clk_s PORT Mem_A = FLASH_Mem_A PORT Mem_CEN = FLASH_Mem_CENEND

BEGIN opb_timer

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PARAMETER INSTANCE = opb_timer_0 PARAMETER HW_VER = 1.00.b PARAMETER C_BASEADDR = 0xffff1000 PARAMETER C_HIGHADDR = 0xffff10ff BUS_INTERFACE SOPB = mb_opb PORT OPB_Clk = sys_clk_s PORT Interrupt = timer_interruptEND

BEGIN opb_intc PARAMETER INSTANCE = opb_intc_0 PARAMETER HW_VER = 1.00.c PARAMETER C_BASEADDR = 0xFFFF3000 PARAMETER C_HIGHADDR = 0xFFFF30FF BUS_INTERFACE SOPB = mb_opb PORT Irq = interrupt PORT Intr = RS232_Interrupt & timer_interrupt PORT OPB_Clk = sys_clk_sEND

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LATS_TestBed.mss


BEGIN OS PARAMETER OS_NAME = standalone PARAMETER OS_VER = 1.00.a PARAMETER PROC_INSTANCE = microblaze_0 PARAMETER STDIN = RS232 PARAMETER STDOUT = RS232END

BEGIN PROCESSOR PARAMETER DRIVER_NAME = cpu PARAMETER DRIVER_VER = 1.00.a PARAMETER HW_INSTANCE = microblaze_0 PARAMETER COMPILER = mb-gcc PARAMETER ARCHIVER = mb-ar PARAMETER XMDSTUB_PERIPHERAL = debug_moduleEND

BEGIN DRIVER PARAMETER DRIVER_NAME = generic PARAMETER DRIVER_VER = 1.00.a PARAMETER HW_INSTANCE = mb_opbEND

BEGIN DRIVER PARAMETER DRIVER_NAME = uartlite PARAMETER DRIVER_VER = 1.00.b PARAMETER HW_INSTANCE = debug_moduleEND

BEGIN DRIVER PARAMETER DRIVER_NAME = bram PARAMETER DRIVER_VER = 1.00.a PARAMETER HW_INSTANCE = dlmb_cntlrEND

BEGIN DRIVER PARAMETER DRIVER_NAME = bram PARAMETER DRIVER_VER = 1.00.a PARAMETER HW_INSTANCE = ilmb_cntlrEND

BEGIN DRIVER PARAMETER DRIVER_NAME = uartlite PARAMETER DRIVER_VER = 1.00.b PARAMETER HW_INSTANCE = RS232END

BEGIN DRIVER

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PARAMETER DRIVER_NAME = gpio PARAMETER DRIVER_VER = 2.00.a PARAMETER HW_INSTANCE = LEDs_8BitEND

BEGIN DRIVER PARAMETER DRIVER_NAME = gpio PARAMETER DRIVER_VER = 2.00.a PARAMETER HW_INSTANCE = Push_Buttons_2BitEND

BEGIN DRIVER PARAMETER DRIVER_NAME = gpio PARAMETER DRIVER_VER = 2.00.a PARAMETER HW_INSTANCE = LCDDISPLAY_12BitEND

BEGIN DRIVER PARAMETER DRIVER_NAME = sdram PARAMETER DRIVER_VER = 1.00.a PARAMETER HW_INSTANCE = SDRAM_4Mx16END

BEGIN DRIVER PARAMETER DRIVER_NAME = emc PARAMETER DRIVER_VER = 1.00.a PARAMETER HW_INSTANCE = FLASHEND

BEGIN DRIVER PARAMETER DRIVER_NAME = tmrctr PARAMETER DRIVER_VER = 1.00.b PARAMETER HW_INSTANCE = opb_timer_0END

BEGIN DRIVER PARAMETER DRIVER_NAME = intc PARAMETER DRIVER_VER = 1.00.c PARAMETER HW_INSTANCE = opb_intc_0END

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APPENDIX B: SOFTWARE SOURCE

uClinux Kernel Configuration

No Cache Enabled: .config (uClinux-dist/linux-2.4.x/.config)## Automatically generated by make menuconfig: don't edit#CONFIG_UCLINUX=yCONFIG_UID16=yCONFIG_RWSEM_GENERIC_SPINLOCK=y# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set# CONFIG_ISA is not set# CONFIG_ISAPNP is not set# CONFIG_EISA is not set# CONFIG_MCA is not set

## Code maturity level options#CONFIG_EXPERIMENTAL=y

## Loadable module support## CONFIG_MODULES is not setCONFIG_MICROBLAZE=y

## Processor type and features## CONFIG_UCLINUX_AUTO is not setCONFIG_MBVANILLA=y# CONFIG_EGRET01 is not set# CONFIG_SUZAKU is not setCONFIG_CPU_CLOCK_FREQ=50000000CONFIG_MICROBLAZE_MSRSETCLR=yCONFIG_MICROBLAZE_HARD_MULT=yCONFIG_MICROBLAZE_HARD_DIV=yCONFIG_MICROBLAZE_HARD_BARREL=y# CONFIG_MICROBLAZE_ICACHE is not set# CONFIG_MICROBLAZE_DCACHE is not set CONFIG_MICROBLAZE_DEBUG_UART=yCONFIG_XILINX_GPIO=y# CONFIG_XILINX_ENET is not set# CONFIG_XILINX_SYSACE is not set# CONFIG_MBVANILLA_CMDLINE is not setCONFIG_ZERO_BSS=yCONFIG_MICROBLAZE_DEBUGGING=y

## General setup## CONFIG_NET is not set

31

# CONFIG_DISK is not set# CONFIG_HOTPLUG is not set# CONFIG_PCMCIA is not set# CONFIG_SYSVIPC is not set# CONFIG_BSD_PROCESS_ACCT is not set# CONFIG_SYSCTL is not setCONFIG_KCORE_ELF=y# CONFIG_KCORE_AOUT is not setCONFIG_BINFMT_FLAT=yCONFIG_BINFMT_ZFLAT=y# CONFIG_CONTIGUOUS_PAGE_ALLOC is not set# CONFIG_MEM_MAP is not set# CONFIG_NO_MMU_LARGE_ALLOCS is not set

## Memory Technology Devices (MTD)#CONFIG_MTD=yCONFIG_MTD_DEBUG=yCONFIG_MTD_DEBUG_VERBOSE=0CONFIG_MTD_PARTITIONS=y# CONFIG_MTD_CONCAT is not set# CONFIG_MTD_REDBOOT_PARTS is not set# CONFIG_MTD_CMDLINE_PARTS is not setCONFIG_MTD_CHAR=yCONFIG_MTD_BLOCK=y# CONFIG_FTL is not set# CONFIG_NFTL is not set# CONFIG_INFTL is not set

## RAM/ROM/Flash chip drivers#CONFIG_MTD_CFI=yCONFIG_MTD_JEDECPROBE=yCONFIG_MTD_GEN_PROBE=y# CONFIG_MTD_CFI_ADV_OPTIONS is not set# CONFIG_MTD_CFI_INTELEXT is not set# CONFIG_MTD_CFI_AMDSTD is not setCONFIG_MTD_CFI_STAA=yCONFIG_MTD_RAM=yCONFIG_MTD_ROM=y# CONFIG_MTD_ABSENT is not set# CONFIG_MTD_OBSOLETE_CHIPS is not set# CONFIG_MTD_AMDSTD is not set# CONFIG_MTD_SHARP is not set# CONFIG_MTD_JEDEC is not set# CONFIG_MTD_PSD4256G is not set

## Mapping drivers for chip access## CONFIG_MTD_PHYSMAP is not set# CONFIG_MTD_DRAGONIX is not set# CONFIG_MTD_NETtel is not set# CONFIG_MTD_SNAPGEODE is not set# CONFIG_MTD_NETteluC is not set

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CONFIG_MTD_MBVANILLA=y# CONFIG_FLASHAUTO is not set# CONFIG_FLASH128KB is not set# CONFIG_FLASH1MB is not set# CONFIG_FLASH2MB is not setCONFIG_FLASH4MB=y# CONFIG_FLASH6MB is not set# CONFIG_FLASH8MB is not set# CONFIG_MTD_SUZAKU is not set# CONFIG_MTD_KeyTechnology is not set# CONFIG_MTD_SED_SIOSIII is not set# CONFIG_MTD_UCLINUX is not set# CONFIG_MTD_PCI is not set# CONFIG_MTD_PCMCIA is not set

## Self-contained MTD device drivers## CONFIG_MTD_PMC551 is not set# CONFIG_MTD_SLRAM is not set# CONFIG_MTD_MTDRAM is not set# CONFIG_MTD_BLKMTD is not set# CONFIG_MTD_DOC1000 is not set# CONFIG_MTD_DOC2000 is not set# CONFIG_MTD_DOC2001 is not set# CONFIG_MTD_DOC2001PLUS is not set# CONFIG_MTD_DOCPROBE is not set

## NAND Flash Device Drivers## CONFIG_MTD_NAND is not set

## Parallel port support## CONFIG_PARPORT is not set

## Block devices## CONFIG_BLK_DEV_FD is not set# CONFIG_BLK_DEV_XD is not set# CONFIG_PARIDE is not set# CONFIG_BLK_CPQ_DA is not set# CONFIG_BLK_CPQ_CISS_DA is not set# CONFIG_CISS_SCSI_TAPE is not set# CONFIG_CISS_MONITOR_THREAD is not set# CONFIG_BLK_DEV_DAC960 is not set# CONFIG_BLK_DEV_UMEM is not set# CONFIG_BLK_DEV_SX8 is not set# CONFIG_BLK_DEV_LOOP is not set# CONFIG_BLK_DEV_NBD is not setCONFIG_BLK_DEV_RAM=yCONFIG_BLK_DEV_RAM_SIZE=4096# CONFIG_BLK_DEV_INITRD is not set# CONFIG_BLK_DEV_RAMDISK_DATA is not set

33

# CONFIG_BLK_DEV_BLKMEM is not set# CONFIG_BLK_STATS is not set

## Character devices## CONFIG_LEDMAN is not set# CONFIG_SNAPDOG is not set# CONFIG_DS1302 is not set# CONFIG_M41T11M6 is not set# CONFIG_VT is not set# CONFIG_SERIAL is not set# CONFIG_SERIAL_EXTENDED is not set# CONFIG_SERIAL_NONSTANDARD is not set

## Serial drivers## CONFIG_SERIAL_8250 is not set# CONFIG_SERIAL_8250_CONSOLE is not set# CONFIG_SERIAL_8250_EXTENDED is not set# CONFIG_SERIAL_8250_MANY_PORTS is not set# CONFIG_SERIAL_8250_SHARE_IRQ is not set# CONFIG_SERIAL_8250_DETECT_IRQ is not set# CONFIG_SERIAL_8250_MULTIPORT is not set# CONFIG_SERIAL_8250_HUB6 is not set# CONFIG_UNIX98_PTYS is not set

## I2C support## CONFIG_I2C is not set

## Mice## CONFIG_BUSMOUSE is not set# CONFIG_MOUSE is not set# CONFIG_EDB7312_TS is not set

## Joysticks## CONFIG_INPUT_GAMEPORT is not set# CONFIG_INPUT_NS558 is not set# CONFIG_INPUT_LIGHTNING is not set# CONFIG_INPUT_PCIGAME is not set# CONFIG_INPUT_CS461X is not set# CONFIG_INPUT_EMU10K1 is not set# CONFIG_INPUT_SERIO is not set# CONFIG_INPUT_SERPORT is not set# CONFIG_INPUT_ANALOG is not set# CONFIG_INPUT_A3D is not set# CONFIG_INPUT_ADI is not set# CONFIG_INPUT_COBRA is not set# CONFIG_INPUT_GF2K is not set# CONFIG_INPUT_GRIP is not set

34

# CONFIG_INPUT_INTERACT is not set# CONFIG_INPUT_TMDC is not set# CONFIG_INPUT_SIDEWINDER is not set# CONFIG_INPUT_IFORCE_USB is not set# CONFIG_INPUT_IFORCE_232 is not set# CONFIG_INPUT_WARRIOR is not set# CONFIG_INPUT_MAGELLAN is not set# CONFIG_INPUT_SPACEORB is not set# CONFIG_INPUT_SPACEBALL is not set# CONFIG_INPUT_STINGER is not set# CONFIG_INPUT_DB9 is not set# CONFIG_INPUT_GAMECON is not set# CONFIG_INPUT_TURBOGRAFX is not set# CONFIG_QIC02_TAPE is not set# CONFIG_IPMI_HANDLER is not set# CONFIG_IPMI_PANIC_EVENT is not set# CONFIG_IPMI_DEVICE_INTERFACE is not set# CONFIG_IPMI_KCS is not set# CONFIG_IPMI_WATCHDOG is not set

## Controller Area Network Cards/Chips## CONFIG_CAN4LINUX is not set

## Watchdog Cards## CONFIG_WATCHDOG is not set# CONFIG_SCx200 is not set# CONFIG_SCx200_GPIO is not set# CONFIG_AMD_PM768 is not set# CONFIG_NVRAM is not set# CONFIG_RTC is not set# CONFIG_DTLK is not set# CONFIG_R3964 is not set# CONFIG_APPLICOM is not set

## Ftape, the floppy tape device driver## CONFIG_FTAPE is not set# CONFIG_AGP is not set

## Direct Rendering Manager (XFree86 DRI support)## CONFIG_DRM is not set

## Misc devices## CONFIG_MICROBLAZE_FSLFIFO is not set

## File systems#

35

# CONFIG_QUOTA is not set# CONFIG_QFMT_V2 is not set# CONFIG_AUTOFS_FS is not set# CONFIG_AUTOFS4_FS is not set# CONFIG_REISERFS_FS is not set# CONFIG_REISERFS_CHECK is not set# CONFIG_REISERFS_PROC_INFO is not set# CONFIG_ADFS_FS is not set# CONFIG_ADFS_FS_RW is not set# CONFIG_AFFS_FS is not set# CONFIG_HFS_FS is not set# CONFIG_HFSPLUS_FS is not set# CONFIG_BEFS_FS is not set# CONFIG_BEFS_DEBUG is not set# CONFIG_BFS_FS is not set# CONFIG_EXT3_FS is not set# CONFIG_JBD is not set# CONFIG_JBD_DEBUG is not set# CONFIG_FAT_FS is not set# CONFIG_MSDOS_FS is not set# CONFIG_UMSDOS_FS is not set# CONFIG_VFAT_FS is not set# CONFIG_EFS_FS is not set# CONFIG_JFFS_FS is not set# CONFIG_JFFS2_FS is not set# CONFIG_CRAMFS is not set# CONFIG_TMPFS is not setCONFIG_RAMFS=y# CONFIG_ISO9660_FS is not set# CONFIG_JOLIET is not set# CONFIG_ZISOFS is not set# CONFIG_JFS_FS is not set# CONFIG_JFS_DEBUG is not set# CONFIG_JFS_STATISTICS is not set# CONFIG_MINIX_FS is not set# CONFIG_VXFS_FS is not set# CONFIG_NTFS_FS is not set# CONFIG_NTFS_RW is not set# CONFIG_HPFS_FS is not setCONFIG_PROC_FS=y# CONFIG_DEVFS_FS is not set# CONFIG_DEVFS_MOUNT is not set# CONFIG_DEVFS_DEBUG is not set# CONFIG_DEVPTS_FS is not set# CONFIG_QNX4FS_FS is not set# CONFIG_QNX4FS_RW is not setCONFIG_ROMFS_FS=yCONFIG_EXT2_FS=y# CONFIG_SYSV_FS is not set# CONFIG_UDF_FS is not set# CONFIG_UDF_RW is not set# CONFIG_UFS_FS is not set# CONFIG_UFS_FS_WRITE is not set# CONFIG_XFS_FS is not set# CONFIG_XFS_QUOTA is not set# CONFIG_XFS_RT is not set# CONFIG_XFS_TRACE is not set

36

# CONFIG_XFS_DEBUG is not set# CONFIG_NCPFS_NLS is not set# CONFIG_SMB_FS is not set# CONFIG_ZISOFS_FS is not set# CONFIG_COREDUMP_PRINTK is not set

## Partition Types## CONFIG_PARTITION_ADVANCED is not set# CONFIG_SMB_NLS is not set# CONFIG_NLS is not set

## Sound## CONFIG_SOUND is not set

## USB support## CONFIG_USB is not set

## Support for USB gadgets## CONFIG_USB_GADGET is not set

## Kernel hacking#CONFIG_FULLDEBUG=y# CONFIG_MAGIC_SYSRQ is not set# CONFIG_PROFILE is not set# CONFIG_NO_KERNEL_MSG is not set

## Cryptographic options## CONFIG_CRYPTO is not set

## Library routines## CONFIG_CRC32 is not setCONFIG_ZLIB_INFLATE=yCONFIG_ZLIB_DEFLATE=y

37

Cache Enabled: .config (uClinux-dist/linux-2.4.x/.config)## Automatically generated by make menuconfig: don't edit#CONFIG_UCLINUX=yCONFIG_UID16=yCONFIG_RWSEM_GENERIC_SPINLOCK=y# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set# CONFIG_ISA is not set# CONFIG_ISAPNP is not set# CONFIG_EISA is not set# CONFIG_MCA is not set

## Code maturity level options#CONFIG_EXPERIMENTAL=y

## Loadable module support## CONFIG_MODULES is not setCONFIG_MICROBLAZE=y

## Processor type and features## CONFIG_UCLINUX_AUTO is not setCONFIG_MBVANILLA=y# CONFIG_EGRET01 is not set# CONFIG_SUZAKU is not setCONFIG_CPU_CLOCK_FREQ=50000000CONFIG_MICROBLAZE_MSRSETCLR=yCONFIG_MICROBLAZE_HARD_MULT=yCONFIG_MICROBLAZE_HARD_DIV=yCONFIG_MICROBLAZE_HARD_BARREL=yCONFIG_MICROBLAZE_ICACHE=yCONFIG_MICROBLAZE_ICACHE_BASE=80000000CONFIG_MICROBLAZE_ICACHE_SIZE=2000CONFIG_MICROBLAZE_DCACHE=yCONFIG_MICROBLAZE_DCACHE_BASE=80000000CONFIG_MICROBLAZE_DCACHE_SIZE=2000CONFIG_MICROBLAZE_DEBUG_UART=yCONFIG_XILINX_GPIO=y# CONFIG_XILINX_ENET is not set# CONFIG_XILINX_SYSACE is not set# CONFIG_MBVANILLA_CMDLINE is not setCONFIG_ZERO_BSS=yCONFIG_MICROBLAZE_DEBUGGING=y

## General setup## CONFIG_NET is not set# CONFIG_DISK is not set

38

# CONFIG_HOTPLUG is not set# CONFIG_PCMCIA is not set# CONFIG_SYSVIPC is not set# CONFIG_BSD_PROCESS_ACCT is not set# CONFIG_SYSCTL is not setCONFIG_KCORE_ELF=y# CONFIG_KCORE_AOUT is not setCONFIG_BINFMT_FLAT=yCONFIG_BINFMT_ZFLAT=y# CONFIG_CONTIGUOUS_PAGE_ALLOC is not set# CONFIG_MEM_MAP is not set# CONFIG_NO_MMU_LARGE_ALLOCS is not set

## Memory Technology Devices (MTD)#CONFIG_MTD=yCONFIG_MTD_DEBUG=yCONFIG_MTD_DEBUG_VERBOSE=0CONFIG_MTD_PARTITIONS=y# CONFIG_MTD_CONCAT is not set# CONFIG_MTD_REDBOOT_PARTS is not set# CONFIG_MTD_CMDLINE_PARTS is not setCONFIG_MTD_CHAR=yCONFIG_MTD_BLOCK=y# CONFIG_FTL is not set# CONFIG_NFTL is not set# CONFIG_INFTL is not set

## RAM/ROM/Flash chip drivers#CONFIG_MTD_CFI=yCONFIG_MTD_JEDECPROBE=yCONFIG_MTD_GEN_PROBE=y# CONFIG_MTD_CFI_ADV_OPTIONS is not set# CONFIG_MTD_CFI_INTELEXT is not set# CONFIG_MTD_CFI_AMDSTD is not setCONFIG_MTD_CFI_STAA=yCONFIG_MTD_RAM=yCONFIG_MTD_ROM=y# CONFIG_MTD_ABSENT is not set# CONFIG_MTD_OBSOLETE_CHIPS is not set# CONFIG_MTD_AMDSTD is not set# CONFIG_MTD_SHARP is not set# CONFIG_MTD_JEDEC is not set# CONFIG_MTD_PSD4256G is not set

## Mapping drivers for chip access## CONFIG_MTD_PHYSMAP is not set# CONFIG_MTD_DRAGONIX is not set# CONFIG_MTD_NETtel is not set# CONFIG_MTD_SNAPGEODE is not set# CONFIG_MTD_NETteluC is not setCONFIG_MTD_MBVANILLA=y

39

# CONFIG_FLASHAUTO is not set# CONFIG_FLASH128KB is not set# CONFIG_FLASH1MB is not set# CONFIG_FLASH2MB is not setCONFIG_FLASH4MB=y# CONFIG_FLASH6MB is not set# CONFIG_FLASH8MB is not set# CONFIG_MTD_SUZAKU is not set# CONFIG_MTD_KeyTechnology is not set# CONFIG_MTD_SED_SIOSIII is not set# CONFIG_MTD_UCLINUX is not set# CONFIG_MTD_PCI is not set# CONFIG_MTD_PCMCIA is not set

## Self-contained MTD device drivers## CONFIG_MTD_PMC551 is not set# CONFIG_MTD_SLRAM is not set# CONFIG_MTD_MTDRAM is not set# CONFIG_MTD_BLKMTD is not set# CONFIG_MTD_DOC1000 is not set# CONFIG_MTD_DOC2000 is not set# CONFIG_MTD_DOC2001 is not set# CONFIG_MTD_DOC2001PLUS is not set# CONFIG_MTD_DOCPROBE is not set

## NAND Flash Device Drivers## CONFIG_MTD_NAND is not set

## Parallel port support## CONFIG_PARPORT is not set

## Block devices## CONFIG_BLK_DEV_FD is not set# CONFIG_BLK_DEV_XD is not set# CONFIG_PARIDE is not set# CONFIG_BLK_CPQ_DA is not set# CONFIG_BLK_CPQ_CISS_DA is not set# CONFIG_CISS_SCSI_TAPE is not set# CONFIG_CISS_MONITOR_THREAD is not set# CONFIG_BLK_DEV_DAC960 is not set# CONFIG_BLK_DEV_UMEM is not set# CONFIG_BLK_DEV_SX8 is not set# CONFIG_BLK_DEV_LOOP is not set# CONFIG_BLK_DEV_NBD is not setCONFIG_BLK_DEV_RAM=yCONFIG_BLK_DEV_RAM_SIZE=4096# CONFIG_BLK_DEV_INITRD is not set# CONFIG_BLK_DEV_RAMDISK_DATA is not set# CONFIG_BLK_DEV_BLKMEM is not set

40

# CONFIG_BLK_STATS is not set

## Character devices## CONFIG_LEDMAN is not set# CONFIG_SNAPDOG is not set# CONFIG_DS1302 is not set# CONFIG_M41T11M6 is not set# CONFIG_VT is not set# CONFIG_SERIAL is not set# CONFIG_SERIAL_EXTENDED is not set# CONFIG_SERIAL_NONSTANDARD is not set

## Serial drivers## CONFIG_SERIAL_8250 is not set# CONFIG_SERIAL_8250_CONSOLE is not set# CONFIG_SERIAL_8250_EXTENDED is not set# CONFIG_SERIAL_8250_MANY_PORTS is not set# CONFIG_SERIAL_8250_SHARE_IRQ is not set# CONFIG_SERIAL_8250_DETECT_IRQ is not set# CONFIG_SERIAL_8250_MULTIPORT is not set# CONFIG_SERIAL_8250_HUB6 is not set# CONFIG_UNIX98_PTYS is not set

## I2C support## CONFIG_I2C is not set

## Mice## CONFIG_BUSMOUSE is not set# CONFIG_MOUSE is not set# CONFIG_EDB7312_TS is not set

## Joysticks## CONFIG_INPUT_GAMEPORT is not set# CONFIG_INPUT_NS558 is not set# CONFIG_INPUT_LIGHTNING is not set# CONFIG_INPUT_PCIGAME is not set# CONFIG_INPUT_CS461X is not set# CONFIG_INPUT_EMU10K1 is not set# CONFIG_INPUT_SERIO is not set# CONFIG_INPUT_SERPORT is not set# CONFIG_INPUT_ANALOG is not set# CONFIG_INPUT_A3D is not set# CONFIG_INPUT_ADI is not set# CONFIG_INPUT_COBRA is not set# CONFIG_INPUT_GF2K is not set# CONFIG_INPUT_GRIP is not set# CONFIG_INPUT_INTERACT is not set

41

# CONFIG_INPUT_TMDC is not set# CONFIG_INPUT_SIDEWINDER is not set# CONFIG_INPUT_IFORCE_USB is not set# CONFIG_INPUT_IFORCE_232 is not set# CONFIG_INPUT_WARRIOR is not set# CONFIG_INPUT_MAGELLAN is not set# CONFIG_INPUT_SPACEORB is not set# CONFIG_INPUT_SPACEBALL is not set# CONFIG_INPUT_STINGER is not set# CONFIG_INPUT_DB9 is not set# CONFIG_INPUT_GAMECON is not set# CONFIG_INPUT_TURBOGRAFX is not set# CONFIG_QIC02_TAPE is not set# CONFIG_IPMI_HANDLER is not set# CONFIG_IPMI_PANIC_EVENT is not set# CONFIG_IPMI_DEVICE_INTERFACE is not set# CONFIG_IPMI_KCS is not set# CONFIG_IPMI_WATCHDOG is not set

## Controller Area Network Cards/Chips## CONFIG_CAN4LINUX is not set

## Watchdog Cards## CONFIG_WATCHDOG is not set# CONFIG_SCx200 is not set# CONFIG_SCx200_GPIO is not set# CONFIG_AMD_PM768 is not set# CONFIG_NVRAM is not set# CONFIG_RTC is not set# CONFIG_DTLK is not set# CONFIG_R3964 is not set# CONFIG_APPLICOM is not set

## Ftape, the floppy tape device driver## CONFIG_FTAPE is not set# CONFIG_AGP is not set

## Direct Rendering Manager (XFree86 DRI support)## CONFIG_DRM is not set

## Misc devices## CONFIG_MICROBLAZE_FSLFIFO is not set

## File systems## CONFIG_QUOTA is not set

42

# CONFIG_QFMT_V2 is not set# CONFIG_AUTOFS_FS is not set# CONFIG_AUTOFS4_FS is not set# CONFIG_REISERFS_FS is not set# CONFIG_REISERFS_CHECK is not set# CONFIG_REISERFS_PROC_INFO is not set# CONFIG_ADFS_FS is not set# CONFIG_ADFS_FS_RW is not set# CONFIG_AFFS_FS is not set# CONFIG_HFS_FS is not set# CONFIG_HFSPLUS_FS is not set# CONFIG_BEFS_FS is not set# CONFIG_BEFS_DEBUG is not set# CONFIG_BFS_FS is not set# CONFIG_EXT3_FS is not set# CONFIG_JBD is not set# CONFIG_JBD_DEBUG is not set# CONFIG_FAT_FS is not set# CONFIG_MSDOS_FS is not set# CONFIG_UMSDOS_FS is not set# CONFIG_VFAT_FS is not set# CONFIG_EFS_FS is not set# CONFIG_JFFS_FS is not set# CONFIG_JFFS2_FS is not set# CONFIG_CRAMFS is not set# CONFIG_TMPFS is not setCONFIG_RAMFS=y# CONFIG_ISO9660_FS is not set# CONFIG_JOLIET is not set# CONFIG_ZISOFS is not set# CONFIG_JFS_FS is not set# CONFIG_JFS_DEBUG is not set# CONFIG_JFS_STATISTICS is not set# CONFIG_MINIX_FS is not set# CONFIG_VXFS_FS is not set# CONFIG_NTFS_FS is not set# CONFIG_NTFS_RW is not set# CONFIG_HPFS_FS is not setCONFIG_PROC_FS=y# CONFIG_DEVFS_FS is not set# CONFIG_DEVFS_MOUNT is not set# CONFIG_DEVFS_DEBUG is not set# CONFIG_DEVPTS_FS is not set# CONFIG_QNX4FS_FS is not set# CONFIG_QNX4FS_RW is not setCONFIG_ROMFS_FS=yCONFIG_EXT2_FS=y# CONFIG_SYSV_FS is not set# CONFIG_UDF_FS is not set# CONFIG_UDF_RW is not set# CONFIG_UFS_FS is not set# CONFIG_UFS_FS_WRITE is not set# CONFIG_XFS_FS is not set# CONFIG_XFS_QUOTA is not set# CONFIG_XFS_RT is not set# CONFIG_XFS_TRACE is not set# CONFIG_XFS_DEBUG is not set

43

# CONFIG_NCPFS_NLS is not set# CONFIG_SMB_FS is not set# CONFIG_ZISOFS_FS is not set# CONFIG_COREDUMP_PRINTK is not set

## Partition Types## CONFIG_PARTITION_ADVANCED is not set# CONFIG_SMB_NLS is not set# CONFIG_NLS is not set

## Sound## CONFIG_SOUND is not set

## USB support## CONFIG_USB is not set

## Support for USB gadgets## CONFIG_USB_GADGET is not set

## Kernel hacking#CONFIG_FULLDEBUG=y# CONFIG_MAGIC_SYSRQ is not set# CONFIG_PROFILE is not set# CONFIG_NO_KERNEL_MSG is not set

## Cryptographic options## CONFIG_CRYPTO is not set

## Library routines## CONFIG_CRC32 is not setCONFIG_ZLIB_INFLATE=yCONFIG_ZLIB_DEFLATE=y

44

Flash Source

Flash.C/****c1481_08.c*32Mb Flash Memory***********************************************Filename: c1481_08.cDescription: Library routines for M29W320DB and M29W320DT32Mb (4Mb x8) Flash Memories.8 bit driver.Revision: 1.00Date: 26/10/01Author: Sylvia Goettl, STMicroelectronics (www.st.com)Copyright (c) 2001 STMicroelectronics.THIS PROGRAM IS PROVIDED “AS IS” WITHOUT WARRANTY OF ANY KIND, EITHEREXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTYOF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISKAS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THEPROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING,REPAIR OR CORRECTION.********************************************************************************Version History.Ver. Date Comments1.00 26/10/01 Initial Release of the Software.********************************************************************************This source file provides library C code for using the M29W320Dx devices.The following devices are supported in the code:M29W320DBM29W320DTThis file is used to access the devices in 8-bit mode only.A separate file is available for users who wish to access thedevice in 16 bit mode (c1481_16.c).The following functions are available in this library:FlashReadReset() to reset the flash for normal memory accessFlashAutoSelect() to get information about the deviceFlashBlockErase() to erase one or more blocksFlashChipErase() to erase the whole chipFlashProgram() to program a byte or an arrayFlashErrorStr() to return the error string of an errorFor further information consult the Data Sheet and the Application Note. TheApplication Note gives information about how to modify this code for aspecific application.The hardware specific functions which need to be modified by the user are:FlashWrite() for writing a byte to the flashFlashRead() for reading a byte from the flashFlashPause() for timing short pauses (in micro seconds)A list of the error conditions is given at the end of the code.There are no timeouts implemented in the loops in the code. At each pointwhere an infinite loop is implemented a comment /# TimeOut! #/ has beenplaced. It is up to the user to implement these to avoid the code hanginginstead of timing out.Since C does not include a method for disabling interrupts to keep timecriticalsections of code from being disabled. The user may wish to disable

45

interrupt during parts of the code to avoid the FLASH_MPU_TOO_SLOW error fromoccuring if an interrupt occurs at the wrong time. Where interrupt should bedisabled and re-enabled there is a /# DSI! #/ or /# ENI! #/ comment.The source code assumes that the compiler implements the numerical types asunsigned char 8 bitsunsigned int 16 bitsunsigned long 32 bitsAdditional changes to the code will be necessary if these are not correct.*******************************************************************************/#include "xparameters.h"

/* Header file with global prototypes */#include "flash.h"

#ifdef USING_FLASH

#include <stdlib.h>#define USE_M29W320DB/*******************************************************************************Constants*******************************************************************************/#define COUNTS_PER_MICROSECOND (200)#define MANUFACTURER_ST (0x20) /* Manufacturer code */#define BASE_ADDR ((volatile unsigned char*)0x81400000)/* BASE_ADDR is the base address of the flash, see the functions FlashRead()and FlashWrite(). Some applications which require a more complicatedFlashRead() or FlashWrite() may not use BASE_ADDR */#define ANY_ADDR (0x0000L)/* Any address offset within the Flash Memory will do */

// #ifdef USE_M29W320DB we are using this one#define EXPECTED_DEVICE (0xCB) /* Device code for the M29W320DB */

/* Block organisation for Bottom Boot Block devices */static const unsigned long BlockOffset[] ={0x000000L, /* Start offset of block 0 */0x004000L, /* Start offset of block 1 */0x006000L, /* Start offset of block 2 */0x008000L, /* Start offset of block 3 */0x010000L, /* Start offset of block 4 */0x020000L, /* Start offset of block 5 */0x030000L, /* Start offset of block 6 */0x040000L, /* Start offset of block 7 */0x050000L, /* Start offset of block 8 */0x060000L, /* Start offset of block 9 */0x070000L, /* Start offset of block 10 */0x080000L, /* Start offset of block 11 */0x090000L, /* Start offset of block 12 */0x0A0000L, /* Start offset of block 13 */0x0B0000L, /* Start offset of block 14 */0x0C0000L, /* Start offset of block 15 */0x0D0000L, /* Start offset of block 16 */

46

0x0E0000L, /* Start offset of block 17 */0x0F0000L, /* Start offset of block 18 */0x100000L, /* Start offset of block 19 */0x110000L, /* Start offset of block 20 */0x120000L, /* Start offset of block 21 */0x130000L, /* Start offset of block 22 */0x140000L, /* Start offset of block 23 */0x150000L, /* Start offset of block 24 */0x160000L, /* Start offset of block 25 */0x170000L, /* Start offset of block 26 */0x180000L, /* Start offset of block 27 */0x190000L, /* Start offset of block 28 */0x1A0000L, /* Start offset of block 29 */0x1B0000L, /* Start offset of block 30 */0x1C0000L, /* Start offset of block 31 */0x1D0000L, /* Start offset of block 32 */0x1E0000L, /* Start offset of block 33 */0x1F0000L, /* Start offset of block 34 */0x200000L, /* Start offset of block 35 */0x210000L, /* Start offset of block 36 */0x220000L, /* Start offset of block 37 */0x230000L, /* Start offset of block 38 */0x240000L, /* Start offset of block 39 */0x250000L, /* Start offset of block 40 */0x260000L, /* Start offset of block 41 */0x270000L, /* Start offset of block 42 */0x280000L, /* Start offset of block 43 */0x290000L, /* Start offset of block 44 */0x2A0000L, /* Start offset of block 45 */0x2B0000L, /* Start offset of block 46 */0x2C0000L, /* Start offset of block 47 */0x2D0000L, /* Start offset of block 48 */0x2E0000L, /* Start offset of block 49 */0x2F0000L, /* Start offset of block 50 */0x300000L, /* Start offset of block 51 */0x310000L, /* Start offset of block 52 */0x320000L, /* Start offset of block 53 */0x330000L, /* Start offset of block 54 */0x340000L, /* Start offset of block 55 */0x350000L, /* Start offset of block 56 */0x360000L, /* Start offset of block 57 */0x370000L, /* Start offset of block 58 */0x380000L, /* Start offset of block 59 */0x390000L, /* Start offset of block 60 */0x3A0000L, /* Start offset of block 61 */0x3B0000L, /* Start offset of block 62 */0x3C0000L, /* Start offset of block 63 */0x3D0000L, /* Start offset of block 64 */0x3E0000L, /* Start offset of block 65 */0x3F0000L /* Start offset of block 66 */};

#define NUM_BLOCKS (sizeof(BlockOffset)/sizeof(BlockOffset[0]))#define FLASH_SIZE (0x400000L) /* 4M *//*******************************************************************************

47

Static PrototypesThe following functions are only needed in this module.*******************************************************************************/static unsigned char FlashWrite( unsigned long ulOff, unsigned char ucVal );static void FlashPause( unsigned int uMicroSeconds );static int FlashDataToggle( void );static int FlashBlockFailedErase( unsigned char ucBlock );/******************************************************************************The function FlashDataPoll() declared below is not used by this library but isprovided as an illustration of the Data Polling Flow Chart*******************************************************************************/#define ILLUSTRATION_ONLY#ifndef ILLUSTRATION_ONLYstatic int FlashDataPoll( unsigned long ulOff, unsigned char ucVal );#endif /* !ILLUSTRATION_ONLY */

/*******************************************************************************Function: unsigned char FlashWrite( unsigned long ulOff, unsigned char ucVal)Arguments: ulOff is the byte offset in the flash to write toucVal is the value to be writtenReturns: ucValDescription: This function is used to write a byte to the flash. On manymicroprocessor systems a macro can be used instead, increasing the speed ofthe flash routines. For example:#define FlashWrite( ulOff, ucVal ) ( BASE_ADDR[ulOff] = (unsigned char) ucVal )A function is used here instead to allow the user to expand it if necessary.The function is made to return ucVal so that it is compatible with the macro.Pseudo Code:Step 1: Write ucVal to the byte offset in the flashStep 2: return ucVal*******************************************************************************/static unsigned char FlashWrite( unsigned long ulOff, unsigned char ucVal ){/* Step1, 2: Write ucVal to the byte offset in the flash and return it */return BASE_ADDR[ulOff] = ucVal;}/*******************************************************************************Function: unsigned char FlashRead( unsigned long ulOff )Arguments: ulOff is the byte offset into the flash to read fromReturns: The unsigned char at the byte offsetDescription: This function is used to read a byte from the flash. On manymicroprocessor systems a macro can be used instead, increasing the speed ofthe flash routines. For example:#define FlashRead( ulOff ) ( BASE_ADDR[ulOff] )A function is used here instead to allow the user to expand it if necessary.Pseudo Code:Step 1: Return the value at byte offset ulOff

48

*******************************************************************************/unsigned char FlashRead( unsigned long ulOff ){/* Step 1 Return the value at byte offset ulOff */return BASE_ADDR[ulOff];}/*******************************************************************************Function: void FlashPause( unsigned int uMicroSeconds )Arguments: uMicroSeconds is the length of the pause in microsecondsReturns: noneDescription: This routine returns after uMicroSeconds have elapsed. It is usedin several parts of the code to generate a pause required for correctoperation of the flash part.The routine here works by counting. The user may already have a more suitableroutine for timing which can be used.Pseudo Code:Step 1: Compute count size for pause.Step 2: Count to the required size.*******************************************************************************/static void FlashPause( unsigned int uMicroSeconds ){volatile unsigned long ulCountSize;/* Step 1: Compute the count size */ulCountSize = (unsigned long)uMicroSeconds * COUNTS_PER_MICROSECOND;/* Step 2: Count to the required size */while( ulCountSize > 0 ) /* Test to see if finished */ulCountSize--; /* and count down */}/*******************************************************************************Function: void FlashReadReset( void )Arguments: noneReturn Value: noneDescription: This function places the flash in the Read mode describedin the Data Sheet. In this mode the flash can be read as normal memory.All of the other functions leave the flash in the Read mode so this isnot strictly necessary. It is provided for completeness.Note: A wait of 10us is required if the command is called during a program orerase instruction. This is included here to guarantee correct operation. Thefunctions in this library call this function if they suspect an errorduring programming or erasing so that the 10us pause is included. Otherwisethey use the single instruction technique for increased speed.Pseudo Code:Step 1: write command sequence (see Commands Table of the Data Sheet)Step 2: wait 10us*******************************************************************************/void FlashReadReset( void ){/* Step 1: write command sequence */FlashWrite( 0x0AAAL, 0xAA ); /* 1st Cycle */FlashWrite( 0x0555L, 0x55 ); /* 2nd Cycle */

49

FlashWrite( ANY_ADDR, 0xF0 ); /* 3rd Cycle: write 0xF0 to ANY address *//* Step 2: wait 10us */FlashPause( 10 );}/*******************************************************************************Function: int FlashAutoSelect( int iFunc )Arguments: iFunc should be set either to the Read Signature values or to theblock number. The header file defines the values for reading the Signature.Note: the first block is Block 0Return Value: When iFunc is >= 0 the function returns FLASH_BLOCK_PROTECTED(01h) if the block is protected and FLASH_BLOCK_UNPROTECTED (00h) if it isunprotected. See the Auto Select command in the Data Sheet for furtherinformation.When iFunc is FLASH_READ_MANUFACTURER (-2) the function returns themanufacturer’s code. The Manufacturer code for ST is 20h.When iFunc is FLASH_READ_DEVICE_CODE (-1) the function returns the DeviceCode. The device codes for the parts are:M29W320DT CAhM29W320DB CBhWhen iFunc is invalid the function returns FLASH_BLOCK_INVALID (-5)Description: This function can be used to read the electronic signature of thedevice, the manufacturer code or the protection level of a block.Pseudo Code:Step 1: Send the Auto Select command to the deviceStep 2: Read the required function from the device.Step 3: Return the device to Read mode.*******************************************************************************/int FlashAutoSelect( int iFunc ){int iRetVal; /* Holds the return value *//* Step 1: Send the Auto Select command */FlashWrite( 0x0AAAL, 0xAA ); /* 1st Cycle */FlashWrite( 0x0555L, 0x55 ); /* 2nd Cycle */FlashWrite( 0x0AAAL, 0x90 ); /* 3rd Cycle *//* Step 2: Read the required function */if( iFunc == FLASH_READ_MANUFACTURER )iRetVal = (int) FlashRead( 0x0000L ); /* A0 = A1 = 0 */else if( iFunc == FLASH_READ_DEVICE_CODE )iRetVal = (int) FlashRead( 0x0002L ); /* A0 = 1, A1 = 0, remember A-1 */else if( (iFunc >= 0) && (iFunc < NUM_BLOCKS) )iRetVal = FlashRead( BlockOffset[iFunc] + 0x0004L );/* A0 = 0, A1 = 1, remember A-1 */elseiRetVal = FLASH_BLOCK_INVALID;/* Step 3: Return to Read mode */FlashWrite( ANY_ADDR, 0xF0 ); /* Use single instruction cycle method */return iRetVal;}/*******************************************************************************Function: int FlashBlockErase( unsigned char ucNumBlocks,unsigned char ucBlock[] )Arguments: ucNumBlocks holds the number of blocks in the array ucBlock

50

ucBlock is an array containing the blocks to be erased.Return Value: The function returns the following conditions:FLASH_SUCCESS (-1)FLASH_TOO_MANY_BLOCKS (-3)FLASH_MPU_TOO_SLOW (-4)FLASH_WRONG_TYPE (-8)FLASH_ERASE_FAIL (-14)Number of the first protected or invalid blockThe user’s array, ucBlock[] is used to report errors on the specifiedblocks. If a time-out occurs because the MPU is too slow then the blocksin ucBlocks which are not erased are overwritten with FLASH_BLOCK_NOT_ERASED(FFh) and the function returns FLASH_MPU_TOO_SLOW.If an error occurs during the erasing of the blocks the function returnsFLASH_ERASE_FAIL.If both errors occur then the function will set the ucBlock array toFLASH_BLOCK_NOT_ERASED for the unerased blocks. It will returnFLASH_ERASE_FAIL even though the FLASH_MPU_TOO_SLOW has also occurred.Description: This function erases up to ucNumBlocks in the flash. The blockscan be listed in any order. The function does not return until the blocks areerased. If any blocks are protected or invalid none of the blocks are erased.During the Erase Cycle the Data Toggle Flow Chart of the Data Sheet isfollowed. The polling bit, DQ7, is not used.Pseudo Code:Step 1: Check for correct flash typeStep 2: Check for protected or invalid blocksStep 3: Write Block Erase commandStep 4: Check for time-out blocksStep 5: Wait for the timer bit to be set.Step 6: Follow Data Toggle Flow Chart until Program/Erase Controller hascompletedStep 7: Return to Read mode (if an error occurred)*******************************************************************************/int FlashBlockErase( unsigned char ucNumBlocks, unsigned char ucBlock[] ){

unsigned char ucCurBlock; /* Range Variable to track current block */int iRetVal = FLASH_SUCCESS; /* Holds return value: optimistic

initially! */unsigned char ucFirstRead, ucSecondRead; /* used to check toggle bit DQ2

*/

/* Step 1: Check for correct flash type */if( !(FlashAutoSelect( FLASH_READ_MANUFACTURER ) == MANUFACTURER_ST)|| !(FlashAutoSelect( FLASH_READ_DEVICE_CODE ) == EXPECTED_DEVICE ) )

return FLASH_WRONG_TYPE;/* Step 2: Check for protected or invalid blocks. */if( ucNumBlocks > NUM_BLOCKS ) /* Check specified blocks <= NUM_BLOCKS

*/return FLASH_TOO_MANY_BLOCKS;

for( ucCurBlock = 0; ucCurBlock < ucNumBlocks; ucCurBlock++ ){

/* Use FlashAutoSelect to find protected or invalid blocks */if( FlashAutoSelect((int)ucBlock[ucCurBlock]) !=

FLASH_BLOCK_UNPROTECTED )return (int)ucBlock[ucCurBlock]; /* Return protected/invalid

blocks */}

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/* Step 3: Write Block Erase command */FlashWrite( 0x0AAAL, 0xAA );FlashWrite( 0x0555L, 0x55 );FlashWrite( 0x0AAAL, 0x80 );FlashWrite( 0x0AAAL, 0xAA );FlashWrite( 0x0555L, 0x55 );/* DSI!: Time critical section. Additional blocks must be added every

50us */for( ucCurBlock = 0; ucCurBlock < ucNumBlocks; ucCurBlock++ ){

FlashWrite( BlockOffset[ucBlock[ucCurBlock]], 0x30 );/* Check for Erase Timeout Period (is bit DQ3 set?) */if( (FlashRead( BlockOffset[ucBlock[0]] ) & 0x08) == 0x08 )break; /* Cannot set any more blocks due to timeout */

}/* ENI! *//* Step 4: Check for time-out blocks *//* if timeout occurred then check if current block is erasing or not *//* Use DQ2 of status register, toggle implies block is erasing */if( ucCurBlock < ucNumBlocks ){

ucFirstRead = FlashRead( BlockOffset[ucBlock[ucCurBlock]] ) & 0x04;

ucSecondRead = FlashRead( BlockOffset[ucBlock[ucCurBlock]] ) & 0x04;

if( ucFirstRead != ucSecondRead ){

ucCurBlock++; /* Point to the next block */}if( ucCurBlock < ucNumBlocks ){

/* Indicate that some blocks have been timed out of the erase list */

iRetVal = FLASH_MPU_TOO_SLOW;}/* Now specify all other blocks as not being erased */while( ucCurBlock < ucNumBlocks ){

ucBlock[ucCurBlock++] = FLASH_BLOCK_NOT_ERASED;}

}/* Step 5: Wait for the Erase Timer Bit (DQ3) to be set */while( 1 ) /* TimeOut!: If, for some reason, the hardware fails then

thisloop may not exit. Use a timer function to implement a timeoutfrom the loop. */{

if( ( FlashRead( BlockOffset[ucBlock[0]] ) & 0x08 ) == 0x08 )break; /* Break when device starts the erase cycle */

}/* Step 6: Follow Data Toggle Flow Chart until Program/Erase Controllercompletes */if( FlashDataToggle() != FLASH_SUCCESS ){

iRetVal = FLASH_ERASE_FAIL;/* Step 7: Return to Read mode (if an error occurred) */FlashReadReset();

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}return iRetVal;

}/*******************************************************************************Function: int FlashChipErase( unsigned char *ucResults )Arguments: ucResults is a pointer to an array where the results will bestored. If ucResults == NULL then no results are stored. Otherwise theresults are written to the array if an error occurs. The array is leftunchanged if the function returns FLASH_SUCCESS.The errors written to the array are:FLASH_BLOCK_ERASED (FDh) if the block erased correctlyFLASH_BLOCK_ERASE_FAILURE (FEh) if the block failed to erasedReturn Value: On success the function returns FLASH_SUCCESS (-1)If a block is protected then the function returns the number of the block andno blocks are erased.If the erase algorithms fails then the function returns FLASH_ERASE_FAIL (-2)If the wrong type of flash is detected then FLASH_WRONG_TYPE (-8) isreturned.Description: The function can be used to erase the whole flash chip so long asno blocks are protected. If any blocks are protected then nothing iserased.Pseudo Code:Step 1: Check for correct flash typeStep 2: Check that all blocks are unprotectedStep 3: Send Chip Erase CommandStep 4: Follow Data Toggle Flow Chart until Program/Erase Controller hascompleted.Step 5: Check for blocks erased correctlyStep 6: Return to Read mode (if an error occurred)*******************************************************************************/int FlashChipErase( unsigned char *ucResults ){

unsigned char ucCurBlock; /* Used to track the current block in a range */

int iRetVal = FLASH_SUCCESS; /* Holds return value: optimistic initially! */


return FLASH_WRONG_TYPE;

/* Step 2: Check that all blocks are unprotected */// Burnette: block 0 is protected so don't try to read it.for( ucCurBlock = 1; ucCurBlock < NUM_BLOCKS; ucCurBlock++ ){

if( FlashAutoSelect( (int)ucCurBlock ) != FLASH_BLOCK_UNPROTECTED )

{ucResults[0] = FLASH_FOUND_PROTECTED_BLOCK;return (int)ucCurBlock; /* Return the first protected block

*/}

}

53

/* Step 3: Send Chip Erase Command */FlashWrite( 0x0AAAL, 0xAA );FlashWrite( 0x0555L, 0x55 );FlashWrite( 0x0AAAL, 0x80 );FlashWrite( 0x0AAAL, 0xAA );FlashWrite( 0x0555L, 0x55 );FlashWrite( 0x0AAAL, 0x10 );

/* Step 4: Follow Data Toggle Flow Chart until Program/Erase Controller has

completed */if( FlashDataToggle() != FLASH_SUCCESS ){

iRetVal = FLASH_ERASE_FAIL;}/* Step 5: Check for blocks erased correctly */if( iRetVal != FLASH_SUCCESS && ucResults != NULL ){

// Burnette: block 0 is protected so don't try to read it.for( ucCurBlock = 1; ucCurBlock < NUM_BLOCKS; ucCurBlock++ ){

if( FlashBlockFailedErase( ucCurBlock ) == FLASH_BLOCK_FAILED_ERASE )

//ucResults[ucCurBlock] = FLASH_BLOCK_ERASE_FAILURE;ucResults[0] = FLASH_BLOCK_ERASE_FAILURE;

elseucResults[0] = FLASH_BLOCK_ERASED;//ucResults[ucCurBlock] = FLASH_BLOCK_ERASED;

}}/* Step 6: Return to Read mode (if an error occurred) */if( iRetVal != FLASH_SUCCESS )

FlashReadReset();

return iRetVal;}/*******************************************************************************Function: int FlashProgram( unsigned long ulOff, size_t NumBytes,void *Array )Arguments: ulOff is the byte offset into the flash to be programmedNumBytes holds the number of bytes in the array.Array is a pointer to the array to be programmed.Return Value: The function returns the following conditions:FLASH_SUCCESS (-1)FLASH_PROGRAM_FAIL (-6)FLASH_OFFSET_OUT_OF_RANGE (-7)FLASH_WRONG_TYPE (-8)Number of the first protected or invalid blockOn success the function returns FLASH_SUCCESS (-1).The function returns FLASH_PROGRAM_FAIL (-6) if a programming failure occurs.If the address range to be programmed exceeds the address range of the FlashDevice the function returns FLASH_OFFSET_OUT_OF_RANGE (-7) and nothing isprogrammed.If the wrong type of flash is detected then FLASH_WRONG_TYPE (-8) isreturned and nothing is programmed.

54

If part of the address range to be programmed falls within a protected block,the function returns the number of the first protected block encountered andnothing is programmed.Description: This function is used to program an array into the flash. It doesnot erase the flash first and may fail if the block(s) are not erased first.Pseudo Code:Step 1: Check for correct flash typeStep 2: Check the offset range is validStep 3: Check that the block(s) to be programmed are not protectedStep 4: While there is more to be programmedStep 5: Check for changes from ‘0’ to ‘1’Step 6: Program the next byteStep 7: Follow Data Toggle Flow Chart until Program/Erase Controller hascompletedStep 8: Return to Read Mode (if an error occurred)Step 9: Update pointers*******************************************************************************/int FlashProgram( unsigned long ulOff, unsigned int NumBytes, void *Array ){

unsigned char *ucArrayPointer; /* Use an unsigned char to access the array */

unsigned long ulLastOff; /* Holds the last offset to be programmed */unsigned char ucCurBlock; /* Range Variable to track current block */


return FLASH_WRONG_TYPE;

/* Step 2: Check the offset and range are valid */ulLastOff = ulOff+NumBytes-1;if( ulLastOff >= FLASH_SIZE )

return FLASH_OFFSET_OUT_OF_RANGE;

/* Step 3: Check that the block(s) to be programmed are not protected */for( ucCurBlock = 0; ucCurBlock < NUM_BLOCKS; ucCurBlock++ ){

/* If the address range to be programmed ends before this block */if( BlockOffset[ucCurBlock] > ulLastOff )

break; /* then we are done *//* Else if the address range starts beyond this block */else if( (ucCurBlock < (NUM_BLOCKS-1)) &&

(ulOff >= BlockOffset[ucCurBlock+1]) )continue; /* then skip this block *//* Otherwise if this block is not unprotected */else if( FlashAutoSelect((int)ucCurBlock) !=

FLASH_BLOCK_UNPROTECTED )return (int)ucCurBlock; /* Return first protected block */

}

/* Step 4: While there is more to be programmed */ucArrayPointer = (unsigned char *)Array;while( ulOff <= ulLastOff ){

/* Step 5: Check for changes from ‘0’ to ‘1’ */if( ~FlashRead( ulOff ) & *ucArrayPointer )

55

/* Indicate failure as it is not possible to change a ‘0’ to a ‘1’using a Program command. This must be done using an Erase command

*/return FLASH_PROGRAM_FAIL;

/* Step 6: Program the next byte */FlashWrite( 0x0AAAL, 0xAA ); /* 1st cycle */FlashWrite( 0x0555L, 0x55 ); /* 2nd cycle */FlashWrite( 0x0AAAL, 0xA0 ); /* Program command */FlashWrite( ulOff, *ucArrayPointer ); /* Program value */

/* Step 7: Follow Data Toggle Flow Chart until Program/Erase Controller

has completed *//* See Data Toggle Flow Chart of the Data Sheet */if( FlashDataToggle() == FLASH_TOGGLE_FAIL ){

/* Step 8: Return to Read Mode (if an error occurred) */FlashReadReset();return FLASH_PROGRAM_FAIL;

}

/* Step 9: Update pointers */ulOff++;ucArrayPointer++;

}return FLASH_SUCCESS;

}/*******************************************************************************Function: static int FlashDataToggle( void )Arguments: noneReturn Value: The function returns FLASH_SUCCESS if the Program/Erase Controlleris successful or FLASH_TOGGLE_FAIL if there is a problem.Description: The function is used to monitor the Program/Erase Controller duringerase or program operations. It returns when the Program/Erase Controller hascompleted. In the Data Sheets, the Data Toggle Flow Chart shows the operationof the function.Pseudo Code:Step 1: Read DQ6 (into a byte)Step 2: Read DQ5 and DQ6 (into another byte)Step 3: If DQ6 did not toggle between the two reads then return FLASH_SUCCESSStep 4: Else if DQ5 is zero then operation is not yet complete, goto 1Step 5: Else (DQ5 != 0), read DQ6 againStep 6: If DQ6 did not toggle between the last two reads then returnFLASH_SUCCESSStep 7: Else return FLASH_TOGGLE_FAIL*******************************************************************************/static int FlashDataToggle( void ){unsigned char uc1, uc2; /* hold values read from any address offset withinthe Flash Memory */while( 1 ) /* TimeOut!: If, for some reason, the hardware fails then this

56

loop may not exit. Use a timer function to implement a timeoutfrom the loop. */{/* Step 1: Read DQ6 (into a byte) */uc1 = FlashRead( ANY_ADDR ); /* Read DQ6 from the Flash (any address) *//* Step 2: Read DQ5 and DQ6 (into another byte) */uc2 = FlashRead( ANY_ADDR ); /* Read DQ5 and DQ6 from the Flash (anyaddress) *//* Step 3: If DQ6 did not toggle between the two reads then returnFLASH_SUCCESS */if( (uc1&0x40) == (uc2&0x40) ) /* DQ6 == NO Toggle */return FLASH_SUCCESS;/* Step 4: Else if DQ5 is zero then operation is not yet complete */if( (uc2&0x20) == 0x00 )continue;/* Step 5: Else (DQ5 == 1), read DQ6 again */uc1 = FlashRead( ANY_ADDR ); /* Read DQ6 from the Flash (any address) *//* Step 6: If DQ6 did not toggle between the last two reads thenreturn FLASH_SUCCESS */if( (uc2&0x40) == (uc1&0x40) ) /* DQ6 == NO Toggle */return FLASH_SUCCESS;/* Step 7: Else return FLASH_TOGGLE_FAIL */else /* DQ6 == Toggle here means fail */return FLASH_TOGGLE_FAIL;} /* end of while loop */}#ifndef ILLUSTRATION_ONLY/*******************************************************************************Function: static int FlashDataPoll( unsigned long ulOff,unsigned char ucVal )Arguments: ulOff should hold a valid offset to be polled. For programmingthis will be the offset of the byte being programmed. For erasing this canbe any offset in the block(s) being erased.ucVal should hold the value being programmed. A value of FFh should be usedwhen erasing.Return Value: The function returns FLASH_SUCCESS if the Program/Erase Controlleris successful or FLASH_POLL_FAIL if there is a problem.Description: The function is used to monitor the Program/Erase Controller duringerase or program operations. It returns when the Program/Erase Controller hascompleted. In the Data Sheets, the Data Toggle Flow Chart shows the operationof the function.Note: this library does not use the Data Polling Flow Chart to assess thecorrect operation of Program/Erase Controller, but uses the Data Toggle FlowChart instead. The FlashDataPoll() function is only provided here as anillustration of the Data Polling Flow Chart in the Data Sheet.The code uses the function FlashDataToggle() instead.Pseudo Code:Step 1: Read DQ5 and DQ7 (into a byte)Step 2: If DQ7 is the same as ucVal(bit 7) then return FLASH_SUCCESSStep 3: Else if DQ5 is zero then operation is not yet complete, goto 1Step 4: Else (DQ5 != 0), Read DQ7Step 5: If DQ7 is now the same as ucVal(bit 7) then return FLASH_SUCCESSStep 6: Else return FLASH_POLL_FAIL

57

*******************************************************************************/static int FlashDataPoll( unsigned long ulOff, unsigned char ucVal ){unsigned char uc; /* holds value read from valid address */while( 1 ) /* TimeOut!: If, for some reason, the hardware fails then thisloop may not exit. Use a timer function to implement a timeoutfrom the loop. */{/* Step 1: Read DQ5 and DQ7 (into a byte) */uc = FlashRead( ulOff ); /* Read DQ5, DQ7 at valid addr *//* Step 2: If DQ7 is the same as ucVal(bit 7) then return FLASH_SUCCESS */if( (uc&0x80) == (ucVal&0x80) ) /* DQ7 == DATA */return FLASH_SUCCESS;/* Step 3: Else if DQ5 is zero then operation is not yet complete */if( (uc&0x20) == 0x00 )continue;/* Step 4: Else (DQ5 == 1) */uc = FlashRead( ulOff ); /* Read DQ7 at valid addr *//* Step 5: If DQ7 is now the same as ucVal(bit 7) thenreturn FLASH_SUCCESS */if( (uc&0x80) == (ucVal&0x80) ) /* DQ7 == DATA */return FLASH_SUCCESS;/* Step 6: Else return FLASH_POLL_FAIL */else /* DQ7 != DATA here means fail */return FLASH_POLL_FAIL;} /* end of while loop */}#endif /* !ILLUSTRATION_ONLY *//*******************************************************************************Function: int FlashBlockFailedErase( unsigned char ucBlock )Arguments: ucBlock specifies the block to be checkedReturn Value: FLASH_SUCCESS (-1) if the block erased successfullyFLASH_BLOCK_FAILED_ERASE (-9) if the block failed to eraseDescription: This function can only be called after an erase operation whichhas failed the FlashDataPoll() function. It must be called before the resetis made.The function reads bit 2 of the Status Register to determine if the blockhas erased successfully or not. Successfully erased blocks should have DQ2set to 1 following the erase. Failed blocks will have DQ2 toggle.Pseudo Code:Step 1: Read DQ2 in the block twiceStep 2: If they are both the same then return FLASH_SUCCESSStep 3: Else return FLASH_BLOCK_FAILED_ERASE*******************************************************************************/static int FlashBlockFailedErase( unsigned char ucBlock ){unsigned char ucFirstRead, ucSecondRead; /* Two variables used for clarity,Optimiser will probably not use any *//* Step 1: Read block twice */ucFirstRead = FlashRead( BlockOffset[ucBlock] ) & 0x04;ucSecondRead = FlashRead( BlockOffset[ucBlock] ) & 0x04;/* Step 2: If they are the same return FLASH_SUCCESS */if( ucFirstRead == ucSecondRead )

58

return FLASH_SUCCESS;/* Step 3: Else return FLASH_BLOCK_FAILED_ERASE */return FLASH_BLOCK_FAILED_ERASE;}/*******************************************************************************Function: char *FlashErrorStr( int iErrNum );Arguments: iErrNum is the error number returned from another Flash RoutineReturn Value: A pointer to a string with the error messageDescription: This function is used to generate a text string describing theerror from the flash. Call with the return value from another flash routine.Pseudo Code:Step 1: Check the error message range.Step 2: Return the correct string.*******************************************************************************/char * FlashErrorStr( int iErrNum ){static char *str[] = { "Flash Success","Flash Poll Failure","Flash Too Many Blocks","MPU is too slow to erase all the blocks","Flash Block selected is invalid","Flash Program Failure","Flash Address Offset Out Of Range","Flash is of Wrong Type","Flash Block Failed Erase","Flash is Unprotected","Flash is Protected","Flash function not supported","Flash Vpp Invalid","Flash Erase Fail","Flash Toggle Flow Chart Failure"};

/* Step 1: Check the error message range */iErrNum = -iErrNum - 1; /* All errors are negative: make +ve & adjust */if( iErrNum < 0 || iErrNum >= sizeof(str)/sizeof(str[0])) /* Check range

*/return "Unknown Error\n";

/* Step 2: Return the correct string */else

return str[iErrNum];}/*******************************************************************************List of Errors and Return values, Explanations and Help.********************************************************************************Return Name: Flash_SUCCESSReturn Value: -1Description: This value indicates that the flash command has executedcorrectly.********************************************************************************

59

Error Name: Flash_POLL_FAILNotes: The Data Polling Flow Chart, which applies to M29 series Flashonly, is not used in this library. The function FlashDataPoll() is onlyprovided as an illustration of the Data Polling Flow Chart. This errorcondition should not occur when using this library.Return Value: -2Description: The Program/Erase Controller algorithm has not managed to completethe command operation successfully. This may be because the device is damagedSolution: Try the command again. If it fails a second time then it islikely that the device will need to be replaced.********************************************************************************Error Name: Flash_TOO_MANY_BLOCKSNotes: Applies to M29 series Flash only.Return Value: -3Description: The user has chosen to erase more blocks than the device has.This may be because the array of blocks to erase contains the same blockmore than once.Solutions: Check that the program is trying to erase valid blocks. The devicewill only have NUM_BLOCKS blocks (defined at the top of the file). Also checkthat the same block has not been added twice or more to the array.********************************************************************************Error Name: Flash_MPU_TOO_SLOWNotes: Applies to M29 series Flash only.Return Value: -4Description: The MPU has not managed to write all of the selected blocks to thedevice before the timeout period expired. See BLOCK ERASE COMMANDsection of the Data Sheet for details.Solutions: If this occurs occasionally then it may be because an interrupt isoccuring between writing the blocks to be erased. Search for “DSI!” inthe code and disable interrupts during the time critical sections.If this error condition always occurs then it may be time for a fastermicroprocessor, a better optimising C compiler or, worse still, learnassembly. The immediate solution is to only erase one block at a time.Disable the test (by #define’ing out the code) and always call the functionwith one block at a time.********************************************************************************Error Name: Flash_BLOCK_INVALIDReturn Value: -5Description: A request for an invalid block has been made. Valid blocks numberfrom 0 to NUM_BLOCKS-1.Solution: Check that the block is in the valid range.********************************************************************************Error Name: Flash_PROGRAM_FAILReturn Value: -6Description: The programmed value has not been programmed correctly.Solutions: Make sure that the block containing the value was erased beforeprogramming. Try erasing the block and re-programming the value. If it failsagain then the device may need to be changed.********************************************************************************Error Name: Flash_OFFSET_OUT_OF_RANGE

60

Return Value: -7Description: The address offset given is out of the range of the device.Solution: Check that the address offset is in the valid range.********************************************************************************Error Name: Flash_WRONG_TYPEReturn Value: -8Description: The source code has been used to access the wrong type of flash.Solutions: Use a different flash chip with the target hardware or contactSTMicroelectronics for a different source code library.********************************************************************************Error Name: Flash_BLOCK_FAILED_ERASEReturn Value: -9Description: The previous erase to this block has not managed to successfullyerase the block.Solution: Sadly the flash needs replacing.********************************************************************************Return Name: Flash_UNPROTECTEDNotes: Applies to some M29 series Flash only. This condition should notoccur when using this library.Return Value: -10Description: The user has requested to unprotect a flash that is alreadyunprotected or the user has requested to re-protect a flash that has noprotected blocks. This is just a warning to the user that their operationdid not make any changes and was not necessary.********************************************************************************Return Name: Flash_PROTECTEDNotes: This condition should not occur when using this library.Return Value: -11Description: The user has requested to protect a flash that is alreadyprotected. This is just a warning to the user that their operation didnot make any changes and was not necessary.********************************************************************************Return Name: Flash_FUNCTION_NOT_SUPPORTEDNotes: This condition should not occur when using this library.Return Value: -12Description: The user has attempted to make use of functionality notavailable on this flash device (and thus not provided by the softwaredrivers). This is simply a warning to the user.********************************************************************************Error Name: Flash_VPP_INVALIDNotes: Applies to M28 series Flash only. This error condition should notoccur when using this library.Return Value: -13Description: A Program or a Block Erase has been attempted with the Vpp supplyvoltage outside the allowed ranges. This command had no effect since aninvalid Vpp has the effect of protecting the whole of the flash device.Solution: The (hardware) configuration of Vpp will need to be modified tomake programming or erasing the device possible.********************************************************************************Error Name: Flash_ERASE_FAIL

61

Return Value: -14Description: This indicates that the previous erasure of one block, many blocksor of the whole device has failed.Solution: Investigate this failure further by attempting to erase each blockindividually. If erasing a single block still causes failure, then the Flashsadly needs replacing.*******************************************************************************Error Name: Flash_TOGGLE_FAILReturn Value: -15Notes: This applies to M29 series Flash only.Description: The Program/Erase Controller algorithm has not managed to completethe command operation successfully. This may be because the device is damaged.Solution: Try the command again. If it fails a second time then it islikely that the device will need to be replaced.*******************************************************************************/

#endif // USING_FLASH

62

Flash.h/****c1481_08.h*Header File for c1481_08.c**************************************Filename: c1481_08.hDescription: Header file for c1481_08.c. Consult the C file for detailsCopyright (c) 2001 STMicroelectronics.THIS PROGRAM IS PROVIDED “AS IS” WITHOUT WARRANTY OF ANY KIND,EITHEREXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTYOF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISKAS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THEPROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING,REPAIR OR CORRECTION.*******************************************************************************//*******************************************************************************Commands for the various functions*******************************************************************************/

#undef USING_FLASH // we're not doing anything with FLASH right now//#define USING_FLASH

// only need all this if we are trying to modify the flash#ifdef USING_FLASH

#define FLASH_READ_MANUFACTURER (-2)#define FLASH_READ_DEVICE_CODE (-1)/*******************************************************************************Error Conditions and return values.See end of C file for explanations and help*******************************************************************************/#define FLASH_BLOCK_PROTECTED (0x01)#define FLASH_BLOCK_UNPROTECTED (0x00)#define FLASH_BLOCK_NOT_ERASED (0xFF)#define FLASH_BLOCK_ERASE_FAILURE (0xFE)#define FLASH_BLOCK_ERASED (0xFD)#define FLASH_FOUND_PROTECTED_BLOCK (0xFC)#define FLASH_SUCCESS (-1)#define FLASH_POLL_FAIL (-2)#define FLASH_TOO_MANY_BLOCKS (-3)#define FLASH_MPU_TOO_SLOW (-4)#define FLASH_BLOCK_INVALID (-5)#define FLASH_PROGRAM_FAIL (-6)#define FLASH_OFFSET_OUT_OF_RANGE (-7)#define FLASH_WRONG_TYPE (-8)#define FLASH_BLOCK_FAILED_ERASE (-9)#define FLASH_ERASE_FAIL (-14)#define FLASH_TOGGLE_FAIL (-15)

63

/*******************************************************************************Function Prototypes*******************************************************************************/extern unsigned char FlashRead( unsigned long ulOff );extern void FlashReadReset( void );extern int FlashAutoSelect( int iFunc );extern int FlashBlockErase( unsigned char ucNumBlocks, unsigned char ucBlock[]);extern int FlashChipErase( unsigned char *ucResults );extern int FlashProgram( unsigned long ulOff, unsigned int NumBytes, void *Array );extern char *FlashErrorStr( int iErrNum );


64

Bootloader Source/************************************************************************ bootloader.c** Simple menu-driven bootloader for microblaze/uclinux/mbvanilla** uClinux kernel command line parameter handling * by Brett Boren <[email protected]>* * updated by John Burnette to work with NuHorizons Spartan 3 * Development board M29W320DB flash chip*************************************************************************** Copyright (C) 2003 John Williams <[email protected]>* Copyright (C) 2004 Brett Boren <[email protected]>** This program is free software; you can redistribute it and/or modify* it under the terms of the GNU General Public License as published by* the Free Software Foundation; either version 2 of the License, or* (at your option) any later version.** This program is distributed in the hope that it will be useful,* but WITHOUT ANY WARRANTY; without even the implied warranty of* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the* GNU General Public License for more details.** You should have received a copy of the GNU General Public License* along with this program; if not, write to the Free Software* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA*****************************************************************************/

/* Get general hardware memory map */#include "xparameters.h"//#include "xbasic_types.h"#include "xstatus.h"#include "mb_interface.h"#include "xuartlite_l.h"#include <stdio.h>#include <stdlib.h>#include <ctype.h>

#include "flash.h"

/* Software flow control characters */#define XON 17#define XOFF 19

#define FLASH_BASEADDR 0x81400000

// this is 2MB minus our start address (0x4000)unsigned int gImageLen=0x1FC000-1;

65

/* Physical start of flash memory */unsigned char *flash_start = (unsigned char *)FLASH_BASEADDR;

/* Place within flash where os/rootfs image goes */unsigned char *flash_image_table[]={

(unsigned char *)(FLASH_BASEADDR+0x4000)};

// This should be 8 bit for our flash, so use charint num_flash_images = sizeof(flash_image_table)/sizeof(unsigned char *);

/* Start and end of SDRAM */unsigned char *sdram_start = (unsigned char *)XPAR_SDRAM_4MX16_BASEADDR;unsigned char *sdram_end = (unsigned char *)XPAR_SDRAM_4MX16_HIGHADDR;

/* Static buffer to store kernel command line */char cmdline[512];int _gerr = 0;

/* Prototypes for menu functions */typedef int (*menu_function)(void);int menu_download_kernel(void);

#ifdef USING_FLASHint menu_image_into_flash(void);int menu_erase_flash(void);int menu_set_cmdline(void);#endif // USING_FLASH

int menu_execute_ram_image(void);int menu_execute_flash_image(void);

typedef struct {menu_function fn;char *menu_string;

} menu_item;

#ifdef USING_FLASHmenu_item main_menu[]={

{menu_execute_flash_image,"Execute Flash image"},{menu_execute_ram_image,"Execute RAM image"},{menu_erase_flash, "Erase Flash"},{menu_image_into_flash,"Write image into Flash"},{menu_set_cmdline,"Set kernel cmdline"},{0,0}};

#elsemenu_item main_menu[]={

{menu_execute_flash_image,"Execute Flash image"},{menu_execute_ram_image,"Execute RAM image"},{0,0}};


// take an argument for the cmdline buffertypedef void (*void_fn)(void *);

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void_fn kernel_start;

extern int _start;

void set_intvecs(void){

unsigned int *ptr=(unsigned int *)0x0;

/* Only care about reset vector, make sure it points at the startup code */

*ptr=(unsigned)&_start;}

#if 0 // don't need this right nowvoid memory_test(unsigned char *start, unsigned char *end){

unsigned char *dst;

print("\n\r\n\rTesting memory...");

for(dst=start; dst<end; dst++)*dst=(unsigned int)dst;

for(dst=start; dst<end; dst++)if(*dst!=(unsigned int)dst){

print("failed at 0x");putnum((int)dst);print("\n\rContents:0x");putnum((int)*dst);print(" expected 0x");putnum((unsigned int)dst);print("\n\rHalting...");for(;;)

;}

}

void clear_memory(unsigned char *start, unsigned char *end){

unsigned char *dst;

for(dst=start; dst< end; dst++)*dst=0;

}#endif // #if 0

void copy_image(unsigned char *src, unsigned char *dst, unsigned int len){

// FlashReadReset();

print("\n\rCopying kernel image from FLASH to SDRAM...");while(len--)

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{*dst++=*src++;

}print("done\n\r");

}

void verify_image(unsigned char *src, unsigned char *dst, unsigned int len){

print("\n\rVerifying Kernel Image in SDRAM...");

// FlashReadReset();

while(len--){

if(*dst++ != *src++){

print("Error at ");putnum((int)dst-1);print("/");putnum((int)src-1);print(" Contents ");putnum(*(src-1));print("/");putnum(*(dst-1));print("\n\rHalting...");for(;;)

;}

}

print("...done\n\r");}

#ifdef USING_FLASHint get_flash_number(void){

int flash_slot=0;

do {xil_printf("Which flash slot? (1-%d, 0 to cancel)

",num_flash_images);flash_slot= get_number();

} while (flash_slot<0 || flash_slot > num_flash_images);

xil_printf("you entered %d\n",flash_slot);

return flash_slot;}

int menu_image_into_flash(void){

unsigned char *ram_ptr = sdram_start, *flash_ptr;unsigned int words_to_write;

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int flash_slot=0;char ch;int _gerr = 0;

flash_slot = get_flash_number();

if(!flash_slot)return -1;

flash_ptr = flash_image_table[flash_slot-1];

print("Are you sure? ");ch=inbyte();

if(ch!='y' && ch!='Y')return -1;

print("\n\r");

words_to_write=(gImageLen);

if(*(flash_ptr) != 0xFF){

print("\n\rError - Flash must be erased first!\n\r");return -1;

}FlashReadReset();

_gerr = FlashProgram( (unsigned long)(flash_ptr - flash_start), words_to_write, ram_ptr );

// check error statusif ( _gerr != FLASH_SUCCESS ){

xil_printf( "Flash Program Error!\r\n%s\r\n", FlashErrorStr( _gerr ) );

}

print("\n\rDone...\n\r");

return 0;}

int menu_erase_flash(void){

char ch;unsigned char ucResults;

print("This will erase the entire flash - are you sure? ");ch=inbyte();

if(ch=='y' || ch=='Y'){

FlashReadReset();print("\r\nErasing flash...\n\r");

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_gerr = FlashChipErase( &ucResults );if ( _gerr != FLASH_SUCCESS ){

print( "Flash Erase Error!\r\n" );

if ( ucResults == FLASH_FOUND_PROTECTED_BLOCK ){

xil_printf("Block 0x%x is protected!\n\r", _gerr );}else{

xil_printf( "%s\r\n", FlashErrorStr( _gerr ) );xil_printf( "Block erase status: 0x%x\r\n",

ucResults );}

}

print("\n\rDone.\n\r");}

return 0;}#endif // USING_FLASH

int menu_execute_ram_image(void){

if(!gImageLen){

print("Error - no image downloaded yet!\n\r");return -1;

}

kernel_start = (void_fn)sdram_start;kernel_start(cmdline); /* Never returns */

return 0;

}

int menu_execute_flash_image(void){

unsigned char *ram_ptr = sdram_start, *flash_ptr;

#ifdef USING_FLASHint flash_slot = get_flash_number();

#elseint flash_slot = 1;


if(!flash_slot)return -1;

flash_ptr = flash_image_table[flash_slot-1];

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print("flash addr "); putnum((int)flash_ptr); print("\n\r");

copy_image(flash_ptr, ram_ptr, (gImageLen));verify_image(flash_ptr, ram_ptr, (gImageLen));

print("Jumping to kernel startup...\n\r\n\r");kernel_start = (void_fn)sdram_start;kernel_start(cmdline);

}

/* simple routine to get a number typed on stdin */int get_number(void){

char ch, buffer[10];unsigned char num_chars;

num_chars=0;

/* Read chars until buffer full or enter pressed */while((ch=inbyte()) != '\r' && num_chars < 99)

if(isdigit(ch))outbyte(buffer[num_chars++]=ch);

print("\n\r");

buffer[num_chars]='\0';

// return (int)atoi(buffer);

if (*buffer == '1') return 1;else if (*buffer == '2') return 2;else if (*buffer == '3') return 3;else if (*buffer == '4') return 4;else if (*buffer == '5') return 5;else return 0;

}

int do_menu(menu_item *menu){

unsigned char menu_choice, num_items=0;

outbyte(XON);

print("\n\n\r");print("JB-Boot Menu\n\r");print("-----------\n\r");print("\n\r");

while(menu[num_items].fn){

xil_printf("%d. %s\n\r",num_items+1,menu[num_items].menu_string);

num_items++;}

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print("\n\r\n\r");

do{

print("Make your choice>");menu_choice = get_number();print( "\r\n" );

} while (menu_choice<1 || menu_choice > num_items);outbyte(XON); return menu[menu_choice-1].fn();

}

#ifdef USING_FLASHint menu_set_cmdline(void){

/* overwrite the first part of the address space since we're pretty well guaranteed not to have to use it again */

int i = 0;char ch = '\0';

outbyte(XON);

print("Enter cmdline: ");

ch = inbyte();

// 0x0d is the carriage return (Enter) ascii value// cmdline buffer is only 512 byteswhile (ch != 0x0d && i < 512-1){

cmdline[i++] = ch;outbyte(XON); outbyte(ch);ch = inbyte();

}

cmdline[i] = '\0';

outbyte(XON);

return 1;}#endif // USING_FLASH

void reset_uarts(void){

unsigned int *uartp;

uartp=(unsigned int *)XPAR_RS232_BASEADDR;uartp[XUL_CONTROL_REG_OFFSET/4]=0x0;

// uartp=(unsigned int *)XPAR_RS232_BASEADDR;//XPAR_DEBUG_UART_BASEADDR;// uartp[XUL_CONTROL_REG_OFFSET/4]=0x0;}

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int main(void){

reset_uarts();

#ifdef USING_FLASHFlashReadReset();

#endif

/* Ensure cmdline defaults to null (zero-length) string */cmdline[0]='\0';

while(1)do_menu(main_menu);

}

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Linker Source

_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x300;

/* Define all the memory regions in the system */MEMORY{ilmb_cntlr : ORIGIN = 0x00000000, LENGTH = 0x1fff}

/** Specify the default entry point to the program*/ENTRY(_start)

/** Define the sections, and where they are mapped in memory*/SECTIONS{

.text : { _ftext = .; *(.text) *(.text.*) *(.gnu.linkonce.t*) _etext = .; } > ilmb_cntlr

.rodata : { _frodata = .; *(.rodata) *(.gnu.linkonce.r*) _erodata = .; } > ilmb_cntlr

/* Alignments by 8 to ensure that _SDA2_BASE_ on a word boundary */ .sdata2 : { . = ALIGN(8); _sdata2_start = .; *(.sdata2) . = ALIGN(8); _sdata2_end = .; } > ilmb_cntlr _sdata2_size = _sdata2_end - _sdata2_start; PROVIDE (_SDA2_BASE_ = _sdata2_start + (_sdata2_size / 2 ));

.data : { . = ALIGN(4); _fdata = .; *(.data) *(.gnu.linkonce.d*) _edata = .; } > ilmb_cntlr

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/* Alignments by 8 to ensure that _SDA_BASE_ on a word boundary */ /* Note that .sdata and .sbss must be contiguous */

.sdata : { . = ALIGN(8); _ssro = .; *(.sdata) } > ilmb_cntlr .sbss : { . = ALIGN(4); PROVIDE (__sbss_start = .); *(.sbss) . = ALIGN(8); _essro = .; } > ilmb_cntlr PROVIDE (__sbss_end = _essro); _ssro_size = _essro - _ssro; PROVIDE (_SDA_BASE_ = _ssro + (_ssro_size / 2 ));

.bss : { . = ALIGN(4); PROVIDE (__bss_start = .); *(.bss) *(COMMON) . = ALIGN(4); PROVIDE (__bss_end = .); } > ilmb_cntlr

.bss_stack : { . = ALIGN(8); _heap = .; _heap_start = _heap; . += _STACK_SIZE; . = ALIGN(8); _stack = .; __stack = _stack; } > ilmb_cntlr}

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Test Application Source: by Jeremy Connor/********************************************************************* * ** Simple Example with a GPIO flash of an LED. *********************************************************************/#include "xparameters.h"#include "xgpio_l.h"#include "xuartlite_l.h"#include "xstatus.h"

/************Definitions***********************/

#define ms_divider 1000#define us_divider 1000000#define clock_freq 50000000

/*************Function Prototypes***************/

void delay_ms(int num_ms);void delay_us(int num_us);

/******************************************************************Function: delay_msFunction: delay_us

This function takes in the number of milliseconds wanted for delayand also the processor speed.

return: none

*******************************************************************/void delay_ms(int num_ms){

int loop_cnt = 0;int count_up = 0;

count_up = clock_freq/ms_divider;count_up = count_up*num_ms;

for (loop_cnt = 0; loop_cnt < (count_up); loop_cnt++);}

void delay_us(int num_us){

int loop_cnt = 0;int count_up = 0;

count_up = clock_freq/us_divider;count_up = count_up*num_us;

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for (loop_cnt = 0; loop_cnt < (count_up); loop_cnt++);}

int main(int argc, char *argv[]){ Xuint8 Helloworld[] = "I Need a Beer"; int SentCount = 0; XStatus Status;

int size = 0; Xuint8 Count = 0;

/* * Set the GPIO to outputs and turn off the LEDs */ XGpio_mSetDataDirection(XPAR_MYGPIO_BASEADDR, 0); XGpio_mSetDataReg(XPAR_MYGPIO_BASEADDR, 0);

while (1) { /* Toggle the LEDs differently each time through the loop */ XGpio_mSetDataReg(XPAR_MYGPIO_BASEADDR, (Xuint32)Count);

/* Good way to send string over rs-232 connection */ SentCount = 0;

size = sizeof(Helloworld);

while (SentCount < size) { XUartLite_SendByte(XPAR_MYUART_BASEADDR, Helloworld[SentCount]); SentCount++; }

/* Delay loop so we can see the LED */delay_ms(500);

Count++; }

return SentCount;}

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APPENDIX C: PROJECT SETUP TUTORIALNote: This tutorial contains some useful information that I gathered as I battled

through each of these things. It is relevant to the NuHorizons Spartan 3 development board (my board is rev 4).

This tutorial shows how to set up the XPS project exactly as we have it. After following these instructions, the hardware will be configured correctly to work with uClinux. This is intended to set up a project that runs at 50 MHz and does NOT have cache enabled. In order to enable cache, follow the instructions in Appendix D: Using Instruction and Data Cache Tutorial.

First: launch XPS, go File> New project > base system builder. Choose your directory, ensure there are no spaces in the full path, click OK. Choose NuHorizons as the vendor, Spartan-III 400 Evaluation Board as board name, click next, and next again, and next a third time, and again. Uncheck ADC and DAC, click next 3 more times, and again, and then Generate. And Finish. Basically, accept all the defaults.

Next, open your project directory, and go to TestApp/source, delete TestApp.c. Now, take our bootloader.c, flash.c, and flash.h, create a new folder in your project directory called “code”, and copy those three files in. Next, take our .mhs and .mss files and overwrite the one in your project directory (be sure the new one has the same name as the old). After this, take our .ucf file and overwrite the one in your project directory’s data folder.

In the Applications tab of your main XPS window, delete TestApp.c from the TestApp project sources list, and add flash.c and bootloader.c instead. Now, go to TestApp/Src and replace the default TestAppLinkScr with our TestAppLinkScr.

All the files in your project directory are now customized to work with the Spartan-III; use the Update Bitstream command in the Tools menu to build the project’s download.bit file.

Finally, use iMPACT to download the resulting bit stream to the hardware for use. When testing this against your uClinux kernel boot, remember to configure the HyperTerminal session to run at 57600 baud with software control, no parity.

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APPENDIX D: USING INSTRUCTION AND DATA CACHE TUTORIAL

Note: This tutorial contains some useful information that I gathered as I battled through each of these things. It is relevant to the NuHorizons Spartan 3 development board (my board is rev 4).

This tutorial assumes you have not already used the Base System Builder (BSB) to set up cache for you. If you have already allowed BSB to do this for you, and you really didn’t have a clue what it was doing for you, this tutorial is useful anyway.

Before using cache you should realize that this will use a lot of the BRAM on the FPGA. The Spartan 3 400 chip (you’ll have to see which version you have) has 32KB BRAM which is broken up into 16 x 2KB blocks. I’ll create a scenario to illustrate how to use these.

Suppose I have one block of BRAM that my Microblaze is using (Microblaze HAS to have its own block and the data and instructions controller base addresses HAVE to start at 0x00000000. As I understand it, you don’t have a choice). You may define other BRAM blocks at other addresses if you want, but for this scenario we just have the one. In this scenario, my I and D controllers take up the following addresses 0x00000000 – 0x00001FFF. So that uses 8KB of our BRAM right there. Now if I go to Project->Add/Edit Cores->Parameters->BRAM I will see the following parameters:

C_MEMSIZE 2048C_PORT_DWIDTH 32C_PORT_AWIDTH 32C_NUM_WE 4

The size of the BRAM is ONLY determined by the address size that you defined the controllers to. So, although C_MEMSIZE is set to 2KB, we know that the BRAM size is really 8KB. Changing the 2048 will do nothing. Also, according to the documentation, 32 is not a valid address width for our Spartan 3. Read SP3datasheet.pdf to determine the address size you should use. For my purposes, I am using C_PORT_ADWIDTH = 12. The default data width is fine.

Now, if I switch to view the Microblaze core parameters I am interested in the following parameters:

C_ICACHE_BASEADDRC_ICACHE_HIGHADDRC_USE_ICACHEC_ADDR_TAG_BITSC_CACHE_BYTE_SIZEC_DCACHE_BASEADDRC_DCACHE_HIGHADDRC_USE_DCACHEC_DCACHE_ADDR_TAGC_DCACHE_BYTE_SIZE

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Suppose I have used BSB to set up my SDRAM and I have configured address space like this:

BaseAddress 0x80000000High Address 0x807FFFFF

which is 8MB.

I decide that I want to cache the entire SDRAM memory space and I want my data and instruction cache sizes to be 8KB each. I need to figure out how many tag bits I need to accomplish this. According to the documentation, the Microblaze does a straight-mapped, four-line cache. Look at the documentation for the details. If I want to keep track of 8MB (2^23) then I need 23 bits to do it.

Total_bits_needed = tag_bits + cache_size_bits

I want my cache size I and D to be 8KB (2^13) each, so I need 13 bits for this. Therefore, plugging our values into the equation above we get

23 = tag_bits + 13, so tag_bits = 10.

So my Microblaze cache parameters should look like this:

C_ICACHE_BASEADDR 0x80000000C_ICACHE_HIGHADDR 0x807FFFFFC_USE_ICACHE 1C_ALLOW_ICACHE_WR 1C_ADDR_TAG_BITS 10C_CACHE_BYTE_SIZE 8192C_DCACHE_BASEADDR 0x80000000C_DCACHE_HIGHADDR 0x807FFFFFC_USE_DCACHE 1C_ALLOW_DCACHE_WR 1C_DCACHE_ADDR_TAG 10C_DCACHE_BYTE_SIZE 8192

So we’re using 8KB for data cache and 8KB for instruction cache. Add that to our Microblaze BRAM and we are now using a total of 24KB. Remember, though, that we have cache address tags and that these don’t come free. If we are using 10 bits for each of these then we lose another 2^10 or 1KB of BRAM. Of course, BRAM does not come in 1KB blocks so actually each tag cache takes up 2KB of BRAM. So for the I and D cache tags we use a total of 4KB. Now our cache usage is up to 28KB. We have 4KB, or 2 blocks, of BRAM left to work with.

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APPENDIX E: MICROBLAZE SYSTEM CLOCK SPEED-UP TUTORIAL

Note: This tutorial contains some useful information that I gathered as I battled through each of these things. It is relevant to the NuHorizons Spartan 3 development board (my board is rev 4).

You have to make sure that the system clock is set to operate at the speed you want. If you use the Base System Builder to set up a XPS project (which you really should do because it makes life easier) you will have the option of setting the cpu speed in the dialog that handles Microblaze setup. Here you can choose whether or not to enable instruction and data caching and set their size. You can also set the processor clock frequency. The defaults are to 50MHz and no cache enabled.

Now, here’s what the clock setup is really doing. Once you’ve generated your project, look in the “system” tab in the explorer window on the left. Find and open the *.ucf file. This is the user constraint file. You use this to manually assign pins to certain locations. If you or the BSB doesn’t do it, your pins will just be assigned anywhere that they fit. So, for example, if you don’t set your LCD pins to the right place, the LCD won’t work. Fortunately, the BSB sets all these up for you. They, NuHorizons folks, managed to mess up the SDRAM setup, but we’ll get to that in a different tutorial.

So, somewhere in the *.ucf file you’ll see Net sys_clk PERIOD = 20000 ps;

somewhere in there. This is assuming that you selected the default of 50MHz (do the math, 1/(20000*10^-9) ). If you now want to change the clock frequency, say to 80 MHz, change the line to

Net sys_clk PERIOD = 12500 ps;

Now you need to make sure the right clock is hooked into your system. The Spartan 3 dev board comes with a 50MHz main oscillator (see Spartan3_400_Rev3_Schematic.PDF and look for part U9) and a 20MHz oscillator with a PLL multiplier circuit (see part U19 in Spartan3_400_Rev3_Schematic.PDF) . If you choose the default 50MHz frequency then the BSB probably tied your sys_clk to the main oscillator. If that’s the case, in your *.ucf you’ll see

Net sys_clk LOC=P79;

Now look at the Spartan3_400_Rev3_Schematic.PDF again and look at pin 79 of the FPGA. You’ll see that pin 79 does, in fact, correspond to a connection with the MAIN_CLK. Also notice that pin 80 connects to the PLL clock. So, if you actually choose to use the PLL in order to get a frequency other than 50MHz, you have to have this one hooked up as your main clock. So instead of the previous line of code, your line in the *.ucf should read

Net sys_clk LOC=P80;

Now go to the Oscillator section of HW-AFX-SP3-400_Manual_V1.4.doc. It’s pretty self-explanatory. If want my PLL clock to be set to 80MHz then I need a 4X multiplication of the 20MHz input clock. So I tie both S0 and S1 to ground with a couple of jumpers. Notice that

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just leaving the pins floating performs a 2X multiplication, so you HAVE to actually ground the pins to get 4X.

You should be good to go now. If you are using a UART, be sure to change the C_CLK_FREQ parameter in the core settings (Project->Add/Edit Cores->Parameters->your uart).

If you are interfacing to SDRAM or Flash, you also have to go to Project->Add/Edit Cores->Parameters->SDRAM, Flash and change C_OPB_CLK_PERIOD_PS to 12500 for the same reason as explained above.

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APPENDIX F: IMPLEMENTING UCLINUX WITH CUSTOM APPLICATIONSInstructions

This tutorial is pretty long; I’ve included a lot of detail in here aimed for senior electrical engineering students who probably aren’t Linux gurus yet, so hopefully its size and helpfulness are directly related. Print it out and read it through at least once before starting so you have an idea of the whole process. For a stripped-down version of this document, which is in much more of a step-by-step outline form, see my uClinux Apps presentation. Lastly, have fun; it’s no fun if you don’t.

IntroductionThis document assumes that anyone wanting to employ these instructions has a fully-

functional Microblaze softcore CPU-based FPGA hardware platform on which to run uClinux. Of course, because uClinux can run on a wide variety of architectures (the full list of currently known builds is available at uclinux.org), these instructions could potentially be reused for other non-Microblaze solutions. For an example of setting up a Microblaze hardware platform, see John Burnette’s tutorial in which he uses a NuHorizons development board with a Spartan 3 FPGA. Also available is the pre-made “mbvanilla” platform designed for Insight’s Virtex-2-based V2MB1000 board, at John Williams’s Microblaze uClinux Project site (itee.uq.edu.au/~jwilliams/mblaze-uclinux). Both examples employ Xilinx Platform Studio and related tools and development kits.

In short, you’ve got a hardware platform synthesized, and you want to do something with it. This tutorial will show you how to get the uClinux source, add your own applications, build an image, download it, and run it. Because creation of a hardware platform and creating a successful uClinux image are interrelated, some material may be repeated in varying levels of detail in John Burnette’s aforementioned tutorial.

A lot of this tutorial is pulled from, or is pointing to, the documentation portion of John Williams’s Microblaze uClinux Project site (again, at itee.uq.edu.au/~jwilliams/mblaze-uclinux/Documentation). His site is a fantastic resource for getting started with plenty of links for help elsewhere as well, and everyone working with uClinux should be subscribed to his mailing list (subscription details on the site) to hear about recent developments and ask for help if you need it. The parts of this tutorial that aren’t replications of that site are my own comments, pointers, and additional information that will make this whole process a lot easier.

Required MaterialsA Windows machine, running Xilinx Platform Studio 6.2 with EDK 6.2 installed, for

quickest results at time of writing, but the uClinux source trees could very well be updated for use with 6.3 or beyond in the future, so just keep an eye out. If you really want, you could probably do the XPS/EDK stuff on the Linux machine, but it’s not that fun (see the comments John Williams makes in the “setting up a development environment” section of his documentation).

A Linux machine, running a reasonably recent distribution, to make the uClinux image. Compiling things will be simplest if it’s an x86 box, too. If you really want, you could probably do the compiling stuff on the Windows machine in Cygwin, but it is horribly awful (see the comments John Williams makes in the “obtaining a toolchain” section of his documentation).

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Some Linux experience will be very helpful too – after all, you’re developing a Linux environment.

The previously-discussed hardware platform, and all materials necessary to communicate with it. This hardware should have JTAG and UART connections, some RAM (8 megs or more preferred), and an FPGA (surprise!) at bare minimum. Other stuff like a few megs of flash will make things easier; stuff like a PS/2 port, Ethernet controller, or LCD will make things more fun. Be sure to have the datasheet for your board handy – you’ll need it.

The BasicsThe very first things required to work with uClinux are the kernel and distribution source

trees, and something to compile them with. The source trees you can download from CVS following the instructions in the “obtaining the sources” portion of the Microblaze uClinux documentation. These downloads could take a while, and requires a lot of space – have one or two gigs free to be on the safe side (after compiling, my uClinux-dist directory houses 750Mb right now!). At the end you’ll have two directories: the distribution tree, uClinux-dist, and the kernel tree, uClinux-2.4.x. Don’t forget to symlink the kernel inside the distro, as per the directions.

The mailing list will often give an indication when you should follow the “maintaining the sources” documentation directions, so keep watch on that since full tree updates can take more than a few minutes and there’s no need to burn time and bandwidth (especially on the part of uclinux.org!) it needlessly.

NOTE: If you’ve made changes to a file maintained by CVS that it doesn’t recognize, it won’t overwrite your file if a new version comes out on the CVS source repository. It will instead recognize the difference and leave it to you to sort out the mismatch, so you don’t have to worry about CVS updates “cleaning” your work. Similarly, it will totally ignore files it does not maintain, wherever they are.

NOTE: For some reason or another, the code trees tend to get messed up somewhat quickly, even with regular CVS updates. If things suddenly break, don’t hesitate to totally blow away your copies of the sources trees and re-download them – just make sure you’ve saved, or can easily replicate, any changes you’ve made to the code tree first! Some great advice I heard from Brent Plump in my EE590 class was to download the tree, copy it somewhere else and use that as your work copy, and regularly blow away and re-acquire the unmodified tree and use a script to manually compare the newly-downloaded tree with your work copy.

This source will give you what you need to build a full-featured (including most standard Linux utilities, lots of drivers, and more) uClinux environment for any architecture it’s been yet ported to, not just Microblaze. The source will also give a lot of great code examples if you want.

Next, something to compile this with: this is Microblaze-specific. Again from the documentation page, in the “obtaining a toolchain” portion, obtain the toolchain, install it, and test it, all per the instructions. If you’re not on an x86 Linux box, you’ll get to experience the fun of trying to compile the toolchain – good luck. If you’re not using Microblaze, you’ll have your own architecture’s compiler from somewhere. Hopefully.

NOTE: When you go to compile things, and get an error along the lines of “-lxil not found”, you’ll need to rummage through the directories in your hardware platform for a certain libxil.a and put it into lib, in the uClinux-dist directory the CVS download will create.

That’s the development environment; now, on to working with it.

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Writing Your Own ApplicationsProgram away, just like writing a Linux app. A system like this, however, will probably

have a lot of hardware interaction, and as such you’ll need drivers. This section could be drastically wrong, just to warn you. I’ve never written a driver before, so if you have, ignore me and do your own thing.

At any rate, on an FPGA you’ll undoubtedly have custom cores synthesized and talking on various busses. Xilinx provides books and books of documentation on function calls to interface with hardware inside of code executed on the Microblaze: find it, and use it. If you just want to try something out, the sample code in Jeremy Connor’s Microblaze tutorial is a good starting point to writing a simple program to play with buttons or LEDs (the tutorial is also a great way to get started with FPGA development, if you’re interested, and it assumes the same board used in John Burnette’s aforementioned tutorial). Because the Microblaze lacks an MMU (memory management unit), directly interacting with registers will work just fine – though the Xilinx functions might go through cleaner means, it seems like that even if they don’t, the functions should still work.

Be sure to test compiling your code with mb-gcc before going on to the next step to integrate it into the larger uClinux distribution – this will save a lot of time since you won’t have to wait for the other stuff to compile before it gets around to testing your code. Also remember to put libxil.a into uClinux-dist/lib if you get a “-lxil not found” error; you might even want to tell uClinux-dist/lib about (by either making a symlink or copying them straight in) all the libraries you can find in your hardware project directory, as a precaution. For other errors… well, there’s always the Microblaze uClinux mailing list, documentation, friends, and Google.

Rolling It All TogetherYou’ve coded something cool, debugged it for hours, and now you’re ready to test it in a

uClinux environment. First, you’ve got to build the uClinux image file (if you emulate videogames on your computer, you’d call this image a ROM, but in this case you made it yourself instead of downloading it). If you follow the directions contained within the “building the kernel and distribution” portion of the documentation on the Microblaze uClinux Project site, you’ll get a default build made for the Insight Virtex2 board John Williams uses. Even if you’re using the same board, the resultant image won’t have your own apps integrated in; luckily, it’s pretty easy to do this.

To add your code to the build list, first make a directory in uClinux-dist/user with the name of your program (I’m not sure how picky the compiler is, but it’s safe to assume no spaces or special characters, and keep its length under the longest directory already in /user) and copy all your headers and sources to it. Then, follow the directions in uClinux-dist/Documentation/Adding-User-Apps-HOWTO – in other words, write a makefile for your program and put it in the directory just created, and edit uClinux-dist/config/Configuration.help and uClinux-dist/config/config.in to add it to the list of compile options, and uClinux-dist/user/Makefile so the compiler knows to do if you select that compile option. The information contained in the HOWTWO on makefiles is rudimentary; for information on making more complicated makefiles see the EE590 Autumn 2004 presentation by Kyle Fitzpatrick and Konstantin Zak.

With your code added to The List, it’s time to do just as the “building the kernel and distribution” documentation says. Switch to the uClinux-dist directory and run “make

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menuconfig”. In “Vendor/Product Selection”, choose Insight as the vendor and mbvanilla_net as the product. This will use the mbvanilla files in the uClinux to build everything; if you find yourself needing to modify these files, you could even copy them to a different name, edit them, and make your own option in this menu following similar steps in the Adding-User-Apps-HOWTO already mentioned, simply because this menu system is no different than the one you modified earlier. This will take plenty of time, so please don’t do it.

NOTE: If you use the pre-made mbvanilla files, there’s a chance you’ll have to modify the hardware addresses, memory sizes, and the like in uClinux-dist/include/asm-microblaze/mbvanilla.h to match your board. Make sure to remember about this file if you have problems!

Once you’ve made those two selections, go back to the main menu and into “Kernel/Library/Defaults Selection”. As per John Williams’s instructions, make sure Libc Version is set to uClibc, but that’s where similarities to his instructions end. Instead of going ahead with a default install, select the two options in the middle: “Customize Kernel Settings” and “Customize Vendor/User Settings”, and exit twice while saving the configuration. Wait a moment, and the Kernel Configuration menu will appear.

The Kernel Configuration menu will be nothing new to anyway who’s ever compiled a Linux kernel, but for everyone else: this is where you pick every driver and bit of hardware support for your system. There are a lot of options, so please look at all of them the first time you see this menu and familiarize yourself with everything.

Of special note for FPGA CPUs is the “Processor type and features” section, where you select things like CPU speed and cache, and can enable the general-purpose I/O (GPIO) driver (the GPIO bus is how most of the internal FPGA cores communicate, so chances are you’ll definitely want this enabled). Also important is the RAM disk support in “Block Devices” – uClinux will need a file system to run from, and because embedded systems seldom have hard disks chances are that a RAM disk will suit your solution best.

Picking out all your hardware drivers will be very board- and FPGA core-specific, but don’t feel like you need to include absolutely everything for your board. If you aren’t using it, you don’t need a driver, and if you’re in the early stages of testing it’s easiest to only enable to bare minimum to get a working system. Once you’ve selected what you will, exit and save your configuration again, wait another moment, and the uClinux Configuration menu will appear.

As you can probably guess, after configuring the kernel you’ve got to configure the distribution. The default settings are fine for many applications, but be sure to select your program in whichever top-level menu you put it in during the Adding-User-Apps HOWTO. Just like with the kernel configuration, take a moment to peruse the options here to see all the Linux utilities and applications uClinux can include. Exit, save your changes, then run “make dep” followed by “make” to build the image. You can run “make dep; make” to automatically run one after another, too, though there’s always the chance make dep will exit with error and then you’ll have to sit through make – which takes quite a lot longer – until you find out there’s a problem.

NOTE: When make finishes, it will copy the resultant image files into /tftpboot, a directory it assumes resides in the root filesystem. If it doesn’t, you’ll get a copy error unless you have permission to touch the root directory. If you have permission (which means either you’re running this as root or the rootdir is writable by non-root users, both of which are bad!) but the directory still doesn’t exist, the image files will overwrite each other and the second one copied will be called “tftpboot” – since there’s no tailing slash in the copy command that gets run, it assumes it should copy the images to the file tftpboot instead of a directory with the same

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name. In short, make sure /tftpboot exists; if it doesn’t, the images will still be in uClinux-dist/images safe and sound.

Congratulations, your image is made! Now all that’s left is to run it, provided all your code and compile options haven’t made the image size exceed the memory you’ve got on your board. If that’s the case, start cutting things and try again!

Executing The ImageIt’s time to download the image file to your board and try all this out. Hook up your

board, turn it and HyperTerminal or the like (56kbaud, no parity, no flow control) on, and configure the FPGA by downloading the download.bit resultant from the hardware platform (or writing to the EEPROM on the board with the .bit converted to a .mcs file). The bootloader menu will appear in your terminal software; let it sit for the time being.

If you’re on Linux, use the dl.sh script included with the mbvanilla_net sample hardware platform available at the Microblaze uClinux Project site (see the Downloads page) to download the image to your board. If you’re on Windows, get the uClinux image you made on to the Windows side, open that dl.sh script, launch XMD (no idea what it stands for) from inside Xilinx Platform Studio, and enter the scripted commands into XMD starting from “xload mhs system.mhs” and ending with exit, substituting $KIMAGE with the name of your image (the echo commands are optional, by the way). You might have other changes to make, such as a RAM starting address different than 0x80000000 or a different mhs filename; substitute at will. XMD works the same as a Linux command prompt, so you can use cd and ls and path names (though they start with C:\ or H:\ or whatever, unlike real Linux which starts with /) to navigate files.

There is one disappointing thing about this whole download procedure: the “dow” command in dl.sh takes, on my systems at least, 20 minutes or more to complete. If you ever find a way to speed this up, tell everyone you can find immediately.

Once the image is downloaded, the immediate next dl.sh command (“rwr”) will execute the image without using the bootloader included in the hardware platform put on the FPGA. This is fine for testing, and hopefully your system will boot alright and you can test away. To avoid the image download every time you powercycle your board, you can copy the image to onboard flash memory – just don’t run the command that executes the image in dl.sh and instead use the bootloader menu’s option to copy SRAM to flash. The existence of this flash copy option depends on which bootloader code you used in your hardware platform: the mbvanilla_net code includes it, John Burnette’s doesn’t (this avoids some issues with cache he’s encountered), though he has a different bootloader devoted to flash functions.

Either you download and directly execute, download, and copy to flash, and execute, or something else, but in the end the image will boot and you should see a neat Linux startup routine, a uClinux logo, and a command prompt. If so, excellent! Your custom app should reside in /bin; try it out. If not, remember to pay close attention to errors given or where the boot halts and start debugging! Check the Microblaze uClinux mailing list archives, documentation, hardware specifications, and so on, and hopefully you’ll get it going eventually.

More Ways To Modify uClinuxLots of Linux programs have configuration files, libraries, even images, that are required

for operation. After booting the image, there are ways of downloading more files via Ethernet or Trivial FTP (tftp), but many times you’ll want to integrate them into the image at start. Adding

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programs is one thing, but adding plain files is another: first go to uClinux-dist/vendors/Insight/mbvanilla_net. Inside you might notice that there are already a few plain files the image eventually holds in /etc. Just put the plain files you want to include next to these, and modify the makefile in that directory such that the files are rolled into romfs.img – this is the image loaded into a RAM disk at boot time to form the basic file system uClinux runs out of.

Say you want your program to automatically boot at start? Add it to “rc” in the above-mentioned mbvanilla_net directory – be sure to put an ampersand (&) at the end of its name in that file so it runs in the background (unless you’re fine with it taking up the console). You could also add it to the Linux task scheduler, Cron, with a scheduling script that runs at boot time via the rc file – but that’s outside the scope of this tutorial. If you want to do anything else to uClinux, go ahead and poke around all you want; it’s open-source, after all.

The Possibility of a Hardware-less Image TestNear the end of the term I was working on this project, a Microblaze emulator for

Windows was released at uclinux.openchip.org. It comes with a sample image to boot so you can see what uClinux looks like in its default form, but that’s all I’ve ever seen work with it. I’m not sure what kernel options they used to build that image, but all the ones I’ve tried refuse to boot. If you can get it to work, it’s a great way to avoid needing Xilinx tools, a dev board, and a 20+ minute download wait time just to test your image, but be forewarned that the emulator’s hardware support is lacking (it could have greatly improved since time of writing, however, and I hope it does!).

Co-Design Tools with uClinux on an FPGACo-Design tools allow one to take a set of tasks and run them in software or turn them

into VHDL hardware files, and test things like speed and power consumption in each case. My (completely untested!) idea is that one could potentially develop an application, allocate a few parts to hardware and a few to software, add the hardware to the FPGA hardware platform and the software to the uClinux image, and have the two sides communicate with each other just fine while uClinux is included for other applications. This is just an idea, mind – your results may vary!

ConclusionWith any degree of luck, this rather long tutorial on doing stuff with uClinux should help

you get started making some really great FPGA projects, or maybe even commercial products. Keep in mind that technology is always changing, and that the information in this tutorial is probably already outdated at time of writing! Write, test, debug, repeat, document, and above all, enjoy yourself.

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Documents

class.ece.uw.edu · Web viewAbstract 1. Introduction 1. Discussion of Project 1. Design Specification 1. Design Procedure 1. Software - uClinux 1. Software - Test Application 2