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Cleaning Medical Electronics
MIKE BIXENMAN – KYZEN CORPORATION
MARK NORTHRUP – DYNAMIC RESEARCH TESTING LAB
DALE LEE – PLEXUS CORPORATION
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Discussion Points
1. Introduction 2. Design for Cleaning3. Test Vehicles
1. Solder Mask Definition2. Voltage Effects3. Frequency
Effects
4. Conclusions
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Medical Electronics
The challenge for Medical OEMs is to Design reliable electronic
hardwarePerforms reliably for the patient
Implantable devices require Increased functionalitySmall form
factor Fast data transfer
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Patient Information on Demand
Trends lead to Electronic component complexity Require faster
signal ratesHigher transmission frequencies
The concern is that Hardware failures will become more
prevalent
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Reliability
Reliability concerns challenge OEMs to Look outside the existing
design rulesToward application specific field simulations Better
understanding of reliability risks
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Circuit Board Design
Plays a role when cleaning is requiredComponent size / standoff
height Solder mask definition Solder paste selection Package
placement / density Thermal heat to solder components Static
solvating rate Dynamic energy rate
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Test Vehicles
1. Designed to test removal of soils Z-Axis gap height Density
Placement
2. Designed to test electrical effects Voltage effects Frequency
effects
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Clean Test Board
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Solder Mask Options
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Miniaturization Continues
01005 chip cap 0.4mm x 0.2mm
Murata introduces new chip capacitor0.25mm x 0.125mm
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Smaller Components
Tighter standoff heights Capillary forces pull flux under
component
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Solder Mask Defined
Solder mask defined pads Solder mask between pads
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Non Solder Mask Defined
Solder mask removed adjacent pads
Solder mask between pads
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No Solder Mask
Solder mask removed adjacent pads
No Solder mask between pads
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SMD 0201 Chip Caps
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Before Cleaning
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NSMD 0201 Chip Caps
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Before Cleaning
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No Solder Mask 0201 Chip Caps
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Before Cleaning
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SMD 0402 Chip Caps
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Before Cleaning
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NSMD 0402 Chip Caps
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Before Cleaning
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No Solder Mask 0402 Chip Caps
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Before Cleaning
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SMD 0805 Chip Caps
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Before Cleaning
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NSMD 0805 Chip Caps
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Before Cleaning
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No Solder Mask 0805 Chip Caps
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Before Cleaning
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SMD 1210 Chip Caps
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Before Cleaning
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NSMD 1210 Chip Caps
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Before Cleaning
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No Solder Mask 1210 Chip Caps
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Before Cleaning
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SMD (QFN/MLF)
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Before Cleaning
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NSMD (QFN / MLF)
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Before Cleaning
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No Solder Mask (QFN / MLF)
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Before Cleaning
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Solder Mask Defined PBGA
Wide Pitch Narrow Pitch
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Before Cleaning
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Non Solder Mask Defined PBGA
Wide Pitch Narrow Pitch
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Before Cleaning
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No Solder Mask (PGBA)
Wide Pitch Narrow Pitch
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Before Cleaning
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Data Findings
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Chip Caps
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18251210080504020201
40
30
20
10
0
51
SMDNSMDNoSM
40
30
20
10
0
Component
Mea
n
Wash Time (min.)
Solder Mask Definition
Main Effects Plot for % Residue under Chip Caps ComponentData
Means
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Ball Grid Arrays
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PBGA676PBGA324BGA360
10.0
7.5
5.0
2.5
0.0
51
SMDNSMDNoSM
10.0
7.5
5.0
2.5
0.0
Component
Mea
n
Wash Time (min.)
Solder Mask Definition
Main Effects Plot for % Residue under BGA ComponentsData
Means
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MLF / QFN
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MLF88
90
80
70
60
50
51
SMDNSMDNoSM
90
80
70
60
50
Component
Mea
n
Wash Time (min.)
Solder Mask Definition
Main Effects Plot for % Residue under QFN ComponentData
Means
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All Component Types
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PBGA
676
PBGA
324
MLF8
8
BGA3
6018
2512
1008
0504
0202
01
80
60
40
20
0
51
SMD
NSMD
NoSM
80
60
40
20
0
Component
Mea
n
Wash Time (min.)
Solder Mask Definition
Main Effects Plot for % Residue under ComponentData Means
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Voltage Effects
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Circuit Designs
SMT
QFN
BGA
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Test Patterns Donut Cross “X”
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Electrical Field – Miniaturization
Lower contamination levelsLess metal is dissolved
With less metal ions levelsElectrical field drives metallic ion
forces
The electric field will be higherAs distance between conductors
reduce
9/18/201241
Minzari et al., 2009
© 2012, Kyzen Corp.
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Constant Voltage
Rises inversely with conductor spacing Traces as small as 48µm
(1.98 mils)
At 5V ~ electric field = 2.5V At 0.4V/mil to 1.6 V/mil the
occurrence of dendrites increased
Bumiler & Hillman (2010)
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Halogen Ions
25 mil comb spacing Withstand higher levels of contamination
>20 µg/in2
12.5 mil comb spacing Levels at 5-20 µg/in2 problematic
6 mil comb spacing Levels of 0-2 µg/in2 problematic
© 2012, Kyzen Corp.
Bumiler & Hillman (2010)
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Electrical Field – High Voltage Data
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Frequency
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Controlled Loss Testing
• Controlled loss testing involves Dissipation factor (Df) of
the PCB material Copper surface roughnessUniformity of the PCB
conductor etched
featuresConductor length and impedance mismatchesPCB surface
finish, solder mask etc.
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Insertion Loss
The PCB alone involves four components of insertion loss which
include
Dielectric Conductor Leakage and Radiation
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Current Cleanliness Testing Protocol
IPC‐TM‐650 Method 2.3.28 ‐
Ion Chromatography
75% IPA / 25% DI water
60 minute extraction period
Ineffective for High Frequency
Foresite C3 Localized extraction
Steam extraction using DI
water 3 minute extraction period
Limited application
Progression of Methods
IPC 2.3.28 (Global)
Foresite C3 (Isolated)
? New Method (Tighter isolation)
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Research in Progress
Correlate chemical with electrical effectsCorrelate Ionics on a
test board to failure with
different frequency levels 1 GHz 10 GHz 20 GHz 40 GHz
Set limits that an engineer can use to predict failure and
control a process
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Test Vehicle
Test from 1, 10, 20, 40 Giga HertzMeasure interactions What do
we measure
Parasitic Capacitance Controlled Impedance Controlled Inductance
Frequency Shift Gain or Loss Phase Shift or Change Scattering(S)
Parameters
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Proposed Test Vehicle Structures
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Loss Data Example
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Concluding Remarks
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Circuit Board Design
Capillary flux action underfills tight gaps Chip caps and QFN
devices
Removal of solder mask reduces Flux residue under component
Increases gap height Easier to clean
BGA components Solder mask defined pads were easier to clean
NSMD were slightly more difficult to clean over SMD No Solder Mask
increased cleaning difficulty
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Voltage
Tighter pitch devices Increases electrical fieldLess
contamination more problematicLower levels of contamination
critical factor
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Frequency
High Frequency More problematic to failure
New test method needed to Quantify ionic contamination with
electricalGuideline for engineers to know limits for
specific voltage, frequency and currents
© 2012, Kyzen Corp. 9/18/2012 56
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Thank You
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Authors Mike Bixenman
Chief Technology OfficeKyzen Corporation [email protected]
Mark NorthrupDirector of Advanced Technical OperationsDynamic
Research Testing Labs (IEC
Electronics)[email protected]
Dale LeeStaff DFX Project EngineerPlexus
[email protected]
© 2012, Kyzen Corp. 589/18/2012
