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C lk & P ll liCrosstalk & Parallelism
Rashad.M.Ramzan, Ph.D
FAST-NU, Islamabad
Today's Topicsoday s op cs
• Crosstalk and Parallelism– Overview
Definition Sources and Dependence– Definition, Sources and Dependence
– Crosstalk Models for simulation
– Near End and Far End Crosstalk
– Crosstalk dependence on terminationp
– Impedance variation due to crosstalk
Case Study– Case Study
High Speed PCB Design: Lecture-6 © Rashad.M.Ramzan 2010-11 2
Noise: Cumulative OverviewNo se: Cu u at ve Ove v ew
High Speed PCB Design: Lecture-6 © Rashad.M.Ramzan 2010-11 3
Noise Coupling Via InterconnectNo se Coup g V a te co ect
High Speed PCB Design: Lecture-6 © Rashad.M.Ramzan 2010-11 4
CrosstalkC ossta• Mutual interference between two circuits give rise to the
crosstalkcrosstalk.
• Inductive Crosstalk (proportional to di/dt of the driven line).
• Capacitive Crosstalk (proportional to dv/dt of the driven line).
• Common Path Crosstalk - Resistive Crosstalk proportional to p pthe current flow.
• Inductive crosstalk > capacitive crosstalk in digital circuits.p g
High Speed PCB Design: Lecture-6 © Rashad.M.Ramzan 2010-11 5
CrosstalkC ossta
• Crosstalk occurs at– On-Chipp– On Chip Package– On PCB– On ConnectorsOn Connectors– On Connector Cables
• Crosstalk change and modify the Zo and propagation delay. This effects system level timing hence Signal Integritysystem level timing hence Signal Integrity.
• Crosstalk depends upon data pattern, line to line spacing and switching rates.
High Speed PCB Design: Lecture-6 © Rashad.M.Ramzan 2010-11 6
Crosstalk Circuit Model
On ChipOn-Chip
dI
Off-Chip dt
dILV driver
mLnoise m=,
dt
dVCI driver
dCnoise m=,
High Speed PCB Design: Lecture-6 © Rashad.M.Ramzan 2010-11 7
Inside IC: Cap Dominatess de C: Cap o ates
High Speed PCB Design: Lecture-6 © Rashad.M.Ramzan 2010-11 8
Crosstalk: Mutual Capacitance & Inductancep
High Speed PCB Design: Lecture-6 © Rashad.M.Ramzan 2010-11 9
Near end and Far end CrosstalkNea e d a d a e d C ossta
N d t lk ill b i t•Near end cross talk will begin at time t=0 and will have duration t=2Td•Far end cross talk will begin at time t=Td and will have duration equal signal rise or fall time.g•The amount and shape depends upon the coupling and termination
High Speed PCB Design: Lecture-6 © Rashad.M.Ramzan 2010-11 10
Near-end and far-end crosstalkNea e d a d a e d c ossta
High Speed PCB Design: Lecture-6 © Rashad.M.Ramzan 2010-11 11
Inductive Coupling (Forward & Reverse)p g ( )
• The negative blip size at the far end is proportional to the total mutual inductance.
• Lengthening the line increases the size of blip at D.
• Height of the positive reverse coupling peak length of line.
High Speed PCB Design: Lecture-6 © Rashad.M.Ramzan 2010-11 12
Capacitive Coupling (Forward & Reverse)p p g ( )
Th t f d ff t l t D• The two forward effects cancel at D.
• Striplines are well balanced between inductive and capacitive couplingcoupling.
• Microstrip electric field lines travel through air (cap coupling smaller)yielding small negative forward coupling coefficient.
High Speed PCB Design: Lecture-6 © Rashad.M.Ramzan 2010-11 13
)y g g p g
Total Crosstalkota C osstaCombining Mutual Inductive and Capacitive Coupling:
TCL1 ⎫⎧
• Amplitude of the crosstalk waves may be approximated by
VT
T
C
C
L
L
2
1V d
r
PMMf
⎭⎬⎫
⎩⎨⎧ −=
)2TT(forVC
C
L
L
4
1V Prd
MMb <
⎭⎬⎫
⎩⎨⎧ +=
CL4 ⎭⎩
F d t lk ld b d b li• Forward crosstalk could be made zero by a proper line arrangement
High Speed PCB Design: Lecture-6 © Rashad.M.Ramzan 2010-11 14
Total Crosstalkota C osstaHow Near-End Crosstalk becomes a Far-End Problem
Reverse coupling reflecting from a low impedance d idriver
Termination to Reduce Crosstalk
A
B
C
Reverse coupling
appearing at Cif termination is Zo
T
DSignal at D due toreverse couplinggetting reflected at D
Tp
Tp Tp Tp0 2 3
High Speed PCB Design: Lecture-6 © Rashad.M.Ramzan 2010-11 15
Tp Tp Tp0 2 3
Near, Far end Crosstalk & Termination,
High Speed PCB Design: Lecture-6 © Rashad.M.Ramzan 2010-11 16
Odd and Even Mode FieldsOdd a d ve ode e ds
High Speed PCB Design: Lecture-6 © Rashad.M.Ramzan 2010-11 17
Impedance variation and Crosstalkpeda ce va at o a d C ossta
High Speed PCB Design: Lecture-6 © Rashad.M.Ramzan 2010-11 18
Crosstalk: Switching Pattern Dependenceg p
High Speed PCB Design: Lecture-6 © Rashad.M.Ramzan 2010-11 19
Crosstalk: Switching Pattern Dependenceg p
1211
1211
LLL
CCC
even
even
+=−=
1211
1211
LLL
CCC
odd
odd
−=+=
1211 LLLZ even +
==
1211
1211
CC
LL
C
LZ
CCCZ
oddodd
eveneven
−==
−
High Speed PCB Design: Lecture-6 © Rashad.M.Ramzan 2010-11 20
1211 CCCoddodd +
Noise-on-Delay Effect: CrosstalkNo se o e ay ect: C ossta
High Speed PCB Design: Lecture-6 © Rashad.M.Ramzan 2010-11 21
Examplea p eCross-talk=R2CM/T10-90, =4pF*37 5Ω/5ns=0 03(3%)4pF 37.5Ω/5ns 0.03(3%) still OK.But when T10-90 = 1 ns, cross-talk=15% !!
High Speed PCB Design: Lecture-6 © Rashad.M.Ramzan 2010-11 22
Examplea p e• Cross-talk=CMR(input R of
/receiver) /Tr
• It is still OK, if the input h ll l ll R fhas a parallel small R of 75Ω. Cross-talk=3%.
• If R2 = 10K (ie Open• If R2 = 10K (ie Open Collector), crosstalk=800%.
• Rule: Add capacitors connected to large pull-up resistors for reducing cross-talk.
High Speed PCB Design: Lecture-6 © Rashad.M.Ramzan 2010-11 23
Crosstalk vs. Geometry of TracesC ossta vs. Geo et y o aces
High Speed PCB Design: Lecture-6 © Rashad.M.Ramzan 2010-11 24
Crosstalk vs. Geometry of TracesC ossta vs. Geo et y o aces
High Speed PCB Design: Lecture-6 © Rashad.M.Ramzan 2010-11 25
Crosstalk in Solid GND PlaneC ossta So d GN a e
High Speed PCB Design: Lecture-6 © Rashad.M.Ramzan 2010-11 26
Crosstalk in Slotted GND PlaneC ossta S otted GN a e
High Speed PCB Design: Lecture-6 © Rashad.M.Ramzan 2010-11 27
Crosstalk in Slotted GND PlaneC ossta S otted GN a e
High Speed PCB Design: Lecture-6 © Rashad.M.Ramzan 2010-11 28
Crosstalk in Crosshatched GND PlaneC ossta C oss atc ed GN a e
High Speed PCB Design: Lecture-6 © Rashad.M.Ramzan 2010-11 29
Crosstalk with PWR and GND FingersC ossta w t W a d GN ge s
High Speed PCB Design: Lecture-6 © Rashad.M.Ramzan 2010-11 30
Guard Rings: Reduce the CrosstalkGua d gs: educe t e C ossta
High Speed PCB Design: Lecture-6 © Rashad.M.Ramzan 2010-11 31
How much Crosstalk?ow uc C ossta ?
How much crosstalk is too much?
• Crosstalk level of 1-3% between adjacent wires is fine
• Assumes that there exists solid ground plane• Assumes that there exists solid ground plane
• Each wire interacts only with its nearest neighbours
• Cross-coupling from other more remote wires is negligible
High Speed PCB Design: Lecture-6 © Rashad.M.Ramzan 2010-11 32
Rule to Minimize Crosstalku e to e C ossta
High Speed PCB Design: Lecture-6 © Rashad.M.Ramzan 2010-11 33
Case Study: False TriggeringCase Study: a se gge g
Problem:8 Bit wide Bus, Four Layer boardDriving Buffer Rs = 30 ΩSwing = 2V, Length of trace= 5 in
Goals is to Determine:1. Self inductance and Capacitance.g , g
Center-Center Spacing =15 Mil, Zo(with Out Cross talk) = 50 Ωε = 4.0 (FR4)
2. Max impedance variation due to Crosstalk?
3. Max velocity variation due to Crosstalk?εr 4.0 (FR4)
Input Buffer capacitance << ignoredMutual inductance = 0.54 nH/inMutual Capacitance = 0 079 pF/in
Crosstalk?4. Input buffer at U2 will switch at 1.0V,
if there is possibility of false triggering?
High Speed PCB Design: Lecture-6 © Rashad.M.Ramzan 2010-11 34
Mutual Capacitance = 0.079 pF/in triggering?
Case Study: False TriggeringCase Study: a se gge g1. Self Inductance and Capacitance:
1−
FHWFR
WH
TF
W
Hr
rre
023/5/4)4(
)1(217.012
12
1
2
1 2
1
=⇒==
−−+⎥⎦⎤
⎢⎣⎡ +
−+
+=
−
ε
εεεε
FHWFR
e
r
)23(05
0.1)14(217.00
5
)2.3(121
2
14
2
14
02.3/5/,4)4(
2
1
−−+⎥⎦⎤
⎢⎣⎡ +
−+
+=
=⇒==−
ε
ε
smsmc
v
e
/10781/100.3
84.2
)2.3(0.5522
88
×=×
==
=⎦⎣
εpsin
ps
inpsinVelocity
713
/0070.0713
5)/( ==
psi
minlengthTD
smv
r
r
713)01
0254.0(
/10781
0.5
/1078.184.2
8===
×===
ε
ε
C
LZ
inpsin
psLCinchperTD
o 50
/6.1420.5
713)(
Ω==
===
Qpinsmc
)0.1
(/1078.1 8×
pFps
CL
LC
Z
TDC
C
o
85.250
6.142====⇒
High Speed PCB Design: Lecture-6 © Rashad.M.Ramzan 2010-11 35
nHCLLCZTDL o 13.7=×=×=⇒
Case Study: False TriggeringCase Study: a se gge g2. Max Velocity variation due to Crosstalk
High Speed PCB Design: Lecture-6 © Rashad.M.Ramzan 2010-11 36
Case Study: False TriggeringCase Study: a se gge g
CCC
LLLZ common
231222
231222,2 −−
++=
pFpFpF
nHnHnHZ common 26.55
079.0079.085.2
54.054.013.7,2 Ω=
−−++
=
CCCLLLTD common ))(( 231222231222,2 −−++=
inpsTD
pFpFpFnHnHnHTD
common
common
/6.148
)079.0079.085.2)(54.054.013.7(
,2
,2
=
−−++=
High Speed PCB Design: Lecture-6 © Rashad.M.Ramzan 2010-11 37
Case Study: False TriggeringCase Study: a se gge g
High Speed PCB Design: Lecture-6 © Rashad.M.Ramzan 2010-11 38
Case Study: False TriggeringCase Study: a se gge g
CCC
LLLZ ldiffrentia
231222,2 ++
−−=
pFpFpF
nHnHnHZ
CCC
ldiffrentia 8.4407900790852
54.054.013.7,2
231222
Ω=++−−
=
++
CCCLLLTD
pFpFpF
ldiffrentia ))((
079.0079.085.2
2312222312222 ++−−=
++
inpsTD
pFpFpFnHnHnHTD
ldiff ti
ldiffrentia
ldiffrentia
/135
)079.0079.085.2)(54.054.013.7(
))((
2
,2
231222231222,2
=
++−−=
inpsTD ldiffrentia /135,2
impadanceandvelocityinVariation
psTDps
Z
impadanceandvelocityinVariation
o
6148135
26.558.44
<<Ω<<Ω
High Speed PCB Design: Lecture-6 © Rashad.M.Ramzan 2010-11 39
psTDps 6.148135 <<
Case Study: False TriggeringCase Study: a se gge g3. If Crosstalk will induce false triggering?
The signal will ring down to a minimum voltage gof 1.84V.
Since the threshold voltage of thisvoltage of this buffer was defined to be 1.0V, and signal does not ring back down toring back down to this value.
The signal i t it ill tintegrity will not cause false triggering.
High Speed PCB Design: Lecture-6 © Rashad.M.Ramzan 2010-11 40
SummerySu e y• There in no velocity variation due to Crosstalk in Striplines but
there is in Microstripthere is in Microstrip.
• The nearest neighbor has greatest effect.
• Common mode (All bit in phase) and differential (only target• Common mode (All bit in phase) and differential (only target out of phase) mode produce worst velocity and impedance variation.
• Low impedance line produces less impedance variation.
• The impedance of the trace is effected by the proximity of the p y p yneighbor traces even when they are not driven,
• Mutual parasitic falls off exponentially with trace-to-trace spacing.
High Speed PCB Design: Lecture-6 © Rashad.M.Ramzan 2010-11 41
Wakeup Please lets havepSome Food….
42