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ELE863 VLSI Systems
On-Chip Power and ClockDistribution
Fei Yuan, PhD. PEng.Department of Electrical & Computer Engineering
Ryerson UniversityToronto, Ontario, Canada
Copyright c©Fei Yuan, 2012
Copyright (c) F. Yuan (1)
Preface
This chapter covers the fundamentals of on-chip power distribution, on-chip clock generation, anddistribution. Materials of this tutorial are drawn from various published texts and published research
papers. Students are strongly advised to read the cited references for further information on thesubjects.
Copyright (c) F. Yuan (2)
OUTLINE
• Power Distribution
• Clock Generation and Distribution
• References
Copyright (c) F. Yuan (3)
Power Distribution
• Introduction
• Power Distribution Guidelines
• Power and Ground Distribution Trees
• Dual Power and Ground Pads and Trees
• Dual Power and Ground Distribution Rings
Copyright (c) F. Yuan (4)
Introduction
• Background
⊲ Power and ground distributions are the number one issue in chip
floor planning.
⊲ Power and ground must be distributed using metal interconnectsdue to their low resistance.
⊲ The top metal layer has the largest thickness (lower resistance perunit width whereas lower metal layers usually have smaller butidentical thickness.
⊲ The minimum width of metal interconnects for power and grounddistribution is governed by (1) electron migration that sets the
maximum allowable average current and (2) the instantaneousvoltage drop along the metal interconnects that sets the peakcurrent.
Copyright (c) F. Yuan (5)
Introduction (cont’d)
• Basic Concepts
⊲ Peak Current Density
Jpeak =Ipeak
A, (1)
where A=cross-section area of interconnect.
⊲ Average Current Density
Javg =1
T
∫ T
0j(t)dt, (2)
where T=period of the waveform of the current flowing through the
interconnect.
⊲ RMS Current Density
Jrms =
√
√
√
√
1
T
∫ T
0j2(t)dt. (3)
⊲ Typical 0.35µm CMOS parameters : At 110C, Jpeak = 1mA/µm,Jpeak,contact = 0.95mA/µm, Jpeak,via = 0.6mAµm. The average
interconnect current can be derived from Jpeak by including thewaveform of the current.
Copyright (c) F. Yuan (6)
Introduction (cont’d)
• Electromigration
⊲ When a current flows through an interconnect, an electron wind isset up opposite to the direction of the current. These electrons,
upon colliding with the metal ions, impact sufficient energy anddisplace the metal ions from their lattice sites, creating vacancies.
These vacancies condense to form voids that result in an increase inthe local resistance of the interconnect and eventually create
open-circuit conditions.
⊲ Electromigration lifetime of interconnects is determined by Javg [10].For signal lines where the currents are usually bi-directional, less
electromigration is observed. For power lines where the currents areusually unidirectional, sever electromigration exists.
Copyright (c) F. Yuan (7)
Introduction (cont’d)
• Self-Heating
⊲ Challenges in thermal management of interconnects
⊲ Increased number of layers of interconnects : 3 metal layers for
0.35µm, 6 metal layers for 0.18µm, 8 metal layers for 0.13µm, 9metal layers for 50nm. The top metal layer is far away from thesubstrate and is isolated by field oxide (SiO2) that is very low
thermal conductivity.
⊲ Reduced contact and via dimensions −→ increased current densityat contacts and vias.
⊲ Low dielectric constant materials are being introduced asalternative insulators to reduce cross-talk among and the parasitic
capacitance between interconnects. These materials have reducedthermal conductivity.
Copyright (c) F. Yuan (8)
Power Distribution Guidelines
⊲ Power and ground interconnects must be sized such that the thereis a safe margin between normal operating currents and the
maximum allowable currents of the interconnects.
⊲ Power and ground interconnects must be sized such that the voltagedrops over the power and ground wires are sufficiently small.
⊲ The number of contacts and vias in power and ground paths mustbe determined so that their overall current-carrying ability issufficient and the voltage drops over them is sufficiently small to
ensure a reliable operation.
Copyright (c) F. Yuan (9)
Power Distribution Guidelines (cont’d)
⊲ Use separate power and ground interconnects for ESD protectioncircuitry and core circuitry. This is because ESD protectioncircuitry will carry very large currents in the case of an ESD strike.
⊲ Use separate power and ground interconnects for analog and digitalcircuits. The details of this criterion were presented in the chapterof simultaneous switching noise (SSN). Refer to SSN chapter of the
details.
⊲ Use separate power and ground interconnects for analog blocks and
their bias circuitry if possible. The reason for this is that theoperation of the biasing circuitry should be absolutely stable.
Main analogcircuits
Biascircuits
Biascircuits
Main analogcircuits
Main VDD
Bias VDD
Main VSS
Bias VSS
Figure 1: Separate power and ground for analog blocks and their bias circuitry
Copyright (c) F. Yuan (10)
Power Distribution Guidelines (cont’d)
⊲ Use separate power and ground interconnects analog blocks andtheir guard rings.
Vss
p+ n+ n+ p+
S G D
Digital portion
Analog portion
Guard ring
Effective on collecting holes fromdigital portion only
VSS
p+ n+ n+ p+
S G D
Digital portion
Analog portion
Double guard rings
Effective on collecting electronsand holes from digital portion
n+n+
VDD
Figure 2: Single and double guide rings
Copyright (c) F. Yuan (11)
Power and Ground Distribution Trees
⊲ Power distribution trees with the power supply at the root and thelogic gates connected to the twinges. Each branch must be wide
enough to carry the current in all of its sub-branches.
VDD
VSS
Figure 3: Power and ground distribution trees
Copyright (c) F. Yuan (12)
Power and Ground Distribution Trees (cont’d)
Figure 4: Power and ground distribution trees [6]
Copyright (c) F. Yuan (13)
Dual Power and Ground Pads and Trees
⊲ Power and ground pads are placed on both sides of the chip to (1)reduce the length of power and ground interconnects and (2) to
reduce the voltage drops along the power and ground interconnects.
CIRCUITS
VDD VSS
VDD VSS
Figure 5: Dual power and ground pads and trees [?]
Copyright (c) F. Yuan (14)
Dual Power and Ground Pads and Trees
Figure 6: Dual power and ground pads and trees
⊲ As an example, let the sheet resistance be R2 = 0.05Ω,
L = 1000µm, W = 1µm, we have R = R2
LW
= 50Ω. If I = 10mA,we have the voltage drop cross the interconnect V = RI = 0.5V.
⊲ More VDD and VSS pads should therefore be used to reduce the
voltage drop along VDD and VSS interconnects.
Copyright (c) F. Yuan (15)
Dual Power and Ground Distribution Rings
VDD
(RING)
VSS
(RING)
CORE
CIRCUITS
VDD
(CORE)
VSS
(CORE)
VDD
(RING)
VSS
(RING)
VDD
(CORE)
VSS
(CORE)
Signal
pad
VDD (RING)
Figure 7: Double power and ground distribution rings
⊲ The outer power and ground rings provide VDD and VSS for ESD
protection circuitry. The inner power and ground rings provideVDD and VSS for core circuitry.
⊲ Separate pads for ring and core circuitry.
Copyright (c) F. Yuan (16)
Clock Generation and Distribution
• Oscillators
• Clock Generators
• Clock Signal Direction
• Clock Skew
• Clock Distribution
Copyright (c) F. Yuan (17)
Oscillators
• Crystal oscillators
• Ring oscillators
• LC tank oscillators
Copyright (c) F. Yuan (18)
Crystal Oscillators
1 2
C1 C2
Crystal
Figure 8: Crystal oscillator
⊲ Crystal oscillators are mechanical oscillators.
⊲ Inverter 1 provides needed voltage difference.
⊲ Crystal can be represented by a RLC equivalent circuit.
⊲ Superior stable oscillation −→ used in most microprocessors.
⊲ Low oscillation frequency. When high clocks of high frequencies areneeded, frequency synthesizers and clock generators are needed.
Copyright (c) F. Yuan (19)
Ring Oscillators
• Static CMOS Inverter Ring Oscillators
• Fully Differential Ring Oscillators
• Voltage-Controlled Ring Oscillators
Copyright (c) F. Yuan (20)
Static CMOS Inverter Ring Oscillators
CLK
CLK
Figure 9: Ring oscillators
⊲ The number of inverters in the ring must be odd.
⊲ Oscillation starts by amplifying the noise residing in the circuit.
Note that a static CMOS inverter has a very large voltage gain inits transition region, the region where both nMOS and pMOS
transistors are in saturation. The small noise is amplified fully suchthat the inverters experience a from small-signal to full-swing
operation.
⊲ Oscillation period T = Nτ , where τ=average propagation delay ofthe inverter and N=number of inverters in the ring.
⊲ Buffers (inverter chain with gradually increased size) are needed to
drive load (CLK and CLK).
⊲ Delay is strongly affected by the fluctuation of VDD and VSS.
Oscillation frequency is process, temperature, and power supplydependent, and is unstable. This type of ring oscillators are used forlow-end processors and applications where absolute clock accuracy
is not critical.
Copyright (c) F. Yuan (21)
Fully Differential Ring Oscillators
Vc
V+ V-
Vb
1 0 1 0 1
0 1 0 1 0
Vc
Vb
Figure 10: Differential-pair Ring oscillator
⊲ Inverters are implemented using differential-mode logic circuits
(CML (current-mode logic) and current-steering logic).Differential-mode logic circuits have the advantages of (1)
high-speed due to reduced voltage/current swing and (2) theminimum switching noise due to the constant tail current.
⊲ Oscillation period T = Nτ , where τ=the average propagation delay
of the inverter and N=number of inverters in the ring.
⊲ Oscillation frequency is independent of power and ground variations(ideally). Attractive for high-speed applications such as RF and
optical communication systems, as well as mixed-mode systems.
⊲ High phase noise due to the up-conversion of 1/f noise of the tailcurrent source citeHajimiri1999.
Copyright (c) F. Yuan (22)
Cross-Coupled VCOs
Vc
V+ V-
1 0 1 0 1
0 1 0 1 0
Vc
Vb
Figure 11: Cross coupled VCO
⊲ The pMOSs are biased in deep triode region and they behave as a
linear resistor approximately [11, 12].
⊲ Positive feedback is used to speed up the state transition region.The transition region is most sensitive to VDD and VSS fluctuations.
Noise injected in this region contribute most to the timing jitter [9].
⊲ The tail current source is removed to eliminate the phase noisearising from the up-conversion of 1/f noise of the tail current
source.
⊲ Very attractive for low-noise applications.
Copyright (c) F. Yuan (23)
LC Tank VCOs
⊲ Parallel RLC networks
z(s) =jωLp
[1 − ( ωωo
)2] + jω Lp
Rp
(4)
⊲ At ωo = 1√CpLp
, z(jωo) = Rp, the network becomes purely resistive.
⊲ At ωo, zL = Rp, vo = −gmRp (-180 degree phase shift).
Lp Rp Cp
|Z|
Z
90
-90
0
Inductive
Capacitive
Resistive
Freq
Freq
wo
Rp
Lp Rp Cp
Vin
Vo
Figure 12: RLC parallel network
Copyright (c) F. Yuan (24)
LC Tank VCOs (cont’d)
Lp Rp Cp
Vo-Vo+
Lp LpRpCp
Varactor(voltge-controlled capacitor)
Spiral inductors or active inductors
Figure 13: LC tank VCO
⊲ At resonant frequency ωo, zL = Rp, Av1 = −gm1Rp, Av2 = −gm2Rp.Both stages give a combined -360 degree phase shift.
⊲ Once the loop gain satisfies Av1Av2 = gm1gm2R2p¿1, oscillation will
start.
⊲ Oscillation frequency is controlled by adjusting the voltage of the
varators (voltage-controlled capacitors).
Copyright (c) F. Yuan (25)
LC Tank VCOs (cont’d)
p+ n+
p-sub
Rsub pn-junction
p+ n+
p-sub
Rn-welln-well
1
2
12
1
2
21
Figure 14: Top - grounded diodes (Varators); Bottom - floating diodes.
⊲ Varators (voltage-controlled capacitors) - the junction capacitance
is a nonlinear function of the reverse biasing voltage
CJ =CJo
√
1 + Vr
φo
, (5)
where CJo=junction capacitance at zero-biasing voltage, φo=built-inpotential of pn-junction. Vr - reverse biasing voltage of the
pn-junction.
Copyright (c) F. Yuan (26)
Clock Generators
single-phase
master
clock
Multi-phase
clocksClock
Generatorf
f1
f2
fn
Figure 15: Clock generator
⊲ Convert a single-phase master clock from a crystal oscillator into a
set of multi-phase slave clocks.
⊲ Improve the driving ability of clock signals −→ use large buffers toprovide large charging and discharging currents.
⊲ Improve the waveforms of clock signals −→ use positive feedbackmechanism to restore waveforms.
Copyright (c) F. Yuan (27)
Clock Generators (cont’d)
• RS-Flipflop Clock Generators
CLK
CLK-1
CLK-2
CLK-2
CLK
CLK-1
t
t
t
Figure 16: Waveforms of RS-Flipflop clock generator (Neglect the delay of the inverter)
Copyright (c) F. Yuan (28)
Clock Generators (cont’d)
• Buffered RS-Flipflop Clock Generators
⊲ To improve the driving ability of clock generators.
CLK
CLK-1
CLK-2
CLK-2
CLK
CLK-1
t
t
t
Inverter with low Vth
Figure 17: Buffered RF-flipflop clock generators
⊲ The delay of the inverter must be small −→ The inverter should
have low Vth so that it can be activated before NOR gates.
⊲ Positive feedback yields output waveforms with sharp edges evenwhen the master clock does not have sharp edges.
⊲ Buffers are often large. When clocked, they dissipate a largeamount of dynamic power.
Copyright (c) F. Yuan (29)
Clock Generators (cont’d)
• Differential Clock Generators
⊲ Motivations - Reduce voltage swing and increase clock speed.
⊲ Circuit configuration:
Master clkMaster clk
Clk
Vdd
Master clkMaster clk
Clk
Vdd
Figure 18: Differential clock buffer
⊲ Only small swing of master clock is needed −→ low powerconsumption and high speed.
⊲ Less noise is injected into the substrate because the bias current is
constant.
⊲ Disadvantages : both MasterClock and its complementary areneeded.
⊲ Note that CLK and CLK are single-ended signals.
Copyright (c) F. Yuan (30)
Clock Generators (cont’d)
• D-Latch and D Flip-Flop
⊲ D-latch : The output Q is transparent to the input D as long as thecontrol signal C is present.
⊲ D-FlipFlop : The output Q is evaluated only at the transition edgesof the control signal C and remains unchanged elsewhere.
C
D
Q
C
D
Q
Waveform of D-latch
Waveform of D-FlipFlop
Figure 19: D-latch and D-Flipflop
Copyright (c) F. Yuan (31)
Clock Generators (cont’d)
• 50% Duty-Cycle Clock Generator
D1
Q1
Q1
CLK
D2
Q2
Q2
F
F1
CLK
t
t
t
tt
t
F
D1
Q1
D2
Q2
Figure 20: 50% Duty-Cycle Clock Generator and its waveforms (neglect the delay of inverter)
⊲ The output of D-latch remains unchanged if Φ = 0.
⊲ The frequency of Φ1 is half of that of Φ.
Copyright (c) F. Yuan (32)
Clock Generators (cont’d)
• 25% Duty-Cycle 25% Separation Clock Generator
D1
Q1
Q1
CLK
D2
Q2
Q2
F
CLK
t
F
D1
Q1
D2
Q2
D2
Q2
Q2
CLK
Delay of D-Flipflop
D-Flipflop D-Flipflop D-Flipflop
Figure 21: 25% Duty-Cycle 25% Separation Clock Generator
Copyright (c) F. Yuan (33)
Clock Signal Direction
⊲ The output of Latch-n responds to its inputs when Φn = 1 andΦn = 0.
⊲ Ideally, the delay of the logic circuit n = the delay of the delay celln.
⊲ Logic circuit n+1 will respond to the output of Latch-n when it is
available.
⊲ If the propagation delay of Logic circuit n + 1 is less than that ofDelay unit n + 1, then the content will be affected by Logic circuit n
when Φn goes HIGH.
Delayn
Delayn+1
Latchn
Latchn+1
Logiccircuitn
Logiccircuitn+1
F
F
F
F
F
F
F FF F
n-1
n-1
n
n n+1
n+1
Data
Figure 22: Clock propagates in the same direction as the data
Copyright (c) F. Yuan (34)
Clock Signal Direction (cont’d)
⊲ Latch n+1 goes into the latch mode before the output of Latch nbegins to move.
⊲ Clock signals should propagate in the opposite direction.
Delayn
Delayn+1
Latchn
Latchn+1
Logiccircuitn
Logiccircuitn+1
F
F
F
F
F
F
F FF F
n-1
n-1
n
n n+1
n+1
Data
Figure 23: Clock propagates in the opposite direction as the data
Copyright (c) F. Yuan (35)
Clock Skew
• Clock Skew
• Positive and Negative Clock Skew
• System-Level Clock Skew
• Phase-Lock Loops
Copyright (c) F. Yuan (36)
Clock Skew
Latchn
Latchn+1
Logiccircuitn
Logiccircuitn+1
F Fn n+1
Data
Figure 24: Clock skew
⊲ Ideally Φn and Φn+1 are synchronized −→ zero clock skew.
⊲ Clock skew is the difference in clock signal arrival time between twosequentially adjacent registers (blocks).
τskew = τn − τn+1 (6)
where τn=delay from the clock source to stage n.
⊲ Clock skew is due to the unbalanced of the data paths (i.e. differentpropagation delay). Although the layout of two data paths isidentical, the different neighboring devices will also results in
different propagation delay, subsequently clock skew.
⊲ The minimum clock period between two registers must be greater
than the sum of propagation delay and the clock skew.
Tmin = τPD + τskew (7)
where τPD=propagation delay between stages n and n + 1,
τskew=clock skew
Copyright (c) F. Yuan (37)
Positive and Negative Clock Skew
F
F
n
n+1
Skewt > 0
F
F
n
n+1
Skewt < 0
Positive clock skew
Negative clock skew
Figure 25: Positive and negative clock skew
⊲ Positive clock skew increases the minimum clock period.
Subsequently reduces the max. operation frequency.
⊲ Positive clock skew does not create race conditions because theinput of the combinational circuits (stage n + 1) are not available
yet.
⊲ Negative clock skew reduces the minimum clock period.Subsequently increase the max. operation frequency.
⊲ Negative clock skew may create race conditions.
⊲ τskew of negative clock skew cases must be LESS THAN the timerequired for the data to leave Latch (n), propagate through the
interconnects and combinational logic circuits (n+1) in between,and allow Latch (n+1) to latch up.
Copyright (c) F. Yuan (38)
System-Level Clock Skew
Masterclock
Clockgenerator
Clockgenerator
Logiccircuits
Logiccircuits
CHIP-1 CHIP-2
F
F1 F2
Figure 26: Clock skew at system levels
⊲ Φ1 and Φ2 are synchronized ideally. In reality, however, Φ1 and Φ2
are not synchronized due to clock skew.
⊲ The outputs generated by chips 1 and 2 are not be synchronized.
⊲ Solution - use phase-lock loop (PLL) to synchronize Φ1 and Φ2.
Copyright (c) F. Yuan (39)
Phase-Lock Loops
Phase-FrequencyDetector
1/N
J
J
Loop filter
Charge pump
Voltage-controlled oscillator
Divided by N
Figure 27: Phase lock loop
⊲ Phase-frequency detector detects the frequency and phase difference
between the incoming master clock and the local clock generated byVCO. It generates binary UP and DN signals.
⊲ Charge pump converters binary UP and DN signals into an analog
signal.
⊲ Loop filter is a low-pass that filters out all high-frequencycomponents of the analog signal from the charge pump. The
low-frequency signal is then used to control the frequency of VCO.
⊲ PLL is a typical mixed analog-digital circuits. In practice, allfunction blocks of PLLs must be differentially configured.
Copyright (c) F. Yuan (40)
Clock Distribution
• Buffered Clock Distribution Tree
Masterclock
Buffer
Figure 28: Buffered Clock Distribution Tree
⊲ Buffers amplify degraded clock signals due to distributedinterconnect impedance.
⊲ Buffers isolate local clock networks from up-stream load impedance.
⊲ Buffers provide sufficient currents to drive the network capacitance
and maintain high quality clock waveforms −→ the outputimpedance of the buffers must be much larger than the impedance
of the interconnect sections being driven.
⊲ Due to the variation of the active device characteristics buffers are aprimary source of clock skew for a well-balanced clock tree .
Copyright (c) F. Yuan (41)
Clock Distribution (cont’d)
• Clock Distribution Tree with Parameterized
Buffered
Masterclock
Buffer
Parameterized buffers
Figure 29: Clock Distribution Tree with parameterized buffers
⊲ Parameterized buffers are used to compensate the variation of clockdelay.
⊲ The size of parameterized buffers differs.
Copyright (c) F. Yuan (42)
Clock Distribution (cont’d)
• Symmetric H-Tree Clock Distribution Networks
Noden+1
Z
ZZ
Node nNode n
n
n+1
n
Taped H-Tree clock distribution network
Figure 30: Symmetric H-Tree Clock Distribution Networks
⊲ The length of interconnects is identical from the source node n + 1to the two destination nodes n.
⊲ The primary delay difference among the clock signal paths is due tothe variations of process parameters affecting (i) interconnectimpedance and (ii) characteristics of buffers.
⊲ The interconnect width is decreased progressively to minimize thereflection of high-speed clock signals. The impedance of theinterconnects leaving node n + 1, denoted by Zn, must be TWICE
the impedance of the interconnects providing the signal to noden + 1.
⊲ Interconnect capacitance is much larger as compared with the
standard clock tree due to longer wire length.
⊲ Difficult to route in practice.
Copyright (c) F. Yuan (43)
References
References
[1] Jan M. Rabaey, Digital Integrated Circuits : A Design Perspective, UpperSaddle River, New Jersey : Prentice-Hall, 1996.
[2] K. Martin, Digital Integrated Circuit Design Oxford University Press, 2000.
[3] Wayne Wolf, Modern VLSI Design : Systems on Silicon, 2nd edition, Prentice
Hall, Upper Saddle River, NJ 07458, 1998.
[4] B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2001.
[5] A. Bellaoura and M. I. Elmasry, Low-power digital VLSI design : Circuits and
Systems, Boston : Kluwer Academic, 1995.
[6] D. Clein, CMOS IC Layout - Concepts, Methodologies, and Tools,Newnes,
Boston, 1999.
[7] E. G. Friedman, “Introduction : clock distribution networks in VLSI circuits
and systems,” pp. 1-35.
[8] Analog Design Flow, Canadian Microelectronics Corporation, 2001.
[9] A. Hajimiri, S. Limotyakis, and T. Lee, “Jitter and phase noise in ringoscillators,” IEEE J. Solid-State Circuits, Vol. 34, No. 6, pp. 790-804, Jun. 1999.
[10] B. Liew, N. Cheung, and C. Hu, “Projecting interconnect electromigrationlifetime fo arbitrary current waveform,” IEEE Trans. on Electron Devices, vol.37, pp. 1343-1350, 1990.
[11] J. Lee and B. Kim, “A low-noise fast-lock phase-locked loop with adaptivebandwidth control,” IEEE J. Solid-State Circuits, vol. 35, No. 8, pp. 1137-1145,
Aug. 2000.
Copyright (c) F. Yuan (44)
[12] J. Kim, S. Lee, T. Jung, C. Kim, S. Cho, and B. Kim, “A low-jittermixed-mode DLL for high-speed DRAM applications,” IEEE J. Solid-State
Circuits, vol. 35, No. 10, pp. 1430-1436, Oct. 2000.
[13] D. Jeong, S. Chai, W. Song, and G. Cho, “CMOS current-controlled oscillators
using multiple-feedback-loop ring architectures,” in Proc. Int’l Solid-State
Circuit Conf., pp.386-387, 1997.
[14] C. Park and B. Kim, “A low-noise, 900-MHz VCO in 0.6µm CMOS,” IEEE J.
Solid-State Circuits, Vol. 34, No. 5, pp. 586-591, May 1999.
[15] Y. Eken and J. Uyemura, “A 5.9-GHz voltage-controlled ring oscillator in
0.18µm CMOS,” IEEE J. Solid-State Circuits, Vol.39, No. 1, pp. 230-233, Jan.2004.
Copyright (c) F. Yuan (45)