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Clock domains & divider Clock & reset distribution. A. Kluge Feb 5 & 6, 2013. clk domains. pixel_hit clk_config clk_dll clk_sync ( hronous ) clk_serial clk_multi_serial. clk_config. clk_multi_serial. clk_sync. clk_serial. clk_dll. Clk distribution: serial 3.2 Gbit /s. - PowerPoint PPT Presentation
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Clock domains & dividerClock & reset
distributionA. Kluge
Feb 5 & 6, 2013
Feb 5 & 6, 2013
clk domains pixel_hit clk_config clk_dll clk_sync(hronous) clk_serial clk_multi_serial
A. Kluge 2
Feb 5 & 6, 2013
A. Kluge 3
clk_syncclk_serial
clk_multi_serial
clk_config
clk_dll
Feb 5 & 6, 2013
Clk distribution: serial 3.2 Gbit/s
A. Kluge 4
Feb 5 & 6, 2013
Clk distribution: serial 3.2 Gbit/s
A. Kluge 5
30 bit shift register
every 6th clock cycle one word is sent to serializer
every 53 MHz new word of 48 bits on 4 outputs 48/4 ports * 53 MHz = 640 MHz
Feb 5 & 6, 2013
clk domain crossingpixel_hit clk_sync
hitArbiterclk_sync clk_serialclk_sync clk_multi_serialclk_config clk_syncclk_dll clk_sync tdc,
qchip
A. Kluge 6
Feb 5 & 6, 2013
A. Kluge 7
clk_syncclk_serial
clk_multi_serial
clk_config
clk_dll
Feb 5 & 6, 2013
clk_sync clk_serial clock_enable_generator frequ_clk_sync =
6 * frequ_clk_fifo_read = 6 * frequ_enable_clk_sync 12 * for modes 1, 4, 6
qchip runs on clk_sync flip flops are enabled only upon enable_clk_sync TDC is read-out only every 6th (12th) clk_sync cycle serializer is loaded only every 6th (12th) clk_sync
cycle
A. Kluge 8
Feb 5 & 6, 2013
clock_enable_generator
Serializer provides sync signal - clk_fifo_read frequency = parallel_word_freqency falling edge + 3 (3.5) serial_frequ/2 marks parallel
load time
clk_enable_generator synchronizes clk_fifo_read to clk_sync domain waits for time-out measures position of clk_fifo_read, once
does not re-adjust later-on produces enable_clk_sync pulse around rising edge
of clk_fifo_read marks safe parallel_word change time
A. Kluge 9
Feb 5 & 6, 2013
clk_sync clk_serial
A. Kluge 10
first_enable_after_delay
Feb 5 & 6, 2013
clock_enable_generator
hold/setup [ns] mode 0: 11.6-9.5 / 13.4/15.5 mode 1: 15.7-13.6 / 9.3 – 11.4 mode 2: 10.3 – 7.2 / 8.5 – 11.6
A. Kluge 11
Feb 5 & 6, 2013
clk_enable_generator
A. Kluge 12
Feb 5 & 6, 2013
A. Kluge 13
clk_syncclk_serial
clk_multi_serial
clk_config
clk_dll
Feb 5 & 6, 2013
multi_serial_synchronisationclk_sync clk_multi_serial
synchronizes enable_clk_sync into clk_multi_serial domain
measures the position of enable_clk_sync once
locks parallel_load time in middle of two enable_clk_sync pulses
hold/setup time of ~ 9 ns
A. Kluge 14
Feb 5 & 6, 2013
multi_serial_synchronisationclk_sync clk_multi_serial
A. Kluge 15
Feb 5 & 6, 2013
multi_serial_synchronisationclk_sync clk_multi_serial
A. Kluge 16
Feb 5 & 6, 2013
A. Kluge 17
clk_syncclk_serial
clk_multi_serial
clk_config
clk_dll
Feb 5 & 6, 2013
clk_config clk_sync
A. Kluge 18
CLK_SYNC
CLK_SYNC
CLK_SYNC
CLK_SYNC
Feb 5 & 6, 2013
Operation modes
A. Kluge 19
serialPLL2.4lowClkSync
serialPLL2.4highClkSync
serialPLL3.2
ext320lowClkSync
ext320highClkSync
ext480lowClkSync
ext480highClkSync
pllOverride
# 0 1 2 3 4 5 6 7code 00111
0000110 001100 H110H
0H100H0
H110H1
H100H1
1011H0
clkInDigital 320 320 320 320 320 480 480 320clkPLL 2400 2400 3200 - - - - 320clkSync 240 480 320 160 320 240 480 32clkFIFOread
40 40 53 27 27 40 40 5.3clkMultiSerial
480 480 640 320 320 480 480 64clkConfig 320 320 320 320 320 240 240 320
Feb 5 & 6, 2013
PLL & clock divider
A. Kluge 20
Feb 5 & 6, 2013A. Kluge 21
Feb 5 & 6, 2013A. Kluge 22
Feb 5 & 6, 2013A. Kluge 23
Feb 5 & 6, 2013A. Kluge 24
Feb 5 & 6, 2013
clock distribution Clock_sync on 5 outputs @PLL&Serializer
block 4 x quarter chip + 5 x TDC & 1 x configuration
block distributed on the top level with clock tree
TDC distributes clock to dll_state_machine_and_lock_detector internally
A. Kluge 25
Feb 5 & 6, 2013
Reset distribution Reset signal arrives from from two sources
externally from a low active input pad internally from the configuration block reset_synchronizer_asynchron
synchronizes the asynchronously arriving external reset_global_i signal to clk_sync in the config block and in the 4 quarter chips blocks
A. Kluge 26
Feb 5 & 6, 2013A. Kluge 27
reset_synchronizer_asynchron
Feb 5 & 6, 2013
Reset distribution quarter chip distributes reset signal to TDC blocks
In TDC reset is synchronized using reset_synchronizer block.
Internally TDC forwards reset to dll_state_machine_and_lock_detector block
where again a reset_synchronizer is used. Staged reset distribution allows simpler
propagation delay management Drawback that all TDCpix blocks are reset in
stages of 3 clock cycles no impact on functionality All synchronizers triplicated and internal reset
signals are forwarded as high active signals whereas external reset_global_i input is low active
A. Kluge 28
Feb 5 & 6, 2013
Reset coarse counter External signal which sets the coarse counter to 0
Connected to dll_clk_fanout fowards it to TDC as a one clock cycle long pulse
to the quarter chip as a two cycle long pulse Two cycle long pulse is needed as the copy of the
coarse counter in the qchip is running on clk_sync on not on clk_dll as in the TDC
If clk_sync is slower than clk_dll one clk_dll long pulses might not be registered by the qChip
Synchronisation of reset_coarse_count uses reset_synchronizer_asynchron
Reset_coarse_counter also can be initiated by software via the configuration block
A. Kluge 29
Feb 5 & 6, 2013
Clock and reset distribution
A. Kluge 30