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Clock Recovery and Channelized SDH/SONET
Tao Lang
Wintegra IncWintegra Inc.
+1-512-345-3808
A Simple Agenda
Problem Statement
S l tiSolution
Summary
Time & Synchronisation in Telecoms Conference 2008 2
E1/T1 Pseudo-wire
E1/T1 E1/T1SAToP/CESoPSN
Packet Network
Logical View
E1/T1PWE3E1/T1
Packets
g
E1/T1 IWFFramer
Time & Synchronisation in Telecoms Conference 2008 3
PWE3: Pseudo Wire Emulation Edge-to-EdgeIWF: Interworking Function
Clock Recovery
Master Clock Recovered Clock
Master Slave
ClockPSN
E1/T1E1/T1
E1/T1Clock
PacketLaunch
E1/T1 FramerDifferentialTimestamp RTP
Timestamp
Differential Reference Clock
For adaptive clock recovery, master clock is encoded in packet launch time– Slave will have to recovery the master clock from packet inter-arrival time
For differential clock recovery master clock is encoded in timestamp
Time & Synchronisation in Telecoms Conference 2008 4
For differential clock recovery, master clock is encoded in timestamp– Slave will have to recovery the master clock from differential timestamp
Apply PWE3 to Wireless Back-Haul Application
4x E1/T1RNC
4x E1/T1CellSite
CentralOffice
PSN
E1/T1PWE3IWF
QuadE1/T1
FPacketsIWFFramer
E1/T1Clocks
Timing is distributed from RNC to base-stationsTiming is distributed from RNC to base-stations
Clock recovery wise– CO box is the master end Encode the master clock in TDM-to-PSN direction
Time & Synchronisation in Telecoms Conference 2008 5
CO box is the master end Encode the master clock in TDM to PSN direction– Cell-site box is the slave end Recover the master clock in PSN-to-TDM direction
If We Try to Scale Up ……
4x E1/T1CellSite
RNC CentralOffice
4x E1/T1CellSite
Cell4x E1/T1
CellSite
E1/T1
PWE3IWF
Clocks252/336E1/T1
Framers
252E1/336T1 It is not practical to have so
many individual E1/T1 ports onFramers many individual E1/T1 ports on a card or box
Must use channelized
Time & Synchronisation in Telecoms Conference 2008 6
SDH/SONET
Adding STM-4/OC12 Interface ……
RNC CentralOffice
STM-4/OC12/OC12
Any off-the-shelf mapper only provides multiplexed parallelMultiplexed
PWE3
provides multiplexed parallel bus to carry large number of E1/T1 tributaries
1/ 1STM-4/OC12
E1/T1
bus carrying252E1/336T1
IWF E1/T1 rate is adapted to SDH/SONET rate with pointer adjustment
/OC12Framer
Mapper
252E1/E1/T1 rate is adapted to multiplexed bus (e.g. SBI) clock rate with byte stuffing
PointerAdjustment
ByteStuffing
252E1/336T1
Time & Synchronisation in Telecoms Conference 2008 7
rate with byte stuffing
A Degraded Master Clock
E1/T1Clocks
PacketLaunch
The master clock seen by the PWE3 IWF is degraded
STM-4/OC12
E1/T1Mapper
DifferentialTimestamp
degraded– SDH/SONET pointer
adjustment– Byte stuffing on
/OC12Framer
Mapper
Differential Reference Clock
E1/T1D t
Byte stuffing on multiplexed bus
This will introduce wander to the master
Pointer Adjustment and Byte Stuffing
Data
Master
wander to the master clock
The wander frequency MasterClock
Adaptive Averaging Window
e a de eque cycan be too low for the clock recovery algorithm to filter out
RecoveredF
pAlgorithm
Averaging Window
f
Time & Synchronisation in Telecoms Conference 2008 8
Frequency
Actual E1/T1 frequency
Problem Statement
E1/T1 clock recovery in channelized SDH/SONET has unique challenge
Master clock will have wander due to pointer adjustment and byte stuffing
Wander frequency can be very low when E1/T1, SDH/SONET and multiplexed bus frequencies are all close to each other
L f d t b filt d t b l kLow frequency wander can not be filtered out by clock recovery algorithm running at the slave end
Time & Synchronisation in Telecoms Conference 2008 9
Solution
E1/T1Clocks
PacketLaunchSTM-4
/OC12E1/T1 Clock
E1/T1Clocks
DifferentialTimestamp
/OC12Framer
Mapper Smoothers
Differential Reference Clock
Clock smoothing is necessary to remove wander at the master end
Time & Synchronisation in Telecoms Conference 2008 10
Differential Clock Recovery (DCR)
E1/T1Clocks
PacketLaunchSTM-4
/OC12E1/T1
MClock
S th
E1/T1Clocks
DifferentialTimestamp
/OC12Framer
Mapper Smoothers
Differential Reference Clock
Smoothed clock is used to generate differential timestamp
Packet launch time is not critical
Need one smoother per E1/T1– Assuming all E1/T1 are independentAssuming all E1/T1 are independent– Up to 252/336 smoothers for channelized STM-4/OC12
Time & Synchronisation in Telecoms Conference 2008 11
A cost effective implementation is the key
Can We Get Rid of the Smoother?
E1/T1Clocks
PacketLaunchSTM-4
/OC12E1/T1
Mapper
Packets
RTP Timestamp
/OC12Framer
MapperDifferentialTimestamp
The current way of generating differential timestamp (based on
Differential Reference Clock
The current way of generating differential timestamp (based on RTP) requires the E1/T1 clock
To get rid of the smoother, differential timestamp must be re-To get rid of the smoother, differential timestamp must be redefined
Time & Synchronisation in Telecoms Conference 2008 12
Can We Get Rid of the Smoother?
E1/T1Clocks
PacketLaunchSTM-4
/OC12E1/T1
Mapper
Packets
RTP Timestamp
/OC12Framer
Mapper
OC12 Clock
Pointer adjustment + stuffing
The current way of generating differential timestamp (based on
Differential Reference Clock
The current way of generating differential timestamp (based on RTP) requires the E1/T1 clock
To get rid of the smoother, differential timestamp must be re-To get rid of the smoother, differential timestamp must be redefined
One example is to pass the pointer adjustment and stuffing p p p j gindication in the packets
Requires standardization work to push forward
Time & Synchronisation in Telecoms Conference 2008 13
Adaptive Clock Recovery (ACR)
E1/T1Clocks
PacketLaunchSTM-4
/OC12E1/T1
MClock
S th
E1/T1Clocks
/OC12Framer
Mapper Smoothers
Smoothed clock is used to launch packetsSmoothed clock is used to launch packets
Some implementation detailsClock distribution– Clock distribution
One clock may drive multiple CESoPSN pseudo-wires if DS0s are from the same E1/T1Load balancing is preferred to avoid transmitting all packets in a burstLoad balancing is preferred to avoid transmitting all packets in a burst
But do we need one smoother per E1/T1– How many independent clock sources or clock domains can ACR
Time & Synchronisation in Telecoms Conference 2008 14
How many independent clock sources or clock domains can ACR support?
Beating Effect
First, there is this beating effect between asynchronous streams
– Outlined in ITU G.8261 10.1.2.3
Beating effect could introduce low frequency wander that can not be filt d t b ACR l ithfiltered out by ACR algorithm
Clock domains must be limited for ACR applicationsACR applications
Time & Synchronisation in Telecoms Conference 2008 15
ACR with Limited Clock Domains
32 E1/T1Clock
PacketLaunchSTM-4 E1/T1 32 Clock
252/336 32STM 4
/OC12Framer
E1/T1Mapper
32 ClockSmoothers
One smoother per clock domain
To save resource and cost, limited number of smoothers (e.g. 32 or less) may be implemented for ACR
Some implementation details– Which E1/T1 is selected to drive the smoother? Failure protection is a must
Cl k di t ib ti– Clock distributionOne clock may drive multiple SAToP/CESoPSN pseudo-wires Load balancing is preferred to avoid transmitting all packets in a burst
Time & Synchronisation in Telecoms Conference 2008 16
A robust implementation is the key
Clock Recovery Measurement
Channelized OC12 (master) to E1/T1 (slave)
Multiple E1/T1 testers all in internal timing mode to emulate multiple clock domainsclock domains
E1/T1 clocks independent of STM-4/OC12 clock
G.8261 modeled packet networkp
E1/T1
E1/T1
E1/T1
PWE3STM-4 E1/T1 Testers
E1/T1
PWE3Master
S/OC12ADM
E1/T1 Testers
STM-4/OC12
PWE3Slave
Time & Synchronisation in Telecoms Conference 2008 17
G.8261 Network
A Real ImplementationCentral
4/8/16E1/T1
CellSite
CentralOffice
RNCSTM-4/OC12
PSN
SBIUFE FPGA
TDM4xGE/SPI3
SBITEMUX336
PM8310
COMETOCTALPM4358
Temux336OC12
Universal Front End(IP from Wintegra)Per DS0 service
Winpath2SAToPCESoPSN
Octal CometT1/E1
Winpath2SAToPCES PSNframer
MapperT1/E1 framers
Per DS0 service TransparentATM TCHDLC
336 clock recoveries
CESoPSNATM/IMAPPP/MLPPPFR/MFR ATM PWE3
FramersCESoPSNATM/IMAPPP/MLPPPFR/MFR ATM PWE3
Time & Synchronisation in Telecoms Conference 2008 18
336 clock smoothers TML2/L3 switch
TML2/L3 switch16 clock recoveries
Test Result #1
Ch li d STM 4 t E1Channelized STM-4 to E1
1 clock domain
No network
STM-4 rate asynchronous (~0.001ppm offset) to the E1 ( pp )under test
TCXO at slave end
Adaptive mode
Without Clock SmootherMTIE = 4us
With Clock Smoother
Time & Synchronisation in Telecoms Conference 2008 19
MTIE = 800ns
Test Result #2
Network Load Vs Time
100
8 T1 pseudo-wires
4 clock domains
20
40
60
80
Load
(%)OC-12 rate asynchronous
(~0.001ppm offset) to the T1 under test
0
20
0 50 100 150 200 250
Time (min)
5 x GE switches
Traffic loading per G.8261 VI 2 2 4VI.2.2.4
10% to 90% ramping
TCXO at slave endTCXO at slave end
With smoothers
Adaptive modep
MTIE = 2us
Time & Synchronisation in Telecoms Conference 2008 20
Summary
Special care has to be taken when running E1/T1 clock recovery from channelized SDH/SONET
The problem is identified as extra wander due to pointer adjustment and/or byte stuffing
The problem can not be resolved by the clock recovery algorithm running at the slave end. It can only be resolved at the master end
Th i l t ti f ACR d DCR h diff t f dThe implementation for ACR and DCR has different focus and considerations
Solution is available in the marketSolution is available in the market
Time & Synchronisation in Telecoms Conference 2008 21