Clock Talk LIVE Schedule Presentation will begin shortly...Proprietary RXAUI/DXAUI 1.8-20 950 JEDEC JESD204B various Per DAC/ADC CCIX CCIX-25G various 350 SMPTE ITU Industry Standard

Clock Talk LIVE Schedule – Presentation will begin shortly

Tuesday, Sept 15th IEEE 1588 Timing Solutions for Non-Telecom Applications

Tuesday, Sept 29th Clock Jitter Demystified and Jitter Requirements for 56/112 SerDes

Tuesday, Oct 13thDesign Considerations When Selecting a XO/VCXO Clock Reference for 56G/112G SerDes

Tuesday, Oct 27thStop Guessing, Use Silicon Labs’ Timing Tools to Build Your Clock Tree

Tuesday, Nov 10thOptimize Timing Solutions for High Speed FPGA and Application Processor Designs

Tuesday, Nov 17th PCIe Gen 4/5/6 Specifications and Jitter Measurement Explained

Tuesday, Dec 1st Timing Solutions for 5G O-RAN Systems

Tuesday, Jan 12th AEC-Q100 Timing Products for Automotive Applications

Tuesday, Jan 26th Timing Solutions for Open-Compute Systems

Register for the series and find past recorded sessions at:

https://www.silabs.com/clock-talk

Respond to the poll to enter to win a $50 Amazon gift card

1

https://www.silabs.com/clock-talk

WELCOME SILICON LABS LIVE

Internet Infrastructure andIndustrial Automation Tech Talks

WELCOMEOptimize Timing Solutions for High-Speed FPGAs & Applications Processor Designs

Linda Lua| Sr. Product Marketing ManagerMurali Chandran| Sr. Product Marketing Manager

▪ Introduction to Silicon Labs timing and Reference design partners

▪ Focus markets and technology trends

▪ Common timing requirements for FPGAs and application processors

▪ Clock trees to optimize performance, board space and cost

▪ Examples of reference designs

▪ Silicon Labs tools to help simplify clock tree designs

Agenda

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Comprehensive Timing Portfolio

XO/VCXO Clock BuffersClock Generators

Jitter Attenuating ClocksSyncE/IEEE 1588 Clocks, Modules,

Software

Wireless Clocks

▪ Leader in high performance clocks and oscillators

▪ Frequency flexibility + ultra-low jitter

▪ Best-in-class integration → single IC clock trees

▪ Highly programmable with quick-turn samples

4

Reference Design Partnerships

▪ FPGAs

▪Optical DSPs and PHYs

▪ Switch SoC and Fabrics

▪ Server/Storage CPUs

▪ARM Processors

▪GPUs

▪Coherent Optics

▪Network Interface SoCs

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https://www.silabs.com/timing/reference-designs

https://www.silabs.com/timing/reference-designs

▪ FPGAs include high speed, sensitive analog interfaces (SerDes) that need low jitter clock references

▪ Interfaces operate synchronously to external sources▪ Recovered clock jitter must be attenuated (includes 1588 PTP)

▪On-chip oscillators are susceptible to extraneous noise from sources like power supplies adding jitter

▪Most systems require multiple reference frequencies▪ CPU, memory, PCIe, ethernet, OIF-CEI, USB, optical, RF

SOLUTION → Provide lowest jitter reference clocks from external clocking sources

Why Do Reference Designs Need External Clocks?

6

https://www.xilinx.com/products/silicon-devices/soc/rfsoc.html

Quad-CoreArm

Cortex-A53

Processing system

Memory

Subsystem

(DDR4)

System Functions

Dual-CoreArm

Cortex-R5

Platform and

Power

ManagementSecurity

Display Port

USB 3.0

SATA

PCIe Gen3

GigE

CAN

NAND

Programmable Logic DSP 33G Tranceivers25G/100G EthernetEmbedded RAMPCIe Gen4

RF-ADCs SD-FEC RF-DACs

https://www.xilinx.com/products/silicon-devices/soc/rfsoc.html

NETWORKING DATA CENTER 5G WIRELESS

Trends Driving Next-Gen Timing Requirements

7

Base Band Units Remote Radio Heads

Small Cells/DAS

Server Accelerators

Edge routersDCI / Optical Modules

Enterprise/Campus Switching

SmartNIC

Broadband

Optical/Ethernet port bandwidths increasing: 10/40/100G →25/100/400G

SerDes bandwidth increasing: 28G NRZ → 56G/112G PAM-4

Data bus bandwidth increasing: PCIe Gen3 → Gen4 → Gen5

IEEE 1588 Precision Time Protocol Adoption

Spine/Leaf Switch

Core Switches

Flash Array Storage Remote PHY (DOCSIS) DSLAM

Common Standards Requirements

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Jitter Band (MHz) Max Jitter (fs rms)

CEI-56G-PAM4-MR/LR 4-20 350

CEI-56G-PAM4-VSR 4-20 240

CEI-112G-PAM4-VSR 4-20 120

XAUI 10GBASE-X 0.6-20 430

CAUI-4 1.9-10 280

CAUI-10 1.9-4 460

OTN (OUT/EPON) 0.6-20 430

SGMII/QSGMII 4-20 1400

Fibre Ch-8G, 16G 0.6-10 240

Fibre Ch-32G 0.6-10 130

PCI Express Gen 3 various 1000



SONET/SDH OC-48 1-20 1000



GPON 0.6-10 1500

SDI 3G/6G 0.1 - F/2 800

SDI 12G 0.1 - F/2 400

SDI 24G 0.1 - F/2 200

Proprietary RXAUI/DXAUI 1.8-20 950

JEDEC JESD204B various Per DAC/ADC

CCIX CCIX-25G various 350

SMPTE

ITU

Industry Standard Interface

OIF

IEEE 802.3

ANSI

PCI-SIG

Recommended Solutions for Intel

9

https://www.silabs.com/documents/login/application-notes/AN699.pdf

Recommended Solutions for Intel

10

-130

-138 -138

-140

-144

-146

-170

-165

-160

-155

-150

-145

-140

-135

-130

-125

-120

10 100 500 3000 10000 20000

dB

c/H

z

Offset(Khz)

Agilex , Stratix 10 (TX/MX) E-Tile PHY

Phase Noise Spec(dBc/Hz) - 156.25

Phase noise of Si5391P - 156.25

Phase Noise Si5392/4/5 - 156.25

Phase Noise Si5348/83/89/1588 Module - 156.25

Phase Noise of Si545 - 156.25

(Clock Generator)

(Jitter Attenuator)

(Network Synchronizer)

(XO)

M U LT I S Y N T H

Any-Frequency clock synthesis

low-jitter performance

Zero ppm error

Differentiated Technology Simplifies Clock Tree Design

D S P L L

Eliminates VCXO and loop filter

Any-frequency synthesis (

Any-Frequency Clocking Enables Single IC Clock Trees

Silicon Labs SolutionConventional Approach

Memory

1G PHY

1G PHY

10G-56G

PHY

10G – 56G

PHY

312.5MHz (LVDS)

125 MHz (LVPECL)

125 MHz (LVPECL)

312.5MHz (LVDS)

100 MHz (HCSL) w/ SSC

133.333 MHz (CMOS)

50 MHz (CMOS)

156.25 MHz (LVDS)

156.25 MHz (LVDS)

Si5341

Memory

10G/40GbE

Switch

1G PHY

1G PHY

10G PHY

10G PHY

312.5MHz (LVDS)

125 MHz (LVPECL)

156.25 MHz (LVDS)

156.25 MHz (LVDS)

50 MHz (CMOS)

133.333 MHz (CMOS)

100 MHz (HCSL)

Buffer

Clock

Clock

Buffer

Si534x/9x

Si5332Clock Generator

FPGA155.52 (LVDS)

10G-

400GbE

Switch

PCIe 3/4PCIe Gen3-5

XO

XO

FPGA155.52 (LVDS)

156.25 MHz (LVDS)156.25 MHz (LVDS)

PCIe Gen3/4100 MHz (HCSL)

Challenges▪ FPGA/Switch/PHY require diverse mix of frequencies, formats

▪ Stringent 28G/56G/112G SerDes jitter requirements

▪ Impact of power supply noise on system performance

▪ Not easy to add SSC or frequency margining

Solution▪ Clock IC generates any mix of frequencies, formats

▪ Best-in-class jitter: 69fs (Si5391P), 230 fs (Si5332)

▪ On-chip LDOs suppress power supply noise

▪ Enable SSC and frequency margining using HW pins or I2C

12

On-Chip Regulator Performance

▪ On-chip regulation ensures low jitter operation in noisy systems

▪ Eliminates or simplifies power supply filtering

▪ Simplifies layout and design

VDD

< 50 fs of additive jitter

13

Precision Calibration Grade Performance with Si539x

Clock Outputs:

▪156.25MHz

▪ 69fs RMS jitter

▪Multiple clocks runningsimultaneously

▪ 312.5MHz

▪ 100MHz

▪ 50MHz

▪ 25MHz

▪No crosstalk spurs

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Example: Intel Stratix 10 FPGA Reference Design

▪ Clock generators and oscillator provide reference clocks for:

▪ Ethernet PHY 56G SerDes

▪ PCI Express

▪ Memory interface

▪ QSFP

▪ Display Port

▪ SDI Video

▪ Solution advantages

▪ High performance allows sufficient design margin

▪ Any-frequency clocks optimize clock tree, minimize PCB area and cost

▪ Reuse of same clock tree to support different design configuration

▪ Cost down path: Fixed configuration clock/oscillator

15

Si5391Clock

Generator

Si5332Clock

Generator

Intel Stratix 10

FPGA

Intel Max V

Si516Oscillator

SDI

Intel Stratix 10 DX Dev Kit

Example: Xilinx Virtex Ultrascale+ FPGA

▪ Jitter attenuator, clock generator, oscillator, buffer provide reference clocks for:

▪ Virtex System Controller

▪ PHY

▪ PCI Express

▪ QSFP

▪ Memory interface


▪ Jitter attenuating clock integrate clock generation function, saving external components, PCB area and cost

▪ Flexible clock tree design with fanout buffers for different number of clock outputs

▪ Cost down path: Fixed frequency oscillator if no programmability is needed

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Si5335Clock

Generator

Si570Oscillator

Si5326BJA

Si53340Buffer

Si53340Buffer

Example: NXP QorIQ Layerscape 1026/1046A Reference Design

▪ Clock generator to provide reference clocks for:

▪ System controller

▪ CPLD

▪ PCI Express

▪ PHY

▪ Retimer

▪ Peripheral interface


▪ Clock tree on a chip, eliminate need for additional buffer

▪ High performance for more design margin

▪ Embedded crystal option

▪ Programmable any-frequency clock for flexible configuration changes

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Si5332Clock

Generator

Example: Marvell ThunderX3 Processor Reference Design

▪ Reference clocks needed for:

▪ PHY

▪ CPLD

▪ PCI Express

▪ Optical, memory and storage interfaces

▪ CPU


▪ Si5332

▪ Up to 12 outputs, any-frequency, any-output format clock generator

▪ Typical jitter performance 270fs RMS (12kHZ – 20MHz)

▪ PCIe Gen 5 compliant, 2 independent spread spectrum domains

▪ Si5350

▪ Low cost, any-frequency LVCMOS clock generator

▪ Si53112

▪ PCIe Zero Delay Buffer

▪ Bypass mode

▪ Low power HCSL outputs

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Reference Clocks ThunderX3 Platform Clock Requirements

PCIe Gen4CPU CCPISATAUSB3/LANCPU DDRCPLDPHY

100MHz x 21125MHz x 6100MHz x 2100MHz x 633MHz x 224/48/50MHz (3)25MHz

500fs RMS (BW 2-4MHz & 5MHz)300fs RMS (12kHz-20MHz)1ps RMS (12kHz-20MHz)1ps RMS (12kHz-20MHz)100ps Pk-Pk100ps Pk-Pk100ps Pk-Pk

Si5332Clock

Generator

ZDB Buffer

Si53112ZDB

Buffer

Si5350Clock

Generator

Example: BRCM Trident/Tomahawk Switch Platform Requirements

▪ High performance clock generator, oscillators, buffer

▪ 100G/400G Switch SoC

▪ QSFP interface

▪ PHY

▪ SyncE/IEEE1588 Support


▪ Si5391

▪ Precision calibrated 156.25MHz to meet 400G with margin

▪ Up to 12 outputs to reduce external components

▪ Si5332

▪ Meets jitter performance requirements for 100G designs

▪ Up to 12 outputs, any-freq, any format for design flexibility

▪ Embedded crystal option to simplify design

▪ Si5388/Si5389

▪ SyncE/1588 HW and SW support

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Reference Clocks Trident/TH2 Requirements (100G) TH3 Requirements (100/400G)

Fabric PLL (XG/LC)PHY Core/CPU/TS PLLPCIeCLK25

156.25MHz x 4 156.25MHz x 4+25 / 50MHz x 4100MHz x 125MHz x 1

300fs RMS (28G)300fs RMS (28G)2ps RMS 1ps RMS100ps P-P

156.25MHz x 4 156.25MHz x 425MHz x 4100MHz x 125MHz x 1

150fs RMS (56G)150fs RMS (56G)350fs RMS1ps RMS 100ps Pk-Pk

Si5391/Si5332Clock Gen

Si533xxBuffer

Xilinx Zynq Ultrascale+ MPSoC/RFSoC 5G 1588 Reference Design

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▪ Clock solution is optimized for entire Zynq family

▪ Si5389 Network Synchronizer

▪ Provides all IEEE 1588 and PHY clocks

▪ AccuTimeTM 1588 servo SW internal to Si5389

▪ AccuTimeTM IEEE 1588 Software Stack

▪ AccuTimeTM stack sw runs on host processor

▪ Easily portable to any Xilinx Zynq family member

▪ Meets G.8273.2 Class C requirements of ±10nS

▪ Si5386 Wireless Clock (RFSoC-only)

▪ Provides clocks for RF ADCs and DACs

▪ Supports up to 5 independent clock domains

▪ Eliminates discrete VCXO and loop filter

▪ Si5341 Clock Generator (both MPSoC & RFSoC)

▪ Provides all general-purpose clocks

Si5341Clock

Generator

33.33MHz LVCMOS CLKPS_REF_CLK

27MHz LVDS CLKGTR_REF_CLK_DP

100MHz LVDS CLKGTR_REF_CLK_PCIe

125MHz LVDS CLKCLK_125

125MHz LVDS CLKGTR_REF_CLK_SATA

300MHz LVDS CLKGTR_REF_CLK_DDR4

156.25MHz LVDS CLKCLK_156

26MHz LVDS CLKGTR_REF_CLK_USB3

Silicon Labs1588 SW

Stack

ARM ® Processor

GTH – MPSoCGTY – RFSoC

Master PHY

390.625MHz → 25G

156.25MHz → 10GClean_SyncE_CLK

SPI

500MHzPTP_SYS_CLK

1PPS

390.625MHz → 25G

156.25MHz → 10GRecovered_SyncE_CLK

RFADCs/DACs

(RFSoC Only)

XTAL

MPSoC

ZCU102

RFSoC

ZCU111

Air Interface

Xilinx® Zynq® Ultrascale+

GTH – MPSoCGTY – RFSoC

Slave PHY

TOD

Si5389Network

SynchronizerClock

TCXOor

OCXO

Silicon Labs1588 SW

Servo

Si5386Wireless

Clock

XO

500MHzPTP_REF_CLK

XTAL

®

PL_SYSREF_FPGA LVDS

PL_FPGA_REFCLK_OUT LVDS

SYSREF_RFSOC LVDS

DAC_RF_CLKLVDS

ADC_RF_CLKLVDS

Optional

Attend the “Timing Solutions for 5G-RAN Systems” Seminar Dec 1 2020 for additional details

https://www.silabs.com/products/timing/clocks/network-synchronizer-clocks/device.si5389ahttps://www.silabs.com/products/timing/clocks/wireless-jitter-attenuators/device.si5386ahttps://www.silabs.com/products/timing/clocks/ultra-low-jitter-clock-generators/device.si5341a

Clock Trees to Optimize Performance, Board Space and Cost

▪ Reference designs need flexibility to cover a wide range of applications with different requirements.

▪ Application specific needs can be met with more cost-effective solutions.

▪ I2C versions are pin compatible with single frequency versions

▪ Silicon Labs offers the widest range of options to meet your specific cost/performance requirements.

Footprint Compatible Cost Down Paths for Oscillators

22

To minimize costs, devices are available in various frequency ranges (“speed grades”). Be sure to select the lowest speed grade option that suits your application’s requirements.

Cost can also be reduced by moving from I2C programmable to fixed frequency options

Ultra Low Jitter

Low Jitter

General Purpose

XO and VCXO Cost Down PathI2C Programmable to Fixed Single Frequency

Single FreqDual FreqQuad FreqAny Freq (I2C)

Si549 (XO)Si569 (VCXO)




Si544 (XO)N/A (VCXO)






Si532/3 (XO)Si552 (VCXO)






N/A (XO)Si597 (VCXO)


N/A (XO)Si596 (VCXO)

N/A (XO)N/A (VCXO)

TYP Jitter

80 fs

125 fs

300 fs

500 fs

800 fs

Co

st &

Pe

rfo

rman

ce

Si545-Si549: Consistent, Ultra Low Jitter Performance for Any Frequency

> 200MHz Typ Jitter ~ 85 fs!

23

Prototype/Validate with I2C version- Verify system timing margin

Convert to non-I2C for volume production

▪ CBPro, PCIe Clock Jitter Tool, Oscillator Phase Noise Look-up Tool

▪ Timing Selector Guide

▪ Documentation

▪ Product Data Sheets

▪ Product Family Reference Manuals

▪ Crystal selector guide

▪ Evaluation boards, programming dongles

▪ Application Notes and White Papers

▪ Knowledge Base and FAQ

▪ Technical Support

Tools, Collateral and Support

24

https://www.silabs.com/products/development-tools/software/clockbuilder-pro-softwarehttps://www.silabs.com/timing/pci-express-learning-centerhttps://www.silabs.com/support/oscillator-phase-noise-lookuphttps://www.silabs.com/documents/public/brochures/timing-selector-guide.pdf



Q&A



Thank you!

Documents

Clock Talk LIVE Schedule Presentation will begin shortly...Proprietary RXAUI/DXAUI 1.8-20 950 JEDEC JESD204B various Per DAC/ADC CCIX CCIX-25G various 350 SMPTE ITU Industry Standard