CMOS Blocks for On-Chip TF Tests Rashad Ramzan, Jerzy Dabrowski Linköping University Dept. of Electrical Engineering SE-581 83 Linköping, Sweden

CMOS Blocks for On-Chip TF Tests

Rashad Ramzan, Jerzy DabrowskiLinköping University

Dept. of Electrical EngineeringSE-581 83 Linköping, Sweden

2June 22-25, 2005MIXDES, Krakow, Poland

Presentation Organization

• Motivation• RF-BIST Block Diagram• Defect Types• Defect/Fault Propagation in RF Path• Generation of Stimulus and RF Path Sensitization• Test Blocks: Test Attenuator (TA) and Multiplexer

(TMUX)• Simulation Results• Conclusions


Motivation

• Complete one Chip CMOS Transceivers are in market now.

• Like TI’s BRF6300 single-chip solution for mobile terminals supporting Bluetooth Specification v2.0

• How to Test Complete one Chip Radio Transceiver On Chip Digital Tests are quite mature. Digital

part can be tested with out packaging the die. What about RF Testing? It’s the bottleneck.


Motivation

How RF is tested: RF testing before packaging: Testing Cost may

approach the cost of chip. Before Packaging: Special Automatic Test Equipment. Special probing requirement, high frequency effects, Special

Pad/Jig requirement etc -> More time Consuming

After the packaging: Package has to be thrown away with faulty chip. And RF package is usually more costly than the chip itself.

• Possible Solution: Defect-oriented BiST for RF front-ends


Loopback test setup for IC RF transceiver front-end

• BiST by reconfiguration• Sharing on-chip resources• BB processor serves as TPG and

response analyzer• Sensitive blocks are not affected –

only TA and TMUX added• Tuning TA for sensitization• Different tests possible• Smaller loop enhances testability

(DAC & ADC)• But not all TRx’s are well suited for

loopback

RF transceiver chip with BiST

Tests supported:SER, EVM, FFT (for IP3), ….


Spot defects classification


Spot defects modeling by hierarchical mapping

• Layout

RSh

RO

• Circuit

LNA

OthersLNARx

SLNA

DevicesLNA

G

NFNFNF

NG

NNF

1

1

• Chip/System

M1in

Vp outM2

R2

R1 R3

Open in poly

Short defect

Poorcontact

LNA

LO

Other

LNA

LNARx IP

G

IPIP 33

1

3

1

Impairments in specs


Spot defects in CMOS

M1

in

Vdd

outM2

Br2

Br1

Br3

Br4

Br5

M3

Br6

Sh1

Sh2

Sh3

Sh4

Sh5

Sh6

Br7

Narrow band LNA /0.35um /1800 MHz

Noise figure

Gain

Noise figure

Gain

Fault simulation for LNA (NF0=3.4dB, G0=18.3dB)

Short faultsBreak faults

Gain and NF impairments against

fault strength Rbr/RS or RS/RSh

Single faults are assumedSpot defects are the main yield limitation in CMOS


Spot defects (NF, G and IP3)

Noise Figure

Conversion Gain

IP3

Impairments in gain and NF for break faults for CMOS Gilbert mixer (NF0=10.8dB, G0= 7.2dB)

The corresponding impairments in IP3 (IP30=7.8dBm)

Less regular vs fault strength

Likely to mask themselves …


Fault propagation in RF signal path

MixerLNA

Other

LNA

MixerLNARx GG

NF

G

NFNFNF

11

Other

MixerLNA

Mixer

LNA

LNARx IP

GG

IP

G

IPIP 333

1

3

1

LNA

LO

LPF

IP3 test less useful for typical spot

defects

GRx = GLNA GMixer GOther

Receiver front-end

Also parametric faults resulting in NF, G or IP3 impairments are addressed


IP3 as test response

If both IP31 and G1 degradedthe fault tends to mask, easier to detect with EVM (or SER)

Resistive break at MOST drain introduces imbalance mostly IP3

affected, gain less

2

1

1 33

1

3

1

IP

G

IPIP

R1

M1 M2

Vb

Vout

R2

Vin

IP3 is a complementarytest for selected faults


Generation of stimulus at BB & Sensitization

QPSK modulatedBB data

AWGN or Toneinterferer

LPFDAC

Constellationwith tone interferer (splitting effect)

Constellationwith AWGN

When tuning with the interferer, TA can be fixed

LO

Decision boundaries must be approached by the constella-tion points in any case


Generation of stimulus at BB & Sensitization

QPSK modulatedBB data

AWGN or Toneinterferer

LPFDAC

Constellationwith tone interferer and contribution of inherent noise

Constellationwith AWGN

When tuning with the interferer, TA can be fixed

LO


QPSK constellation

BER (Bit Error Rate) & EVM (Error Vector Magnitude)

EVM vs receiver NF for QPSK system

1

0001

1011

sk zk

2

in

ref

out

kk

kkk

S

N

NFd

EVMdSNREVM

sszEVM

)(,1

2

22

Sin/Nref = 20dB

20dB

17dB

17dB

18.7dB

18.7dB


Test attenuator design

If SNR is low then SNRout SNRin

irrespective large NF

Very large !

LNA

50 50

Antenna inputDigital

control

Sin Sout

NFTA = Power Loss

But we can keep SNR under control


Implementation in CMOSfor Wi-Fi/Bluetooth

En

Input

D0

D1

D2

Output

D3

D4

D5

Gnd

TA can be disabled in normal operation mode (all MOST off)

O.35 m AMS MS/RF process

Layout (80 x 60) mArea < 10% of LNA area (capacitors 10pF)

En D3-5 D0-2

Out

In


Attenuator performance

Relatively low reflection coefficient

Also good linearity: IIP3 +20 dBm

S11 = -27dB@ 2.4GHz

Variable wide band attenuator, little impact of parasitics, 2 dB steps in 3 sub-ranges

TA power gain TA impedance matching


2:1 Multiplexer Design

TMUX connects LNA and Mixer in Normal mode and TA and MUX in Test Mode


Test Results RF Frontend with and without Test Blocks

Total Noise Figure of Frontend Total Gain of Frontend


Conclusions

• On-Chip Test blocks facilitate the BiST but increase chip area and tend to degrade the performance.

• Good models of circuits and faults supported by statistical data are needed.

• Sensitizing the test path very useful but not always possible.

• Nonstandard test stimuli and signatures very useful (invention needed).

• Careful DfT in initial design phase can mitigate performance degradation of RF chip.


Thank You Very much for Patience!

Questions??

Documents

CMOS Blocks for On-Chip TF Tests Rashad Ramzan, Jerzy Dabrowski Linköping University Dept. of Electrical Engineering SE-581 83 Linköping, Sweden