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CMOS DIFFERENTIAL ANALOG OTICAL RECEIVERS WITH HYBRID INTEGRATED I-MSM
DETECTOR
A thesis presented to the academic faculty
By
Jae Joon Chang
In partial fulfillment of the requirements for the degree of Doctor of
Philosophy in School of Electrical and Computer Engineering
Georgia Institute of Technology
June 2000
A CMOS DIFFERENTIAL ANALOG OTICAL
RECEIVER WITH HYBRID INTEGRATED I-MSM
DETECTOR
APPROVED:
____________________________________
Martin A. Brooke, Chairman
____________________________________
Joy Laskar
____________________________________
Gary May
____________________________________
Scott Wills
____________________________________
Paul Kohl
Date approved by chairman:_____________
iii
ACKNOWLEDGEMENT
First and foremost, I would like to thank God for blessing me and giving me this
chance to study, work and fulfill this dream.
I would like to extend my deepest appreciation to the many people who provided
encouragement and support throughout my graduate program. I’m extremely grateful for
the guidance, encouragement, and support that I received from Dr. Martin A. Brooke. He
has always nourished me with a fresh idea to overcome the barriers in front of me. I
would also like to thank Dr. Nan M. Jokerst and her group members, Michael Vrazel and
Olivier Vendier, for their support by providing optoelectronic devices and guidance in
my experiments and studies. Also, I can’t forget the concerns and helpful advice of Dr.
Myunghee Lee.
I gratefully acknowledge Dr. Joy Laskar, Dr. Scott Wills, Dr. Mark Allen, Dr.
Gary May, and Dr. Paul Kohl for their services and comments as exam committee
members during my doctoral program. I would like to thank Dr. Laskar for allowing me
to use his equipments and join his group parties. Also, I would like to thank Dr. Phillip
Allen for his valuable analog classes.
Special thanks go to my group members and all the folks of MiRC including Dr.
Brooke’s EDA group members, Dr. Phillip Allen’s Analog system design group
members, Dr. April’s Semiconductor material group members, Dr. Laskar’s MMIC group
members for their encouragement, cooperation, technical help, and insightful discussions
related with my research.
Last but most importantly, I would like to express my gratitude to my parents, my
brothers, and my wife for their encouragement, support, endurance, and love.
iv
TABLE OF CONTENTS
ACKNOWLEDGMENTS..........................................................................iii
LIST OF TABLES ...................................................................................viii
LIST OF FIGURES.................................................................................... ix
SUMMARY ...................................................................................xvi
Chapter I INTRODUCTION............................................................... 1
Chapter II. BACKGROUND AND RECEIVER
SYSTEM DESIGN CONSIDERATION ..........................10
2.1 Background ............................................................................ 10
2.1.1. Receiver Sensitivity and Bit-Error Rate (BER) ......... 10
2.1.2. Eye Diagram.............................................................. 14
2.2 Principal Receiver Configurations ......................................... 18
2.2.1. Low Impedance Open Loop Receiver........................ 19
2.2.2. High Impedance Open Loop Receiver ....................... 20
2.2.3. Transimpedance Feedback type Optical Receiver ..... 22
2.3 Metal-Semiconductor-Metal (MSM) Photodetector .............. 25
2.4 Noise issue of receiver design................................................ 28
2.4.1. Device Intrinsic Noise Sources .................................. 30
2.4.2. Detector Noise............................................................ 31
2.4.3. Noise Requirements ................................................... 32
2.5 Receiver System Design Consideration ................................. 40
v
Chapter III LOW INPUT RESISTANCE OPEN LOOP OPTICAL
RECEIVER ............................................................................ 44
3.1 Introduction and Applications................................................ 44
3.2 Amplifier Design.................................................................... 46
3.2.1. Front-end Design........................................................ 46
3.2.2. Post Voltage Gain Stage............................................. 51
3.3 Simulation .............................................................................. 56
3.4 Layout .................................................................................... 65
3.5 Measurements......................................................................... 69
3.5.1. Transient Measurement Result with Eye-diagram..... 74
3.5.2. ISI Effect Measurement ............................................. 80
Chapter IV DIFFERENTIAL TOPOLOGY OF RECEIVER .................. 93
4.1 Introduction ............................................................................ 93
4.2 Background and Applications ................................................ 95
4.3 Simulations and Comparison ................................................. 98
4.4 Mixed Signal Chip Design and Test .................................... 103
4.5 Measurement and Test Results............................................. 109
4.6 Summary .............................................................................. 123
Chapter V TRANS-IMPEDANCE FEEDBACK TYPE
OPTICAL RECEIVER FRONT-END DESIGN ................. 124
5.1 Introduction and Applications.............................................. 124
5.2 Amplifier Design.................................................................. 127
5.2.1. Front-end Current-to-Voltage Conversion
vi
Stage Design............................................................. 127
5.2.2. Post Voltage Amplifier and Pad Driver Stage
Design....................................................................... 132
5.3 Simulation ............................................................................ 138
5.3.1. Transient Simulation at different speeds
and different input capacitance ................................ 138
5.3.2. AC Analysis and Noise Analysis ............................. 141
5.3.3. Line Impedance effect simulation ............................ 147
5.4 Layout .................................................................................. 152
5.5 Measurements....................................................................... 156
5.5.1. Test Setup................................................................. 156
5.5.2. BER Measurement ................................................... 162
5.5.3. ISI Effect Measurement ........................................... 168
Chapter VI CONCLUSIONS AND PROPOSED FUTURE
RESEARCH......................................................................... 170
6.1 Contribution ......................................................................... 170
6.2 Future Research.................................................................... 174
6.3 Conclusions .......................................................................... 178
Appendix I Brief SONET Specifications ........................................... 179
Appendix II HSPICE INPUT CONTROL FILES AND BSIM
MODEL PARAMETERS USED IN SIMULATION
AND MATHCAD FILE FOR ISI EFFECT.................... 182
Appendix 2.1. BSIM Model Parameter Used in Development
vii
of Low-Input Impedance Optical Receiver.............. 182
Appendix 2.2 SPICE Netlist and Input Control File....................... 186
Appendix 2.2.1. Prc Btc Low Input Impedance Optical
Receiver Netlist ........................................................ 186
Appendix 2.2.2. Prc Btc Low Input Impedance Optical
Receiver SPICE Input Control File.......................... 209
Appendix 2.2.3. NSC Transimpedance Optical Receiver
Netlist ....................................................................... 211
Appendix 2.2.4. NSC Transimpedance Optical Receiver
SPICE Input Control File ......................................... 247
Appendix 2.3 Mathcad Simulation for ISI Effect ........................... 249
Appendix III HSPICE TRANSIENT SIMULATION RESULT .......... 250
Appendix 3.1 Low Impedance Open Loop Optical Receiver......... 250
Appendix 3.2 Transimpedance type Optical Receiver.................... 263
References .................................................................................. 275
VITA .................................................................................. 286
viii
LIST OF TABLES
Tables Page
2.1 Example Numbers of Power Unit Conversion................................... 11
2.2 The relationship between parameter “Q” and Required BER............ 35
2.3 The relationship between BER and SNR ........................................... 39
2.4 Levels of the SONET Signal Hierarchy and Electrical
Equivalents .................................................................................... 41
2.5 List of Recent Research in CMOS Optical Receiver ......................... 43
3.1 3dB Frequency at different Input Capacitance................................... 60
3.2 Optical Power Conversion Table ....................................................... 80
3.3 Maximum Allowable Resistance at Different Data Rates ................. 90
4.1 Sampled Output from Microprocessor............................................. 121
5.1 Design Goal of Transimpedance Feedback type Differential
Amplifier .................................................................................. 126
5.2 Power Consumption of Transimpedance Optical Amplifier............ 137
5.3 3dB Frequency of front-end Receiver .............................................. 142
6.1 The performance comparison of the receivers in this research
with other recently published and developed optical receivers........ 171
ix
LIST OF FIGURES
Figures Page
1.1 Block Diagram of Fiber Optical Communication System ................... 3
1.2 Computer Clock Speed History Chart.................................................. 4
1.3 Diagram of Digital Optical Receiver System....................................... 5
2.1 Example Plot of Digital Receiver Performance BER ........................ 12
2.2 SONET Eye Diagram Mask with Specification Parameters.............. 17
2.3 Equivalent Circuit of Low Impedance Open Loop Optical
Receiver .................................................................................... 20
2.4 Equivalent Circuit of High Impedance Open Loop Optical
Receiver .................................................................................... 21
2.5 Simplest Configuration of Equalization Stage ................................... 21
2.6 Transimpedance Feedback Type Optical Receiver ............................ 23
2.7 Capacitance value of 250µm x 250µm MSM Photodetector ............. 26
2.8 Relation of Noise and BER ................................................................ 33
2.9 Probability of Error vs. Q for a Gaussian Noise Distribution in
Amplifier .................................................................................... 38
3.1 Basic Schematic of Current Mirror .................................................... 47
3.2 Transimpedance Stage of Front-end .................................................. 48
3.3 The Schematic of Front-end of Optical Receiver............................... 50
x
3.4 Post Voltage-mode Differential Amplifier......................................... 52
3.5 The structure of Optical Receiver with Sub-components .................. 54
3.6 Transient Response to 16µA Input Current with 0.1pF Input
Capacitance at 480Mbps .................................................................... 57
3.7 Transient Response to 16µA Input Current with 1.0pF Input
Capacitance at 480Mbps .................................................................... 57
3.8 Transient Response to 16µA Input Current with 0.1pF Input
Capacitance at 622Mbps .................................................................... 58
3.9 Transient Response to 16µA Input Current with 1.0pF Input
Capacitance at 622Mbps .................................................................... 58
3.10 AC Sweep and Noise Analysis with zero Input Capacitance............. 61
3.11 AC Sweep and Noise Analysis with 0.1pF Input Capacitance .......... 61
3.12 AC Sweep and Noise Analysis with 0.5pF Input Capacitance .......... 62
3.13 AC Sweep and Noise Analysis with 1.0pF Input Capacitance .......... 62
3.14 CMRR of Front-end Stage ................................................................. 64
3.15 CMRR of Optical Receiver ................................................................ 64
3.16 MAGIC Layout of Low Input Impedance Differential Optical
Receiver .................................................................................... 66
3.17 MAGIC Layout of Chip ..................................................................... 67
3.18 Photo-picture of Chip ......................................................................... 70
3.19 Photo-picture of Test Board ............................................................... 71
3.20 Direct Modulation of Optical Signal.................................................. 72
3.21 Test Setup Block Diagram ................................................................. 73
xi
3.22 622Mbps, transient, 2V optical power ............................................... 75
3.23 622Mbps, eye diagram, 2V optical power ......................................... 75
3.24 622Mbps, Transient, 0.5V Optical power .......................................... 77
3.25 622Mbps, Transient, 0.5V Optical power .......................................... 77
3.26 480Mbps, Transient, 0.5V Optical power .......................................... 78
3.27 480Mbps, Eye-diagram, 0.5V Optical power .................................... 78
3.28 Bit Error Rate Performance Test Result (C=622Mbps,
D=580Mbps, E=520Mbps, F=480Mbps, G=450Mbps,
400Mbps) .................................................................................... 79
3.29 Example of Intersymbol Interference................................................. 81
3.30 Transient Response of ISI Effect Simulation when pole=1 ............... 85
3.31 Frequency Response of ISI Effect Simulation when pole=1 ............. 85
3.32 Transient Response of ISI Effect Simulation when pole=2.5 ............ 86
3.33 Frequency Response of ISI Effect Simulation when pole=2.5 .......... 86
3.34 Transient Response of ISI Effect Simulation when pole=5 ............... 87
3.35 Frequency Response of ISI Effect Simulation when pole=5 ............. 87
3.36 Transient Response of ISI Effect Simulation when pole=7.5 ............ 88
3.37 Frequency Response of ISI Effect Simulation when pole=7.5 .......... 88
3.38 Transient Response of ISI Effect Simulation when pole=10 ............. 89
3.39 Frequency Response of ISI Effect Simulation when pole=10 ........... 89
3.40 BER Measurement Result with ISI effect .......................................... 92
4.1 Comparison of Isolation vs. Differential Topology Method in
Reducing Digital Noise ...................................................................... 96
xii
4.2 Top trace: the simulated output signal (voltage) of the single
ended receiver with a certain degree of substrate noise applied
to the input. Bottom trace: the noise-free input to the receiver
(1 micro amp peak to peak)................................................................ 99
4.3 Power supply current for single ended receiver when a certain
amount of substrate noise is applied to the input. Even when
assuming normal operation without substrate noise, there is a
600 microampere variation in the current ........................................ 100
4.4 Top trace: output signal of the differential receiver when a
certain amount of digital noise is applied to input. Bottom
trace: the noise free input (1 microampere peak to peak) ................ 101
4.5 Power supply current for fully differential receiver. There is
a 40 micro amp variation in the current ........................................... 102
4.6 Block diagram of a SIMD Pixel Processor node.............................. 104
4.7 Single part of Differential Amplifier Front-end............................... 105
4.8 Circuit diagram of the fully differential current input receiver
circuit .................................................................................. 106
4.9 Photo picture of the Chip : (Left: Simpil Microprocessor, A
quarter position From the Right: Photodetector, Right Most
:Optical Differential Receiver)......................................................... 108
4.10 Test setup used to test receiver operation......................................... 109
4.11 Test setup for digital noise immunity measurements....................... 110
4.12 Test Setup for Optical Test (With Digital Operation)...................... 111
xiii
4.13 Measured output of receiver without operation of digital
circuitry: (the two lower traces are the differential receiver
outputs) .................................................................................. 114
4.14 Measured outputs eye-diagram of receiver when digital
circuitry is not in operation .............................................................. 115
4.15 Measured output of receiver with operation of digital circuitry:
(the two lower traces are the differential receiver outputs).............. 116
4.16 Measured output eye-diagram of receiver when digital
circuitry is in operation .................................................................... 117
4.17 Measured outputs of receiver and comparator with operation
of digital circuitry: (Top trace: One of differential receiver
output, Bottom trace: On-chip comparator output).......................... 118
4.18 Measured output Eye-diagrams of receiver and comparator
with operation of digital circuitry: (Top trace: One of differential
receiver output, Bottom trace: On-chip comparator output) ............ 119
4.19 Two differential Outputs from Digital Circuitry after Digital
Pad Driver .................................................................................. 122
5.1 Conventional Negative Feedback Transimpedance Optical
Front-end .................................................................................. 128
5.2 Input inverter-feedback stage and Inverter characteristic ................ 129
5.3 Differential Version of Trans-impedance Front-end........................ 130
5.4 Schematic of Front-end .................................................................... 131
5.5 Differential Voltage Amplifier......................................................... 133
xiv
5.6 Buffer to drive Output Stage ............................................................ 134
5.7 50 Ω output Driving Circuit ............................................................. 135
5.8 Differential Offset Stage .................................................................. 136
5.9 Transient Response to 16uA Input Current with 0.1pF input
Capacitance at 800Mbps .................................................................. 139
5.10 Transient Response to 16uA Input Current with 1.0pF input
Capacitance at 800Mbps .................................................................. 139
5.11 Transient Response to 16uA Input Current with 0.1pF input
Capacitance at 1Gbps ....................................................................... 140
5.12 Transient Response to 16µA Input Current with 1.0pF input
Capacitance at 1Gbps ....................................................................... 140
5.13 AC Sweep Simulation and Noise Analysis with Zero Input
Capacitance .................................................................................. 143
5.14 AC Sweep Simulation and Noise Analysis with 0.1pF Input
Capacitance .................................................................................. 143
5.15 AC Sweep Simulation and Noise Analysis with 0.5pF Input
Capacitance .................................................................................. 144
5.16 AC Sweep Simulation and Noise Analysis with 1.0pF Input
Capacitance .................................................................................. 144
5.17 CMRR of Front-end Stage ............................................................... 146
5.18 CMRR of Transimpedance Optical Receiver................................... 146
5.19 Line Impedance Circuit .................................................................... 148
5.20 Output line impedance with 50Ohm Termination............................ 148
xv
5.21 Line Impedance effect simulation I.................................................. 149
5.22 Line impedance effect simulation II................................................. 150
5.23 Temperature simulation at 27(top 2 figures) and 100
(bottom 2 figures)............................................................................. 151
5.24 Layout of Transimpedance Optical Receiver................................... 153
5.25 Cadence Layout of Whole Chip Submitted to Fabrication .............. 154
5.26 Direct Modulation Method............................................................... 157
5.27 Photo Picture of Chip ....................................................................... 158
5.28 Test Board with a Bonded Chip ....................................................... 159
5.29 Test Setup Diagram.......................................................................... 161
5.30 NSC 622Mbps Transient Response.................................................. 163
5.31 NSC 622Mbps Eye Diagram............................................................ 163
5.32 NSC 900Mbps Transient.................................................................. 164
5.33 NSC 900Mbps Eye diagram............................................................. 164
5.34 NSC 1Gbps Transient....................................................................... 165
5.35 NSC 1Gbps Eye diagram ................................................................. 165
5.36 BER Test Result I............................................................................. 166
5.37 BER Test Result II ........................................................................... 167
5.38 ISI Effect Test Result of Transimpedance Optical Amplifier.......... 168
6.1 High input impedance Optical Receiver Structure and
Characteristics .................................................................................. 177
xvi
SUMMARY
To realize a future society that can share information at super fast speeds, new
systems for the transmission, reception and processing of variety of signal and
information are gaining importance. In state-of-the-art technology, optoelectronic
communication devices and systems are now being developed for wide spread
commercial use. Optoelectronic integrated circuits make use of the advantages of both
light and electrons. They exploit the advantage of low insertion loss and fast transmission
of light through the fiber and relatively easy controllability of electrons on the
semiconductor device.
To date, the majority of optical receivers have been designed using different
technologies other than CMOS due to wider bandwidth and good quality of passive
components. However, the standard digital CMOS technology provides advantages such
as low power, low cost of fabrication due to high yield, and a higher degree of
integration. In addition, new technology such as Epitaxial-Lift-Off (ELO) is now
available to integrate a multi-material device into a silicon material substrate. These two
technologies show great potential for achieving a very low cost optoelectronic (OE)
interface especially in current computer information sharing world with the advent of
Internet.
In this thesis, the development of a CMOS optical receiver suitable for low cost
desktop application using ELO integrated photodetector by means of different circuit
design techniques is described. Basic two different techniques were employed in the
design. The two types of CMOS optical receivers were hybrid integrated with a
compound photodetector using ELO technology after fabrication and fully characterized
in simulation and measurement.
1
CHAPTER I
INTRODUCTION
To realize a future society that can share information at super fast speeds, new
systems for the transmission, reception and processing of variety of signal and
information are gaining importance. In state-of-the-art technology, optoelectronic
communication devices and systems are now being developed for wide spread
commercial use [1].
Light, generally, doesn’t suffer from attenuation very much as it goes through
transmission media, generally, 0.35dB/km and 0.2dB/km in the 1300nm and 1500nm
windows [112]. In addition, light travels at high speed, for example, the bandwidth of
typical optic fiber is at least 4 orders of magnitude wider than that of good quality coaxial
cable. In contrast, Even though electrons are easy to control, their finite mass and electric
charge means they suffer high attenuation, and information carried by electrons moves at
relatively low speeds compared with light [111].
Optoelectronic integrated circuits make use of the advantages of both light and
electrons. In other words, they exploit the advantage of low insertion loss and fast
2
transmission of light through the fiber and relatively easy controllability of electrons on
semiconductor devices [2].
The simplest form of a fiber-optic system is illustrated in the Figure 1-1. As with
any communication system, there is a transmitter, a receiver, and a channel to convey
energy from transmitter to receiver. At the transmitter, the information is combined with
the drive signals needed to operate a laser. The laser output is coupled into an optical
fiber through which it propagates to the receiver. The light leaving the fiber is collected
on a photodetector that generates an electrical signal in response to the optical excitation.
The electrical signal is typically low-level and requires amplification and signal
processing for the information to be recovered.
3
Figure 1-1: Block Diagram of Fiber Optical Communication System
To date, researchers have designed optical receivers using many different circuit
technologies for different speeds and different applications, for example, CMOS
[20,22,23,57,80,83,91,92,94,97], silicon bipolar [4,5], GaAs MESFET [6-16], or novel
devices [26]. And commercially interesting speeds have progressed with computer clock
speed advances and the advent of the Internet as shown in the following chart. (1990’:
4.77MHz, Today: Several hundred megahertz)
4
Figure 1-2: Computer Clock Speed History Chart [116]
The enormous development of research in the field of optical receiver in different
technologies is not only because bipolar or GaAs transistors usually provide wider
bandwidth, but also because the process technology associated with these transistors can
provide relatively good quality of passive components such as resistors, capacitors, and
even on-chip inductors. However, standard digital CMOS technology provides
advantages such as low power, low cost of fabrication due to high yield, and a higher
degree of integration [42]. This design lure for MOSFET circuits was initially developed
around the NMOS technology [21], but NMOS technology is limited by design
constraints associated with the lack of complimentary devices [113]. Although CMOS
5
circuits are somewhat more difficult to fabricate than NMOS circuits, the availability of
complementary devices makes many powerful circuit design techniques possible. In fact,
CMOS is currently the most popular technology among integrated MOS technologies in
both of analog and digital circuit design fields.
Of the receiver components shown in the Figure 1-3, with the exception of the
photodiode, all are standard electrical components, and can be easily integrated on the
same chip by using standard integrated-circuit (IC) technology developed for
microelectronic devices.
Figure 1-3: Diagram of Digital Optical Receiver System
In the past 10 or more years, standard digital CMOS technology has been steadily
improved [22,32], and therefore, is taking over the area of other technologies. At the
same time, new technology such as Epitaxial-Lift-Off (ELO) [24,25,56,72] is now
available to integrate a multi-material device into a silicon material substrate. These two
6
technologies show great potential for achieving a very low cost optoelectronic(OE)
interface [57,71,78,89,102].
Considerable effort has been directed at developing monolithic optical receivers
that integrate all components on the same chip by using optoelectronic integrated-circuit
(OEIC) technology [66-73]. Such a complete integration is relatively easy for GaAs
receivers, and the technology behind GaAs-based OEICs is quite advanced. A new type
of photodiode structure, known as the metal-semiconductor-metal (MSM) photodiode,
has proved especially useful, as it is structurally compatible with the well-developed
field-effect-transistor (FET) technology [31]. However, for lightwave systems operating
in the 1.3-1.6µm wavelength range, It has been required to have InP-based OEIC
receivers. Considerable advances have been made in this direction [68]. Single-channel
InGaAs OEIC receivers operating a 5 Gb/s were demonstrated [72] in 1991 [108].
However, due to material incompatibility between optoelectronic devices and the
circuitry of the optical receivers, commercially available optical receivers often use
hybrid devices or discrete devices on printed circuit boards [17]. In these products, the
photodetector and the circuitry are made using separate processes and connected by
bonding wire or external connectors. These connection methods cause unwanted
inductance and capacitance parasitics between the photodetector and the circuitry,
degrading the system performance. Specifically, the combination of discrete photodiodes
and integrated signal processing circuits possesses several disadvantages: 1) low noise
immunity or poor electromagnetic interference (EMI) properties; 2) poor bandwidth or
resonance effects due to parasitic capacitances and inductances; 3) high fabrication costs
7
due to packaging of at least two chips [62]. Some researchers [22,26,96] have tried to use
the same semiconductor material for the photodetector and the circuitry to a fully
monolithic device. However, this technology is not mature yet and special fabrication
processes, rather than a standard process, are necessary, resulting in low yield, very
expensive devices.
Photoreceiver is a key element in a fiber-optic communication system, which is a
backbone of today’s information superhighway. Also, integration can potentially reduce
the size, weight, and cost of photoreceivers. Besides, Integration enhances circuit
reliability and reproducibility, and eliminates the undesired parasitic elements in the
circuits [25].
The primary object of this research is to develop an optical receiver suitable for
ELO integrated CMOS technology by means of different circuit design techniques. The
CMOS optical receiver will be hybrid integrated with a compound photodetector using
ELO technology. That is, the optical receiver is designed for large detectors for low cost
alignment tolerance package.
In this research, three types of optical receivers are introduced; two of them are
designed, fabricated and fully tested. First one is using low input resistance open loop
type focused to meet SONET OC-9, 480Mbps data rate and the other one is the optical
receiver employing transimpedance feedback topology, tested to meet SONET OC-12,
622Mbps data rate [35]. With this smaller feature size of technology, 1Gbps performance
was attempted, but best performance was 10-10 at 900Mbps due to the poor packaging
8
resources causing oscillation problem. Also, a rough idea for the other one out of three
types is proposed but a detailed works are left for the future work.
This dissertation consists of 6 chapters; this is chapter 1, dealing with introduction
to the research history of optical receiver development and purpose of the research for
CMOS optical receiver.
In chapter 2, background to design an optical receiver will be reviewed, the 3
basic technologies of design a optical receiver are presented and the advantages and
disadvantages of each design method are addressed and a brief description of MSM
detector with its advantage over a PIN diode is given. As a factor of design, noise issue
will be discussed in the following section along with other design factors such as ISI
effect. Then, system requirements for the development of proposed optical receiver
follows.
Chapter 3 starts from the design of front-end of low impedance open loop type
optical receiver, and it covers the details of operation including simulation results, layout,
integration of detector and ends with various measurement results. The performance
results related with optical power are also presented.
Chapter 4 addresses the development and application of an amplifier, which has a
differential topology in mixed-system environment. Since the research has taken a part in
the long-term research to develop a system including digital microprocessor circuitry
(Mixed signal system) or optical transmitter system (TXRX system), the substrate
coupling noise has been an issue. The differential or balanced circuit topology method
9
employed in the optical interface design has been verified to be a possible way to get
around this noise problem.
Chapter 5 states the design of transimpedance type feedback amplifier design, in
first section, it starts with front-end design and it continues to differential amplifier speed
up technique which was used in post voltage amplification stages. The details of design
such as layout, integration of detector are followed by measurement result taken up to
900Mbps with 10-11 BER performance.
In Chapter 6, the possible future work after this research will be addressed. Since,
in this research, the two of basic topologies of optical receiver have been covered, the rest
type, which is high impedance open loop version of optical receiver with following
equalization stage, is proposed as a future research candidate. As will be mentioned later,
this type of receiver has best performance in terms of noise and sensitivity, but, as
expected, the cost of high performance of noise, which is bandwidth, is compensated in
the following equalization stage.
Also, this final chapter of this dissertation is devoted to the summary of this
dissertation, it concludes this dissertation and states the contribution made by this
research and the further research to make-up the optical receiver system.
10
CHAPTER II
BACKGROUND AND RECEIVER SYSTEM DESIGN
CONSIDERATION
2.1 Background
Basically, optical receiver consists of two main parts, a semiconductor
photodetector followed by electronic signal amplifier. The photodetector detects the
optical signal and generates electrical power that can be fed into the following electrical
amplifier, this electrical amplifier is working as a buffer between the photodetector and
the signal processing circuitry that follows.
2.1.1 Receiver Sensitivity and Bit-Error Rate (BER)
A receiver is said to be more sensitive if it achieves the same performance with
less optical power incident on it. The launched optical power is an important parameter,
11
as it indicates how much light is arriving the surface of detector. It is often expressed in
units of dBm with 1mW as the reference level. The general definition is
)1
(log10)( 10 mWwerIncidentPodBmPower ⋅= (2.1)
Thus 1 mW is 0 dBm, but 1 µW corresponds to –30 dBm. The following table
shows examples of power unit conversion.
Table 2-1: Example Numbers of Power Unit Conversion
dBm -3 -5 -8 -14 -15 -18 -20 -23
µW 501.187 316.228 158.489 39.811 31.623 15.849 10 5.012
In digital systems, the signal uses digital discrete modulation of optical field. The
receiver recovers a sequence of binary digits (bits) from the incoming optical signal field.
So, the technique used to specify a digital receiver’s sensitivity is different from that used
with an analog receiver. The primary measure of a digital link’s performance is the
probability that the receiver will make an incorrect decision, resulting in a bit-error. In a
digital receiver, the amount of optical signal power needed to obtain the desired bit-error-
rate (BER) is specified.
The BER is defined as the probability of incorrect identification of a bit by the
decision circuit of the receiver. Hence, a BER of 2 x 10-9 corresponds to on average 2
12
errors per thousand million bits. If one varies the amount of received optical power and
measures BER at the same time, a plot similar to the one illustrated in the Figure 2-1 will
be obtained [110].
Figure 2-1: Example Plot of Digital Receiver Performance BER
In the Figure 2-1, at low levels of received optical power range, the error rate will
be relatively high. As the received optical signal power increases, the probability of
making a bit-error decreases. In a correctly designed link, a point will be reached that
13
satisfies the user’s quality-of-service requirements for bit-error-rate. For the case
illustrated in the figure above, as in the normal case, this is a BER below 10-9. At higher
received optical signal power levels the bit-error-rate will usually continue to decrease
and the system will become error-free. However, it is possible for a BER “floor” to be
observed in some systems. These are usually caused by subtle receiver degradations that
are independent of the amount of received optical signal power. Some forms of
interference, clock jitter, data pattern dependence, and setup and hold-time violations in
digital circuit designs can cause BER floors to be observed.
Ultimately, if the received power continues to increase, the receiver will
eventually overload and the error rate will rise [95]. The difference between the point at
which there is just enough received optical signal power to meet the desired BER and the
point at which receiver overload causes the BER to rise to unacceptable levels is the
receiver dynamic range. In other words, the minimum allowable optical power at the
receiver input is determined by the receiver sensitivity. The receiver has to operate not
only at the minimum detectable power but also at optical power levels which can be
significantly larger. The receiver dynamic range is the difference (in dB) between the
minimum detectable power levels or receiver sensitivity and the maximum detectable
power level. Maximum allowable input received power levels can be determined when
the amplifier output starts to be affected by nonlinear dynamic effects.
The dynamic range is a function of the bias resistor or the feedback resistor. As
the bias resistor decreases, the maximum allowable received optical power increases.
Thus, the dynamic range is increased. However, a reduction in the resistor value results in
14
an increase in the amplifier noise level. Therefore, trade-off is required between high
receiver sensitivity and wide dynamic range [89].
The amount of optical signal power that produces a receiver BER of 10-9 is a
widely used measure of receiver performance [109] and is frequently termed the receiver
sensitivity. Most lightwave systems specify a BER of less than 10-9 as the operating
requirement, even though some require a BER as small as 10-14 [104]. Although the BER
can be defined as the number of errors made per second, such a definition makes the BER
bit-rate dependent.
2.1.2 Eye Diagram
When observing data recovered by optical amplifier on the oscilloscope, there is a
visual method that is often used to qualitatively measure the properties of a recovered
data waveform. If we superimpose all of the various symbol transitions at their respective
decision times, we obtain a waveform looking like a human eye. This is called an eye-
diagram due to its similarity of shape to a human eye.
An eye diagram is easily generated using an oscilloscope that is triggered by the
symbol timing clock and keeping the curve trace for certain duration of time. The eye
diagram is a composite of multiple pulses captured with a series of triggers based on
data-clock pulse fed separately into the scope. The scope overlays the multiple pulses to
15
form the eye diagram. The eye diagram waveform should not enter into this masked area
because closing of the eye is an indication that the receiver is not performing properly.
Usually, long pseudo-random data patterns are often used when generating eye-
diagrams to guarantee that the eye-diagram is representative of virtually all possible
symbol transitions. By measuring the width of the opening of the eye in both the vertical
and horizontal directions we obtain information about the system’s ISI, noise, and jitter.
The jitter, whether due to variations in the received pulse duration or the accuracy of the
recovered symbol clock, will cause the eye to close in the horizontal direction. Noise and
ISI cause the eye to close in the vertical dimension. The ideal decision sampling point
occurs at the time of maximum vertical opening. This point corresponds to the time when
the signal-to-noise ration is at its maximum. Also, depending on the data rate, the size
and shape of the mask changes.
The decision circuit which follows the amplifier, compares the output from the
linear channel to a threshold level and decides whether the signal corresponds to bit “1”
or bit “0”. The best sampling time corresponds to the situation in which the signal level
difference between “1” and “0” is maximum. It can be determined from the eye diagram
formed by superposing electrical pulses corresponding to different bits on top of each
other.
For evaluating the digital transmission systems, the eye diagram is the key tool to
estimate the system reliability. In addition to the qualitative measurements obtained with
an oscilloscope it is possible to obtain more detailed information using eye-diagrams.
More quantitative results can be obtained by either accurately sampling the eye-pattern
16
and constructing histograms of jitter and noise or by combining the eye-diagram
measurements with bit-error-rate measurements taken with an accurate decision sample
gate. This allows contours of constant error-rate to be obtained for the eye diagram that
can sometimes reveal subtle performance degradation mechanisms.
According to the Bellcore’s technical report [35], the SONET specifications
provide a mask inside and around the eye diagram with required parameter values that
can sustain the system link BER as shown in the following figure.
Because of noise inherent in any receiver, there is always a finite probability that
a bit would be incorrectly identified by the decision circuit. Digital receivers are designed
to operate in such a way that error probability is quite small (typically < 10-9). The issues
related to the receiver noise and decision errors are discussed later.
17
Rates X1 X2 Y1
OC –1 and OC –3 0.15 0.35 0.20
OC –9 Through OC - 24 0.25 0.40 0.20
Figure 2-2: SONET Eye Diagram Mask with Specification Parameters [35]
18
2.2 Principal Receiver Configurations
In designing optical receiver, It is necessary to consider 2 major factors; which are
the bandwidth of amplifier and input sensitivity. The bandwidth of optical amplifier is
determined primarily by input stage, especially, by RC time constant contributed by
detector stray capacitance and electrical amplifier input resistance and input parasitic
capacitance [28]. While the noise is primarily determined by input resistance in which
bias current is flowing through. The most crucial thing in the design of optical receiver is
figuring out an optimum degree in choosing bandwidth and input signal sensitivity to
employ best topology for the system requirements.
There are 3 main possible configurations for the electrical amplifier design, first,
low input impedance open loop configuration, second, high input impedance open loop
configuration, and finally, transimpedance feedback loop configuration, this categories of
design is determined by the value of resistance used in biasing detector, and existence of
feedback loop in front-end.
Each of design configuration method displays different characteristic and these
merits and demerits of each design configuration allow circuit designer freedom to
choose one of them for specific design application.
19
2.2.1 Low Impedance Open Loop Receiver
The Figure 2-3 shows the simplest form of low impedance open loop receiver
design. In the figure, R represents the detector biasing resistance, C does total capacitance
produced by photodetector, input resistance and amplifier input node. Rin is an effective
small signal input resistance of the amplifier. If the signal gain of the amplifier is
assumed to be unity and Rin >> R, the transfer function (transimpedance power gain) of
this stage is determined to be
2
22
)(1)(
wCRRfH
+= (2.2)
As seen in the equation, the bandwidth of this receiver front-end stage is
determined by R and C, However, C is predetermined by device physical size and process
characteristic, and R has an effect on the noise which means sensitivity of amplifier, so in
design of this stage, compromise between noise and bandwidth is required.
20
R C R in
Figure 2-3: Equivalent Circuit of Low Impedance Open Loop Optical Receiver
2.2.2 High Impedance Open Loop Receiver
The general simplest form of high Impedance open loop receiver is depicted in
Figure 2-4 below. The equalization stage following the amplification stage is realized by
High Pass Filter to boost up the gain lessened by frequency bandwidth limitation
constrained by high input resistance.
21
R C Rin
Photodetector
Equalization Stage
Figure 2-4: Equivalent Circuit of High Impedance Open Loop Optical Receiver
The simplest configuration of the equalization stage can be implemented using
parallel resistance and capacitance in series between amplifier output and next stage input
as show in Figure 2-5 [33]. In this figure, Ro represents the output resistance of the
amplifier, and Ri is input resistance of the following signal processing stage.
Following StageRe
Ce
RiRo
Figure 2-5: Simplest Configuration of Equalization Stage
22
The transfer function of the power from input to output follows with the
assumption, Re > Ri > Ro and with condition of
+
⋅
= 2
222
)(1)(
ie
i
e
ie RwC
RRRfH (2.3)
Then, the total power transfer function of the optical receiver becomes
+
⋅
=
)
222
(1)(
ee
i
e RwCR
RRfH (2.4)
with the condition of
1)(1)(12
2
≈+
+wCR
RwC ee (2.5)
The amplifier gain was normalized to unity for the convenience of the calculation.
According to the equation for the total amplifier stage derived above, the
bandwidth of high impedance open loop optical receiver is independent of R and C of the
input stage, it is now determined by Ce and Re of the equalization stage. But it is not
possible to ignore the effect of R and C because they can affect amplifier noise
performance which is related to the amplifier sensitivity.
2.2.3 Transimpedance Feedback type Optical Receiver
Recently, most of optical receiver commercially available use transimpedance
configuration [91,92], the reason of this is that it is a medium way of design method
23
between high input resistance and low input resistance design, and that it is a simple
design. Basically, transimpedance type optical receiver consists of infinite input
resistance amplifier and negative feedback resistance. The simple form of this is shown in
the figure below. In the figure R stands for feedback resistance and C represents the total
capacitance comprised of photodetector device capacitance and amplifier input parasitic
capacitance. Also, Cf embodies the parasitic stray capacitance of the feedback resistance.
C
Photodetector
R
Cf
Figure 2-6: Transimpedance Feedback Type Optical Receiver
If we assume that the gain of amplifier is greater than unity and greater than the
value of R times Cf. the power function of the circuit is
( )[ ]2
22
1)(
ACCwR
RfHf ++
= (2.6)
According to the equation above, the bandwidth of the transimpedance optical
receiver is dependent on the feedback resistance, capacitance, feedback resistor parasitic
24
stray capacitance and amplifier gain. Generally, Cf increases as the gain of amplifier, A,
increases [113]. So freedom of design usually determined by feedback resistance, R
which is a dominant component in noise consideration, too.
25
2.3 Metal-Semiconductor-Metal (MSM) Photodetector
MSM photodetectors for integrated photoreceivers have attracted much attention
because of their inherent advantages, such as a simple structure, low capacitance (because
of its planar structure), high speed, high sensitivity, and ease of integration [51,57]. The
structure of an MSM photodetector consists of two inter-digitated electrodes on a
semiconductor plane. Both electrodes are contributed by Schottky junctions (or contacts)
with the semiconductor. As a bias is applied, one junction is reverse biased, while the
other is forward biased [27,37,41]. The reverse biased junction extends its depletion
region through electrode spacing to provide a high electric field in the region. When this
region absorbs photons and generates electron-hole pairs, the high electric field separates
electrons and holes, and sweeps them to positive and negative electrodes, respectively.
The absorption region of a photodetector should be lightly doped or undoped to keep
residual doping from shielding the electric field. Since both electrodes are on the same
semiconductor plane and have the same Schottky contact property, they can be fabricated
in a single process step without alignment problems [51].
An MSM photodetector has low capacitance because of its planar structure. A
close approximation to an MSM structure is an infinite series of alternating, infinitely
thin, parallel microstrips. For a typical 25 x 25 µm2 MSM detector with 1um electrodes
and 1um spacing, the capacitance is ~20fF [73]. Low capacitance should lead to high
speed and high sensitivity.
26
The figure 2-7 illustrates MSM capacitance values of the photodetector of size of
250µm x 250µm, which was used in this research project, as a function of fingers.
0
0.5
1
1.5
2
2 4 6 8 10
MSM Capacitance as a function of Finger Width and Spacing (250 micron)
1micron fingers2micron fingers3 micron fingers
Cap
acita
nce
(pF)
Finger Spacing (Microns)
Figure 2-7: Capacitance value of 250µm x 250µm MSM Photodetector
The speed performance of a typical electronic device is determined by two
factors: the RC time constant and the transit time constant [30]. The speed of an MSM
photodetector is limited by carrier transit time, which depends on electrode spacing and
absorption layer thickness. The RC time constant is a period of time for carriers charging
27
or discharging the associated capacitance through the associated resistance, while the
transit time is a period of time for carriers drifting through a physical distance. The transit
time constant of an MSM photodetector with 1µm electrodes and 1µm spacing will be of
order [electrode separation/2(saturation velocity)], which is a few tens of picoseconds. In
comparison, the RC time constant is just 1 ps for a 50Ω load. Therefore, typical MSM
photodetectors are transit time limited. Moreover, the transient response of an MSM
photodetector depends heavily on device geometry, such as electrode spacing and
absorption layer thickness. Clearly, as the electrode spacing is reduced, the transit time
between the electrodes decreases, and therefore the cut-off frequency (bandwidth) of the
device should increase.
Although the speed performance of MSM photodetectors is transit-time limited
according to the above discussion, the speed performance of MSM-FET photoreceivers is
RC time constant limited when the photodetector is combined with amplifier circuit.
Therefore, low MSM capacitance is preferred for high speed MSM-FET photoreceivers.
The MSM capacitance (CMSM) is in parallel with FET related capacitance. The FET
related capacitance consists of the gate-source capacitance, gate-drain capacitance, and, if
the feedback method is adopted in the receiver design, the feedback capacitance. Since
FET related capacitance dominates the total capacitance (CT) observed at the input port of
an MSM-FET receiver, the receiver is RC time constant limited.
28
2.4 Noise issue of receiver design
Optical Receiver consists of a photodetector, Amplifier circuit, and a
demodulator. Generally, semiconductor photodiodes are used as photodetectors because
of their compatibility with the whole system. The design of demodulator depends on the
modulation used by the lightwave system. The use of FSK and PSK formats, generally
appropriate for coherent communication systems, requires heterodyne or homodyne
demodulation techniques; such coherent receivers have many components and are
relatively expensive [104]. Often the received signal is in the form of optical pulses
representing “1” and “0” bits and is converted directly into electrical current. Such a
scheme is referred to as intensive modulation with direct detection (IM/DD) in contrast
with coherent detection. Demodulation is done by a decision circuit that identifies bits as
1 and 0 depending on the amplitude of electric current. The accuracy of the decision
circuit depends on the SNR of the electrical signal generated at the photodetector.
An important parameter that is indicative of the receiver performance is called the
receiver sensitivity. It is usually defined as the minimum average received optical power
for which the BER of the optical receiver is 10-9. The receiver sensitivity depends on the
SNR, which in turn depends on various noise sources that corrupt the received signal.
Even for a perfect receiver, the process of photodetection itself introduces some noise.
This is referred to as the quantum noise or the shot noise, as it has its origin in the particle
nature of electrons [58]. Optical receivers operating at the shot-noise limit are called
29
quantum-noise-limited receivers. No practical receiver operates at the quantum-noise
limit, since many other noise sources decreases the SNR considerably below the shot-
noise limit. Some of the noise sources such as thermal noise and amplifier noise are
internal to the receiver. Others originate at the transmitter or during propagation inside
the fiber. For instance, the optical signal launched by the transmitter has inherent
intensity and phase fluctuations that have their origin in the fundamental process of
spontaneous emission. Chromatic dispersion of optical fibers can add additional noise
through phenomena such as intersymbol interference (ISI) and mode-partition noise.
The receiver sensitivity is determined by a cumulative effect of all possible noise
mechanisms that degrade the SNR at the decision circuit. In general, it also depends on
the bit rate, since the contribution of some noise sources (e.g., shot noise) increases in
proportion to the signal bandwidth.
In designing integrated circuits, especially in case of amplifier design, it is
possible to realize amplifiers that exhibit an extremely high gain. Indeed, a gain of almost
any desired magnitude can be obtained by cascading stages. This might seem to imply
that an arbitrary small signal can be amplified to any desired level. However, this is not
true because there is always a limit to the smallest signal that can be amplified [98]. This
limit is determined by electronic noise. If a signal is so small that it is masked by the
noise in an amplifier, it is impossible to recover the signal by amplification.
30
2.4.1 Device Intrinsic Noise Sources
The device intrinsic noise is present in all electronic circuits and categorized in
major 3 noise sources, they are thermal noise, shot noise and flicker noise.
Firstly, thermal noise is generated when thermal energy causes free electrons to
move randomly in a resistive material, generally, open circuit rms thermal noise voltage
in a Thevenin model across a resistor is given by fkTRVt ∆= 4 , and the short circuit
rms thermal noise current in the Norton model is given by R
fkTRV
I tt
∆== 4 , where k
is Boltzmann’s constant, T is the absolute temperature, R is the resistance, and f is
bandwidth in Hertz over which the noise is measured.
Second noise source in intrinsic semiconductor is shot noise, which is generated
when a current flows across a potential barrier. It is caused by the random fluctuation of
the current about its average value and occurs in vacuum tubes and in semiconductor
devices. In semiconductors, it is generated by the random diffusion of holes and electrons
through a p-n junction and by the random generation and recombination of hole-electron
pairs. The shot noise is generally modeled by a parallel noise current source as a white
noise and the rms value of shot noise is given by fqII sh ∆= 2
Third, the flicker noise is caused by the imperfect contact between two
conducting materials when the conductivity is fluctuating in the presence of dc current. In
MOSFET, it occurs in the drain bias current. Flicker noise is modeled by a noise current
31
source in parallel with the device and given as n
mf
f ffIK
I∆
= , where n ~1 and 1<
m <3 [34].
2.4.2 Detector Noise
Sensitivity is a critical operating parameter for photoreceivers. A photoreceiver
with an MSM photodetector has a higher sensitivity than with a PIN photodetector (or
another type of popular photodetector) at a bandwidth of less than 11GHz [112]. The
receiver sensitivity is defined as the minimum optical power that must reach the receiver
for a given bit error rate (BER) in a digital system or for a given signal-to-noise ration
(SNR) in an analog system. The minimum optical power is limited by the total equivalent
noise current at the input of a receiver. The total equivalent noise current, <i2n>1/2, is the
integral over the bandwidth of a detector of the noise spectral density, and can be written
as follows for a receiver with an FET front-end amplifier:
21
2221
2 )(424)(
+++=
m
ampDLn g
CCkTwqI
RkTwi
(2.7)
Here, the first term is the thermal noise due to resistance, R, present at the input.
The second term is the shot noise due to the leakage current plus the average signal
photocurrent, IL. In most optical communication systems, this second term is small and
can be neglected for low dark current photodetectors. The last term is due to transistor
32
noise. In this term, Camp is the amplifier input capacitance, CD is the detector capacitance,
and gm is the FET transconductance. From the above expression, the photoreceiver with
an MSM photodetector has a lower noise current, and thus a higher sensitivity because of
the lower capacitance of the MSM photodetector. According to Rogers [30],
photoreceivers with MSM photodetectors have a higher sensitivity than those with PIN
photodetectors, at least for photoreceivers with bandwidth of less than 11 GHz.
2.4.3 Noise Requirements
To derive a relationship between SNR in analog system and BER in digital
communication system, the assumption that normal hypothesis testing is applicable must
be made. The error probability of a two-level digital signal can be expressed in terms of a
priori probabilities of 1, pr(1) and 0, pr(0) decisions and the conditional probabilities of
error, pr(1|0) and pr(0|1). Hence the definition of the probability of error, pr, that
Gaussian noise will cause the signal plus noise at the decision instant to cross the
threshold level to the opposite side from the signal alone is
( ) ( ) ( ) ( )110001 prprprprpr ⋅+⋅= (2.8)
by symmetry, the conditional probabilities are equal, and if ones and zeros are equally
probable, the probabilities pr(1) and pr(0) are both 0.5. These quantities are illustrated in
the following figure.
33
Figure 2-8: Relation of Noise and BER
It can be shown that since pr = pr(1|0) because of these assumptions, this can be
written as
( ) ∫== dxxpprpr )(01 (2.9)
Where the integrand is a Gaussian distribution, and the definite integral has a lower limit
equal to half the peak-to-peak value Vpp/2, say, between a one and a zero, and an upper
limit of infinity. Because the distribution is Gaussian, the right-hand side can be
expressed by
34
( ) ∫−⋅= dxxpr )
2exp(
21 2
21
π (2.10)
where the lower limit of integration is now Vpp/2σ = Vp/σ. This ratio is customarily
denoted by Q, hence we obtain
⋅=
⋅⋅⋅=
25.0
225.0 QerfcVerfcpr PP
σ (2.11)
For the case of binary signaling the probability of error, pr, is more commonly called the
binary error rate or BER.
The relation between BER and Q is often given graphically, but in some respects
a table of values is preferable.
35
Table 2-2: The relationship between parameter “Q” and Required BER
BER Q from Ref
[115]
Q from Ref
[114] Error(%)
10-4 3.72003 3.71902 0.0200
10-5 4.26530 4.26489 0.0096
10-6 4.75362 4.75342 0.0042
10-7 5.19944 5.19934 0.0019
10-8 5.61206 5.61200 0.0010
10-9 5.99784 5.99781 0.0005
10-10 6.36136 6.36134 0.0003
10-11 6.70603 6.70602 0.000
10-12 7.03450 7.03448 -
10-13 7.34880 7.34880 -
10-14 7.65063 7.65063
36
The reason why two columns of values of Q are presented is the equation relating
Q and BER is nonlinear and is thus best solved numerically. The differences are
negligible in practice since only two or three significant figure values of Q are normally
used. This probability and the quantity Q can be related to voltages at the input to the
decision circuit. It is assumed that this voltage at the decision instants are Gaussian
random variables with mean values V0 and V1 for a zero and a one, respectively, and with
variance σ02 equal to the worst-case noise for zeros and σ1
2 equal to the corresponding
value for ones. It can be shown that the optimum value of the threshold VT is a linear
function of V1, the interference VI, together with a third term proportional to the mean
square noise voltage, the actual expression is
−
++=)1(1
)0(ln2 1
21
prpr
VVvV IT
σ (2.12)
But for simplicity the interference term will be neglected.
The optimum decision threshold must be set between V0 and V1, so that
0
0
1
1
σσVVQVV TT −==− (2.13)
Here, VT must be Qσ1, volts below V1 or, equivalently, Q standard derivation σ0 above
V0 to obtain the desired BER. The corresponding value of Q can be taken from the table
and the signal peak-to-peak voltage from equation
σ⋅⋅=−= QVVVPP 201 (2.14)
37
Assuming that σ1 = σ0. These calculation apply directly to baseband systems, but in a
carrier system the effect of the channel on the carrier enters the equation through the
mean and r.m.s. values.
So, simply speaking, the parameter Q is a ratio of peak signal to r.m.s value of
noise [29]. Thus, the maximum input noise level to acquire a certain level of BER can be
obtained by the equation and specified parameter Q.
2
22
noise
signal
II
Q = (2.15)
where, Q is a power signal-to-noise ration (SNR) and is given in the previous table. for
example, 6.36136 for 10-10 BER [115]. Isignal is the current input signal from a
photodetector, and <I2noise> is the total input-referred noise power. Therefore, the Inoise
requirement can be obtained since the Isignal is known from the light power arriving at the
photodetector by using Eq. (2.15) given the responsivity of the photodetector. The value
of Q varies with the required BER and originated from a digital communication theory
[41]. The table below shows the relationship between BER in digital communication
systems and signal-to-noise ratio (SNR) in analog communication systems. Once the light
power arrived at the photodetector is known, the sensitivity requirement of the receiver
amplifier at a certain BER can be obtained from the following relationship given by
−⋅=
2exp
21 2QBERπ
(2.16)
38
and the Figure 2.9 shows one of example of the probability of error vs. Q for a Gaussian
noise distribution of amplifier.
10-16
10-14
10-12
10-10
10-8
10-6
0.0001
0.01
1 2 3 4 5 6 7 8 9Value 'Q'
Prob
abili
ty o
f Err
or, (
BE
R)
Figure 2-9: Probability of Error vs. Q for a Gaussian Noise Distribution in Amplifier
39
Table 2-3: The relationship between BER and SNR
BER 10-7 10-8 10-9 10-10 10-11 10-12 10-13 10-14 10-15
SNR(dB) 14.3 14.8 15.5 16.1 16.6 17.0 17.3 17.7 18.0
40
2.5 Receiver System Design Consideration
For the development of proposed optical receiver amplifiers, the SONET standard
for high-speed, digital communications networks is selected. The SONET is a newly
developed (in 1985) transmission standard which stands for Synchronous Optical
NETwork. This standardized synchronous system will allow greater flexibility in adding
new services to existing SONET installations. The basic SONET transmission rate is OC-
1 (Optical Carrier at level 1) at 51.8Mbps. The electrical equivalent is STS-1
(Synchronous Transport Signal at level 1). Higher levels of SONET rates are shown in
the table [35].
41
Table 2-4: Levels of the SONET Signal Hierarchy and Electrical Equivalents
LEVEL Equivalent Electrical
Standard LINE RATE (Mbits/s)
OC – 1 STS – 1 51.840
OC – 3 STS – 3 155.520
OC - 9 STS – 9 466.560
OC – 12 STS – 12 622.080
OC – 24 STS – 24 1244.160
OC – 36 STS – 36 1866.240
OC - 48 STS – 48 2488.320
The SONET physical layer defines optical parameters for each level of the
SONET hierarchy in the three broad application categories: Long Reach (LR),
Intermediate Reach (IR), and Short Reach (SR). The more detailed specifications are
provided in Appendix I. Currently, 8 different optical line rate (N times 51.840 Mbits/s,
where N=1, 3, 9, 12, 18, 24, 36, or 48) are specified in the physical layer and each data
rate has different requirements depending on the distance between the transmitter and the
42
receiver. For all SONET optical system interfaces, binary Non-Return-to-Zero (NRZ)
optical line coding is used. The parameters are specified relative to an optical system
design objective of a Bit Error Rate (BER) not worse than 1 x 10-10 for the extreme case
of optical path attenuation and dispersion condition for each application specified.
The following table shows the lists of recent technology related with optical
receivers using digital CMOS process.
43
Table 2-5: List of Recent Research in CMOS Optical Receiver
Ref Speed BER Sensitivity Power Supply Pre-amp
Bandwidth
Input
Capacitance
Trans
Gain
Gate
Length
[91] 1 10-9 1.5 2.2 0.1 0.35
[94] 2.4 104 2 5.9 0.3 59 0.15
[92] 1 10-12 -24 155 5 0.66 0.7 66.5 0.8
[76] 0.8 10-9 -8.5 10 0.05 0.8
[97] 1 -40 100 5 0.8 60 0.7
Unit Gb/s dBm mW V GHz pF dBΩ µm
* Detector Information is provided in Table 6-1
* Only [76] uses Hybrid Integrated Photodetector
44
CHAPTER III
LOW INPUT RESISTANCE OPEN LOOP OPTICAL
RECEIVER
3.1 Introduction and Applications
In determining the topology of optical receiver, low impedance open loop type
among three types of basics mentioned in Chapter 2 has been selected for this design. As
explained in the previous chapter, the characteristics of this type of optical receiver are;
1) wide bandwidth, 2) not as good as the others in terms of noise performance resulting in
requirement of big optical power. Also, It has been experimentally proved that receivers
that have single input/output can easily pick up noise from power supply rails and digital
circuitry if mixed analog and digital circuitry coexist on a same die [83-85]. For this
reason, to have a better immunity to noise and to stabilize the bias at high speed,
differential version, i.e., balanced topology instead of single version was selected. And as
a second consideration of amplifier design method, the electrical amplifier must be
working with hybrid integrated MSM photo-detector with a size of 250 x 250um to
45
increase fiber alignment tolerance, this size of detector is normally known to be huge [76]
and has a big capacitance compared with other commercial detector. In order to combine
this huge detector with high performance electrical amplifier, low input resistance
electrical amplifier topology has been selected for the design of optical system.
In this research, a wide-bandwidth optical receiver having a differential, current-
mode input stage with low input impedance has been designed. The amplifier has been
simulated and laid out using magic layout tool, and fabricated using HP 0.6um
technology through MOSIS foundry, and afterward, it has been tested showing 10-11 BER
performance at a speed of 622Mbps at a sensitivity of –12.2 dBm.
46
3.2 Amplifier Design
A differential-input, current-mode, low input impedance amplifier topology is
selected, because it does not need a passive bias resistor and gives programmability to the
input impedance level. This also helps control the input noise for a given bandwidth. For
amplifiers with a multi-stage configuration, it is true that the noise contribution from the
later stage is negligible compared to that from the first stage [5]. Therefore, voltage-mode
amplifiers can be used for post amplification to minimize the power dissipation since
voltage-mode amplifiers consume the minimum power [89].
3.2.1 Front-end Design
Researchers have introduced design techniques of current-mode approaches
[46,47]. The following figure shows a simple MOSFET current mirror which provides a
current gain or attenuation form the input current, iin to the output current, iout , based on
the size ratio of two transistors.
47
Figure 3-1: Basic Schematic of Current Mirror
Also, the following figure illustrates the differential current-mode amplifier stage
after using a current mirror as the input pair. For the output load resistance, a high-speed,
diode-connected active transistors are employed to obtain the maximum bandwidth. The
tail current, Ibias is supplied by another current mirror which is not shown in the figure.
From the hand calculate analysis, a cascode current mirror for the tail current is desirable
because it can provide high enough working voltage level.
48
Figure 3-2: Transimpedance Stage of Front-end
The transimpedance gain of the current-mode amplifier is given by
51
52
11
gmgmgm
gmIVA
in
outR ≅
⋅
== (3.1)
where gmx is the transconductance of transistor Mx. It is designed so that bias currents of
two current mirrors are the same. The bias currents for transistors M1 through M4 are all
the same. So, the equation above can be simplified to 1/gm5 [60].
The whole circuitry including cascode bias circuits is shown in the following
figure. In the figure, I_bias1 and I_bias2 are also used to bias the both inputs. I_bias2 is
49
four times larger than I_bias1 or I_bias3. It is obvious that it is possible to adjust the input
impedance by controlling the bias current ratio. The input impedance at both inputs are
not symmetrical, thought. The in+ input node has a lower impedance than in- node since
the impedance at the in+ input node is determined by the parallel combination of
transistor M1 and M9, while the impedance at the in- node is determined mainly by the
bias current flowing through transistor M3. The cascode current mirrors formed by
transistors, M9 through M14, are desirable, since it gives not only a higher impedance to
the drain of each transistor, M9, M11, and M13, but sets the bias voltage of the two input
nodes at the middle of two power supply rails, Vdd and Vss.
51
3.2.2 Post Voltage Gain Stage
As a post amplifier after the current-mode input stage, differential voltage-mode
amplifiers were employed to have a high voltage gain. It has been reported by some
researchers that voltage-mode amplifier consumes less power for a given bandwidth than
current-mode amplifiers [89]. Therefore, a cascaded differential voltage amplifiers are
used for the later stage to minimize the overall power dissipation. As shown in the figure
below, the NMOSFET diode-connected transistors are used for the output load resistance.
There are two reasons of this, first, using NMOS diode-connected transistor makes the
output load more symmetric than high impedance current mirror output load, second,
they have less gain so they have wider 3 dB bandwidth.
52
Figure 3-4: Post Voltage-mode Differential Amplifier
The gain of differential voltage amplifier is given by
3
11
m
mv g
gA = (3.2)
where gm1 and gm3 are the transconductances of transistors, M1 and M3, respectively.
The overall amplifier including detailed schematic of each part is shown in the
figure below and its overall transimpedance gain, ATOTAL, is given as follows
26
1 VVRTOTAL AAAA ⋅⋅= (3.3)
53
where AR is the transimpedance gain of the current-mode amplifier stage which is given
by Equation (3.1) and AV1 is the post differential voltage amplifier gain which is given by
Equation (3.2). Av2 is the voltage gain of the differential-input-single-output stage and is
designed to have a value twice that of AV1.
The offsets provided by 3rd and 4th post voltage differential stage are to
compensate the voltage offsets introduced by first front-end current-mode amplifier.
Also, these offsets set swing point of output voltage so that they can be used as inputs of
the comparator stage following amplification circuitry.
The following figure illustrates the amplifier sub-components (Front-end and post
voltage-mode amplifier) and block diagram to show the structure of whole optical
receiver at a glance.
54
Figure 3-5: The structure of Optical Receiver with Sub-components
According to the simulation result, which will be discussed in the next section, the
bandwidth of the amplifier is mainly determined by the RC time constant at the input.
55
Again, the total capacitance is composed of the photodetector capacitance, pad
capacitance, stray capacitance, and input capacitance of the current-mode front-end
amplifier. The input resistance is 1/gm1 controlled by the transconductance of transistor
M1.
56
3.3 Simulation
The HSPICE simulation [49] on the overall amplifier has been performed using
0.6um, BSIM level 4 model parameters (See Appendix II) provided by MOSIS service
[42]. The figures below show the simulation results.
The figures from Figure 3-6 to 3-7 are transient response of optical receiver at
480Mbps speed, the simulations are performed at different optical power and different
input capacitance which primarily determine the bandwidth of receiver. Likewise, the
ones from Figure 3-8 to 3-9 are the transient simulation result performed at SONET OC-
12, 622Mbps speed. The top traces are transient output from the final stage with input
which is depicted on the bottom trace, this is shown because eye-diagram alone cannot
reveal that fact that there is a missing bit in the output stream. The middle traces are eye-
diagram to show how well the receiver is complying with the incoming bit streams.
As shown in the simulation results, the input current magnitude and input
capacitances are important factors, which affect the size and shape of eye-diagram.
Obviously, the bigger input current and smaller input capacitance results in bigger eye
with shorter rising and falling time constants.
57
Figure 3-6: Transient Response to 16µA Input Current with 0.1pF Input Capacitance at 480Mbps
Figure 3-7: Transient Response to 16µA Input Current with 1.0pF Input Capacitance at 480Mbps
58
Figure 3-8: Transient Response to 16µA Input Current with 0.1pF Input Capacitance at 622Mbps
Figure 3-9: Transient Response to 16µA Input Current with 1.0pF Input Capacitance at 622Mbps
59
The following 4 figures illustrate AC sweep result of Front-end along with noise
analysis results with different input capacitances, the top trace shows output noise and the
second one does input noise calculated by HSPICE emulator, the third one is AC sweep
result up to 10GHz.
Since neither output noise nor input calculated noise doesn’t have any meaningful
value at a certain frequency. In calculation of input referred noise which has a meaning in
figuring out minimum optical power required to meet SONET standard specification, the
squared value of all the noise components explained in chapter 2 were integrated from
DC to a high enough frequency point and square root was taken and divided by low
frequency gain to have a r.m.s. value of input referred noise. The following equation was
exploited.
( )GainfrequencyLow
noiseoutputsmrNoise
__
_.)..(
2∫= (3.4)
According to the simulation result, the input capacitance not only reduces the
bandwidth of receiver, but also increases input referred noise current. However, even
with maximum expectable (and feasible) capacitance value (1.0pF), the noise was less
than 800nA which means that minimum sensitivity of receiver is 5.088µA meeting
SONET OC-12 specification.
The low frequency transimpedance gain of front-end was 229. The table below
shows the bandwidth of front-end receiver at different input capacitances.
60
Table 3-1: 3dB Frequency at different Input Capacitance
Input
Capacitance
Zero Input
Capacitance
0.1pF Input
Capacitance
0.5pF Input
Capacitance
1.0pF Input
Capacitance
3dB BW 852MHz 824MHz 697MHz 572MHz
61
Figure 3-10: AC Sweep and Noise Analysis with zero Input Capacitance
Figure 3-11: AC Sweep and Noise Analysis with 0.1pF Input Capacitance
62
Figure 3-12: AC Sweep and Noise Analysis with 0.5pF Input Capacitance
Figure 3-13: AC Sweep and Noise Analysis with 1.0pF Input Capacitance
63
As a final simulation result, the Common Mode Rejection Ratio (CMRR) was
shown in following two figures, the first one shows the one regarding front-end only, and
the second one shows CMRR of whole stage.
65
3.4 Layout
In the layout of the circuit, splitting the power supply rails helps to reduce
parasitic feedback, which usually causes oscillation. For this amplifier, the power
supplies are separated into two halves. The first half serves only those parts of the circuit
that amplify small signals at the input side, while the second serves the large signal and
output portion of the circuit. This prevents the larger output signal from generating small
feedback signals in the sensitive small signal parts of the circuits. Another aspect of the
layout that reduces unwanted coupling into the input signal is the long, thin left-to-right
geometry of the layout. Small input signals enter on the far left, while the output signals
exit on the far right. This maximizes the separation of the sensitive input stages from the
larger signal output stages. Finally, the bonding pads on the critical signal path are as
small as possible to minimize the pad capacitance.
The amplifier was laid out carefully for fabrication as shown in the figure below.
There are two separate power rails for the sensitive input signal portion and the output
portion, which has a relatively large signal swing. It was found out that the input
capacitance was very detrimental to the system performance. So, every effort was made
to minimize the input capacitance. Once again, two small pads were prepared for post
processing, in which a compound semiconductor was integrated.
66
Front-end Stage Offset Stage
Post Differential Voltage Amplification StageCurrent Mirror Reference Parts
Figure 3-16: MAGIC Layout of Low Input Impedance Differential Optical Receiver
To bond the compound semiconductor photodetector to the circuit at the signal
input side, two small pads are required with open overglass. The pad size must be as
small as possible to minimize the pad capacitance since this capacitance directly
contributes to the input capacitance, and in turn, increases the input impedance required.
To reduce the input capacitance due to the pad, placing a floating n-well underneath the
pad helps reduce the pad capacitance since the well capacitance is in series with the pad
capacitance [50]. This technique also prevents the pad metal from spiking into the
substrate. The figure below shows the MAGIC layout before fabrication. Two small pads
at left center are prepared for photodetector integration. The pad connected to the
amplifier input contributes a large portion of input capacitance. So, it should be made as
small as possible.
67
Low Impedance Differential Amplifier Clocked Comparator 8 bit Shift Register
TransmitterD/A Converter
Detector Integration Area
Figure 3-17: MAGIC Layout of Chip
The chip was fabricated using Hewlett Packard AMOS 14TB Process of which the
feature size is 0.5um. This CMOS n-well process has 3 metal layers, 1 poly layer, and
options for linear capacitor (2250aF/um2) and silicide block [42]. The process is for 3.3
volt application originally. Fabricated silicon chips are delivered without packaging from
68
MOSIS to allow post-processing. The detailed description of the process is provided in
Appendix II. The design rule that was used for the layout and post simulation after
extraction was SCMOS rule. In this rule the lambda is 0.35um and feature size of the
minimum transistor is 0.6um. However, the fabrication vendor, MOSIS shrinks all
SCMOS drawn poly by 0.1 µm so that a drawn 2 lambda (0.7 µm) gate will achieve the
process minimum poly width of 0.6 µm. This is done by shrinking all poly everywhere in
each SCMOS design by a uniform 0.1 µm. No modification is applied to
SCMOS_SUBM poly, since its minimum size matches the process.
The design was focused on the scalability for easiness of future development and
application in system level design. Fro scalability, the design doesn’t contain any passive
components such as on-chip resistor and capacitor. This low impedance open loop
receiver was fabricated using standard digital CMOS 2.0µm, 1.2µm, 1.0µm, 0.8µm,
0.5µm, and 0.35µm processes and all circuits were working to generate appropriate
performance.
69
3.5 Measurements
After chip fabrication without packaging, photo detector was integrated in post-
processing, the figure below illustrates a microphotograph of the chip after the integration
of the photodetector. The photodetector is 250um size in each side. It has small metal
contact fingers extending from each of two sides of the photodetector on the bottom of
the photodetector. A metal-semiconductor-metal (MSM) photodetector was selected
since low capacitance per unit area is of vital importance in the design of high speed, low
power and alignment tolerance aspects. The I-MSM, with the electrodes defined on the
bottom of the device, overcomes the low responsivity problem of conventional MSM
detectors with fingers on the top by eliminating the shadowing effect of the electrodes
[52]. The I-MSMs demonstrated up to 0.7 amp/Watt responsivity and the leakage current
is less than 10nA at 10V bias. The frequency response is up to 6 GHz with a 50-Ohm
load. The measured capacitance was 0.4pF for this 250um active area I-MSMs with 1um
finger width and spacing between fingers.
The integrated OEIC’s were bonded directly onto the test boards. As shown in the
Figure 3-18. The boards were solely tested before bonding and proved to work up to 1.2
Gbps without apparent signal distortion. The Figure 3-19 shows the test board with a
bonded chip and an integrated detector on top of it.
71
Figure 3-19: Photo-picture of Test Board
For the modulation of optical signal incident on photodetector, direct modulation
which is depicted in the Figure 3-20 was employed. The modulating digital signal was
provided by BERT TX system and summed with DC bias to drive a commercial laser
diode.
The optical power incident on the detector was estimated using the bias current
through the laser and the figures are provided in Table 3-2.
72
Figure 3-20: Direct Modulation of Optical Signal
The figure below shows the test setup block diagram for the integrated receiver.
The test setup consists of Bit Error Tester (BERT) which generates different modes of
pseudorandom digital pulse stream and measures the probability of an transmitted data
error rate through the device under test, a modulator to generate an adequate pulse to a
light emitting source, a pig-tail laser source to illuminate lightwave upon the
photodetector of the receiver.
74
3.5.1. Transient Measurement Result with Eye-diagram
An eye diagram and a pulsed waveform of these integrated receivers were
measured using 27 –1 NRZ pseudorandom bit stream (PRBS) which simulates the real
data pattern specified in SONET specifications. Target operating speed is 622Mbps. The
amplifiers were designed to operate at a 5V single power supply. However, bias currents
and the detector bias were adjusted to achieve the best operating speed for each circuit.
An output load of 50 Ohm was used at the scope and at the termination of BER tester.
The figures below from Figure 3-22 to 3-23 show the result of test at 622Mbps
speeds and at Maximum allowable optical power. The top trace is triggering signal and
middle one is amplifier output captured on the oscilloscope screen and the inverted one of
differential signals was being fed into the BER tester. The bottom signal is the
comparator output signal. In Figure 3-23, the middle trace is a eye-diagram captured on
the oscilloscope with 10 seconds of duration, the bottom one is an eye-diagram of
comparator output which has no meaning since it cannot reveal a missing bit if any.
75
Figure 3-22: 622Mbps, transient, 2V optical power
Figure 3-23: 622Mbps, eye diagram, 2V optical power
76
The next four figures from 3-24 to 3-27 were captured test results with lower
optical signal which is -18 dBm and at lower speed. Obviously, the size of eye reduced
by a certain amount, and this caused low BER in BER test. The eye diagrams were taken
with 10 seconds duration.
77
Figure 3-24: 622Mbps, Transient, 0.5V Optical power
Figure 3-25: 622Mbps, Transient, 0.5V Optical power
78
Figure 3-26: 480Mbps, Transient, 0.5V Optical power
Figure 3-27: 480Mbps, Eye-diagram, 0.5V Optical power
79
10-12
10-10
10-8
10-6
10-4
0.01
1
0 0.5 1 1.5 2 2.5
"See Optical Power Conversion Table"
C
DEFGH
BE
R (L
og S
cale
)
Optical Power
Figure 3-28: Bit Error Rate Performance Test Result (C=622Mbps, D=580Mbps, E=520Mbps, F=480Mbps, G=450Mbps, H=400Mbps)
80
Table 3-2: Optical Power Conversion Table
Voltage
applied 2 1.8 1.6 1.4 1.2 1.0 0.8 0.6 [V]
In µA 60 54 48 42 36 30 24 18 [µA]
In dBm -12.2 -12.6 -13.2 -13.8 -14.4 -15.2 -16.2 -17.4 [dBm]
3.5.2 ISI Effect Measurement
Dispersion of the transmitted optical signal at the output causes distortion for both
digital and analog transmission along optical fiber path. When considering the major
implementation of optical fiber transmission which involves some form of digital
modulation, then dispersion mechanisms within the fiber, coupler, and amplifier front-
end cause broadening of the transmitted light pulses as they travel along the channel
[103]. As seen in the following figure, any energy that spills out of the expected pulse
position is lost to the receiver for use in detecting the pulse of interest and it may be
observed that each pulse broadens and overlaps with its neighbors, eventually becoming
indistinguishable at the receiver input. This effect is known as Inter-Symbol Interference
(ISI). So, if large enough, this energy might trigger a false detection in the adjacent time
slot. While this Inter-Symbolic Interference may be partially corrected by the use of
81
properly designed equalization amplifier (at the expense of increased noise level), the
brief explanation of this equalization stage will be given in the following last chapter.
Figure 3-29: Example of Intersymbol Interference
As a result, an increasing number of errors may be encountered on the digital
optical channel as the ISI becomes more pronounced. The error rate is also a function of
the signal attenuation on the link and the subsequent signal to noise ratio (SNR) at the
receiver. However, signal dispersion itself limits the maximum possible bandwidth
attainable with a particular optical fiber to the point where individual symbols can no
longer be distinguished.
For light pulses down on an optical fiber link the digital bit rate BT must be less
than the reciprocal of the broadened (through dispersion) pulse duration (2τ).i.e.,
82
τ⋅≤
21
TB (3.5)
This assumes that the pulse broadening due to dispersion on the channel is τ
which dictates the input pulse duration which is also τ. Hence, the equation above gives a
conservative estimate of the maximum bit rate that may be obtained on an optical fiber
link as 1/2τ.
Another more accurate estimate of the maximum bit rate for an optical channel
with dispersion may be obtained by considering the light pulses at the output to have a
Gaussian shape with an rms width of σ. Unlike the relationship given in the equation
(3.5), this analysis allows for the existence of a certain amount of signal overlap on the
channel, whilst avoiding any SNR penalty which occurs when inter-symbolic interference
becomes pronounced. The maximum bit rate is given approximately by [111]
BT(max) =~ 0.2/σ [bit/s] (3.6)
It must be noted that certain source [107] gives the constant term in the numerator
of Equation above as 0.25. However, we take the slightly more conservative estimate
given. Equation above gives a reasonably good approximation for other pulse shapes
which may occur on the channel resulting from the various dispersive mechanisms within
the fiber. Also, σ may be assumed to represent the rms impulse response for the channel.
The conversion of bit rate to bandwidth in hertz depends on the digital coding
format used. For metallic conductors when a non-return to zero code is employed, the
binary one level is half for the whole bit period τ. In this case there are two bit periods in
83
one wavelength (i.e. two bits per second per hertz). Hence the maximum bandwidth B is
one half the maximum data rate or
BT(max) = 2B (3.7)
In most cases, the RC time constant at the input is a major operating speed limit
for optical receiver amplifier design. The total input capacitance consists of the
photodetector capacitance, pad capacitance, input transistor capacitance, parasitic
capacitance, and any other capacitance connected to the input node. In general, the
photodetector capacitance is the dominant factor to the input capacitance. Therefore, it is
very important to get a photodetector with low capacitance. Once the photodetector is
selected and then the dominant input capacitance is fixed, the only design factor is the
input resistance, R. For a given bandwidth, the resistor value will be determined from tr =
2.2 x RC [36]. f-3dB of the amplifier can be obtained from following equation.
ππππBitRate
BitRatetRC
fr
dB×=
×⋅⋅
=⋅⋅
=⋅⋅
=−2.2
212
2.22
2.22
13 (3.8)
To illustrate the effect of input capacitance combined with input resistance, the
mathematical simulation was performed. When considering only front-end input stage,
the stage is a low pass filter which has a pole of inversely proportional value to input RC
constant as mentioned in the Equation (3.8).
In the simulation, a FDDI PR signal was passed through the filter, which is
composed of only one pole that is contributed by input resistance and capacitance. And
output frequency response and transient response were compared with input signal’s
84
responses at different pole locations. The following figures from Figure 3-30 to 39 shows
the results. As shown in the results, RC time constant increase, which is closeness of pole
to the origin, causes bandwidth decrease with closing of eye in eye-diagram resulting in
higher (worse) BER due to ISI effect.
In the Figure 3-30 to 3-39, the red color traces represent incoming fddi PRS
signal, and blue color trace represent output signal after simple RC filter. The even
number figures are transient response and the other are frequency response.
85
0.6
0.6
sigvp
sigivp
0
14012.25 140 tp
20 40 60 80 100 120 140
0.5
0
0.5
FDDI codeBand Passed FDDI CodeZero Crossing
Figure 3-30: Transient Response of ISI Effect Simulation when pole=1
2.236
4.616 10 3.
if fsigp2 0> fsigp2, 0.01,
if filtvp2 0> filtvp2, 0.01,
640.1
1
if p2520. 0> p2
520., 0.1,
0.1 1 10 1001 .10 3
0.01
0.1
1
10
Figure 3-31: Frequency Response of ISI Effect Simulation when pole=1
86
0.6
0.6
sigvp
sigivp
0
14012.25 140 tp
20 40 60 80 100 120 140
0.5
0
0.5
FDDI codeBand Passed FDDI CodeZero Crossing
Figure 3-32: Transient Response of ISI Effect Simulation when pole=2.5
2.236
4.616 10 3.
if fsigp2 0> fsigp2, 0.01,
if filtvp2 0> filtvp2, 0.01,
640.1
1
if p2520. 0> p2
520., 0.1,
0.1 1 10 1001 .10 3
0.01
0.1
1
10
Figure 3-33: Frequency Response of ISI Effect Simulation when pole=2.5
87
0.6
0.6
sigvp
sigivp
0
14012.25 140 tp
20 40 60 80 100 120 140
0.5
0
0.5
FDDI codeBand Passed FDDI CodeZero Crossing
Figure 3-34: Transient Response of ISI Effect Simulation when pole=5
2.236
4.616 10 3.
if fsigp2 0> fsigp2, 0.01,
if filtvp2 0> filtvp2, 0.01,
640.1
1
if p2520. 0> p2
520., 0.1,
0.1 1 10 1001 .10 3
0.01
0.1
1
10
Figure 3-35: Frequency Response of ISI Effect Simulation when pole=5
88
0.6
0.6
sigvp
sigivp
0
14012.25 140 tp
20 40 60 80 100 120 140
0.5
0
0.5
FDDI codeBand Passed FDDI CodeZero Crossing
Figure 3-36: Transient Response of ISI Effect Simulation when pole=7.5
2.236
4.616 10 3.
if fsigp2 0> fsigp2, 0.01,
if filtvp2 0> filtvp2, 0.01,
640.1
1
if p2520. 0> p2
520., 0.1,
0.1 1 10 1001 .10 3
0.01
0.1
1
10
Figure 3-37: Frequency Response of ISI Effect Simulation when pole=7.5
89
0.6
0.6
sigvp
sigivp
0
14012.25 140 tp
20 40 60 80 100 120 140
0.5
0
0.5
FDDI codeBand Passed FDDI CodeZero Crossing
Figure 3-38: Transient Response of ISI Effect Simulation when pole=10
2.236
4.616 10 3.
if fsigp2 0> fsigp2, 0.01,
if filtvp2 0> filtvp2, 0.01,
640.1
1
if p2520. 0> p2
520., 0.1,
0.1 1 10 1001 .10 3
0.01
0.1
1
10
Figure 3-39: Frequency Response of ISI Effect Simulation when pole=10
90
The following table shows the maximum allowable resistance values and –3 dB
bandwidth of different data rates and different input total capacitances, the input
resistance can be easily obtained by the bandwidth requirement.
Table 3-3: Maximum Allowable Resistance at Different Data Rates
51.84 Mbits/s 155.52 Mbits/s 455 Mbits/s
f-3dB [MHz] 36.30 108.90 318.62
Input Capacitance [pF] 0.4 0.4 0.4
Input Resistance [Ω] 10961 3653.6 1248.83
622 Mbits/s 1.2 Gbits/s 2.4 Gbits/s
f-3dB 435.57 840.33 1680.67
Input Capacitance [pF] 0.4 0.4 0.4
Input Resistance [Ω] 913 473 236.75
The following figure shows the effect of ISI noise. Specifically, the effect of
difference of numbers of ones and zeros in a sequence of 27-1 bit stream. In the graph, it
is shown that as the number of 1’s in the bit stream increases, BER is getting worse.
91
Originally, the 27-1 bit stream consists of recursive 27-1 bit streams and the longest 1’s in
the bit stream is 7. this effect is caused by limited charging time and discharging time due
to the input capacitance. As a result, this ISI effect is reduced as incident optical power
decreases.
In other words, as shown in the experimental results, the difference between the
numbers of 1’s and 0’s in a certain interval of incoming signal has a detrimental effect on
BER, this phenomena can be explained by the effect of input capacitance. The bigger the
difference in the numbers of 1’s and 0’s in the incoming signal stream, the more severely
input capacitance is charged/discharged and as this effect is being accumulated, this
works as changing offset of front-end stage.
The experimental result was taken at a speed of 270Mbps with different optical
power input conditions.
92
10-12
10-10
10-8
10-6
10-4
0.01
0 20 40 60 80 100 120 140
"See Optical Power Conversion Table"
Optical Power = 21.81.61.41.21.00.8
BE
R
Number of Zeros in One Sequence
Figure 3-40: BER Measurement Result with ISI effect.
93
CHAPTER IV
DIFFERENTIAL TOPOLOGY OF RECEIVER
4.1 Introduction
As a demand for the use of optics in computing increases, integration of
optoelectronic (OE) devices, interface circuitry and VLSI CMOS circuits is becoming an
issue in the fields of the realization of systems which can perform highly complex
processing tasks [75]. Using hybrid integration of OE devices with CMOS VLSI, one
exciting prospect for optics is that of optical interconnect for connecting high speed
digital processors, since conventional wire based interconnect and packaging
technologies are reaching limits of both speed and packing density [2]. To increase the
complexity of electronic functions in computational systems that use optical
interconnections, analog optoelectronic (OE) devices and interface circuits must operate
in the presence of digital processing circuitry which produce digital switching noise [86].
Sensitive CMOS receivers operating next to a running microprocessor have not been
demonstrated yet in spite of many endeavors to develop CMOS analog interface circuitry
94
operating with a digital microprocessor on a same die. In the noisy digital microprocessor
environment, noise levels of hundreds of millivolts with picosecond rising times are not
uncommon [63,64], which significantly and negatively impact receiver operation. A
differential or balanced circuit topology employed in receiver design shows better
performance than single-sided or ended receivers especially in terms of substrate
coupling noise when employed in mixed signal system design or one-chip transmitter and
receiver design [46,47,85,90,102]. The reason of this can be summarized in two major
factors, firstly, the same noise reaching the both of inputs of amplifier doesn’t being
amplified as it goes through multiple amplifier stages because of CMRR, secondly, bias
current stabilization using balanced topology prevents incoming noise components which
has same harmonics as the signal. So differential topologies are preferred from crosstalk
perspective. In this research, a simultaneously working fully differential optoelectronic
(OE) receiver fabricated in Si CMOS with digital SIMD microprocessor on the same die
next to analog, optical interface circuitry has been developed, the receiver have been
hybrid integrated with a thin film InP-based inverted (I)-MSM photodetector and optically
tested using external light source modulated by digital input signal. The noise immunity
to mixed-signal digital switching noise of the differential receiver has been shown to be
good enough to generate 10-9 BER.
95
4.2 Background and Applications
The primary methods used to eliminate digital noise present in a mixed digital and
analog integrated circuit are isolation and differential amplification [46,47,84]. Isolation
means the designs attempting to keep the sensitive analog circuitry separate from the
noisy digital circuitry, or to block the transmission of the noise from the digital circuitry
to the analog circuits. But, when building sensitive optical receivers next to a
microprocessor or on-chip transmitter part, achieving good isolation is difficult, and
perhaps, futile. Digital circuit designers typically work with noise margins of hundreds of
millivolts and signal edges in the picoseconds, which creates noise levels that permeate
even the best isolation. Thus differential design techniques must be used in most mixed
signal systems or one-chip transmitter and receiver systems that are susceptible to
substrate noise.
Differential receiver designs attempt to remove noise from their inputs by using
parallel, but inverted, signal paths, with subsequent subtraction of the two signals to
obtain a resultant signal without the noise. By having two parallel signal paths designers
hope that very similar noise signals will corrupt in the middle of both signal paths. Thus,
if the desirable signal is inverted (or absent) on one path, and the noise is the same on
both paths, subtraction of the two signal paths should remove the noise. To succeed,
differential amplifiers must have carefully designed signal paths to ensure both paths
collect the same noise. They also need sufficient dynamic range at each amplification
96
stage to prevent the noise signal (which may well be 100 times larger than the input
signal) from degrading the desired signal [65]. Finally, the common mode rejection (the
quality of the subtraction performed on the two inputs) of the differential amplifier stages
must be high enough to extract the signal from the noise. The basic idea of reducing noise
in differential topology is depicted in following figure.
Figure 4-1: Comparison of Isolation vs. Differential Topology Method in
Reducing Digital Noise
97
In this research, an experimental verification is presented to show that a carefully
designed fully differential receiver can operate successfully on the same chip as an
operating microprocessor. It begins by presenting simulation results that demonstrate the
advantages of fully differential receivers over single ended (not differential) designs. In
the following section, it will be shown that differential designs can remove input noise
and that they create little noise themselves, whereas single ended designs are sensitive to
noise and may even make noise that may hamper their own operation. Then we describe
the integrated digital CMOS mixed signal system used to verify the operation of the
differential receiver. This is a portion of a multi layer, high frame rate focal plane
processor fabricated at Georgia Tech. Finally we present experimental results that show
the operation of the amplifier both with and without digital noise, and then show that the
receiver can feed data to the microprocessor circuitry for processing.
98
4.3 Simulation and Comparison
Single ended receiver designs have no mechanism to remove noise picked up
from their environment. In addition, single ended designs can produce noise because of
large changes in their supply currents. To illustrate the risks associated with not using a
fully differential receiver design, a single ended receiver [57] has been simulated (using
HSPICE) in the presence of large digital noise at the input. The single ended receiver
design and operation is described in detail in Reference [61]. The figure below shows the
receiver input and output signal when a certain amount of substrate noise reaches the
input node of receiver. The output signal has been highly corrupted by the digital noise,
and is not a useful signal.
99
Figure 4-2: Top trace: the simulated output signal (voltage) of the single
ended receiver with a certain degree of substrate noise applied to the input.
Bottom trace: the noise-free input to the receiver (1 micro amp peak to peak)
To illustrate the noise production problem with single ended designs, the power
supply current of the same single ended receiver has also been simulated using SPICE.
The following figure shows the results; there is nearly a 1 milliamp change in the supply
current in less than 1 ns. This much current change can produce 5-10 millivolts of noise
in a 5-10 nH bond wire inductance (50 to 100 micron diameter wire 5 to 10 mm long).
numerically,
100
mVnsmAnH
dtdiL 10
1110 =×=⋅ (4.1)
This noise voltage magnitude is comparable to the input voltage magnitude found
on the receiver, which will result in noise problems (oscillation) due to output feedback
in this amplifier.
Figure 4-3: Power supply current for single ended receiver when a certain
amount of substrate noise is applied to the input. Even when assuming
normal operation without substrate noise, there is a 600 microampere
variation in the current
Using the fully differential receiver discussed later herein, the same simulation of
large digital noise added to the receiver input was performed using SPICE. The results
are presented in the figure below. The amount of noise present in the output signal has
been greatly reduced in comparison to the single ended receiver case.
101
Figure 4-4: Top trace: output signal of the differential receiver when a certain
amount of digital noise is applied to input. Bottom trace: the noise free input
(1 microampere peak to peak)
The possibility of the receiver generating noise due to fluctuations in the power
supply current is also significantly reduced in the differential receiver case, as the SPICE
simulation results illustrated in the figure below. This lower current variation will
produce 20-30 times less supply ripple. These simulations show a dramatic improvement
in the noise immunity related performance of the differential amplifier over the single
ended design.
102
Figure 4-5: Power supply current for fully differential receiver. There is a 40
microamp variation in the current
103
4.4 Mixed Signal Chip Design and Test
For this research, a differential analog receiver has been integrated with a digital
microprocessor on the same die to test the implications of the noisy digital environment
on the analog interface circuit. The digital circuitry is a single instruction multiple data
(SIMD) microprocessor, which acts as a digital noise source for the analog receiver
circuit. The integrated receiver/SIMD circuit is a portion of an on-focal plane imaging
system, in which the SIMD microprocessor processes data from an imaging array that is
preprocessed and subsequently passed to the receiver using an optical link [87]. This
processor node is part of a processor array called SIMPil [88]. The following figure is a
block diagram of one SIMPil node. This figure also illustrates how a single node
interfaces to a sub-array of detectors, and how each node is connected to each other in a
mesh network to operate in SIMD mode. Each node of the SIMPil array includes a
traditional RISC load/store data path plus an interface to the detector array via an OE data
channel. Initially, an 8-bit data path SIMPil node was implemented.
104
N N N
N N N
N N N
N N N
N N N
N N N
N N N
N N N
N N N
N N N
N N N
N N NLocal
Memory(64 words)
NEWS Registers
Register File(8 words)
Arithmetic,Logical, and
Shift Unit
Multiply Accumulator
Special Registers
Thin FilmDetector Array
S&HandADC
PE
Figure 4-6: Block diagram of a SIMD Pixel Processor node
The node includes a traditional processor data path plus additional units for
interfacing with the detector array. The first implementation of the node includes an 8-bit
data path with an arithmetical, logical, shift unit, and a 16-bit multiply-accumulator
(MACC) used in many image-processing applications. These functional units access an
eight-word register file. Each node has 64 words of local memory. Up to 256 words can
be addressed in the instruction set. SIMPil nodes communicate through a nearest
neighbor NEWS (north, east, west and south) network using special registers in the data
path.
The actual design of optical receiver of differential or balanced topology starts
from single-ended one. The general procedure of the design is; first, design single-ended
one, then, making an image of single side and modification of it to have big enough
105
CMRR and stabilized bias. For the design of differential optical receiver in this research,
the single current mirror with output resistance to convert current input to voltage as
shown in the figure below has been employed. The following figure shows the original
single version of receiver that was used in implementing differential version, the bottom
two transistors are to bias upper part of current mirror and to give a relative operation
voltage level.
Figure 4-7: Single part of Differential Amplifier Front-end
The differential receiver has been designed, tested, and integrated with the SIMD
microprocessor has a fully differential current mode input, current to voltage conversion,
106
and voltage gain stages. In fact, this optical receiver is identical with the one as a low
input impedance high speed one introduced in chapter 3 except the feature size of
transistors. The circuit diagram for this differential receiver appears in Figure 4-8.
I bias
VDD1
VSS
VDD2
VSS2
VOUT
Stage2
Stage6
bias
Figure 4-8: Circuit diagram of the fully differential current input receiver
circuit
The full SIMD node and the differential receiver were fabricated on the same chip
through the MOSIS foundry in 0.8 µm CMOS. (Feature size of transistor gate length is
1.0um).
After fabrication of the CMOS circuitry through the MOSIS foundry, the
unpackaged die was hybrid integrated with a thin film InP-based I-MSM, as shown in
Figure 4-9. Thin film InP-based I-MSMs (MSMs with the fingers on the bottom of the
107
device to avoid low responsivity due to finger shadowing) were bonded onto the receiver
input pads. The photodetector layers were: an InP (substrate) /InGaAs (100 nm, etch layer) /
InAlAs (40 nm) / InGaAs (1000 nm) / InAlAs (40 nm), with all layers nominally undoped.
The metal device fingers were defined, the layers mesa etched, the substrate
removed, and the thin film devices transferred and metal/metal bonded to pads on the
receiver circuit. These thin film I-MSM structures have demonstrated up to 0.7 A/W
responsivity [25,51] and, in this size, operation up to 1.1 GHz with leakage current less than
150 nA at 10 V bias has been observed. A capacitance of 250 fF is typical for these 250x250
µm2 active area I-MSMs with 2µm finger width and 8µm finger spacing. The hybrid
integrated OEIC was then wire bonded into a 144-pin grid array package, and tested.
108
Figure 4-9: Photo picture of the Chip : (Left: Simpil Microprocessor, A
quarter position From the Right: Photodetector, Right Most: Optical
Differential Receiver)
SIMD Microprocess I-MSM Photo-Detector
Differential Optical Receiver
109
4.5 Measurement and Test Results
Before the optical test of receiver, the electrical performance of the differential
receiver integrated with the microprocessor has been measured. The following figure is
an illustration of the test apparatus. The voltage input from a Tektronix BERT-1400
transmitter was attenuated and converted to a current input. The gain of the receiver
(shown as the triangle) is controlled through external current biasing.
BERT-1400 TXVoltage to CurrentCoversion Circuit
Offset Current Input
Decoupling Cap
Keithley SMUFor Voltage Biasing
Keithley SMU ForGain control Current
Voltage out1
Voltage out2
Figure 4-10: Test setup used to test receiver operation
Operating at a data rate of 1 Mbps with an electrical input signal of 5 µA (which
corresponds to an input sensitivity of -20 dBm, assuming a 0.5 A/W detector
responsivity) into a 50 ohm input resistance with a coupling capacitance of 10 nF, the
BER was 10-9. The receiver power dissipation was approximately 50 mW. To prove that
the differential receiver reduces the digital noise levels to an acceptable value, the
110
receiver was operated both with and without power and clocks to the digital circuitry in
the SIMD processor. The test setup used for these measurements is shown in Figure 4-
11. This apparatus used an arbitrary function generator to provide the 40 Mbps non-
overlapping clocks to synchronize the entire system.
BERT-1400Tx, DRx
Voltage-to-CurrentConversion
SIMDMicroprocessor
Arbitrary WaveformGenerator (AWG2041)
DC(HP E3610A)
8 bit Demultiplexed Shift Outputs
SynchronizingComparator
Figure 4-11: Test setup for digital noise immunity measurements
After electrical functionality checkup, the circuit was optically tested with
synchronized system clock signal generated by Digital Waveform Generator, the test
setup diagram with all digital function apparatus is shown in the following figure.
111
Figure 4-12: Test Setup for Optical Test (With Digital Operation)
At a data rate of 1 Mbps, in the presence of digital noise, with an electrical input
current of 5 µA (equivalent to an input sensitivity of -20 dBm, for a 0.5 A/W responsivity
detector) into a 50 Ω input resistance with a coupling capacitance of 10 nF in electrical
test, the BER was 10-9, with a power dissipation of approximately 50 mW. With a
detector integrated onto the receiver and optical signal applied, the receiver output
voltage signals (before the on-chip comparator) were measured. The comparator is a
clocked comparator synchronized by the external microprocessor operation clock The eye
diagrams (one for each of the parallel differential channels) are quite noisy; this is due to
112
pickup of digital noise in the interconnect from the receiver output to the scope. When the
scope leads are removed and the outputs fed to the on chip comparator a bit error rate of
less than 10-9 was measured. The fact that so much digital noise can be picked up on the
wires running from the chip to the scope is indicative of the severity of the digital noise
environment the receiver is operating in. The comparator output is digital so the eye
diagram is completely open
Figures from 4-13 to 4-14 show the measured optical receiver performance data
when digital circuitry is not in operation, when taking this output, the digital circuitry was
powered up but not fed the operation clock. The big rising and falling time shown in the
trace was caused by high impedance termination (1MΩ) to drive digital circuit input
since the output of amplifier was split into digital input node and measurement equipment
input.
Figure from 4-15 to 4-16 show receiver outputs when digital circuit is in
operation, that is, the case when digital part was powered and clock applied. As clearly
seen, the outputs of the receiver is corrupted due to the digital noise, however, this noise
was caused by pickup of digital noise in the interconnect from the receiver output to the
scope. When the scope leads are removed and the outputs fed to the on chip comparator a
bit error rate of less than 10-9 was measured.
The next two figures from 4-17 to 4-18 show the transient curve and eye-diagram
of receiver output along with comparator output, the top traces are receiver output and the
bottom traces are comparator output. The corrupted receiver output has been improved
113
dramatically. The comparator was clocked by 40 Mbps non-overlapping digital system
clock through on-chip multiplexer.
114
Figure 4-13: Measured output of receiver without operation of digital
circuitry: (the two lower traces are the differential receiver outputs)
115
Figure 4-14: Measured outputs eye-diagram of receiver when digital circuitry
is not in operation
116
Figure 4-15: Measured output of receiver with operation of digital circuitry:
(the two lower traces are the differential receiver outputs)
118
Figure 4-17: Measured outputs of receiver and comparator with operation of
digital circuitry: (Top trace: One of differential receiver output, Bottom trace:
On-chip comparator output)
119
Figure 4-18: Measured output Eye-diagrams of receiver and comparator with
operation of digital circuitry: (Top trace: One of differential receiver output,
Bottom trace: On-chip comparator output)
120
The primary purpose of this measurement is to take a numerical data of BER of
optical interface while digital microprocessor is working and performing a certain
function.
For a BER measurement of the analog optical interface circuitry, BER
Transmitter part was synchronized with the Digital waveform generator, the received
signal which was modulated by the PSR signal from BER transmitter is then fed into the
decision circuit and goes through shift register. One of shift register outputs is selected as
a reference for a BER receiver part. Since all the data stream after receiver circuit are
synchronized with a clock provided from the external clock generator, the noise which
can ruin analog interface can be generated at each clock rising moment.
As a final proof of the successful operation of the receiver in a noisy digital
environment, it was operated with the running digital SIMD circuitry, and outputs from
the digital circuitry were derived from the receiver input while running the
microprocessor clock at 40 MHz. To prove functionality of the system, digital input
optical signal to the photodetector was generated by the commercial laser source and fed
into the optical photo-detector through single-mode fiber. This signal was modulated by
Digital Waveform Generator to provide a certain calculation.
For a certain function of digital microprocessor, saving a serially received signal
after a decision circuit which is comparator, feeding in the data stream into the BUS logic
circuitry, adding up a certain number with this data, saving again the added number into
the ROM, and repeating this add-up calculation has been selected. The sampled output in
the following table shows the result when the microprocessor was manipulating simple
121
calculation (saving the input data and adding 4 iteratively). The output signal of the
digital circuitry appeared to be just a time-delayed version of the receiver input. Figure 4-
19 shows the digital outputs formatted in eye-diagram. Since this is digital data, the
output traces don’t show rising or falling time due to the function of digital pad driver.
Table 4-1: Sampled Output from Microprocessor
123
4.5 Summary
A fully differential CMOS analog optoelectronic receiver on the same die as a
digital CMOS microprocessor successfully designed, fabricated, and electrically and
optically tested. The receiver was designed to reduce the anticipated levels of the digital
noise in this harsh environment. The noise due to the digital processor operation in the
receiver output experimentally measured, and it was shown to be possible that the
receiver can successfully feed received data to the digital system to be processed without
being affected by the noise.
It appears that this type of fully differential receiver is sufficiently noise immune
to operate usefully in a mixed signal environment or on-chip TXRX system. This means
that single or multi chip optically connected smart photonic arrays of processors of this
type are feasible from a signal integrity standpoint. This type of optical connection
between processing array elements may play a key role in future generations of 3-D
integrated circuit interconnect.
124
CHAPTER V
TRANS-IMPEDANCE FEEDBACK TYPE OPTICAL
RECEIVER FRONT-END DESIGN
5.1 Introduction and Applications
As introduced in chapter 2, transimpedance feedback type receiver provides the
medium way between noise and bandwidth performance. Also, when using digital CMOS
process, generally, the feedback resistor is implemented by using NMOS [92,76,97]
(PMOS is also possible [91]). The merit of this implementation is that it can have
different resistance value if the gate voltage of the MOS is controllable from external
voltage source [55], and this leads to the possible solution in finding an optimal
resistance value between the one which can provide best sensitivity and the other one
which can do highest bandwidth since its value is dependent upon the output voltage
swing, it may cause instability as its phase difference is 180 degree out of feedback loop
delay. This effect requires careful design consideration.
125
For the development of high-speed receiver and transmitter system on a same die,
national semiconductor 0.35um technology process has been used (feature size of
minimum gate length is 0.4um). Because the chip contains transmitter side near to the
sensitive analog optical receiver, it may generate substrate noise which is similar to
digital switching noise and to have a better performance at high speed up to 1Gbps by
more stabilized bias currents into the bias voltages [93], the optical receiver of
differential or balanced design topology with high CMRR and high noise rejection has
been employed in this project.
Also, again in this project, for the optical interconnection, a hybrid MSM on-chip
photodetector of a huge size of 250um in each side has been integrated on top of the Si
die to have a better fiber alignment tolerance performance.
In this research, a wide-bandwidth optical receiver having a differential current-
mode input stage with transimpedance front-end has been designed. The amplifier has
been laid out in magic layout tool and extracted and simulated repeatedly. Final layout
has been converted into cadence layout with existing electric static protection circuitry
provided by National Semiconductor, then extracted and simulated again in cadence tool
environment to make sure circuit functionality. The chip has been fabricated using
national semiconductor 0.35um technology process (feature size 0.4um), and afterward, it
has been tested meeting the design goal which has been predetermined.
The design goal of receiver was determined as in Table 5-1 below.
126
Table 5-1: Design Goal of Transimpedance Feedback type Differential Amplifier
Specification Predetermined Goal of Design Note
Speed 800Mbps ~ 1Gbps
Power < 100mW
Input
Sensitivity
-18dBm
(-15uA input current)
Output > 200mV
Current Density
< 80uA/1um square meter
Meeting At least
SR-OC 12
Specification
When Driving 50 Ω Termination
127
5.2 Amplifier Design
In this project, a differential-input, current-mode, transimpedance amplifier
topology has been selected, because the optical receiver has to work at high speed with
stabilized bias and the controllable feedback resistors help optimization of input
sensitivity for a given bandwidth. As in the amplifier introduced in chapter 3, since the
noise contribution from the later stage is negligible compared to that from the first stage
[34], voltage-mode multiple amplifiers are used for post amplification to minimize the
power dissipation.
5.2.1 Front-end Current-to-Voltage Conversion Stage Design
First, the design of transimpedance stage begins with conventional configuration
employing basic OP-Amp, as shown in the figure below, it consists of an OP-Amp with
negative feedback resistor, when a current generated by the detector comes into the OP-
Amp input, it results in negative output voltage.
128
+
_
V_detector
Vout
R(feedback)
Figure 5-1: Conventional Negative Feedback Transimpedance Optical Front-end
Up to date, many researchers have developed many design techniques of current-
mode amplifier with transimpedance topology [46,47]. However, recently, most of
commercial transimpedance optical receivers or the ones under the research exploit
inverter instead of using complex OP-amp stage not to make speed limited by OP-Amp
bandwidth [91,92], this configuration has been most commonly used in single-ended
optical receivers,
129
R
Vdd
VssI_in
Vout=-R x I_in
Vout
Vin
Slope=x
Figure 5-2: Input inverter-feedback stage and Inverter characteristic
According to the figure above, input resistance is determined to be R/(x+1), since
the feedback resistor is implemented by MOSFET with gate, of which voltage is
controllable by externally applied voltage source, the factor freedom of control over the
input resistance is 2, and transimpedance gain is R because the gain of conversion is
dependent on the feedback resistance by resistance value R.
To convert this single-ended topology into differential or balanced topology,
identical extra single-ended amplifier sharing same current bias was added to side as
shown in the figure below. The basic differential amplifier with low gain by using low
output impedance has been used to prevent the effect of finite load impedance effect. As
in the amplifier introduced in chapter 3, the diode-connected NMOSFET were utilized to
increase bandwidth. Also, bias of differential amplifier and the two single ended current
to voltage conversion stage has been split to increase CMRR of this stage. In terms of
design method, CMRR is highly dependent on the fact how symmetric front-end receiver
130
is. The low input impedance optical receiver introduced in chapter 3 is not exactly
symmetrical since it has different two input resistance. However, since the symmetric
factor has been focused in this design, the two inputs have identical input resistance and it
results in almost 10 times high CMRR.
Figure 5-3: Differential Version of Trans-impedance Front-end
For the feedback resistors, small NMOSFET were employed. And for the bias
current source and steady voltage source of the inverter bottom voltage, current mirrors
were exploited. The final version of differential transimpedance optical receiver front-end
is shown below, as mentioned above, the feedback resistance for current to voltage
131
conversion stage is implemented using NMOSFET, when laying out this circuit, gate
voltage of the NMOSFET used as a resistance could have been split from the bias voltage
to make voltage control to be available.
Figure 5-4: Schematic of Front-end
The common-mode rejection ration (CMRR) of this front-end stage is critical
because it has an important role in reducing the noise arriving at both input nodes.
According to the HSPICE simulation result, CMRR of this stage is more than 20 up to
1GHz.
132
5.2.2 Post Voltage Amplifier and Pad Driver Stage Design
In developing post differential amplifier, originally, the common, ordinary
differential amplifier was employed, but it was bandwidth limited at around 700Mhz
even with the maximum current bias it can handle. This factor leaded to a newly
developed differential amplifier containing additional current providing components, the
idea of additional current is, that the original voltage gain is determined by two transistor
(input gm transistor and output load transistor), but to have a enough gain, input gm
transistor should be large or output load transistor should be small. But we have two main
restrictions here, if we increase the input gm transistor, the parasitic capacitance will be
increasing accordingly and this lowers bandwidth. In addition, if we are to decrease the
output load transistor size, the transistor size is limited by the current bias since there’s a
limitation that one transistor can afford. So, to have enough gain while keeping input
transistor size same, additional circuitry was needed to provide additional current to the
input gm transistor.
Mathematically, the gain is gm5/gm7 and gm is root-square proportional to device
size (aspect ratio) and Id current. So, 3 times bigger current is flowing into input gm
transistor than into the load transistor. This makes the gain to be about 3 since the size is
also 3 times bigger, too.
133
Figure 5-5: Differential Voltage Amplifier
To drive pads which have big capacitances and 50Ω terminated equipments such
as Oscilloscope and BER tester, output stage is following differential voltage amplifier.
However, the input transistor of the output stage is big, and there is a possibility of speed
bottleneck between the post differential amplifier and output stage. So, this stage is to
drive big output stage which drives the pad of big capacitance. Since the purpose of this
stage is not to have a gain, the gain of this buffer was set to be about 1.2.
134
Figure 5-6: Buffer to drive Output Stage
To drive 50Ω output termination and be capable of producing at least 200mV
output swing, big output driving stage is required. The topology of the circuits is identical
to the differential amplifier stage but has bigger size of transistors to handle the bigger
current which will flow back and forth toward pads.
135
Figure 5-7: 50 Ω output Driving Circuit
Since there is always dark current at the photodetector and offsets which are
inherited from circuit, to compensate this effect and for easiness of measurement, the
following offset stage was employed between front-end stage and post voltage-mode
amplification stage.
136
+
+
+
+
-
-
-
-
In +
In -
O u t-
O u t+
V o ffset1
V o ffset2
O F F S E T S tag e
Figure 5-8: Differential Offset Stage
Regarding power consumption, the following numbers in the table calculated
using HSPICE simulation. According to the simulation result, without using this 50-Ω
Output driving stage, the power consumption of post stages reduces to approximately
20mW. Our final goal of power consumption is less than 30mW. So, it is possible to
achieve this goal when there’s no need to drive 50-Ω output which is a real case of
application.
137
Table 5-2: Power Consumption of Transimpedance Optical Amplifier
Current in mA Power in milliwatt
Front-end Power Consumption 3.355 11.0714
Output stage Power Consumption 25.8954 85.4548
Total Power Consumption 96.52
138
5.3 Simulation
5.3.1 Transient Simulation at different speeds and different input capacitance
The HSPICE simulation on the overall amplifier has been performed using 0.4um,
BSIM level 4 model parameters (See Appendix II) provided by national semiconductor.
The figure below shows the simulation results.
The figures from 5-9 to 5-10 are transient response of optical receiver at 800Mbps
speed, the simulations were performed at different optical power (2uA, 4uA, 8uA, and
16uA) and with different input capacitances (0.1pF, 0.5pF, and 1.0pF), the other figures
are shown in Appendix III. Also the figures form 5-11 to 5-12 represent transient
simulation results performed at 1Gbps with same environment used at 800Mbps
simulation. In all simulations, the top trace represents the transient output to the input
which is depicted in the bottom trace, this trace was shown to prove that there wasn’t any
missing bit which cannot be revealed in simple eye-diagram. The middle trace is a eye-
diagram of outputs to show how well the optical receiver comply with the incoming bit
stream.
As shown in the simulation results, the input current magnitude, which means
input optical power, and input capacitance, which is primarily determined by
photodetector size, are important factors in design of optical receiver.
139
Figure 5-9: Transient Response to 16µA Input Current with 0.1pF input Capacitance at 800Mbps
Figure 5-10: Transient Response to 16µA Input Current with 1.0pF input Capacitance at 800Mbps
140
Figure 5-11: Transient Response to 16µA Input Current with 0.1pF input Capacitance at 1Gbps
Figure 5-12 Transient Response to 16µA Input Current with 1.0pF input Capacitance at 1Gbps
141
5.3.2. AC Analysis and Noise Analysis
The following 4 figures illustrate AC sweep simulation result of front-end
amplifier along with noise analysis result with different input capacitances (zero, 0.1pF,
0.5pF, and 1.0pF). From top to bottom trace, the traces show output noise, input noise,
AC gain of front-end and HSPICE calculated input referred noise.
As in the chapter 3, to calculate the input referred noise, the following equation
has been used.
( )GainfrequencyLow
noiseoutputsmrNoise
__
_.)..(
2∫= (5.1)
As shown in the simulation results, the input capacitance not only reduces the
bandwidth of receiver front-end, but also increases input noise current which means that
the bigger input noise, the bigger the sensitivity is.
The low frequency transimpedance gain of front-end was 1280 and the following
table shows the 3dB bandwidth of front-end.
Because this transimpedance front-end stage has bigger input resistance compared
with the low input impedance optical receiver introduced in chapter 3, a small increase of
input capacitance value had very detrimental effect on the bandwidth of front-end stage.
In other words, in the case of low input impedance receiver in chapter 3, the 3dB
bandwidth variation in accordance with input capacitance variation from zero to 1.0pF
142
was 852 / 572 = 1.4895. However, in this case of transimpedance optical receiver, the
ratio of variation to same input capacitance value increase was 3070 / 476 = 6.4495.
If it is assumed that the bandwidth of front-end receiver is totally determined by
RC time constant of input stage, the resistance ratio of input capacitances is 6.4495 /
1.4895 = 4.33. i.e., the input resistance value of this transimpedance optical receiver
front-end is 4.33 times bigger than the one of low input impedance optical receiver.
The worst-case input referred noise at 1.0pF input capacitance was about 615nA.
With this noise, the minimum sensitivity to have a 10-10 BER performance is 615 X 6.35
= 3.9µA.
Table 5-3: 3dB Frequency of front-end Receiver
Input
Capacitance
Zero Input
Capacitance
0.1pF Input
Capacitance
0.5pF Input
Capacitance
1.0pF Input
Capacitance
3dB BW 3.07 GHz 2.16 GHz 881 MHz 476 MHz
143
Figure 5-13: AC Sweep Simulation and Noise Analysis with Zero Input Capacitance
Figure 5-14: AC Sweep Simulation and Noise Analysis with 0.1pF Input Capacitance
144
Figure 5-15: AC Sweep Simulation and Noise Analysis with 0.5pF Input Capacitance
Figure 5-16: AC Sweep Simulation and Noise Analysis with 1.0pF Input Capacitance
145
The following two figures from 5-36 to 5-37 show the simulation result of
CMRR, the top trace represents the differential-mode gain of front-end (whole stage in
the second figure) and the middle one does common-mode gain, and the bottom one
shows the CMRR of front-end (whole stage in the second figure)
Because the front-end is more symmetric than the one in the low input impedance
optical receiver introduced in chapter 3, CMRR of this stage is bigger than 10 up to
1GHz and this is almost 6 times bigger. The bigger CMRR of this stage results in
immunity to substrate noise if any.
Considering whole stage, since it has employed many differential voltage mode
amplifiers, which have big CMRR, in post amplification stage, the minimum CMRR was
30 along the frequency sweep.
147
5.3.3 Line Impedance effect simulation
This simulation is to figure out the value of capacitance required to suppress the
effect of line impedance to make sure that the circuit works in testing environment with
real value of parasitics such as line inductive impedance and pad and board capacitive
impedance. First of all, the line impedance includes 1) package bonding wire impedance,
2) board line impedance and 3) bias wire impedance. The model values of these
impedance were approximately estimated or provided by manufacturing company. And
secondly, the capacitive impedance includes on-chip metal capacitance, pad and board
bonding pad capacitance. Each simulation includes output line impedance effect pictured
in the figure below.
Bias line has parasitic impedance in itself. By including the circuit above in
simulation, simulation can be more realistic. Wire inductance represents the inductance
from the source to the board, which is 185nH, (this value came was provided by product
company), and the board inductance and bonding wire inductance were all from
estimation. According to the simulation results, the bigger the decoupling capacitance,
the smaller ripple was caused.
148
Figure 5-19: Line Impedance Circuit
Also, in the simulation, 50 Ohm termination of equipment which will be used in
test environment such as oscilloscope and BER tester was included as shown in the
following figure.
Figure 5-20: Output line impedance with 50Ohm Termination
149
Figure 5-21: Line Impedance effect simulation I
The figure above 5-21 shows the effect of line impedance, when it is assumed that
biasing line has an inductance of 10nH, and there’s no coupling capacitance attached to
the circuit at all, the output affected by this effect is shown in transient analysis (middle)
and eye-diagram (bottom). As shown in the simulation result, eye is completely closed
due to the effect of parasitic inductance. This shows the importance of coupling
capacitance. Even though the circuit may work in simulation without consideration of
bias line parasitics, it won’t work in real world, which means the real test environment
where the parasitics exist. To prevent this unexpected insistency, it is necessary to
150
consider, and predict the parasitics that can come into real test environment and check the
functionality of amplifier.
Figure 5-22: Line impedance effect simulation II
The figure above shows the result with 100nH line impedance and 10nF
decoupling capacitance. Even with this small capacitance, the output has improved a lot.
Temperature analysis
Basically, amplifier gets slower as temperature goes up due to the mobility
variation. The next simulation is to make sure that receiver works at higher temperature
well enough to generate high BER. As shown in the figure below, output seems a little
151
slower at 100oC temperature than 27oC room temperature, But still provides opened eye-
diagram with 200mV output swing when driving 50Ω termination.
Figure 5-23: Temperature simulation at 27oC (top 2 figures) and 100oC (bottom 2 figures)
152
5.4 Layout
As in the optical receiver design in chapter 3, the method to split the power supply
rails into two parts for front-end and post voltage amplification stage has been employed
in the design of this transimpedance optical receiver design. The first part of power
supply serves only front-end and the latter one does for both of post voltage amplification
stage and output driving stage and the thin and long left-to-right geometry of layout was
used to maximize the separation of signal from big output swing part to small signal input
part. Also, as shown in the following figure, to prevent unwanted power supply ripple as
signal goes through the circuitry, the decoupling capacitance using metal1, metal2,
metal3, and metal4 was used, from the previous experience, this on-chip metal
capacitance can generate a few tenth of pico farad of capacitance and helps stabilizing
bias voltage.
Also, the design was focused on the scalability of design for easiness of future
development and application of system level implementation. For scalability, the circuit
design doesn’t contain any passive components such as resistor and capacitor [53,54].
The same receiver was fabricated using 0.25µm CMOS technology, but the test result is
not available at the time of writing.
153
Front-end Offset Stage Buffer Stage Output Driving Stage
PostAmp Decoupling Capacitor Frontend Decoupling Capacitor
Figure 5-24: Layout of Transimpedance Optical Receiver
154
Transimpedance Differential Amplfier
D/A Converter
Transmitter
Detector Integration Area
Figure 5-25: Cadence Layout of Whole Chip Submitted to Fabrication
The figure above shows the layout of the chip submitted to MOSIS for fabrication
performed in layplus of CADENCE tool. The upper side is receiver part composed of
front-end, post voltage amplification stage and output driving stage. The black area in the
155
middle of chip is for photodetector which was integrated using ELO technology after
fabrication. The bottom side is transmitter part and the circuitry located in the side is
DAC for the autobias of receiver and transmitter respectively.
156
5.5 Measurements
Measurements were performed in 2 phases, first, BER measurement was
performed observing time-domain transient output signal and eye-diagram at different
speeds and at different optical power.
5.5.1. Test Setup
The modulation method employed in the test of optical receiver in chapter 3
couldn’t be used for speed limitation reason. The maximum speed of the commercial
laser used in the previous test was 622Mbps and this could prevent the test of higher
speed range above 622Mbps. For the modulation of optical signal in this test, another
simple method of direct modulation of intensity of the output of a laser with Mach-
Zehnder modulator has been employed as seen in the following figure. The bias and
modulating signal were provided by Hewlett Packard Error Performance Analyzer.
158
Figure 5-27: Photo Picture of Chip
The photo picture of the chip with bonding wire is shown in the figure above,
after chip fabrication, a photodetector of 250µm size was integrated on top of the chip.
Optical receiver is shown in upper part along with integrated MSM photodetector right
under it. The white area under the photodetector is a metal on-chip capacitance to
decouple unwanted bias ripple through the biases.
159
Figure 5-28: Test Board with a Bonded Chip
The figure above shows test board. To get around the speed limitation of
commercial package, the chip was bonded right on top of the test board. The board was
previously tested and experimentally showed no apparent distortion up to 1.5Gbps. Also,
from the previous experimental results, the decoupling capacitance should be close to the
chip because, otherwise, it could result in bigger unwanted parasitic inductance caused by
the line between the chip and the point where chip capacitance was located and prevent
stable bias of the circuitry.
160
The figure 5-29 shows the test setup diagram, CW light source was generated by a
commercial laser source and the light signal was modulated using Mach-Zehnder
modulator, the modulating AC signal and bias DC was provided by HP70843A Error
Performance Analyzer which is synchronized by the clock from external clock source,
and the clock was shared with HP70843A RX. Not to have speed bottleneck and signal
dispersion caused by fiber bandwidth limitation, single-mode optical fiber was used.
162
5.5.2. BER Measurement
The figure from 5-30 to 5-35 show measurement results at different speeds
(622Mbps, 900Mbps and 1Gbps). The figures 5-30, 32 and 34 are transient output
from the receiver (middle trace) and comparator output from the BER tester (bottom
trace). And the figures 5-31, 33 and 35 show eye-diagram at each speed operation. As
shown in the first two figures, the transimpedance optical amplifier could function
well enough to provide 10-10 BER with clearly opened eye-diagram. However, as
speed goes higher, the eye starts closing as shown in the next two figures.
Because the optical receiver can provide different BER at different biasing
condition, the test followed best to worst procedure, first, amplifier bias was set to
generate best performance at a certain high enough speed, and then BER was taken as
speed was lowered down.
Even though some researchers have reported the relationship between shape and
size of eye and BER performance. It was possible to get a good enough BER even
with very clear but small eye opening. From the experimental result, the BER was
dependent on the opening size of clear area rather than the shape of it.
166
This figure 5-36 shows BER measurement result starting from 800Mbps best
performance. To get a certain BER, 10 times more bits were sent to make sure the
functionality of circuit operation, for example to have 1 x 10-11 BER performance, at least
1012 bits were sent to the amplifier inputs. In the figure above, the 10-11 is not a noise
floor, 10-11 is a minimum BER that could be achieved due to the easiness and time
limitation of test (for example to get 10-12 BER, it was required to send 1013 bits at
500Mbps and it takes 2 x 104 seconds which is 5.555 hours)
Figure 5-36: BER Test Result I
167
This figure is another BER measurement diagram which was starting from
900Mbps best performance. At 900Mbps, the optical receiver showed not worse than 10-
10 BER performance. The optical power incident on the photodetector is converted to
power from used voltage unit and provided in Table 3-2.
10-12
10-10
10-8
10-6
10-4
0.01
1
0 0.5 1 1.5 2 2.5
(See Optical Power Conversion Table)
1G980M970M950M930M920M
900M
850M 800M
BE
R
Optical Power
Figure 5-37: BER Test Result II
168
5.5.3. ISI Effect Measurement
For the test of ISI effect onto the BER performance of receiver, different word
coding has been employed in this test. When there is same number of ones and zeros in a
8-bit word, receiver provided best performance at 600Mbps. However, as the number of
bit difference increased, it showed worse BER performance.
10-12
10-10
10-8
10-6
10-4
0.01
1
0 1 2 3 4 5 6 7 8
(See Optical Power Conversion Table)
0.50.81.01.52.0
BE
R
Number of One In 8 bit Word ( Worst Case Taken )
Figure 5-38: ISI Effect Test Result of Transimpedance Optical Amplifier
169
In the figure above, the x-axis represents the number of 1’s in 8-bit word. Since
there can be multiple cases for a one situation, for example, 6 bits of ones in 8-bit word
can be either 00000011 or 00001010, always worst case 00001010 was taken for the
measurement. As shown in the measurement result graph, it has been proved that the
number of bit difference along with higher optical power worsens BER performance due
to the effect of input capacitance charging and discharging time constant.
170
CHAPTER VI
CONCLUSIONS
AND
PROPOSED FUTURE RESEARCH
In this chapter, conclusions regarding the accomplished work and contribution of
this research in development of optical receiver using standard digital CMOS process and
integrated photodetector using ELO technology are discussed. Also, possible future
research direction is proposed.
6.1 Contribution
The quasi-monolithic optical receivers (an OEIC photodetector and an amplifier)
working up to 622Mbps and 900Mbps speeds with 10-11 BER performance were
developed by using available standard digital CMOS technology (0.5µm and 0.35µm,
171
feature sizes are 0.6µm and 0.4µm for minimum transistor gate length, respectively).
They were first digital CMOS receiver amplifiers to date running at these speeds with a
big photodetector size of 250µm x 250µm for high alignment tolerance by using both of
CMOS and ELO technology. The following table compares the achievement of this
research with other recently developed optical receiver performance.
Table 6-1: The performance comparison of the receivers in
this research with other recently published and developed
optical receivers
Ref. Process L*
[µm] Speed [Mbps]
Photo-detector
Power Diss. [mW]
Sensitivity
by BER Remarks
This work I
Digital CMOS 0.5 622
I-MSM (Hybrid)
120 -12.2 dBm@10-11 0.4 ~ 0.5pF detector Capacitance
This work II
Digital CMOS 0.35 900
I-MSM (Hybrid)
35 -12.2 dBm@10-11 0.4 ~ 0.5pF detector Capacitance
[23] Digital
CMOS 0.8 240 P-i-N
(ext.) N/A N/A
(Scope data only)
-No BER
-1 µA input signal
[32] Digital CMOS 0.8 150 P-i-N
(ext.) 27 N/A
-870 nm wavelength
[91] Digital CMOS 0.35 1000 P-i-N Off chip
driver -6.2 dBm @10-9 850nm wavelength
[76] Digital CMOS 0.8 800 P-i-N
(Integ.) 10(Font
-end only)
-8.5dBm@10-9 50fF Photodiode Capacitance.
[18] Analog CMOS 1.75 50 P-i-N
(Ext.) 500 N/A
(Eye diagram only)
-Twin-tub,double-poly.
-48 nArms @10-9 BER
172
[19] Analog CMOS 1.2 60 P-i-N
(ext.) 900 N/A
(Eye diagram only)
-Double poly CMOS.
-18 mVp-p @215-1 PRBS
[20] Analog CMOS 0.7 266 P-i-N
(ext.) 800 N/A -Double poly.
[92] Analog CMOS 0.8 1000 P-i-N
(ext.) 155 -24dBm@10-12 320fF Photodiode Cap.
[94] Analog CMOS 0.15 2400 N/A 284mW N/A Didn’t mention optical
Specification
[97] Analog CMOS 0.7 1000 N/A 100 N/A Didn’t mention optical
Specification
[22] BiCMOS 0.45 531, 266
Si P-i-N 66 -14.2 dBm @10-9,
-15.9 dBm @10-9 -Fully Monolithic.
[21] Analog
NMOS 0.45 850
InGaAs P-i-N (ext.)
300 -25.4 dBm -Fineline NMOS (AT&T).
In this research, two basic schemes of design method have been employed and
compared. The idea and potential usefulness of both designs can be employed in
improvement of optical receiver system in the future research.
Also, the usefulness of differential topology of optical receiver in mixed-signal
system has been proved. The functioning chip with optical interface along with running
digital microprocessor next to the analog circuitry on a same die was the world widely
first one.
Besides the development of quasi-monolithic receiver, the characterization of
receiver has been made in this field; first, the BER performance measurement at specified
sensitivity was done. Secondly, ISI noise effect was measured in terms of BER
performance. Most of recent researches provided only scope captured data or eye-
173
diagram without characterized BER data, not to mention the primary noise source such as
ISI effect analysis at high speed.
Thus, the main two design topologies with characterized data can lead to a one-
chip optical receiver solution supporting full function of the SONET standard simply by
incorporating digital circuitry on the same chip.
174
6.2 Future Research
Since this research covered only two schemes of basic topologies for the design of
optical receiver front-end, one left topology, which is a high-input impedance open-loop
version, can be tried in the future research [103]. This approach substantially reduces the
effect of the thermal noise of the load resistor, resulting in improved sensitivity [77]. The
high-impedance receiver is based on a technique that has been successfully used with
other capacitive current sources in implementing low-noise front-end design [115].
The basic design principle is to load the current-source (photodetector) with as
large impedance as possible [3]. This tends to maximize the amount of voltage developed
at the input of the amplifier, the idea is that since the voltage is maximized, the effects of
any amplifier noise source will be reduced. Ultimately the ability to realize a high
impedance is limited by the capacitance present in the circuit. In fact, the receiver is
usually constructed so that the input impedance is dominated by the total capacitance at
the amplifier’s input node. Since the voltage across a capacitor is the integral of the
current through the capacitor, the amplifier’s input voltage will be the integral of the
photocurrent. This fact lends the high-impedance front-end its alternative name, the
integrating front-end. Since the response is that of an integrator, which is a single-pole
roll-off with frequency, we must equalize the response with a differentiator if we are to
obtain a flat receiver passband up to a certain frequency bandwidth.
175
As mentioned in chapter 2, the low-noise can be obtained by making the load
resistor as large as possible. A high-impedance receiver front-end is illustrated in the
following Figure 6-1. A large value load resistor is still usually included. It is beneficial
in that it can provide a DC current path for the photodiode and it allows us to control and
stabilize the low-frequency pole location ωP so that we can accurately equalize the
response.
Low-noise is the high-impedance front-end’s principal benefit. Limited dynamic
range and relatively narrow bandwidth are generally considered to be its principal
drawbacks. In spite of this limitation, high-impedance front-ends have been routinely
used in many high sensitivity applications and are commercially available in the form of
p-i-n photoreceiver. Thus, in future research, this type of optical receiver is worth of try.
In fact, we have tried to develop an equalization stage to improve frequency response of
the transimpedance receiver that was introduced in chapter 5, but haven’t had satisfactory
result until the time of writing.
In addition to the optical receiver developed in this research, many other function
blocks are necessary, for example, 1) a high-speed, high-resolution comparator is
required to convert amplified analog signal into digitized signal that can be processed in
the following circuit, 2) a clock recovery circuit to synchronize the system 3) a
demultiplexer to deserialize the high-speed incoming data stream into lower speed
parallel signals.
176
Also, the driver circuitry which can be compatible with the receivers in this
research is needed to implement a bona fide transceiver system.
178
6.3 Conclusions
Two optical receiver meeting SONET OC-9 and OC-12 standard were designed
and tested. The amplifiers were fabricated using different standard digital CMOS process
(0.5µm, 0.35µm minimum feature gate length) through MOSIS and National
Semiconductor respectively. Since they used different receiver design topologies, the
merits and demerits of each design topology have been verified along with BER
measurement result and ISI noise effect analysis (In chapter 2 and chapter 5).
Both of designs were scalable designs since they didn’t use any passive
components in the designs [100]. So, as the minimum geometry size of a transistor
shrinks, the receiver amplifier performance improvement is expected in accordance with
reduced feature size of transistors.
These amplifiers have been integrated with thin film photodetectors using
Epitaxial Lift-Off (ELO) technology to achieve a quasi-monolithic optical receiver front-
end. Also, since the receiver have used standard digital CMOS process, which is another
advantage of differential topology, that it can easily incorporate digital circuitry on a
same die for mixed signal processing, have been verified (In chapter 4).
179
APPENDIX I
Brief SONET Specifications
Appendix 1.1 Three broad application categories in SONET physical layer
Type System Loss Budget Distance Remarks
Long Distance (LR) 10 dB – 20 dB > 40 km or 24 mile 500 µW or –3 dBm
MLM/SLM Laser
Intermediate Distance (IR) 0 dB – 12 dB > 15 km or 9.3 mile
50 µW or –13 dBm
SLM or MLM Laser
Short Distance (SR) 0 dB – 7 dB > 2 km or 1.2 mile LED or Low-Power MLM Laser
MLM: Multi Longitudinal Mode
SLM: Single Longitudinal Mode
LR, IR, SR: Nominal 1310 nm-source on dispersion-unshifted single-mode fiber.
LR, IR: Nominal 1520 nm-source on both dispersion-unshifted and dispersion-shifted single-mode fiber
180
Appendix 1.2. The SONET Specification for Maximum and Minimum Power Requirements at Different Speeds
STS-1/OC-1 STS-3/OC-3 STS-9/OC-9 STS-12/OC-12
Data Rate 51.84 Mb/s 155.52 Mb/s 466.56 Mb/s 622.08 Mb/s
PTmax/PRmax 0/-10 0/-10 1/-10 +2/-8
PTmin/PRmin -5/-34 -5/-34 -4/-29 -3/-28 LR
Laser Type MLM/SLM MLM/SLM MLM/SLM MLM/SLM
PTmax/PRmax -8/-8 -8/-8 -8/-8 -8/-8
PTmin/PRmin -15/-28 -15/-28 -15/-28 -15/-28 IR
Laser Type MLM/SLM MLM/SLM MLM/SLM MLM/SLM
PTmax/PRmax -14/-14 -8/-8 -8/-8 -8/-8
PTmin/PRmin -23/-31 -15/-23 -15/-23 -15/-23 SR
Laser Type MLM MLM MLM MLM
*Remark: The Unit of Power Level is dBm
181
STS-18/OC-18 STS-24/OC-24 STS-48/OC-48
Data Rate 933Mb/s 1244 Mb/s 2488.32 Mb/s
PTmax/PRmax +2/-8 0/-10 0/-10
PTmin/PRmin -3/-28 -5/-26 -5/-26 LR
Laser Type MLM/SLM MLM/SLM SLM
PTmax/PRmax 0/0 0/0 0/0
PTmin/PRmin -5/-18 -5/-18 -5/-18 IR
Laser Type MLM/SLM SLM SLM
PTmax/PRmax -8/-8 -5/-5 -3/-3
PTmin/PRmin -15/-23 -12/-20 -10/-18 SR
Laser Type MLM MLM MLM
*Remark: The Unit of Power Level is dBm
182
Appendix II
HSPICE INPUT CONTROL FILES AND BSIM MODEL
PARAMETERS USED IN SIMULATION
Appendix 2.1. BSIM Model Parameter Used in Development of Low-Input
Impedance Optical Receiver
Hewlett Packard-AMOS 14TB Parameters VENDOR: HP-NID TECHNOLOGY: SCN05H: FEATURE SIZE: 0.5 microns
Transistor Parameters W/L N-Channel P-Channel Units
Minimum Vth 0.9/0.6 0.76 -0.83 Volts
Short 20/0.6
Idss 358 -184 UA/um
Vth 0.67 -0.84 Volts
Vpt 10.0 -9.9 Volts
Wide 20/0.6
183
Ids0 0.6 -0.1 p/um
Large 50/50
Vth 0.71 -0.86 Volts
Vjbkd 11.6 -9.9 Volts
Ijlk -25.3 -8.8 PA
Gamma 0.68 0.47 V0.5
K’ (U0*COX/2) 72.8 -22.3 UA/V2
Process N+Active P+Active Poly MTL1 MTL2 MTL3 PLY+BLK Units
Sheet Resistance
2.7 2.3 2.4 0.07 0.07 0.05 114.5 Ω/sq
Width Variation
-0.42 -0.30 -0.04 0.21 0.08 -0.32 microns
Contact Resistance
2.3 2.0 1.9 0.5 0.5 Ω
Gate Oxide Thickness
97 angstrong
******************************************************************************** PROCESS PARAMETERS N_WELL UNITS Sheet Resistance 725 ohms/sq ******************************************************************************** • CIRCUIT PARAMETERS UNITS Inverters K Vinv 1.0 1.35 Volts Vinv 1.5 1.50 Volts Vol (100 uA) 2.0 0.27 Volts Voh (100 uA) 2.0 2.98 Volts Vinv 2.0 1.60 Volts Gain 2.0 -17.92 ******************************************************************************** Ring Oscillator Freq. DIV256 (31-stage,3.3V) 125.17 MHz Ring Oscillator Power DIV256 (31-stage,3.3V) 0.20 uW/MHz/g ******************************************************************************** SPICE BSIM3 VERSION 3.1 PARAMETERS SPICE 3f5 Level 8, Star-HSPICE Level 49, UTMOST Level 8 Temperature parameters=Default ******************************************************************************** .MODEL CMOSN NMOS ( LEVEL = 49 +VERSION = 3.1 TNOM = 27 TOX = 9.7E-9
184
+XJ = 1.5E-7 NCH = 1.7E17 VTH0 = 0.6627089 +K1 = 0.8204775 K2 = -0.0357452 K3 = 30.8029268 +K3B = 0.2357821 W0 = 3.97005E-6 NLX = 5.311185E-9 +DVT0W = 0 DVT1W = 0 DVT2W = 0 +DVT0 = 10.3699188 DVT1 = 0.892779 DVT2 = -0.1135401 +U0 = 416.1575558 UA = 5.068355E-12 UB = 1.428896E-18 +UC = 9.8303E-12 VSAT = 1.40837E5 A0 = 0.8718292 +AGS = 0.1886642 B0 = 1.70183E-6 B1 = 5E-6 +KETA = -3.402474E-3 A1 = 0 A2 = 1 +RDSW = 1.306118E3 PRWG = 0.0725795 PRWB = 0.101557 +WR = 1 WINT = 2.373491E-7 LINT = 7.243473E-8 +XL = -1E-7 XW = 0 DWG = -4.40159E-9 +DWB = 1.367703E-8 VOFF = -0.0538757 NFACTOR = 0.8006889 +CIT = 0 CDSC = 1E-3 CDSCD = 1E-3 +CDSCB = 2.979369E-5 ETA0 = 1.523547E-4 ETAB = -0.0364279 +DSUB = 0.5950961 PCLM = 0.4123813 PDIBLC1 = 0.2834078 +PDIBLC2 = 6.483013E-3 PDIBLCB = 0.01 DROUT = 0.7652431 +PSCBE1 = 1.698449E10 PSCBE2 = 5.545971E-9 PVAG = 0.1081861 +DELTA = 0.01 MOBMOD = 1 PRT = 0 +UTE = -1.5 KT1 = -0.11 KT1L = 0 +KT2 = 0.022 UA1 = 4.31E-9 UB1 = -7.61E-18 +UC1 = -5.6E-11 AT = 3.3E4 WL = 0 +WLN = 1 WW = -1.245E-15 WWN = 1.1025 +WWL = 0 LL = 0 LLN = 1 +LW = 0 LWN = 1 LWL = 0 +CAPMOD = 2 XPART = 0.4 CGDO = 2.38E-10 +CGSO = 2.38E-10 CGBO = 0 CJ = 5.165425E-4 +PB = 0.99 MJ = 0.6746368 CJSW = 3.603845E-10 +PBSW = 0.99 MJSW = 0.1 PVTH0 = 9.947253E-3 +PRDSW = -69.9728391 PK2 = 0.0120098 WKETA = -0.0105598 +LKETA = -1.46004E-3 PAGS = 0.1068 ) * ******************************************************************************** .MODEL CMOSP PMOS ( LEVEL = 49 +VERSION = 3.1 TNOM = 27 TOX = 9.7E-9 +XJ = 1.5E-7 NCH = 1.7E17 VTH0 = -0.833195 +K1 = 0.386829 K2 = 0.022582 K3 = 29.3277382 +K3B = -0.86387 W0 = 2.854858E-6 NLX = 1.044671E-7 +DVT0W = 0 DVT1W = 0 DVT2W = 0 +DVT0 = 5.2354155 DVT1 = 0.6121054 DVT2 = -0.0381627 +U0 = 173.9742045 UA = 1.01198E-9 UB = 1.182595E-18 +UC = -6.05246E-11 VSAT = 1.428327E5 A0 = 0.8959358 +AGS = 0.2401793 B0 = 5.016138E-6 B1 = 5E-6 +KETA = 1.283908E-3 A1 = 0 A2 = 1 +RDSW = 2.797697E3 PRWG = 1.66935E-3 PRWB = -6.267217E-3 +WR = 1 WINT = 2.100239E-7 LINT = 3.025085E-8 +XL = -1E-7 XW = 0 DWG = -1.387209E-8 +DWB = 8.399122E-9 VOFF = -0.0547874 NFACTOR = 0 +CIT = 0 CDSC = 2.318403E-4 CDSCD = 2.363737E-4 +CDSCB = 1E-3 ETA0 = 0.3611232 ETAB = 4.822174E-3 +DSUB = 0.7287356 PCLM = 6.5248377 PDIBLC1 = -0.024947 +PDIBLC2 = 0.0792883 PDIBLCB = -0.0999889 DROUT = 6.913356E-3 +PSCBE1 = 6.068042E9 PSCBE2 = 3.911355E-9 PVAG = 13.9932286 +DELTA = 0.01 MOBMOD = 1 PRT = 0 +UTE = -1.5 KT1 = -0.11 KT1L = 0 +KT2 = 0.022 UA1 = 4.31E-9 UB1 = -7.61E-18
185
+UC1 = -5.6E-11 AT = 3.3E4 WL = 0 +WLN = 1 WW = 0 WWN = 1 +WWL = 0 LL = 0 LLN = 1 +LW = 0 LWN = 1 LWL = 0 +CAPMOD = 2 XPART = 0.4 CGDO = 2.53E-10 +CGSO = 2.53E-10 CGBO = 0 CJ = 9.474733E-4 +PB = 0.9307577 MJ = 0.4755936 CJSW = 1.447938E-10 +PBSW = 0.99 MJSW = 0.1093835 PVTH0 = 5.37484E-3 +PRDSW = 77.9797784 PK2 = 2.745602E-3 WKETA = 3.887713E-3 +LKETA = 1.156908E-3 PAGS = 0.10532 ) * ********************************************************************************
186
Appendix 2.2 SPICE Netlist and Input Control File
Appendix 2.2.1. Prc Btc Low Input Impedance Optical Receiver Netlist
****** top level cell is ./Prc_Diff_Sim.ext M1 1 2 2 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=14.9U M2 1 2 2 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=14.9U M3 1 2 2 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=14.9U M4 1 2 2 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=14.9U M5 1 2 2 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=14.9U M6 1 2 2 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=14.9U M7 1 2 2 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=14.9U M8 1 2 2 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=14.9U M9 1 2 2 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=14.9U M10 1 2 2 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=14.9U M11 2 4 4 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=14.9U AS=0.0P PS=14.9U M12 2 4 4 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=14.9U AS=0.0P PS=14.9U M13 2 4 4 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=14.9U AS=0.0P PS=14.9U M14 2 4 4 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=14.9U AS=0.0P PS=14.9U M15 2 4 4 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=14.9U AS=0.0P PS=14.9U M16 2 4 4 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=14.9U AS=0.0P PS=14.9U M17 2 4 4 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=14.9U AS=0.0P PS=14.9U M18 2 4 4 3 NMOS W=1.4U L=0.7U
+ AD=0.0P PD=14.9U AS=0.0P PS=14.9U M19 2 4 4 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=14.9U AS=0.0P PS=14.9U M20 2 4 4 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=14.9U AS=0.0P PS=14.9U M21 5 5 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.0U AS=0.0P PS=7.4U M22 5 5 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.0U AS=0.0P PS=7.4U M23 5 5 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.0U AS=0.0P PS=7.4U M24 5 5 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.0U AS=0.0P PS=7.4U M25 5 5 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.0U AS=0.0P PS=7.4U M26 5 5 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.0U AS=0.0P PS=7.4U M27 5 5 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.0U AS=0.0P PS=7.4U M28 5 5 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.0U AS=0.0P PS=7.4U M29 6 5 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.0U AS=0.0P PS=7.4U M30 6 5 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.0U AS=0.0P PS=7.4U M31 6 5 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.0U AS=0.0P PS=7.4U M32 6 5 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.0U AS=0.0P PS=7.4U M33 6 5 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.0U AS=0.0P PS=7.4U M34 6 5 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.0U AS=0.0P PS=7.4U M35 6 5 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.0U AS=0.0P PS=7.4U M36 6 5 1 3 NMOS W=1.4U L=0.7U
187
+ AD=0.0P PD=7.0U AS=0.0P PS=7.4U M37 1 5 5 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=7.0U M38 1 5 5 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=7.0U M39 1 5 5 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=7.0U M40 1 5 5 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=7.0U M41 1 5 5 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=7.0U M42 1 5 5 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=7.0U M43 1 5 5 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=7.0U M44 1 5 5 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=7.0U M45 1 5 6 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=7.0U M46 1 5 6 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=7.0U M47 1 5 6 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=7.0U M48 1 5 6 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=7.0U M49 1 5 6 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=7.0U M50 1 5 6 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=7.0U M51 1 5 6 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=7.0U M52 1 5 6 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=7.0U M53 5 5 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.0U AS=0.0P PS=7.4U M54 5 5 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.0U AS=0.0P PS=7.4U M55 5 5 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.0U AS=0.0P PS=7.4U M56 5 5 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.0U AS=0.0P PS=7.4U M57 5 5 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.0U AS=0.0P PS=7.4U M58 5 5 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.0U AS=0.0P PS=7.4U M59 5 5 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.0U AS=0.0P PS=7.4U M60 5 5 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.0U AS=0.0P PS=7.4U M61 6 5 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.0U AS=0.0P PS=7.4U M62 6 5 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.0U AS=0.0P PS=7.4U M63 6 5 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.0U AS=0.0P PS=7.4U M64 6 5 1 3 NMOS W=1.4U L=0.7U
+ AD=0.0P PD=7.0U AS=0.0P PS=7.4U M65 6 5 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.0U AS=0.0P PS=7.4U M66 6 5 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.0U AS=0.0P PS=7.4U M67 6 5 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.0U AS=0.0P PS=7.4U M68 6 5 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.0U AS=0.0P PS=7.4U M69 1 5 5 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=7.0U M70 1 5 5 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=7.0U M71 1 5 5 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=7.0U M72 1 5 5 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=7.0U M73 1 5 5 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=7.0U M74 1 5 5 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=7.0U M75 1 5 5 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=7.0U M76 1 5 5 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=7.0U M77 1 5 6 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=7.0U M78 1 5 6 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=7.0U M79 1 5 6 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=7.0U M80 1 5 6 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=7.0U M81 1 5 6 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=7.0U M82 1 5 6 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=7.0U M83 1 5 6 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=7.0U M84 1 5 6 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=7.0U M85 5 5 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.0U AS=0.0P PS=7.4U M86 5 5 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.0U AS=0.0P PS=7.4U M87 5 5 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.0U AS=0.0P PS=7.4U M88 5 5 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.0U AS=0.0P PS=7.4U M89 5 5 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.0U AS=0.0P PS=7.4U M90 5 5 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.0U AS=0.0P PS=7.4U M91 5 5 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.0U AS=0.0P PS=7.4U M92 5 5 1 3 NMOS W=1.4U L=0.7U
188
+ AD=0.0P PD=7.0U AS=0.0P PS=7.4U M93 6 5 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.0U AS=0.0P PS=7.4U M94 6 5 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.0U AS=0.0P PS=7.4U M95 6 5 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.0U AS=0.0P PS=7.4U M96 6 5 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.0U AS=0.0P PS=7.4U M97 6 5 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.0U AS=0.0P PS=7.4U M98 6 5 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.0U AS=0.0P PS=7.4U M99 6 5 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.0U AS=0.0P PS=7.4U M100 6 5 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.0U AS=0.0P PS=7.4U M101 1 7 7 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=14.9U M102 1 7 7 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=14.9U M103 1 7 7 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=14.9U M104 1 7 7 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=14.9U M105 1 7 7 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=14.9U M106 1 7 7 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=14.9U M107 1 7 7 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=14.9U M108 1 7 7 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=14.9U M109 1 7 7 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=14.9U M110 1 7 7 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=14.9U M111 7 8 8 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=14.9U AS=0.0P PS=14.9U M112 7 8 8 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=14.9U AS=0.0P PS=14.9U M113 7 8 8 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=14.9U AS=0.0P PS=14.9U M114 7 8 8 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=14.9U AS=0.0P PS=14.9U M115 7 8 8 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=14.9U AS=0.0P PS=14.9U M116 7 8 8 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=14.9U AS=0.0P PS=14.9U M117 7 8 8 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=14.9U AS=0.0P PS=14.9U M118 7 8 8 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=14.9U AS=0.0P PS=14.9U M119 7 8 8 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=14.9U AS=0.0P PS=14.9U M120 7 8 8 3 NMOS W=1.4U L=0.7U
+ AD=0.0P PD=14.9U AS=0.0P PS=14.9U M121 6 6 9 10 PMOS W=1.4U L=0.7U + AD=0.8P PD=6.0U AS=0.6P PS=5.5U M122 6 6 9 10 PMOS W=1.4U L=0.7U + AD=0.8P PD=6.0U AS=0.6P PS=5.5U M123 6 6 9 10 PMOS W=1.4U L=0.7U + AD=0.8P PD=6.0U AS=0.6P PS=5.5U M124 6 6 9 10 PMOS W=1.4U L=0.7U + AD=0.8P PD=6.0U AS=0.6P PS=5.5U M125 6 6 9 10 PMOS W=1.4U L=0.7U + AD=0.8P PD=6.0U AS=0.6P PS=5.5U M126 6 6 9 10 PMOS W=1.4U L=0.7U + AD=0.8P PD=6.0U AS=0.6P PS=5.5U M127 6 6 9 10 PMOS W=1.4U L=0.7U + AD=0.8P PD=6.0U AS=0.6P PS=5.5U M128 6 6 9 10 PMOS W=1.4U L=0.7U + AD=0.8P PD=6.0U AS=0.6P PS=5.5U M129 9 6 6 10 PMOS W=1.4U L=0.7U + AD=0.6P PD=5.5U AS=0.8P PS=6.0U M130 9 6 6 10 PMOS W=1.4U L=0.7U + AD=0.6P PD=5.5U AS=0.8P PS=6.0U M131 9 6 6 10 PMOS W=1.4U L=0.7U + AD=0.6P PD=5.5U AS=0.8P PS=6.0U M132 9 6 6 10 PMOS W=1.4U L=0.7U + AD=0.6P PD=5.5U AS=0.8P PS=6.0U M133 9 6 6 10 PMOS W=1.4U L=0.7U + AD=0.6P PD=5.5U AS=0.8P PS=6.0U M134 9 6 6 10 PMOS W=1.4U L=0.7U + AD=0.6P PD=5.5U AS=0.8P PS=6.0U M135 9 6 6 10 PMOS W=1.4U L=0.7U + AD=0.6P PD=5.5U AS=0.8P PS=6.0U M136 9 6 6 10 PMOS W=1.4U L=0.7U + AD=0.6P PD=5.5U AS=0.8P PS=6.0U M137 11 6 9 10 PMOS W=23.8U L=0.7U + AD=11.7P PD=80.9U AS=9.6P PS=92.9U M138 12 9 9 3 NMOS W=11.5U L=0.7U + AD=0.0P PD=39.3U AS=0.0P PS=114.3U M139 13 9 9 3 NMOS W=7.0U L=0.7U + AD=0.0P PD=24.0U AS=0.0P PS=69.3U M140 14 9 9 3 NMOS W=7.0U L=0.7U + AD=0.0P PD=24.0U AS=0.0P PS=69.3U M141 15 9 9 3 NMOS W=7.0U L=0.7U + AD=0.0P PD=24.0U AS=0.0P PS=69.3U M142 16 9 9 3 NMOS W=7.0U L=0.7U + AD=0.0P PD=24.0U AS=0.0P PS=69.3U M143 17 9 9 3 NMOS W=11.5U L=0.7U + AD=0.0P PD=39.3U AS=0.0P PS=114.3U M144 18 6 9 10 PMOS W=23.8U L=0.7U + AD=11.9P PD=80.9U AS=9.6P PS=92.9U M145 6 6 9 10 PMOS W=1.4U L=0.7U + AD=0.8P PD=6.0U AS=0.6P PS=5.5U M146 6 6 9 10 PMOS W=1.4U L=0.7U + AD=0.8P PD=6.0U AS=0.6P PS=5.5U M147 6 6 9 10 PMOS W=1.4U L=0.7U + AD=0.8P PD=6.0U AS=0.6P PS=5.5U M148 6 6 9 10 PMOS W=1.4U L=0.7U
189
+ AD=0.8P PD=6.0U AS=0.6P PS=5.5U M149 6 6 9 10 PMOS W=1.4U L=0.7U + AD=0.8P PD=6.0U AS=0.6P PS=5.5U M150 6 6 9 10 PMOS W=1.4U L=0.7U + AD=0.8P PD=6.0U AS=0.6P PS=5.5U M151 6 6 9 10 PMOS W=1.4U L=0.7U + AD=0.8P PD=6.0U AS=0.6P PS=5.5U M152 6 6 9 10 PMOS W=1.4U L=0.7U + AD=0.8P PD=6.0U AS=0.6P PS=5.5U M153 9 6 11 10 PMOS W=23.8U L=0.7U + AD=9.6P PD=92.9U AS=11.7P PS=80.9U M154 9 9 12 3 NMOS W=11.5U L=0.7U + AD=0.0P PD=114.3U AS=0.0P PS=39.3U M155 19 20 20 3 NMOS W=7.0U L=0.7U + AD=0.0P PD=24.0U AS=0.0P PS=42.0U M156 21 20 20 3 NMOS W=7.0U L=0.7U + AD=0.0P PD=24.0U AS=0.0P PS=42.0U M157 22 20 20 3 NMOS W=7.0U L=0.7U + AD=0.0P PD=24.0U AS=0.0P PS=42.0U M158 23 20 20 3 NMOS W=7.0U L=0.7U + AD=0.0P PD=24.0U AS=0.0P PS=42.0U M159 24 20 20 3 NMOS W=7.0U L=0.7U + AD=0.0P PD=24.0U AS=0.0P PS=42.0U M160 25 20 20 3 NMOS W=7.0U L=0.7U + AD=0.0P PD=24.0U AS=0.0P PS=42.0U M161 26 20 20 3 NMOS W=7.0U L=0.7U + AD=0.0P PD=24.0U AS=0.0P PS=42.0U M162 27 20 20 3 NMOS W=7.0U L=0.7U + AD=0.0P PD=24.0U AS=0.0P PS=42.0U M163 28 20 20 3 NMOS W=7.0U L=0.7U + AD=0.0P PD=24.0U AS=0.0P PS=42.0U M164 29 20 20 3 NMOS W=7.0U L=0.7U + AD=0.0P PD=24.0U AS=0.0P PS=42.0U M165 30 20 20 3 NMOS W=7.0U L=0.7U + AD=0.0P PD=24.0U AS=0.0P PS=42.0U M166 31 20 20 3 NMOS W=7.0U L=0.7U + AD=0.0P PD=24.0U AS=0.0P PS=42.0U M167 32 20 20 3 NMOS W=7.0U L=0.7U + AD=0.0P PD=24.0U AS=0.0P PS=42.0U M168 33 20 20 3 NMOS W=7.0U L=0.7U + AD=0.0P PD=24.0U AS=0.0P PS=42.0U M169 9 9 17 3 NMOS W=11.5U L=0.7U + AD=0.0P PD=114.3U AS=0.0P PS=39.3U M170 9 6 18 10 PMOS W=23.8U L=0.7U + AD=9.6P PD=92.9U AS=11.9P PS=80.9U M171 9 6 6 10 PMOS W=1.4U L=0.7U + AD=0.6P PD=5.5U AS=0.8P PS=6.0U M172 9 6 6 10 PMOS W=1.4U L=0.7U + AD=0.6P PD=5.5U AS=0.8P PS=6.0U M173 9 6 6 10 PMOS W=1.4U L=0.7U + AD=0.6P PD=5.5U AS=0.8P PS=6.0U M174 9 6 6 10 PMOS W=1.4U L=0.7U + AD=0.6P PD=5.5U AS=0.8P PS=6.0U M175 9 6 6 10 PMOS W=1.4U L=0.7U + AD=0.6P PD=5.5U AS=0.8P PS=6.0U M176 9 6 6 10 PMOS W=1.4U L=0.7U
+ AD=0.6P PD=5.5U AS=0.8P PS=6.0U M177 9 6 6 10 PMOS W=1.4U L=0.7U + AD=0.6P PD=5.5U AS=0.8P PS=6.0U M178 9 6 6 10 PMOS W=1.4U L=0.7U + AD=0.6P PD=5.5U AS=0.8P PS=6.0U M179 11 6 9 10 PMOS W=23.8U L=0.7U + AD=11.7P PD=80.9U AS=9.6P PS=92.9U M180 6 6 9 10 PMOS W=1.4U L=0.7U + AD=0.8P PD=6.0U AS=0.6P PS=5.5U M181 6 6 9 10 PMOS W=1.4U L=0.7U + AD=0.8P PD=6.0U AS=0.6P PS=5.5U M182 6 6 9 10 PMOS W=1.4U L=0.7U + AD=0.8P PD=6.0U AS=0.6P PS=5.5U M183 6 6 9 10 PMOS W=1.4U L=0.7U + AD=0.8P PD=6.0U AS=0.6P PS=5.5U M184 6 6 9 10 PMOS W=1.4U L=0.7U + AD=0.8P PD=6.0U AS=0.6P PS=5.5U M185 6 6 9 10 PMOS W=1.4U L=0.7U + AD=0.8P PD=6.0U AS=0.6P PS=5.5U M186 6 6 9 10 PMOS W=1.4U L=0.7U + AD=0.8P PD=6.0U AS=0.6P PS=5.5U M187 6 6 9 10 PMOS W=1.4U L=0.7U + AD=0.8P PD=6.0U AS=0.6P PS=5.5U M188 9 6 11 10 PMOS W=23.8U L=0.7U + AD=9.6P PD=92.9U AS=11.7P PS=80.9U M189 9 6 6 10 PMOS W=1.4U L=0.7U + AD=0.6P PD=5.5U AS=0.8P PS=6.0U M190 9 6 6 10 PMOS W=1.4U L=0.7U + AD=0.6P PD=5.5U AS=0.8P PS=6.0U M191 9 6 6 10 PMOS W=1.4U L=0.7U + AD=0.6P PD=5.5U AS=0.8P PS=6.0U M192 9 6 6 10 PMOS W=1.4U L=0.7U + AD=0.6P PD=5.5U AS=0.8P PS=6.0U M193 9 6 6 10 PMOS W=1.4U L=0.7U + AD=0.6P PD=5.5U AS=0.8P PS=6.0U M194 9 6 6 10 PMOS W=1.4U L=0.7U + AD=0.6P PD=5.5U AS=0.8P PS=6.0U M195 9 6 6 10 PMOS W=1.4U L=0.7U + AD=0.6P PD=5.5U AS=0.8P PS=6.0U M196 9 6 6 10 PMOS W=1.4U L=0.7U + AD=0.6P PD=5.5U AS=0.8P PS=6.0U M197 11 6 9 10 PMOS W=23.8U L=0.7U + AD=11.7P PD=80.9U AS=9.6P PS=92.9U M198 6 6 9 10 PMOS W=1.4U L=0.7U + AD=0.8P PD=6.0U AS=0.6P PS=5.5U M199 6 6 9 10 PMOS W=1.4U L=0.7U + AD=0.8P PD=6.0U AS=0.6P PS=5.5U M200 6 6 9 10 PMOS W=1.4U L=0.7U + AD=0.8P PD=6.0U AS=0.6P PS=5.5U M201 6 6 9 10 PMOS W=1.4U L=0.7U + AD=0.8P PD=6.0U AS=0.6P PS=5.5U M202 6 6 9 10 PMOS W=1.4U L=0.7U + AD=0.8P PD=6.0U AS=0.6P PS=5.5U M203 6 6 9 10 PMOS W=1.4U L=0.7U + AD=0.8P PD=6.0U AS=0.6P PS=5.5U M204 6 6 9 10 PMOS W=1.4U L=0.7U
190
+ AD=0.8P PD=6.0U AS=0.6P PS=5.5U M205 6 6 9 10 PMOS W=1.4U L=0.7U + AD=0.8P PD=6.0U AS=0.6P PS=5.5U M206 9 6 6 10 PMOS W=1.4U L=0.7U + AD=0.6P PD=5.5U AS=0.8P PS=6.0U M207 9 6 6 10 PMOS W=1.4U L=0.7U + AD=0.6P PD=5.5U AS=0.8P PS=6.0U M208 9 6 6 10 PMOS W=1.4U L=0.7U + AD=0.6P PD=5.5U AS=0.8P PS=6.0U M209 9 6 6 10 PMOS W=1.4U L=0.7U + AD=0.6P PD=5.5U AS=0.8P PS=6.0U M210 9 6 6 10 PMOS W=1.4U L=0.7U + AD=0.6P PD=5.5U AS=0.8P PS=6.0U M211 9 6 6 10 PMOS W=1.4U L=0.7U + AD=0.6P PD=5.5U AS=0.8P PS=6.0U M212 9 6 6 10 PMOS W=1.4U L=0.7U + AD=0.6P PD=5.5U AS=0.8P PS=6.0U M213 9 6 6 10 PMOS W=1.4U L=0.7U + AD=0.6P PD=5.5U AS=0.8P PS=6.0U M214 12 9 9 3 NMOS W=11.5U L=0.7U + AD=0.0P PD=39.3U AS=0.0P PS=114.3U M215 17 9 9 3 NMOS W=11.5U L=0.7U + AD=0.0P PD=39.3U AS=0.0P PS=114.3U M216 9 9 12 3 NMOS W=11.5U L=0.7U + AD=0.0P PD=114.3U AS=0.0P PS=39.3U M217 9 9 17 3 NMOS W=11.5U L=0.7U + AD=0.0P PD=114.3U AS=0.0P PS=39.3U M218 12 9 9 3 NMOS W=11.5U L=0.7U + AD=0.0P PD=39.3U AS=0.0P PS=114.3U M219 17 9 9 3 NMOS W=11.5U L=0.7U + AD=0.0P PD=39.3U AS=0.0P PS=114.3U M220 18 6 9 10 PMOS W=23.8U L=0.7U + AD=11.9P PD=80.9U AS=9.6P PS=92.9U M221 13 12 34 3 NMOS W=10.5U L=0.7U + AD=0.0P PD=36.0U AS=0.0P PS=42.4U M222 15 13 35 3 NMOS W=10.5U L=0.7U + AD=0.0P PD=36.0U AS=0.0P PS=42.4U M223 9 6 18 10 PMOS W=23.8U L=0.7U + AD=9.6P PD=92.9U AS=11.9P PS=80.9U M224 19 15 36 3 NMOS W=10.5U L=0.7U + AD=0.0P PD=36.0U AS=0.0P PS=42.4U M225 22 4 37 3 NMOS W=10.5U L=0.7U + AD=0.0P PD=36.0U AS=0.0P PS=42.4U M226 24 23 38 3 NMOS W=10.5U L=0.7U + AD=0.0P PD=36.0U AS=0.0P PS=42.4U M227 26 24 39 3 NMOS W=10.5U L=0.7U + AD=0.0P PD=36.0U AS=0.0P PS=42.4U M228 28 26 40 3 NMOS W=10.5U L=0.7U + AD=0.0P PD=36.0U AS=0.0P PS=42.4U M229 30 28 41 3 NMOS W=10.5U L=0.7U + AD=0.0P PD=36.0U AS=0.0P PS=42.4U M230 32 30 42 3 NMOS W=10.5U L=0.7U + AD=0.0P PD=36.0U AS=0.0P PS=42.4U M231 34 12 13 3 NMOS W=10.5U L=0.7U + AD=0.0P PD=42.4U AS=0.0P PS=36.0U M232 35 13 15 3 NMOS W=10.5U L=0.7U
+ AD=0.0P PD=42.4U AS=0.0P PS=36.0U M233 18 6 9 10 PMOS W=23.8U L=0.7U + AD=11.9P PD=80.9U AS=9.6P PS=92.9U M234 36 15 19 3 NMOS W=10.5U L=0.7U + AD=0.0P PD=42.4U AS=0.0P PS=36.0U M235 37 4 22 3 NMOS W=10.5U L=0.7U + AD=0.0P PD=42.4U AS=0.0P PS=36.0U M236 38 23 24 3 NMOS W=10.5U L=0.7U + AD=0.0P PD=42.4U AS=0.0P PS=36.0U M237 39 24 26 3 NMOS W=10.5U L=0.7U + AD=0.0P PD=42.4U AS=0.0P PS=36.0U M238 40 26 28 3 NMOS W=10.5U L=0.7U + AD=0.0P PD=42.4U AS=0.0P PS=36.0U M239 41 28 30 3 NMOS W=10.5U L=0.7U + AD=0.0P PD=42.4U AS=0.0P PS=36.0U M240 42 30 32 3 NMOS W=10.5U L=0.7U + AD=0.0P PD=42.4U AS=0.0P PS=36.0U M241 13 12 34 3 NMOS W=10.5U L=0.7U + AD=0.0P PD=36.0U AS=0.0P PS=42.4U M242 15 13 35 3 NMOS W=10.5U L=0.7U + AD=0.0P PD=36.0U AS=0.0P PS=42.4U M243 19 15 36 3 NMOS W=10.5U L=0.7U + AD=0.0P PD=36.0U AS=0.0P PS=42.4U M244 22 4 37 3 NMOS W=10.5U L=0.7U + AD=0.0P PD=36.0U AS=0.0P PS=42.4U M245 24 23 38 3 NMOS W=10.5U L=0.7U + AD=0.0P PD=36.0U AS=0.0P PS=42.4U M246 26 24 39 3 NMOS W=10.5U L=0.7U + AD=0.0P PD=36.0U AS=0.0P PS=42.4U M247 28 26 40 3 NMOS W=10.5U L=0.7U + AD=0.0P PD=36.0U AS=0.0P PS=42.4U M248 30 28 41 3 NMOS W=10.5U L=0.7U + AD=0.0P PD=36.0U AS=0.0P PS=42.4U M249 32 30 42 3 NMOS W=10.5U L=0.7U + AD=0.0P PD=36.0U AS=0.0P PS=42.4U M250 34 12 13 3 NMOS W=10.5U L=0.7U + AD=0.0P PD=42.4U AS=0.0P PS=36.0U M251 35 13 15 3 NMOS W=10.5U L=0.7U + AD=0.0P PD=42.4U AS=0.0P PS=36.0U M252 36 15 19 3 NMOS W=10.5U L=0.7U + AD=0.0P PD=42.4U AS=0.0P PS=36.0U M253 37 4 22 3 NMOS W=10.5U L=0.7U + AD=0.0P PD=42.4U AS=0.0P PS=36.0U M254 38 23 24 3 NMOS W=10.5U L=0.7U + AD=0.0P PD=42.4U AS=0.0P PS=36.0U M255 39 24 26 3 NMOS W=10.5U L=0.7U + AD=0.0P PD=42.4U AS=0.0P PS=36.0U M256 40 26 28 3 NMOS W=10.5U L=0.7U + AD=0.0P PD=42.4U AS=0.0P PS=36.0U M257 41 28 30 3 NMOS W=10.5U L=0.7U + AD=0.0P PD=42.4U AS=0.0P PS=36.0U M258 42 30 32 3 NMOS W=10.5U L=0.7U + AD=0.0P PD=42.4U AS=0.0P PS=36.0U M259 14 17 34 3 NMOS W=10.5U L=0.7U + AD=0.0P PD=36.0U AS=0.0P PS=42.4U M260 16 14 35 3 NMOS W=10.5U L=0.7U
191
+ AD=0.0P PD=36.0U AS=0.0P PS=42.4U M261 6 6 9 10 PMOS W=1.4U L=0.7U + AD=0.8P PD=6.0U AS=0.6P PS=5.5U M262 6 6 9 10 PMOS W=1.4U L=0.7U + AD=0.8P PD=6.0U AS=0.6P PS=5.5U M263 6 6 9 10 PMOS W=1.4U L=0.7U + AD=0.8P PD=6.0U AS=0.6P PS=5.5U M264 6 6 9 10 PMOS W=1.4U L=0.7U + AD=0.8P PD=6.0U AS=0.6P PS=5.5U M265 6 6 9 10 PMOS W=1.4U L=0.7U + AD=0.8P PD=6.0U AS=0.6P PS=5.5U M266 6 6 9 10 PMOS W=1.4U L=0.7U + AD=0.8P PD=6.0U AS=0.6P PS=5.5U M267 6 6 9 10 PMOS W=1.4U L=0.7U + AD=0.8P PD=6.0U AS=0.6P PS=5.5U M268 6 6 9 10 PMOS W=1.4U L=0.7U + AD=0.8P PD=6.0U AS=0.6P PS=5.5U M269 43 11 11 3 NMOS W=11.5U L=0.7U + AD=0.0P PD=45.9U AS=0.0P PS=39.3U M270 9 6 6 10 PMOS W=1.4U L=0.7U + AD=0.6P PD=5.5U AS=0.8P PS=6.0U M271 9 6 6 10 PMOS W=1.4U L=0.7U + AD=0.6P PD=5.5U AS=0.8P PS=6.0U M272 9 6 6 10 PMOS W=1.4U L=0.7U + AD=0.6P PD=5.5U AS=0.8P PS=6.0U M273 9 6 6 10 PMOS W=1.4U L=0.7U + AD=0.6P PD=5.5U AS=0.8P PS=6.0U M274 9 6 6 10 PMOS W=1.4U L=0.7U + AD=0.6P PD=5.5U AS=0.8P PS=6.0U M275 9 6 6 10 PMOS W=1.4U L=0.7U + AD=0.6P PD=5.5U AS=0.8P PS=6.0U M276 9 6 6 10 PMOS W=1.4U L=0.7U + AD=0.6P PD=5.5U AS=0.8P PS=6.0U M277 9 6 6 10 PMOS W=1.4U L=0.7U + AD=0.6P PD=5.5U AS=0.8P PS=6.0U M278 43 11 12 3 NMOS W=11.5U L=0.7U + AD=0.0P PD=45.9U AS=0.0P PS=39.3U M279 43 18 17 3 NMOS W=11.5U L=0.7U + AD=0.0P PD=45.9U AS=0.0P PS=39.3U M280 43 18 18 3 NMOS W=11.5U L=0.7U + AD=0.0P PD=45.9U AS=0.0P PS=39.3U M281 21 8 36 3 NMOS W=10.5U L=0.7U + AD=0.0P PD=36.0U AS=0.0P PS=42.4U M282 23 16 37 3 NMOS W=10.5U L=0.7U + AD=0.0P PD=36.0U AS=0.0P PS=42.4U M283 25 19 38 3 NMOS W=10.5U L=0.7U + AD=0.0P PD=36.0U AS=0.0P PS=42.4U M284 27 25 39 3 NMOS W=10.5U L=0.7U + AD=0.0P PD=36.0U AS=0.0P PS=42.4U M285 29 27 40 3 NMOS W=10.5U L=0.7U + AD=0.0P PD=36.0U AS=0.0P PS=42.4U M286 31 29 41 3 NMOS W=10.5U L=0.7U + AD=0.0P PD=36.0U AS=0.0P PS=42.4U M287 33 31 42 3 NMOS W=10.5U L=0.7U + AD=0.0P PD=36.0U AS=0.0P PS=42.4U M288 11 11 43 3 NMOS W=11.5U L=0.7U
+ AD=0.0P PD=39.3U AS=0.0P PS=45.9U M289 12 11 43 3 NMOS W=11.5U L=0.7U + AD=0.0P PD=39.3U AS=0.0P PS=45.9U M290 17 18 43 3 NMOS W=11.5U L=0.7U + AD=0.0P PD=39.3U AS=0.0P PS=45.9U M291 34 17 14 3 NMOS W=10.5U L=0.7U + AD=0.0P PD=42.4U AS=0.0P PS=36.0U M292 35 14 16 3 NMOS W=10.5U L=0.7U + AD=0.0P PD=42.4U AS=0.0P PS=36.0U M293 18 18 43 3 NMOS W=11.5U L=0.7U + AD=0.0P PD=39.3U AS=0.0P PS=45.9U M294 36 8 21 3 NMOS W=10.5U L=0.7U + AD=0.0P PD=42.4U AS=0.0P PS=36.0U M295 37 16 23 3 NMOS W=10.5U L=0.7U + AD=0.0P PD=42.4U AS=0.0P PS=36.0U M296 38 19 25 3 NMOS W=10.5U L=0.7U + AD=0.0P PD=42.4U AS=0.0P PS=36.0U M297 39 25 27 3 NMOS W=10.5U L=0.7U + AD=0.0P PD=42.4U AS=0.0P PS=36.0U M298 40 27 29 3 NMOS W=10.5U L=0.7U + AD=0.0P PD=42.4U AS=0.0P PS=36.0U M299 41 29 31 3 NMOS W=10.5U L=0.7U + AD=0.0P PD=42.4U AS=0.0P PS=36.0U M300 42 31 33 3 NMOS W=10.5U L=0.7U + AD=0.0P PD=42.4U AS=0.0P PS=36.0U M301 43 11 11 3 NMOS W=11.5U L=0.7U + AD=0.0P PD=45.9U AS=0.0P PS=39.3U M302 14 17 34 3 NMOS W=10.5U L=0.7U + AD=0.0P PD=36.0U AS=0.0P PS=42.4U M303 16 14 35 3 NMOS W=10.5U L=0.7U + AD=0.0P PD=36.0U AS=0.0P PS=42.4U M304 43 11 12 3 NMOS W=11.5U L=0.7U + AD=0.0P PD=45.9U AS=0.0P PS=39.3U M305 43 18 17 3 NMOS W=11.5U L=0.7U + AD=0.0P PD=45.9U AS=0.0P PS=39.3U M306 43 18 18 3 NMOS W=11.5U L=0.7U + AD=0.0P PD=45.9U AS=0.0P PS=39.3U M307 21 8 36 3 NMOS W=10.5U L=0.7U + AD=0.0P PD=36.0U AS=0.0P PS=42.4U M308 23 16 37 3 NMOS W=10.5U L=0.7U + AD=0.0P PD=36.0U AS=0.0P PS=42.4U M309 25 19 38 3 NMOS W=10.5U L=0.7U + AD=0.0P PD=36.0U AS=0.0P PS=42.4U M310 27 25 39 3 NMOS W=10.5U L=0.7U + AD=0.0P PD=36.0U AS=0.0P PS=42.4U M311 29 27 40 3 NMOS W=10.5U L=0.7U + AD=0.0P PD=36.0U AS=0.0P PS=42.4U M312 31 29 41 3 NMOS W=10.5U L=0.7U + AD=0.0P PD=36.0U AS=0.0P PS=42.4U M313 33 31 42 3 NMOS W=10.5U L=0.7U + AD=0.0P PD=36.0U AS=0.0P PS=42.4U M314 11 11 43 3 NMOS W=11.5U L=0.7U + AD=0.0P PD=39.3U AS=0.0P PS=45.9U M315 34 17 14 3 NMOS W=10.5U L=0.7U + AD=0.0P PD=42.4U AS=0.0P PS=36.0U M316 35 14 16 3 NMOS W=10.5U L=0.7U
192
+ AD=0.0P PD=42.4U AS=0.0P PS=36.0U M317 12 11 43 3 NMOS W=11.5U L=0.7U + AD=0.0P PD=39.3U AS=0.0P PS=45.9U M318 17 18 43 3 NMOS W=11.5U L=0.7U + AD=0.0P PD=39.3U AS=0.0P PS=45.9U M319 36 8 21 3 NMOS W=10.5U L=0.7U + AD=0.0P PD=42.4U AS=0.0P PS=36.0U M320 37 16 23 3 NMOS W=10.5U L=0.7U + AD=0.0P PD=42.4U AS=0.0P PS=36.0U M321 38 19 25 3 NMOS W=10.5U L=0.7U + AD=0.0P PD=42.4U AS=0.0P PS=36.0U M322 39 25 27 3 NMOS W=10.5U L=0.7U + AD=0.0P PD=42.4U AS=0.0P PS=36.0U M323 40 27 29 3 NMOS W=10.5U L=0.7U + AD=0.0P PD=42.4U AS=0.0P PS=36.0U M324 41 29 31 3 NMOS W=10.5U L=0.7U + AD=0.0P PD=42.4U AS=0.0P PS=36.0U M325 42 31 33 3 NMOS W=10.5U L=0.7U + AD=0.0P PD=42.4U AS=0.0P PS=36.0U M326 18 18 43 3 NMOS W=11.5U L=0.7U + AD=0.0P PD=39.3U AS=0.0P PS=45.9U M327 43 11 11 3 NMOS W=11.5U L=0.7U + AD=0.0P PD=45.9U AS=0.0P PS=39.3U M328 43 11 12 3 NMOS W=11.5U L=0.7U + AD=0.0P PD=45.9U AS=0.0P PS=39.3U M329 43 18 17 3 NMOS W=11.5U L=0.7U + AD=0.0P PD=45.9U AS=0.0P PS=39.3U M330 43 18 18 3 NMOS W=11.5U L=0.7U + AD=0.0P PD=45.9U AS=0.0P PS=39.3U M331 34 44 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.4U M332 34 44 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.4U M333 34 44 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.4U M334 34 44 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.4U M335 34 44 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.4U M336 34 44 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.4U M337 34 44 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.4U M338 34 44 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.4U M339 35 44 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.4U M340 35 44 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.4U M341 35 44 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.4U M342 35 44 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.4U M343 35 44 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.4U M344 35 44 1 3 NMOS W=1.4U L=0.7U
+ AD=0.0P PD=5.7U AS=0.0P PS=7.4U M345 35 44 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.4U M346 35 44 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.4U M347 36 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M348 36 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M349 36 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M350 36 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M351 36 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M352 36 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M353 36 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M354 36 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M355 37 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M356 37 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M357 37 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M358 37 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M359 37 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M360 37 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M361 37 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M362 37 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M363 38 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M364 38 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M365 38 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M366 38 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M367 38 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M368 38 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M369 38 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M370 38 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M371 39 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M372 39 44 45 3 NMOS W=1.4U L=0.7U
193
+ AD=0.0P PD=5.7U AS=0.0P PS=7.8U M373 39 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M374 39 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M375 39 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M376 39 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M377 39 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M378 39 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M379 40 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M380 40 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M381 40 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M382 40 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M383 40 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M384 40 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M385 40 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M386 40 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M387 41 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M388 41 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M389 41 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M390 41 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M391 41 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M392 41 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M393 41 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M394 41 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M395 42 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M396 42 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M397 42 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M398 42 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M399 42 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M400 42 44 45 3 NMOS W=1.4U L=0.7U
+ AD=0.0P PD=5.7U AS=0.0P PS=7.8U M401 42 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M402 42 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M403 1 44 34 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=5.7U M404 1 44 34 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=5.7U M405 1 44 34 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=5.7U M406 1 44 34 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=5.7U M407 1 44 34 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=5.7U M408 1 44 34 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=5.7U M409 1 44 34 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=5.7U M410 1 44 34 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=5.7U M411 1 44 35 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=5.7U M412 1 44 35 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=5.7U M413 1 44 35 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=5.7U M414 1 44 35 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=5.7U M415 1 44 35 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=5.7U M416 1 44 35 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=5.7U M417 1 44 35 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=5.7U M418 1 44 35 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=5.7U M419 46 11 11 3 NMOS W=11.2U L=0.7U + AD=0.0P PD=35.8U AS=0.0P PS=38.1U M420 47 11 43 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=6.7U AS=0.0P PS=5.6U M421 47 11 43 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=6.7U AS=0.0P PS=5.6U M422 47 11 43 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=6.7U AS=0.0P PS=5.6U M423 47 11 43 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=6.7U AS=0.0P PS=5.6U M424 47 11 43 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=6.7U AS=0.0P PS=5.6U M425 47 11 43 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=6.7U AS=0.0P PS=5.6U M426 47 11 43 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=6.7U AS=0.0P PS=5.6U M427 47 11 43 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=6.7U AS=0.0P PS=5.6U M428 47 11 43 3 NMOS W=1.4U L=0.7U
194
+ AD=0.0P PD=6.7U AS=0.0P PS=5.6U M429 47 11 43 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=6.7U AS=0.0P PS=5.6U M430 47 11 43 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=6.7U AS=0.0P PS=5.6U M431 47 11 43 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=6.7U AS=0.0P PS=5.6U M432 47 11 43 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=6.7U AS=0.0P PS=5.6U M433 47 11 43 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=6.7U AS=0.0P PS=5.6U M434 47 11 43 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=6.7U AS=0.0P PS=5.6U M435 47 11 43 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=6.7U AS=0.0P PS=5.6U M436 47 11 43 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=6.7U AS=0.0P PS=5.6U M437 48 11 18 3 NMOS W=11.5U L=0.7U + AD=0.0P PD=37.0U AS=0.0P PS=39.3U M438 45 44 36 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M439 45 44 36 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M440 45 44 36 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M441 45 44 36 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M442 45 44 36 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M443 45 44 36 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M444 45 44 36 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M445 45 44 36 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M446 45 44 37 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M447 45 44 37 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M448 45 44 37 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M449 45 44 37 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M450 45 44 37 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M451 45 44 37 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M452 45 44 37 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M453 45 44 37 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M454 45 44 38 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M455 45 44 38 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M456 45 44 38 3 NMOS W=1.4U L=0.7U
+ AD=0.0P PD=7.8U AS=0.0P PS=5.7U M457 45 44 38 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M458 45 44 38 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M459 45 44 38 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M460 45 44 38 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M461 45 44 38 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M462 45 44 39 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M463 45 44 39 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M464 45 44 39 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M465 45 44 39 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M466 45 44 39 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M467 45 44 39 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M468 45 44 39 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M469 45 44 39 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M470 45 44 40 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M471 45 44 40 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M472 45 44 40 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M473 45 44 40 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M474 45 44 40 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M475 45 44 40 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M476 45 44 40 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M477 45 44 40 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M478 45 44 41 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M479 45 44 41 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M480 45 44 41 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M481 45 44 41 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M482 45 44 41 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M483 45 44 41 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M484 45 44 41 3 NMOS W=1.4U L=0.7U
195
+ AD=0.0P PD=7.8U AS=0.0P PS=5.7U M485 45 44 41 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M486 45 44 42 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M487 45 44 42 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M488 45 44 42 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M489 45 44 42 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M490 45 44 42 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M491 45 44 42 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M492 45 44 42 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M493 45 44 42 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M494 11 11 46 3 NMOS W=11.2U L=0.7U + AD=0.0P PD=38.1U AS=0.0P PS=35.8U M495 34 44 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.4U M496 34 44 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.4U M497 34 44 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.4U M498 34 44 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.4U M499 34 44 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.4U M500 34 44 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.4U M501 34 44 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.4U M502 34 44 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.4U M503 35 44 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.4U M504 35 44 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.4U M505 35 44 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.4U M506 35 44 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.4U M507 35 44 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.4U M508 35 44 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.4U M509 35 44 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.4U M510 35 44 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.4U M511 43 11 47 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.6U AS=0.0P PS=6.7U M512 43 11 47 3 NMOS W=1.4U L=0.7U
+ AD=0.0P PD=5.6U AS=0.0P PS=6.7U M513 43 11 47 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.6U AS=0.0P PS=6.7U M514 43 11 47 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.6U AS=0.0P PS=6.7U M515 43 11 47 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.6U AS=0.0P PS=6.7U M516 43 11 47 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.6U AS=0.0P PS=6.7U M517 43 11 47 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.6U AS=0.0P PS=6.7U M518 43 11 47 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.6U AS=0.0P PS=6.7U M519 43 11 47 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.6U AS=0.0P PS=6.7U M520 43 11 47 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.6U AS=0.0P PS=6.7U M521 43 11 47 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.6U AS=0.0P PS=6.7U M522 43 11 47 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.6U AS=0.0P PS=6.7U M523 43 11 47 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.6U AS=0.0P PS=6.7U M524 43 11 47 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.6U AS=0.0P PS=6.7U M525 43 11 47 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.6U AS=0.0P PS=6.7U M526 43 11 47 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.6U AS=0.0P PS=6.7U M527 43 11 47 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.6U AS=0.0P PS=6.7U M528 18 11 48 3 NMOS W=11.5U L=0.7U + AD=0.0P PD=39.3U AS=0.0P PS=37.0U M529 36 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M530 36 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M531 36 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M532 36 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M533 36 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M534 36 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M535 36 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M536 36 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M537 37 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M538 37 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M539 37 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M540 37 44 45 3 NMOS W=1.4U L=0.7U
196
+ AD=0.0P PD=5.7U AS=0.0P PS=7.8U M541 37 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M542 37 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M543 37 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M544 37 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M545 38 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M546 38 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M547 38 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M548 38 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M549 38 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M550 38 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M551 38 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M552 38 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M553 39 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M554 39 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M555 39 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M556 39 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M557 39 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M558 39 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M559 39 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M560 39 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M561 40 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M562 40 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M563 40 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M564 40 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M565 40 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M566 40 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M567 40 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M568 40 44 45 3 NMOS W=1.4U L=0.7U
+ AD=0.0P PD=5.7U AS=0.0P PS=7.8U M569 41 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M570 41 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M571 41 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M572 41 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M573 41 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M574 41 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M575 41 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M576 41 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M577 42 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M578 42 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M579 42 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M580 42 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M581 42 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M582 42 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M583 42 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M584 42 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M585 46 11 11 3 NMOS W=11.2U L=0.7U + AD=0.0P PD=35.8U AS=0.0P PS=38.1U M586 1 44 34 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=5.7U M587 1 44 34 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=5.7U M588 1 44 34 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=5.7U M589 1 44 34 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=5.7U M590 1 44 34 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=5.7U M591 1 44 34 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=5.7U M592 1 44 34 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=5.7U M593 1 44 34 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=5.7U M594 1 44 35 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=5.7U M595 1 44 35 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=5.7U M596 1 44 35 3 NMOS W=1.4U L=0.7U
197
+ AD=0.0P PD=7.4U AS=0.0P PS=5.7U M597 1 44 35 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=5.7U M598 1 44 35 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=5.7U M599 1 44 35 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=5.7U M600 1 44 35 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=5.7U M601 1 44 35 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=5.7U M602 47 11 43 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=6.7U AS=0.0P PS=5.6U M603 47 11 43 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=6.7U AS=0.0P PS=5.6U M604 47 11 43 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=6.7U AS=0.0P PS=5.6U M605 47 11 43 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=6.7U AS=0.0P PS=5.6U M606 47 11 43 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=6.7U AS=0.0P PS=5.6U M607 47 11 43 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=6.7U AS=0.0P PS=5.6U M608 47 11 43 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=6.7U AS=0.0P PS=5.6U M609 47 11 43 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=6.7U AS=0.0P PS=5.6U M610 47 11 43 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=6.7U AS=0.0P PS=5.6U M611 47 11 43 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=6.7U AS=0.0P PS=5.6U M612 47 11 43 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=6.7U AS=0.0P PS=5.6U M613 47 11 43 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=6.7U AS=0.0P PS=5.6U M614 47 11 43 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=6.7U AS=0.0P PS=5.6U M615 47 11 43 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=6.7U AS=0.0P PS=5.6U M616 47 11 43 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=6.7U AS=0.0P PS=5.6U M617 47 11 43 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=6.7U AS=0.0P PS=5.6U M618 47 11 43 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=6.7U AS=0.0P PS=5.6U M619 48 11 18 3 NMOS W=11.5U L=0.7U + AD=0.0P PD=37.0U AS=0.0P PS=39.3U M620 11 11 46 3 NMOS W=11.2U L=0.7U + AD=0.0P PD=38.1U AS=0.0P PS=35.8U M621 45 44 36 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M622 45 44 36 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M623 45 44 36 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M624 45 44 36 3 NMOS W=1.4U L=0.7U
+ AD=0.0P PD=7.8U AS=0.0P PS=5.7U M625 45 44 36 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M626 45 44 36 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M627 45 44 36 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M628 45 44 36 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M629 45 44 37 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M630 45 44 37 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M631 45 44 37 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M632 45 44 37 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M633 45 44 37 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M634 45 44 37 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M635 45 44 37 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M636 45 44 37 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M637 45 44 38 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M638 45 44 38 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M639 45 44 38 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M640 45 44 38 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M641 45 44 38 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M642 45 44 38 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M643 45 44 38 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M644 45 44 38 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M645 45 44 39 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M646 45 44 39 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M647 45 44 39 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M648 45 44 39 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M649 45 44 39 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M650 45 44 39 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M651 45 44 39 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M652 45 44 39 3 NMOS W=1.4U L=0.7U
198
+ AD=0.0P PD=7.8U AS=0.0P PS=5.7U M653 45 44 40 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M654 45 44 40 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M655 45 44 40 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M656 45 44 40 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M657 45 44 40 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M658 45 44 40 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M659 45 44 40 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M660 45 44 40 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M661 45 44 41 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M662 45 44 41 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M663 45 44 41 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M664 45 44 41 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M665 45 44 41 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M666 45 44 41 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M667 45 44 41 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M668 45 44 41 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M669 45 44 42 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M670 45 44 42 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M671 45 44 42 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M672 45 44 42 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M673 45 44 42 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M674 45 44 42 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M675 45 44 42 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M676 45 44 42 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M677 34 44 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.4U M678 34 44 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.4U M679 34 44 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.4U M680 34 44 1 3 NMOS W=1.4U L=0.7U
+ AD=0.0P PD=5.7U AS=0.0P PS=7.4U M681 34 44 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.4U M682 34 44 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.4U M683 34 44 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.4U M684 34 44 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.4U M685 35 44 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.4U M686 35 44 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.4U M687 35 44 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.4U M688 35 44 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.4U M689 35 44 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.4U M690 35 44 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.4U M691 35 44 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.4U M692 35 44 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.4U M693 43 11 47 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.6U AS=0.0P PS=6.7U M694 43 11 47 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.6U AS=0.0P PS=6.7U M695 43 11 47 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.6U AS=0.0P PS=6.7U M696 43 11 47 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.6U AS=0.0P PS=6.7U M697 43 11 47 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.6U AS=0.0P PS=6.7U M698 43 11 47 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.6U AS=0.0P PS=6.7U M699 43 11 47 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.6U AS=0.0P PS=6.7U M700 43 11 47 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.6U AS=0.0P PS=6.7U M701 43 11 47 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.6U AS=0.0P PS=6.7U M702 43 11 47 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.6U AS=0.0P PS=6.7U M703 43 11 47 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.6U AS=0.0P PS=6.7U M704 43 11 47 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.6U AS=0.0P PS=6.7U M705 43 11 47 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.6U AS=0.0P PS=6.7U M706 43 11 47 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.6U AS=0.0P PS=6.7U M707 43 11 47 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.6U AS=0.0P PS=6.7U M708 43 11 47 3 NMOS W=1.4U L=0.7U
199
+ AD=0.0P PD=5.6U AS=0.0P PS=6.7U M709 43 11 47 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.6U AS=0.0P PS=6.7U M710 18 11 48 3 NMOS W=11.5U L=0.7U + AD=0.0P PD=39.3U AS=0.0P PS=37.0U M711 46 11 11 3 NMOS W=11.2U L=0.7U + AD=0.0P PD=35.8U AS=0.0P PS=38.1U M712 36 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M713 36 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M714 36 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M715 36 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M716 36 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M717 36 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M718 36 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M719 36 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M720 37 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M721 37 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M722 37 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M723 37 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M724 37 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M725 37 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M726 37 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M727 37 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M728 38 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M729 38 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M730 38 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M731 38 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M732 38 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M733 38 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M734 38 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M735 38 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M736 39 44 45 3 NMOS W=1.4U L=0.7U
+ AD=0.0P PD=5.7U AS=0.0P PS=7.8U M737 39 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M738 39 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M739 39 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M740 39 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M741 39 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M742 39 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M743 39 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M744 40 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M745 40 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M746 40 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M747 40 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M748 40 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M749 40 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M750 40 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M751 40 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M752 41 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M753 41 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M754 41 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M755 41 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M756 41 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M757 41 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M758 41 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M759 41 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M760 42 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M761 42 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M762 42 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M763 42 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M764 42 44 45 3 NMOS W=1.4U L=0.7U
200
+ AD=0.0P PD=5.7U AS=0.0P PS=7.8U M765 42 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M766 42 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M767 42 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M768 1 44 34 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=5.7U M769 1 44 34 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=5.7U M770 1 44 34 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=5.7U M771 1 44 34 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=5.7U M772 1 44 34 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=5.7U M773 1 44 34 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=5.7U M774 1 44 34 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=5.7U M775 1 44 34 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=5.7U M776 1 44 35 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=5.7U M777 1 44 35 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=5.7U M778 1 44 35 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=5.7U M779 1 44 35 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=5.7U M780 1 44 35 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=5.7U M781 1 44 35 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=5.7U M782 1 44 35 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=5.7U M783 1 44 35 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=5.7U M784 47 11 43 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=6.7U AS=0.0P PS=5.6U M785 47 11 43 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=6.7U AS=0.0P PS=5.6U M786 47 11 43 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=6.7U AS=0.0P PS=5.6U M787 47 11 43 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=6.7U AS=0.0P PS=5.6U M788 47 11 43 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=6.7U AS=0.0P PS=5.6U M789 47 11 43 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=6.7U AS=0.0P PS=5.6U M790 47 11 43 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=6.7U AS=0.0P PS=5.6U M791 47 11 43 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=6.7U AS=0.0P PS=5.6U M792 47 11 43 3 NMOS W=1.4U L=0.7U
+ AD=0.0P PD=6.7U AS=0.0P PS=5.6U M793 47 11 43 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=6.7U AS=0.0P PS=5.6U M794 47 11 43 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=6.7U AS=0.0P PS=5.6U M795 47 11 43 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=6.7U AS=0.0P PS=5.6U M796 47 11 43 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=6.7U AS=0.0P PS=5.6U M797 47 11 43 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=6.7U AS=0.0P PS=5.6U M798 47 11 43 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=6.7U AS=0.0P PS=5.6U M799 47 11 43 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=6.7U AS=0.0P PS=5.6U M800 47 11 43 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=6.7U AS=0.0P PS=5.6U M801 48 11 18 3 NMOS W=11.5U L=0.7U + AD=0.0P PD=37.0U AS=0.0P PS=39.3U M802 1 46 46 3 NMOS W=11.2U L=0.7U + AD=0.0P PD=59.2U AS=0.0P PS=35.8U M803 45 44 36 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M804 45 44 36 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M805 45 44 36 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M806 45 44 36 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M807 45 44 36 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M808 45 44 36 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M809 45 44 36 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M810 45 44 36 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M811 45 44 37 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M812 45 44 37 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M813 45 44 37 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M814 45 44 37 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M815 45 44 37 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M816 45 44 37 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M817 45 44 37 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M818 45 44 37 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M819 45 44 38 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M820 45 44 38 3 NMOS W=1.4U L=0.7U
201
+ AD=0.0P PD=7.8U AS=0.0P PS=5.7U M821 45 44 38 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M822 45 44 38 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M823 45 44 38 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M824 45 44 38 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M825 45 44 38 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M826 45 44 38 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M827 45 44 39 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M828 45 44 39 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M829 45 44 39 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M830 45 44 39 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M831 45 44 39 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M832 45 44 39 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M833 45 44 39 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M834 45 44 39 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M835 45 44 40 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M836 45 44 40 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M837 45 44 40 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M838 45 44 40 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M839 45 44 40 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M840 45 44 40 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M841 45 44 40 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M842 45 44 40 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M843 45 44 41 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M844 45 44 41 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M845 45 44 41 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M846 45 44 41 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M847 45 44 41 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M848 45 44 41 3 NMOS W=1.4U L=0.7U
+ AD=0.0P PD=7.8U AS=0.0P PS=5.7U M849 45 44 41 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M850 45 44 41 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M851 45 44 42 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M852 45 44 42 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M853 45 44 42 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M854 45 44 42 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M855 45 44 42 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M856 45 44 42 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M857 45 44 42 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M858 45 44 42 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M859 34 44 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.4U M860 34 44 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.4U M861 34 44 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.4U M862 34 44 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.4U M863 34 44 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.4U M864 34 44 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.4U M865 34 44 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.4U M866 34 44 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.4U M867 35 44 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.4U M868 35 44 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.4U M869 35 44 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.4U M870 35 44 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.4U M871 35 44 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.4U M872 35 44 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.4U M873 35 44 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.4U M874 35 44 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.4U M875 1 46 47 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=6.7U M876 1 46 47 3 NMOS W=1.4U L=0.7U
202
+ AD=0.0P PD=7.4U AS=0.0P PS=6.7U M877 1 46 47 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=6.7U M878 1 46 47 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=6.7U M879 1 46 47 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=6.7U M880 1 46 47 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=6.7U M881 1 46 47 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=6.7U M882 1 46 47 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=6.7U M883 1 46 47 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=6.7U M884 1 46 47 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=6.7U M885 1 46 47 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=6.7U M886 1 46 47 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=6.7U M887 1 46 47 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=6.7U M888 1 46 47 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=6.7U M889 1 46 47 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=6.7U M890 1 46 47 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=6.7U M891 1 46 47 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=6.7U M892 1 46 48 3 NMOS W=11.5U L=0.7U + AD=0.0P PD=61.1U AS=0.0P PS=37.0U M893 36 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M894 36 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M895 36 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M896 36 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M897 36 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M898 36 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M899 36 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M900 36 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M901 37 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M902 37 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M903 37 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M904 37 44 45 3 NMOS W=1.4U L=0.7U
+ AD=0.0P PD=5.7U AS=0.0P PS=7.8U M905 37 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M906 37 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M907 37 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M908 37 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M909 38 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M910 38 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M911 38 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M912 38 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M913 38 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M914 38 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M915 38 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M916 38 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M917 39 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M918 39 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M919 39 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M920 39 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M921 39 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M922 39 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M923 39 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M924 39 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M925 40 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M926 40 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M927 40 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M928 40 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M929 40 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M930 40 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M931 40 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M932 40 44 45 3 NMOS W=1.4U L=0.7U
203
+ AD=0.0P PD=5.7U AS=0.0P PS=7.8U M933 41 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M934 41 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M935 41 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M936 41 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M937 41 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M938 41 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M939 41 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M940 41 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M941 42 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M942 42 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M943 42 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M944 42 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M945 42 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M946 42 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M947 42 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M948 42 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=5.7U AS=0.0P PS=7.8U M949 46 46 1 3 NMOS W=11.2U L=0.7U + AD=0.0P PD=35.8U AS=0.0P PS=59.2U M950 1 44 34 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=5.7U M951 1 44 34 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=5.7U M952 1 44 34 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=5.7U M953 1 44 34 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=5.7U M954 1 44 34 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=5.7U M955 1 44 34 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=5.7U M956 1 44 34 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=5.7U M957 1 44 34 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=5.7U M958 1 44 35 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=5.7U M959 1 44 35 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=5.7U M960 1 44 35 3 NMOS W=1.4U L=0.7U
+ AD=0.0P PD=7.4U AS=0.0P PS=5.7U M961 1 44 35 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=5.7U M962 1 44 35 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=5.7U M963 1 44 35 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=5.7U M964 1 44 35 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=5.7U M965 1 44 35 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=5.7U M966 47 46 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=6.7U AS=0.0P PS=7.4U M967 47 46 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=6.7U AS=0.0P PS=7.4U M968 47 46 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=6.7U AS=0.0P PS=7.4U M969 47 46 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=6.7U AS=0.0P PS=7.4U M970 47 46 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=6.7U AS=0.0P PS=7.4U M971 47 46 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=6.7U AS=0.0P PS=7.4U M972 47 46 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=6.7U AS=0.0P PS=7.4U M973 47 46 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=6.7U AS=0.0P PS=7.4U M974 47 46 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=6.7U AS=0.0P PS=7.4U M975 47 46 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=6.7U AS=0.0P PS=7.4U M976 47 46 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=6.7U AS=0.0P PS=7.4U M977 47 46 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=6.7U AS=0.0P PS=7.4U M978 47 46 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=6.7U AS=0.0P PS=7.4U M979 47 46 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=6.7U AS=0.0P PS=7.4U M980 47 46 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=6.7U AS=0.0P PS=7.4U M981 47 46 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=6.7U AS=0.0P PS=7.4U M982 47 46 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=6.7U AS=0.0P PS=7.4U M983 48 46 1 3 NMOS W=11.5U L=0.7U + AD=0.0P PD=37.0U AS=0.0P PS=61.1U M984 1 46 46 3 NMOS W=11.2U L=0.7U + AD=0.0P PD=59.2U AS=0.0P PS=35.8U M985 1 46 47 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=6.7U M986 1 46 47 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=6.7U M987 1 46 47 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=6.7U M988 1 46 47 3 NMOS W=1.4U L=0.7U
204
+ AD=0.0P PD=7.4U AS=0.0P PS=6.7U M989 1 46 47 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=6.7U M990 1 46 47 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=6.7U M991 1 46 47 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=6.7U M992 1 46 47 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=6.7U M993 1 46 47 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=6.7U M994 1 46 47 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=6.7U M995 1 46 47 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=6.7U M996 1 46 47 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=6.7U M997 1 46 47 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=6.7U M998 1 46 47 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=6.7U M999 1 46 47 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=6.7U M1000 1 46 47 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=6.7U M1001 1 46 47 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=6.7U M1002 1 46 48 3 NMOS W=11.5U L=0.7U + AD=0.0P PD=61.1U AS=0.0P PS=37.0U M1003 46 46 1 3 NMOS W=11.2U L=0.7U + AD=0.0P PD=35.8U AS=0.0P PS=59.2U M1004 47 46 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=6.7U AS=0.0P PS=7.4U M1005 47 46 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=6.7U AS=0.0P PS=7.4U M1006 47 46 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=6.7U AS=0.0P PS=7.4U M1007 47 46 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=6.7U AS=0.0P PS=7.4U M1008 47 46 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=6.7U AS=0.0P PS=7.4U M1009 47 46 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=6.7U AS=0.0P PS=7.4U M1010 47 46 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=6.7U AS=0.0P PS=7.4U M1011 47 46 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=6.7U AS=0.0P PS=7.4U M1012 47 46 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=6.7U AS=0.0P PS=7.4U M1013 47 46 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=6.7U AS=0.0P PS=7.4U M1014 47 46 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=6.7U AS=0.0P PS=7.4U M1015 47 46 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=6.7U AS=0.0P PS=7.4U M1016 47 46 1 3 NMOS W=1.4U L=0.7U
+ AD=0.0P PD=6.7U AS=0.0P PS=7.4U M1017 47 46 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=6.7U AS=0.0P PS=7.4U M1018 47 46 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=6.7U AS=0.0P PS=7.4U M1019 47 46 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=6.7U AS=0.0P PS=7.4U M1020 47 46 1 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=6.7U AS=0.0P PS=7.4U M1021 48 46 1 3 NMOS W=11.5U L=0.7U + AD=0.0P PD=37.0U AS=0.0P PS=61.1U M1022 1 46 46 3 NMOS W=11.2U L=0.7U + AD=0.0P PD=59.2U AS=0.0P PS=35.8U M1023 45 44 36 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M1024 45 44 36 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M1025 45 44 36 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M1026 45 44 36 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M1027 45 44 36 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M1028 45 44 36 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M1029 45 44 36 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M1030 45 44 36 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M1031 45 44 37 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M1032 45 44 37 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M1033 45 44 37 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M1034 45 44 37 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M1035 45 44 37 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M1036 45 44 37 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M1037 45 44 37 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M1038 45 44 37 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M1039 45 44 38 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M1040 45 44 38 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M1041 45 44 38 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M1042 45 44 38 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M1043 45 44 38 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M1044 45 44 38 3 NMOS W=1.4U L=0.7U
205
+ AD=0.0P PD=7.8U AS=0.0P PS=5.7U M1045 45 44 38 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M1046 45 44 38 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M1047 45 44 39 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M1048 45 44 39 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M1049 45 44 39 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M1050 45 44 39 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M1051 45 44 39 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M1052 45 44 39 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M1053 45 44 39 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M1054 45 44 39 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M1055 45 44 40 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M1056 45 44 40 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M1057 45 44 40 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M1058 45 44 40 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M1059 45 44 40 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M1060 45 44 40 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M1061 45 44 40 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M1062 45 44 40 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M1063 45 44 41 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M1064 45 44 41 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M1065 45 44 41 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M1066 45 44 41 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M1067 45 44 41 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M1068 45 44 41 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M1069 45 44 41 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M1070 45 44 41 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M1071 45 44 42 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M1072 45 44 42 3 NMOS W=1.4U L=0.7U
+ AD=0.0P PD=7.8U AS=0.0P PS=5.7U M1073 45 44 42 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M1074 45 44 42 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M1075 45 44 42 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M1076 45 44 42 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M1077 45 44 42 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M1078 45 44 42 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=5.7U M1079 1 46 47 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=6.7U M1080 1 46 47 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=6.7U M1081 1 46 47 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=6.7U M1082 1 46 47 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=6.7U M1083 1 46 47 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=6.7U M1084 1 46 47 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=6.7U M1085 1 46 47 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=6.7U M1086 1 46 47 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=6.7U M1087 1 46 47 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=6.7U M1088 1 46 47 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=6.7U M1089 1 46 47 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=6.7U M1090 1 46 47 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=6.7U M1091 1 46 47 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=6.7U M1092 1 46 47 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=6.7U M1093 1 46 47 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=6.7U M1094 1 46 47 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=6.7U M1095 1 46 47 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.4U AS=0.0P PS=6.7U M1096 1 46 48 3 NMOS W=11.5U L=0.7U + AD=0.0P PD=61.1U AS=0.0P PS=37.0U M1097 45 44 44 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=7.0U M1098 45 44 44 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=7.0U M1099 45 44 44 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=7.0U M1100 45 44 44 3 NMOS W=1.4U L=0.7U
206
+ AD=0.0P PD=7.8U AS=0.0P PS=7.0U M1101 45 44 44 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=7.0U M1102 45 44 44 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=7.0U M1103 45 44 44 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=7.0U M1104 45 44 44 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=7.0U M1105 44 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.0U AS=0.0P PS=7.8U M1106 44 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.0U AS=0.0P PS=7.8U M1107 44 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.0U AS=0.0P PS=7.8U M1108 44 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.0U AS=0.0P PS=7.8U M1109 44 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.0U AS=0.0P PS=7.8U M1110 44 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.0U AS=0.0P PS=7.8U M1111 44 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.0U AS=0.0P PS=7.8U M1112 44 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.0U AS=0.0P PS=7.8U M1113 45 44 44 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=7.0U M1114 45 44 44 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=7.0U M1115 45 44 44 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=7.0U M1116 45 44 44 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=7.0U M1117 45 44 44 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=7.0U M1118 45 44 44 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=7.0U M1119 45 44 44 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=7.0U M1120 45 44 44 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=7.0U M1121 44 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.0U AS=0.0P PS=7.8U M1122 44 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.0U AS=0.0P PS=7.8U M1123 44 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.0U AS=0.0P PS=7.8U M1124 44 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.0U AS=0.0P PS=7.8U M1125 44 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.0U AS=0.0P PS=7.8U M1126 44 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.0U AS=0.0P PS=7.8U M1127 44 44 45 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.0U AS=0.0P PS=7.8U M1128 44 44 45 3 NMOS W=1.4U L=0.7U
+ AD=0.0P PD=7.0U AS=0.0P PS=7.8U M1129 45 44 44 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=7.0U M1130 45 44 44 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=7.0U M1131 45 44 44 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=7.0U M1132 45 44 44 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=7.0U M1133 45 44 44 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=7.0U M1134 45 44 44 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=7.0U M1135 45 44 44 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=7.0U M1136 45 44 44 3 NMOS W=1.4U L=0.7U + AD=0.0P PD=7.8U AS=0.0P PS=7.0U C1 37 19 1.1F C2 36 21 1.1F C3 47 43 4.6F C4 44 35 4.2F C5 43 17 1.5F C6 45 36 3.9F C7 34 12 1.7F C8 41 29 1.7F C9 46 1 3.1F C10 38 23 1.7F C11 35 14 1.7F C12 44 39 4.2F C13 45 40 4.3F C14 42 33 1.1F C15 39 26 1.3F C16 9 1 155.1F C17 37 16 1.7F C18 36 19 1.3F C19 44 45 13.9F C20 44 34 4.2F C21 18 9 2.8F C22 43 12 1.5F C23 35 13 1.7F C24 41 28 1.7F C25 40 29 1.1F C26 9 6 24.9F C27 44 1 3.2F C28 35 1 4.3F C29 37 23 1.1F C30 47 46 1.4F C31 44 38 4.2F C32 17 12 1.7F C33 34 14 1.1F C34 45 39 4.3F C35 42 32 1.3F C36 37 4 1.7F C37 39 25 1.7F C38 43 11 3.4F
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C39 17 9 1.5F C40 36 8 1.7F C41 34 13 1.3F C42 40 28 1.3F C43 34 1 3.9F C44 37 22 1.3F C45 44 37 4.2F C46 45 38 4.5F C47 41 31 1.1F C48 42 31 1.7F C49 48 1 1.5F C50 39 24 1.7F C51 38 25 1.1F C52 6 1 5.7F C53 44 41 4.2F C54 48 18 1.5F C55 36 15 1.7F C56 35 16 1.1F C57 44 42 4.2F C58 12 9 1.5F C59 40 27 1.7F C60 38 19 1.7F C61 46 11 1.5F C62 43 18 2.2F C63 44 36 4.2F C64 45 37 4.3F C65 34 17 1.7F C66 41 30 1.3F C67 42 30 1.7F C68 17 1 1.1F C69 47 1 4.7F C70 38 24 1.3F C71 5 1 5.6F C72 18 17 1.6F C73 44 40 4.2F C74 35 15 1.3F C75 45 41 4.3F C76 45 42 4.3F C77 11 9 2.8F C78 40 26 1.7F C79 39 27 1.1F C80 21 0 11.1F C81 1 0 263.2F C82 37 0 27.9F C83 15 0 16.9F C84 30 0 14.9F C85 5 0 40.0F C86 48 0 14.8F C87 11 0 76.1F C88 46 0 44.2F C89 39 0 27.9F C90 19 0 19.5F C91 32 0 9.4F C92 33 0 12.4F C93 45 0 244.1F C94 23 0 17.8F
C95 42 0 27.9F C96 40 0 27.9F C97 44 0 287.3F C98 6 0 75.7F C99 27 0 17.9F C100 34 0 27.9F C101 8 0 21.6F C102 4 0 22.3F C103 22 0 8.1F C104 38 0 27.9F C105 29 0 17.9F C106 26 0 14.9F C107 41 0 27.9F C108 12 0 30.9F C109 17 0 28.1F C110 7 0 10.3F C111 35 0 27.9F C112 9 0 287.7F C113 25 0 17.9F C114 28 0 14.9F C115 43 0 53.4F C116 47 0 37.8F C117 36 0 27.9F C118 2 0 10.3F C119 31 0 17.9F C120 16 0 24.3F C121 14 0 17.9F C122 13 0 14.9F C123 20 0 86.3F C124 24 0 14.9F C125 18 0 44.3F *** Node Listing for subckt: Prc_Diff_Sim ** 0 Node 0 is the global ground node ** 1 Vss1_amp ** 2 a_626_432# ** 3 Gnd! ** 4 v_offset2 ** 5 Ibiasn2p ** 6 biasp ** 7 a_626_352# ** 8 v_offset1 ** 9 Vdd1_amp ** 10 Vdd! ** 11 I_Amp_in ** 12 cmAmp_out+ ** 13 vamp_out- ** 14 vamp_out+ ** 15 a_497_270# ** 16 a_497_228# ** 17 cmAmp_out- ** 18 iin2 ** 19 a_618_269# ** 20 Vdd2_amp ** 21 a_618_227# ** 22 a_699_269# ** 23 a_699_227#
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** 24 a_778_269# ** 25 a_778_227# ** 26 a_859_269# ** 27 a_859_227# ** 28 a_940_269# ** 29 a_940_227# ** 30 a_1021_269# ** 31 a_1021_227# ** 32 Amp_out1 ** 33 Amp_out2 ** 34 a_416_136# ** 35 a_497_136# ** 36 a_618_135# ** 37 a_699_135# ** 38 a_778_135# ** 39 a_859_135# ** 40 a_940_135# ** 41 a_1021_135# ** 42 a_1102_135# ** 43 com1 ** 44 biasn ** 45 Vss2_amp ** 46 gd1 ** 47 com2 ** 48 d2 .END
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Appendix 2.2.2. Prc Btc Low Input Impedance Optical Receiver SPICE
Input Control File
***** Differential Amplifier Simulation ***** .options ACCURATE post list .param I_1=-8u I_2=8u I_0=-8u bps=2.085n slope=0.001n *.temp 27 100 Vdd! 10 0 2.5v Vgnd! 3 0 -2.5v Vdd1 9 0 2.5v Vdd2 20 0 2.5v Vss1 1 0 -2.5v Vss2 45 0 -2.5v ************************************ Voffset1 8 0 -7mv Voffset2 4 0 76.8mv IbiasN 0 44 1m IbiasN2P 0 5 1.2m ************************************ C_in 0 11 1.0p V_in 981 11 0v I_in2 0 18 ac 0.5 I_in 0 981 ac 0.5 dc 0 pwl + (0ns,'I_1') ('2*bps-slope','I_1') + ('2*bps','I_2') ('9*bps','I_2') + ('9*bps+slope','I_1') ('10*bps','I_1') + ('10*bps+slope','I_2') ('11*bps','I_2') + ('11*bps+slope','I_1') ('18*bps','I_1') + ('18*bps+slope','I_2') ('19*bps','I_2') + ('19*bps+slope','I_1') ('20*bps','I_1') + ('20*bps+slope','I_2') ('22*bps','I_2') + ('22*bps+slope','I_1') ('23*bps','I_1') + ('23*bps+slope','I_2') ('24*bps','I_2') + ('24*bps+slope','I_1') ('26*bps','I_1') + ('26*bps+slope','I_2') ('28*bps','I_2') + ,R Vdum 999 0 pulse 0 1 0n '3*bps-slope/100' 'slope/100' 0n '3*bps' Rout1 32 0 50 Rout2 33 0 50 .include '../../../MISC/LIB/0.5_model/05model_13.lib' .tran .01n 200n .ac Dec 1000 1mega 10giga
210
.noise V(17) I_in 10000 cmAmp output = 12 and 17 .plot noise onoise .dc Voffset1 -1m 1m .1m .include 'Prc_Diff_Sim.spice' .op .end
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Appendix 2.2.3. NSC Transimpedance Optical Receiver Netlist
***** top level cell is ./FRONT_POST3_SIM.ext M1 1 2 2 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.2U AS=0.0P PS=2.4U M2 2 2 1 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.4U AS=0.0P PS=3.2U M3 4 1 1 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=3.2U M4 1 1 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.2U AS=0.0P PS=2.8U M5 1 2 2 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.2U AS=0.0P PS=2.4U M6 2 2 1 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.4U AS=0.0P PS=3.2U M7 4 1 1 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=3.2U M8 1 1 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.2U AS=0.0P PS=2.8U M9 1 2 2 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.2U AS=0.0P PS=2.4U M10 2 2 1 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.4U AS=0.0P PS=3.2U M11 4 1 1 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=3.2U M12 1 1 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.2U AS=0.0P PS=2.8U M13 5 6 6 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.2U AS=0.0P PS=2.4U M14 6 6 5 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.4U AS=0.0P PS=3.2U M15 4 5 5 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=3.2U M16 5 5 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.2U AS=0.0P PS=2.8U M17 5 6 6 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.2U AS=0.0P PS=2.4U M18 6 6 5 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.4U AS=0.0P PS=3.2U M19 4 5 5 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=3.2U M20 5 5 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.2U AS=0.0P PS=2.8U M21 5 6 6 3 NMOS W=0.8U L=0.4U
+ AD=0.0P PD=3.2U AS=0.0P PS=2.4U M22 6 6 5 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.4U AS=0.0P PS=3.2U M23 4 5 5 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=3.2U M24 5 5 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.2U AS=0.0P PS=2.8U M25 7 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M26 7 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M27 7 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M28 7 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M29 7 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M30 7 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M31 7 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M32 7 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M33 7 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M34 7 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M35 7 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M36 7 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M37 9 8 7 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M38 9 8 7 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M39 9 8 7 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M40 9 8 7 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M41 9 8 7 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M42 9 8 7 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M43 9 8 7 10 PMOS W=0.8U L=0.4U
212
+ AD=0.3P PD=3.0U AS=0.3P PS=2.4U M44 9 8 7 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M45 9 8 7 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M46 9 8 7 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M47 9 8 7 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M48 9 8 7 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M49 7 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M50 7 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M51 7 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M52 7 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M53 7 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M54 7 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M55 7 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M56 7 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M57 7 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M58 7 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M59 7 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M60 7 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M61 9 8 7 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M62 9 8 7 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M63 9 8 7 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M64 9 8 7 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M65 9 8 7 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M66 9 8 7 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M67 9 8 7 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M68 9 8 7 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M69 9 8 7 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M70 9 8 7 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M71 9 8 7 10 PMOS W=0.8U L=0.4U
+ AD=0.3P PD=3.0U AS=0.3P PS=2.4U M72 9 8 7 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M73 7 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M74 7 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M75 7 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M76 7 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M77 7 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M78 7 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M79 7 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M80 7 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M81 7 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M82 7 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M83 7 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M84 7 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M85 9 8 7 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M86 9 8 7 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M87 9 8 7 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M88 9 8 7 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M89 9 8 7 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M90 9 8 7 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M91 9 8 7 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M92 9 8 7 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M93 9 8 7 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M94 9 8 7 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M95 9 8 7 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M96 9 8 7 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M97 7 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M98 7 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M99 7 8 9 10 PMOS W=0.8U L=0.4U
213
+ AD=0.3P PD=2.4U AS=0.3P PS=3.0U M100 7 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M101 7 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M102 7 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M103 7 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M104 7 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M105 7 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M106 7 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M107 7 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M108 7 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M109 9 8 7 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M110 9 8 7 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M111 9 8 7 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M112 9 8 7 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M113 9 8 7 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M114 9 8 7 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M115 9 8 7 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M116 9 8 7 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M117 9 8 7 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M118 9 8 7 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M119 9 8 7 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M120 9 8 7 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M121 11 12 13 10 PMOS W=6.4U L=0.4U + AD=2.2P PD=21.8U AS=2.5P PS=21.8U M122 14 15 13 10 PMOS W=6.4U L=0.4U + AD=2.2P PD=21.8U AS=2.5P PS=21.8U M123 16 13 13 3 NMOS W=6.4U L=0.4U + AD=0.0P PD=21.8U AS=0.0P PS=33.3U M124 17 13 13 3 NMOS W=6.4U L=0.4U + AD=0.0P PD=21.8U AS=0.0P PS=33.3U M125 13 12 11 10 PMOS W=6.4U L=0.4U + AD=2.5P PD=21.8U AS=2.2P PS=21.8U M126 18 9 9 3 NMOS W=15.2U L=0.4U + AD=0.0P PD=45.6U AS=0.0P PS=207.4U M127 7 9 9 3 NMOS W=15.2U L=0.4U
+ AD=0.0P PD=45.6U AS=0.0P PS=207.4U M128 9 9 18 3 NMOS W=15.2U L=0.4U + AD=0.0P PD=207.4U AS=0.0P PS=45.6U M129 9 9 7 3 NMOS W=15.2U L=0.4U + AD=0.0P PD=207.4U AS=0.0P PS=45.6U M130 13 15 14 10 PMOS W=6.4U L=0.4U + AD=2.5P PD=21.8U AS=2.2P PS=21.8U M131 13 13 16 3 NMOS W=6.4U L=0.4U + AD=0.0P PD=33.3U AS=0.0P PS=21.8U M132 13 13 17 3 NMOS W=6.4U L=0.4U + AD=0.0P PD=33.3U AS=0.0P PS=21.8U M133 11 12 13 10 PMOS W=6.4U L=0.4U + AD=2.2P PD=21.8U AS=2.5P PS=21.8U M134 14 15 13 10 PMOS W=6.4U L=0.4U + AD=2.2P PD=21.8U AS=2.5P PS=21.8U M135 16 13 13 3 NMOS W=6.4U L=0.4U + AD=0.0P PD=21.8U AS=0.0P PS=33.3U M136 17 13 13 3 NMOS W=6.4U L=0.4U + AD=0.0P PD=21.8U AS=0.0P PS=33.3U M137 13 12 11 10 PMOS W=6.4U L=0.4U + AD=2.5P PD=21.8U AS=2.2P PS=21.8U M138 13 15 14 10 PMOS W=6.4U L=0.4U + AD=2.5P PD=21.8U AS=2.2P PS=21.8U M139 13 13 16 3 NMOS W=6.4U L=0.4U + AD=0.0P PD=33.3U AS=0.0P PS=21.8U M140 13 13 17 3 NMOS W=6.4U L=0.4U + AD=0.0P PD=33.3U AS=0.0P PS=21.8U M141 11 12 13 10 PMOS W=6.4U L=0.4U + AD=2.2P PD=21.8U AS=2.5P PS=21.8U M142 19 9 9 3 NMOS W=2.6U L=0.4U + AD=0.0P PD=9.2U AS=0.0P PS=35.5U M143 20 9 9 3 NMOS W=2.4U L=0.4U + AD=0.0P PD=8.4U AS=0.0P PS=32.7U M144 20 21 9 10 PMOS W=0.8U L=0.4U + AD=0.6P PD=2.4U AS=0.3P PS=3.0U M145 20 21 9 10 PMOS W=0.8U L=0.4U + AD=0.6P PD=2.4U AS=0.3P PS=3.0U M146 20 21 9 10 PMOS W=0.8U L=0.4U + AD=0.6P PD=2.4U AS=0.3P PS=3.0U M147 14 15 13 10 PMOS W=6.4U L=0.4U + AD=2.2P PD=21.8U AS=2.5P PS=21.8U M148 22 9 9 3 NMOS W=2.4U L=0.4U + AD=0.0P PD=8.4U AS=0.0P PS=32.7U M149 23 9 9 3 NMOS W=2.4U L=0.4U + AD=0.0P PD=8.4U AS=0.0P PS=32.7U M150 23 24 9 10 PMOS W=0.8U L=0.4U + AD=0.6P PD=2.4U AS=0.3P PS=3.0U M151 23 24 9 10 PMOS W=0.8U L=0.4U + AD=0.6P PD=2.4U AS=0.3P PS=3.0U M152 23 24 9 10 PMOS W=0.8U L=0.4U + AD=0.6P PD=2.4U AS=0.3P PS=3.0U M153 25 9 9 3 NMOS W=2.4U L=0.4U + AD=0.0P PD=8.4U AS=0.0P PS=32.7U M154 26 9 9 3 NMOS W=2.4U L=0.4U + AD=0.0P PD=8.4U AS=0.0P PS=32.7U M155 26 27 9 10 PMOS W=0.8U L=0.4U
214
+ AD=0.6P PD=2.4U AS=0.3P PS=3.0U M156 26 27 9 10 PMOS W=0.8U L=0.4U + AD=0.6P PD=2.4U AS=0.3P PS=3.0U M157 26 27 9 10 PMOS W=0.8U L=0.4U + AD=0.6P PD=2.4U AS=0.3P PS=3.0U M158 28 9 9 3 NMOS W=2.6U L=0.4U + AD=0.0P PD=9.2U AS=0.0P PS=35.5U M159 29 9 9 3 NMOS W=2.4U L=0.4U + AD=0.0P PD=8.4U AS=0.0P PS=32.7U M160 29 30 9 10 PMOS W=0.8U L=0.4U + AD=0.6P PD=2.4U AS=0.3P PS=3.0U M161 29 30 9 10 PMOS W=0.8U L=0.4U + AD=0.6P PD=2.4U AS=0.3P PS=3.0U M162 29 30 9 10 PMOS W=0.8U L=0.4U + AD=0.6P PD=2.4U AS=0.3P PS=3.0U M163 31 9 9 3 NMOS W=2.6U L=0.4U + AD=0.0P PD=9.2U AS=0.0P PS=35.5U M164 32 9 9 3 NMOS W=2.4U L=0.4U + AD=0.0P PD=8.4U AS=0.0P PS=32.7U M165 32 33 9 10 PMOS W=0.8U L=0.4U + AD=0.6P PD=2.4U AS=0.3P PS=3.0U M166 32 33 9 10 PMOS W=0.8U L=0.4U + AD=0.6P PD=2.4U AS=0.3P PS=3.0U M167 32 33 9 10 PMOS W=0.8U L=0.4U + AD=0.6P PD=2.4U AS=0.3P PS=3.0U M168 16 13 13 3 NMOS W=6.4U L=0.4U + AD=0.0P PD=21.8U AS=0.0P PS=33.3U M169 17 13 13 3 NMOS W=6.4U L=0.4U + AD=0.0P PD=21.8U AS=0.0P PS=33.3U M170 34 12 11 3 NMOS W=6.4U L=0.4U + AD=0.0P PD=28.5U AS=0.0P PS=22.7U M171 9 21 20 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.6P PS=2.4U M172 9 21 20 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.6P PS=2.4U M173 9 21 20 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.6P PS=2.4U M174 35 9 9 3 NMOS W=5.0U L=0.4U + AD=0.0P PD=15.0U AS=0.0P PS=68.2U M175 36 9 9 3 NMOS W=5.0U L=0.4U + AD=0.0P PD=15.0U AS=0.0P PS=68.2U M176 18 35 37 3 NMOS W=28.8U L=0.4U + AD=0.0P PD=86.4U AS=0.0P PS=100.8U M177 9 9 35 3 NMOS W=5.0U L=0.4U + AD=0.0P PD=68.2U AS=0.0P PS=15.0U M178 9 9 36 3 NMOS W=5.0U L=0.4U + AD=0.0P PD=68.2U AS=0.0P PS=15.0U M179 37 35 18 3 NMOS W=28.8U L=0.4U + AD=0.0P PD=100.8U AS=0.0P PS=86.4U M180 34 15 14 3 NMOS W=6.4U L=0.4U + AD=0.0P PD=28.5U AS=0.0P PS=22.7U M181 9 24 23 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.6P PS=2.4U M182 9 24 23 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.6P PS=2.4U M183 9 24 23 10 PMOS W=0.8U L=0.4U
+ AD=0.3P PD=3.0U AS=0.6P PS=2.4U M184 9 27 26 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.6P PS=2.4U M185 9 27 26 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.6P PS=2.4U M186 9 27 26 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.6P PS=2.4U M187 9 30 29 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.6P PS=2.4U M188 9 30 29 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.6P PS=2.4U M189 9 30 29 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.6P PS=2.4U M190 9 33 32 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.6P PS=2.4U M191 9 33 32 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.6P PS=2.4U M192 9 33 32 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.6P PS=2.4U M193 19 16 38 3 NMOS W=3.6U L=0.4U + AD=0.0P PD=12.7U AS=0.0P PS=15.6U M194 19 21 9 10 PMOS W=0.8U L=0.4U + AD=0.6P PD=2.4U AS=0.3P PS=3.0U M195 19 21 9 10 PMOS W=0.8U L=0.4U + AD=0.6P PD=2.4U AS=0.3P PS=3.0U M196 19 21 9 10 PMOS W=0.8U L=0.4U + AD=0.6P PD=2.4U AS=0.3P PS=3.0U M197 22 19 39 3 NMOS W=3.6U L=0.4U + AD=0.0P PD=12.6U AS=0.0P PS=15.6U M198 22 24 9 10 PMOS W=0.8U L=0.4U + AD=0.6P PD=2.4U AS=0.3P PS=3.0U M199 22 24 9 10 PMOS W=0.8U L=0.4U + AD=0.6P PD=2.4U AS=0.3P PS=3.0U M200 22 24 9 10 PMOS W=0.8U L=0.4U + AD=0.6P PD=2.4U AS=0.3P PS=3.0U M201 39 19 22 3 NMOS W=3.6U L=0.4U + AD=0.0P PD=15.6U AS=0.0P PS=12.6U M202 38 16 19 3 NMOS W=3.6U L=0.4U + AD=0.0P PD=15.6U AS=0.0P PS=12.7U M203 9 21 19 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.6P PS=2.4U M204 9 21 19 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.6P PS=2.4U M205 9 21 19 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.6P PS=2.4U M206 40 11 16 3 NMOS W=6.4U L=0.4U + AD=0.0P PD=28.5U AS=0.0P PS=21.8U M207 40 14 17 3 NMOS W=6.4U L=0.4U + AD=0.0P PD=28.5U AS=0.0P PS=21.8U M208 12 13 11 3 NMOS W=3.2U L=0.4U + AD=0.0P PD=16.0U AS=0.0P PS=11.3U M209 11 12 34 3 NMOS W=6.4U L=0.4U + AD=0.0P PD=22.7U AS=0.0P PS=28.5U M210 14 15 34 3 NMOS W=6.4U L=0.4U + AD=0.0P PD=22.7U AS=0.0P PS=28.5U M211 16 11 40 3 NMOS W=6.4U L=0.4U
215
+ AD=0.0P PD=21.8U AS=0.0P PS=28.5U M212 17 14 40 3 NMOS W=6.4U L=0.4U + AD=0.0P PD=21.8U AS=0.0P PS=28.5U M213 34 12 11 3 NMOS W=6.4U L=0.4U + AD=0.0P PD=28.5U AS=0.0P PS=22.7U M214 34 15 14 3 NMOS W=6.4U L=0.4U + AD=0.0P PD=28.5U AS=0.0P PS=22.7U M215 40 11 16 3 NMOS W=6.4U L=0.4U + AD=0.0P PD=28.5U AS=0.0P PS=21.8U M216 40 14 17 3 NMOS W=6.4U L=0.4U + AD=0.0P PD=28.5U AS=0.0P PS=21.8U M217 11 12 34 3 NMOS W=6.4U L=0.4U + AD=0.0P PD=22.7U AS=0.0P PS=28.5U M218 14 13 15 3 NMOS W=3.2U L=0.4U + AD=0.0P PD=11.3U AS=0.0P PS=16.0U M219 20 17 38 3 NMOS W=3.6U L=0.4U + AD=0.0P PD=12.6U AS=0.0P PS=15.6U M220 25 6 41 3 NMOS W=3.6U L=0.4U + AD=0.0P PD=12.6U AS=0.0P PS=15.6U M221 25 27 9 10 PMOS W=0.8U L=0.4U + AD=0.6P PD=2.4U AS=0.3P PS=3.0U M222 25 27 9 10 PMOS W=0.8U L=0.4U + AD=0.6P PD=2.4U AS=0.3P PS=3.0U M223 25 27 9 10 PMOS W=0.8U L=0.4U + AD=0.6P PD=2.4U AS=0.3P PS=3.0U M224 41 6 25 3 NMOS W=3.6U L=0.4U + AD=0.0P PD=15.6U AS=0.0P PS=12.6U M225 9 24 22 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.6P PS=2.4U M226 9 24 22 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.6P PS=2.4U M227 9 24 22 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.6P PS=2.4U M228 23 2 39 3 NMOS W=3.6U L=0.4U + AD=0.0P PD=12.6U AS=0.0P PS=15.6U M229 21 21 9 10 PMOS W=0.8U L=0.4U + AD=0.8P PD=4.0U AS=0.3P PS=3.0U M230 21 21 9 10 PMOS W=0.8U L=0.4U + AD=0.8P PD=4.0U AS=0.3P PS=3.0U M231 21 21 9 10 PMOS W=0.8U L=0.4U + AD=0.8P PD=4.0U AS=0.3P PS=3.0U M232 14 15 34 3 NMOS W=6.4U L=0.4U + AD=0.0P PD=22.7U AS=0.0P PS=28.5U M233 38 17 20 3 NMOS W=3.6U L=0.4U + AD=0.0P PD=15.6U AS=0.0P PS=12.6U M234 9 27 25 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.6P PS=2.4U M235 9 27 25 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.6P PS=2.4U M236 9 27 25 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.6P PS=2.4U M237 28 26 42 3 NMOS W=3.6U L=0.4U + AD=0.0P PD=12.7U AS=0.0P PS=15.6U M238 28 30 9 10 PMOS W=0.8U L=0.4U + AD=0.6P PD=2.4U AS=0.3P PS=3.0U M239 28 30 9 10 PMOS W=0.8U L=0.4U
+ AD=0.6P PD=2.4U AS=0.3P PS=3.0U M240 28 30 9 10 PMOS W=0.8U L=0.4U + AD=0.6P PD=2.4U AS=0.3P PS=3.0U M241 42 26 28 3 NMOS W=3.6U L=0.4U + AD=0.0P PD=15.6U AS=0.0P PS=12.7U M242 9 30 28 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.6P PS=2.4U M243 9 30 28 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.6P PS=2.4U M244 9 30 28 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.6P PS=2.4U M245 26 20 41 3 NMOS W=3.6U L=0.4U + AD=0.0P PD=12.6U AS=0.0P PS=15.6U M246 24 24 9 10 PMOS W=0.8U L=0.4U + AD=0.8P PD=4.0U AS=0.3P PS=3.0U M247 24 24 9 10 PMOS W=0.8U L=0.4U + AD=0.8P PD=4.0U AS=0.3P PS=3.0U M248 24 24 9 10 PMOS W=0.8U L=0.4U + AD=0.8P PD=4.0U AS=0.3P PS=3.0U M249 39 2 23 3 NMOS W=3.6U L=0.4U + AD=0.0P PD=15.6U AS=0.0P PS=12.6U M250 29 22 42 3 NMOS W=3.6U L=0.4U + AD=0.0P PD=12.6U AS=0.0P PS=15.6U M251 27 27 9 10 PMOS W=0.8U L=0.4U + AD=0.8P PD=4.0U AS=0.3P PS=3.0U M252 27 27 9 10 PMOS W=0.8U L=0.4U + AD=0.8P PD=4.0U AS=0.3P PS=3.0U M253 27 27 9 10 PMOS W=0.8U L=0.4U + AD=0.8P PD=4.0U AS=0.3P PS=3.0U M254 41 20 26 3 NMOS W=3.6U L=0.4U + AD=0.0P PD=15.6U AS=0.0P PS=12.6U M255 43 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M256 43 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M257 43 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M258 43 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M259 43 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M260 43 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M261 43 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M262 43 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M263 43 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M264 43 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M265 43 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M266 43 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M267 9 44 43 10 PMOS W=0.8U L=0.4U
216
+ AD=0.3P PD=3.0U AS=0.3P PS=2.4U M268 9 44 43 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M269 9 44 43 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M270 9 44 43 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M271 9 44 43 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M272 9 44 43 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M273 9 44 43 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M274 9 44 43 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M275 9 44 43 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M276 9 44 43 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M277 9 44 43 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M278 9 44 43 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M279 43 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M280 43 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M281 43 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M282 43 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M283 43 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M284 43 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M285 43 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M286 43 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M287 43 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M288 43 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M289 43 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M290 43 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M291 9 44 43 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M292 9 44 43 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M293 9 44 43 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M294 9 44 43 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M295 9 44 43 10 PMOS W=0.8U L=0.4U
+ AD=0.3P PD=3.0U AS=0.3P PS=2.4U M296 9 44 43 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M297 9 44 43 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M298 9 44 43 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M299 9 44 43 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M300 9 44 43 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M301 9 44 43 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M302 9 44 43 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M303 43 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M304 43 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M305 43 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M306 43 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M307 43 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M308 43 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M309 43 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M310 43 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M311 43 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M312 43 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M313 43 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M314 43 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M315 9 44 43 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M316 9 44 43 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M317 9 44 43 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M318 9 44 43 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M319 9 44 43 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M320 9 44 43 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M321 9 44 43 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M322 9 44 43 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M323 9 44 43 10 PMOS W=0.8U L=0.4U
217
+ AD=0.3P PD=3.0U AS=0.3P PS=2.4U M324 9 44 43 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M325 9 44 43 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M326 9 44 43 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M327 43 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M328 43 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M329 43 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M330 43 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M331 43 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M332 43 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M333 43 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M334 43 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M335 43 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M336 43 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M337 43 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M338 43 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M339 9 44 43 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M340 9 44 43 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M341 9 44 43 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M342 9 44 43 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M343 9 44 43 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M344 9 44 43 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M345 9 44 43 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M346 9 44 43 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M347 9 44 43 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M348 9 44 43 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M349 9 44 43 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M350 9 44 43 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M351 18 8 9 10 PMOS W=0.8U L=0.4U
+ AD=0.3P PD=2.4U AS=0.3P PS=3.0U M352 18 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M353 18 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M354 18 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M355 18 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M356 18 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M357 18 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M358 18 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M359 18 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M360 18 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M361 18 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M362 18 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M363 9 8 18 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M364 9 8 18 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M365 9 8 18 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M366 9 8 18 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M367 9 8 18 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M368 9 8 18 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M369 9 8 18 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M370 9 8 18 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M371 9 8 18 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M372 9 8 18 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M373 9 8 18 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M374 9 8 18 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M375 18 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M376 18 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M377 18 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M378 18 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M379 18 8 9 10 PMOS W=0.8U L=0.4U
218
+ AD=0.3P PD=2.4U AS=0.3P PS=3.0U M380 18 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M381 18 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M382 18 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M383 18 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M384 18 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M385 18 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M386 18 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M387 9 8 18 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M388 9 8 18 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M389 9 8 18 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M390 9 8 18 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M391 9 8 18 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M392 9 8 18 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M393 9 8 18 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M394 9 8 18 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M395 9 8 18 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M396 9 8 18 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M397 9 8 18 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M398 9 8 18 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M399 18 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M400 18 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M401 18 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M402 18 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M403 18 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M404 18 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M405 18 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M406 18 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M407 18 8 9 10 PMOS W=0.8U L=0.4U
+ AD=0.3P PD=2.4U AS=0.3P PS=3.0U M408 18 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M409 18 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M410 18 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M411 9 8 18 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M412 9 8 18 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M413 9 8 18 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M414 9 8 18 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M415 9 8 18 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M416 9 8 18 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M417 9 8 18 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M418 9 8 18 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M419 9 8 18 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M420 9 8 18 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M421 9 8 18 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M422 9 8 18 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M423 18 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M424 18 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M425 18 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M426 18 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M427 18 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M428 18 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M429 18 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M430 18 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M431 18 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M432 18 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M433 18 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M434 18 8 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M435 9 8 18 10 PMOS W=0.8U L=0.4U
219
+ AD=0.3P PD=3.0U AS=0.3P PS=2.4U M436 9 8 18 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M437 9 8 18 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M438 9 8 18 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M439 9 8 18 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M440 9 8 18 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M441 9 8 18 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M442 9 8 18 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M443 9 8 18 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M444 9 8 18 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M445 9 8 18 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M446 9 8 18 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M447 18 35 37 3 NMOS W=28.8U L=0.4U + AD=0.0P PD=86.4U AS=0.0P PS=100.8U M448 37 35 18 3 NMOS W=28.8U L=0.4U + AD=0.0P PD=100.8U AS=0.0P PS=86.4U M449 35 31 45 3 NMOS W=6.0U L=0.4U + AD=0.0P PD=18.0U AS=0.0P PS=23.5U M450 31 28 46 3 NMOS W=3.6U L=0.4U + AD=0.0P PD=12.7U AS=0.0P PS=15.6U M451 31 33 9 10 PMOS W=0.8U L=0.4U + AD=0.6P PD=2.4U AS=0.3P PS=3.0U M452 31 33 9 10 PMOS W=0.8U L=0.4U + AD=0.6P PD=2.4U AS=0.3P PS=3.0U M453 31 33 9 10 PMOS W=0.8U L=0.4U + AD=0.6P PD=2.4U AS=0.3P PS=3.0U M454 45 31 35 3 NMOS W=6.0U L=0.4U + AD=0.0P PD=23.5U AS=0.0P PS=18.0U M455 46 28 31 3 NMOS W=3.6U L=0.4U + AD=0.0P PD=15.6U AS=0.0P PS=12.7U M456 9 33 31 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.6P PS=2.4U M457 9 33 31 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.6P PS=2.4U M458 9 33 31 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.6P PS=2.4U M459 32 29 46 3 NMOS W=3.6U L=0.4U + AD=0.0P PD=12.6U AS=0.0P PS=15.6U M460 30 30 9 10 PMOS W=0.8U L=0.4U + AD=0.8P PD=4.0U AS=0.3P PS=3.0U M461 30 30 9 10 PMOS W=0.8U L=0.4U + AD=0.8P PD=4.0U AS=0.3P PS=3.0U M462 30 30 9 10 PMOS W=0.8U L=0.4U + AD=0.8P PD=4.0U AS=0.3P PS=3.0U M463 16 11 40 3 NMOS W=6.4U L=0.4U
+ AD=0.0P PD=21.8U AS=0.0P PS=28.5U M464 17 14 40 3 NMOS W=6.4U L=0.4U + AD=0.0P PD=21.8U AS=0.0P PS=28.5U M465 34 12 11 3 NMOS W=6.4U L=0.4U + AD=0.0P PD=28.5U AS=0.0P PS=22.7U M466 42 22 29 3 NMOS W=3.6U L=0.4U + AD=0.0P PD=15.6U AS=0.0P PS=12.6U M467 7 36 37 3 NMOS W=28.8U L=0.4U + AD=0.0P PD=86.4U AS=0.0P PS=100.8U M468 37 36 7 3 NMOS W=28.8U L=0.4U + AD=0.0P PD=100.8U AS=0.0P PS=86.4U M469 36 32 45 3 NMOS W=6.0U L=0.4U + AD=0.0P PD=18.0U AS=0.0P PS=23.5U M470 7 36 37 3 NMOS W=28.8U L=0.4U + AD=0.0P PD=86.4U AS=0.0P PS=100.8U M471 45 32 36 3 NMOS W=6.0U L=0.4U + AD=0.0P PD=23.5U AS=0.0P PS=18.0U M472 33 33 9 10 PMOS W=0.8U L=0.4U + AD=0.8P PD=4.0U AS=0.3P PS=3.0U M473 33 33 9 10 PMOS W=0.8U L=0.4U + AD=0.8P PD=4.0U AS=0.3P PS=3.0U M474 33 33 9 10 PMOS W=0.8U L=0.4U + AD=0.8P PD=4.0U AS=0.3P PS=3.0U M475 46 29 32 3 NMOS W=3.6U L=0.4U + AD=0.0P PD=15.6U AS=0.0P PS=12.6U M476 37 36 7 3 NMOS W=28.8U L=0.4U + AD=0.0P PD=100.8U AS=0.0P PS=86.4U M477 34 15 14 3 NMOS W=6.4U L=0.4U + AD=0.0P PD=28.5U AS=0.0P PS=22.7U M478 47 9 9 3 NMOS W=15.2U L=0.4U + AD=0.0P PD=45.6U AS=0.0P PS=207.4U M479 43 9 9 3 NMOS W=15.2U L=0.4U + AD=0.0P PD=45.6U AS=0.0P PS=207.4U M480 9 9 47 3 NMOS W=15.2U L=0.4U + AD=0.0P PD=207.4U AS=0.0P PS=45.6U M481 9 9 43 3 NMOS W=15.2U L=0.4U + AD=0.0P PD=207.4U AS=0.0P PS=45.6U M482 47 18 48 3 NMOS W=28.8U L=0.4U + AD=0.0P PD=86.4U AS=0.0P PS=100.8U M483 48 18 47 3 NMOS W=28.8U L=0.4U + AD=0.0P PD=100.8U AS=0.0P PS=86.4U M484 47 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M485 47 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M486 47 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M487 47 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M488 47 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M489 47 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M490 47 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M491 47 44 9 10 PMOS W=0.8U L=0.4U
220
+ AD=0.3P PD=2.4U AS=0.3P PS=3.0U M492 47 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M493 47 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M494 47 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M495 47 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M496 9 44 47 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M497 9 44 47 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M498 9 44 47 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M499 9 44 47 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M500 9 44 47 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M501 9 44 47 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M502 9 44 47 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M503 9 44 47 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M504 9 44 47 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M505 9 44 47 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M506 9 44 47 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M507 9 44 47 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M508 47 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M509 47 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M510 47 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M511 47 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M512 47 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M513 47 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M514 47 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M515 47 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M516 47 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M517 47 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M518 47 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M519 47 44 9 10 PMOS W=0.8U L=0.4U
+ AD=0.3P PD=2.4U AS=0.3P PS=3.0U M520 9 44 47 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M521 9 44 47 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M522 9 44 47 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M523 9 44 47 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M524 9 44 47 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M525 9 44 47 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M526 9 44 47 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M527 9 44 47 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M528 9 44 47 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M529 9 44 47 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M530 9 44 47 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M531 9 44 47 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M532 47 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M533 47 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M534 47 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M535 47 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M536 47 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M537 47 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M538 47 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M539 47 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M540 47 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M541 47 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M542 47 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M543 47 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M544 9 44 47 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M545 9 44 47 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M546 9 44 47 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M547 9 44 47 10 PMOS W=0.8U L=0.4U
221
+ AD=0.3P PD=3.0U AS=0.3P PS=2.4U M548 9 44 47 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M549 9 44 47 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M550 9 44 47 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M551 9 44 47 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M552 9 44 47 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M553 9 44 47 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M554 9 44 47 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M555 9 44 47 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M556 47 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M557 47 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M558 47 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M559 47 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M560 47 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M561 47 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M562 47 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M563 47 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M564 47 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M565 47 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M566 47 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M567 47 44 9 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=2.4U AS=0.3P PS=3.0U M568 9 44 47 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M569 9 44 47 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M570 9 44 47 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M571 9 44 47 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M572 9 44 47 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M573 9 44 47 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M574 9 44 47 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M575 9 44 47 10 PMOS W=0.8U L=0.4U
+ AD=0.3P PD=3.0U AS=0.3P PS=2.4U M576 9 44 47 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M577 9 44 47 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M578 9 44 47 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M579 9 44 47 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.3P PS=2.4U M580 47 18 48 3 NMOS W=28.8U L=0.4U + AD=0.0P PD=86.4U AS=0.0P PS=100.8U M581 48 18 47 3 NMOS W=28.8U L=0.4U + AD=0.0P PD=100.8U AS=0.0P PS=86.4U M582 8 8 9 10 PMOS W=0.8U L=0.4U + AD=0.6P PD=2.4U AS=0.3P PS=3.0U M583 8 8 9 10 PMOS W=0.8U L=0.4U + AD=0.6P PD=2.4U AS=0.3P PS=3.0U M584 8 8 9 10 PMOS W=0.8U L=0.4U + AD=0.6P PD=2.4U AS=0.3P PS=3.0U M585 8 8 9 10 PMOS W=0.8U L=0.4U + AD=0.6P PD=2.4U AS=0.3P PS=3.0U M586 8 8 9 10 PMOS W=0.8U L=0.4U + AD=0.6P PD=2.4U AS=0.3P PS=3.0U M587 8 8 9 10 PMOS W=0.8U L=0.4U + AD=0.6P PD=2.4U AS=0.3P PS=3.0U M588 8 8 9 10 PMOS W=0.8U L=0.4U + AD=0.6P PD=2.4U AS=0.3P PS=3.0U M589 8 8 9 10 PMOS W=0.8U L=0.4U + AD=0.6P PD=2.4U AS=0.3P PS=3.0U M590 8 8 9 10 PMOS W=0.8U L=0.4U + AD=0.6P PD=2.4U AS=0.3P PS=3.0U M591 8 8 9 10 PMOS W=0.8U L=0.4U + AD=0.6P PD=2.4U AS=0.3P PS=3.0U M592 8 8 9 10 PMOS W=0.8U L=0.4U + AD=0.6P PD=2.4U AS=0.3P PS=3.0U M593 8 8 9 10 PMOS W=0.8U L=0.4U + AD=0.6P PD=2.4U AS=0.3P PS=3.0U M594 9 8 8 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.6P PS=2.4U M595 9 8 8 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.6P PS=2.4U M596 9 8 8 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.6P PS=2.4U M597 9 8 8 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.6P PS=2.4U M598 9 8 8 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.6P PS=2.4U M599 9 8 8 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.6P PS=2.4U M600 9 8 8 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.6P PS=2.4U M601 9 8 8 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.6P PS=2.4U M602 9 8 8 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.6P PS=2.4U M603 9 8 8 10 PMOS W=0.8U L=0.4U
222
+ AD=0.3P PD=3.0U AS=0.6P PS=2.4U M604 9 8 8 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.6P PS=2.4U M605 9 8 8 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.6P PS=2.4U M606 8 8 9 10 PMOS W=0.8U L=0.4U + AD=0.6P PD=2.4U AS=0.3P PS=3.0U M607 8 8 9 10 PMOS W=0.8U L=0.4U + AD=0.6P PD=2.4U AS=0.3P PS=3.0U M608 8 8 9 10 PMOS W=0.8U L=0.4U + AD=0.6P PD=2.4U AS=0.3P PS=3.0U M609 8 8 9 10 PMOS W=0.8U L=0.4U + AD=0.6P PD=2.4U AS=0.3P PS=3.0U M610 8 8 9 10 PMOS W=0.8U L=0.4U + AD=0.6P PD=2.4U AS=0.3P PS=3.0U M611 8 8 9 10 PMOS W=0.8U L=0.4U + AD=0.6P PD=2.4U AS=0.3P PS=3.0U M612 8 8 9 10 PMOS W=0.8U L=0.4U + AD=0.6P PD=2.4U AS=0.3P PS=3.0U M613 8 8 9 10 PMOS W=0.8U L=0.4U + AD=0.6P PD=2.4U AS=0.3P PS=3.0U M614 8 8 9 10 PMOS W=0.8U L=0.4U + AD=0.6P PD=2.4U AS=0.3P PS=3.0U M615 8 8 9 10 PMOS W=0.8U L=0.4U + AD=0.6P PD=2.4U AS=0.3P PS=3.0U M616 8 8 9 10 PMOS W=0.8U L=0.4U + AD=0.6P PD=2.4U AS=0.3P PS=3.0U M617 8 8 9 10 PMOS W=0.8U L=0.4U + AD=0.6P PD=2.4U AS=0.3P PS=3.0U M618 43 7 48 3 NMOS W=28.8U L=0.4U + AD=0.0P PD=86.4U AS=0.0P PS=100.8U M619 48 7 43 3 NMOS W=28.8U L=0.4U + AD=0.0P PD=100.8U AS=0.0P PS=86.4U M620 43 7 48 3 NMOS W=28.8U L=0.4U + AD=0.0P PD=86.4U AS=0.0P PS=100.8U M621 9 8 8 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.6P PS=2.4U M622 9 8 8 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.6P PS=2.4U M623 9 8 8 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.6P PS=2.4U M624 9 8 8 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.6P PS=2.4U M625 9 8 8 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.6P PS=2.4U M626 9 8 8 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.6P PS=2.4U M627 9 8 8 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.6P PS=2.4U M628 9 8 8 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.6P PS=2.4U M629 9 8 8 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.6P PS=2.4U M630 9 8 8 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.6P PS=2.4U M631 9 8 8 10 PMOS W=0.8U L=0.4U
+ AD=0.3P PD=3.0U AS=0.6P PS=2.4U M632 9 8 8 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.6P PS=2.4U M633 48 7 43 3 NMOS W=28.8U L=0.4U + AD=0.0P PD=100.8U AS=0.0P PS=86.4U M634 44 44 9 10 PMOS W=0.8U L=0.4U + AD=0.6P PD=2.4U AS=0.3P PS=3.0U M635 44 44 9 10 PMOS W=0.8U L=0.4U + AD=0.6P PD=2.4U AS=0.3P PS=3.0U M636 44 44 9 10 PMOS W=0.8U L=0.4U + AD=0.6P PD=2.4U AS=0.3P PS=3.0U M637 44 44 9 10 PMOS W=0.8U L=0.4U + AD=0.6P PD=2.4U AS=0.3P PS=3.0U M638 44 44 9 10 PMOS W=0.8U L=0.4U + AD=0.6P PD=2.4U AS=0.3P PS=3.0U M639 44 44 9 10 PMOS W=0.8U L=0.4U + AD=0.6P PD=2.4U AS=0.3P PS=3.0U M640 44 44 9 10 PMOS W=0.8U L=0.4U + AD=0.6P PD=2.4U AS=0.3P PS=3.0U M641 44 44 9 10 PMOS W=0.8U L=0.4U + AD=0.6P PD=2.4U AS=0.3P PS=3.0U M642 44 44 9 10 PMOS W=0.8U L=0.4U + AD=0.6P PD=2.4U AS=0.3P PS=3.0U M643 44 44 9 10 PMOS W=0.8U L=0.4U + AD=0.6P PD=2.4U AS=0.3P PS=3.0U M644 44 44 9 10 PMOS W=0.8U L=0.4U + AD=0.6P PD=2.4U AS=0.3P PS=3.0U M645 44 44 9 10 PMOS W=0.8U L=0.4U + AD=0.6P PD=2.4U AS=0.3P PS=3.0U M646 9 44 44 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.6P PS=2.4U M647 9 44 44 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.6P PS=2.4U M648 9 44 44 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.6P PS=2.4U M649 9 44 44 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.6P PS=2.4U M650 9 44 44 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.6P PS=2.4U M651 9 44 44 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.6P PS=2.4U M652 9 44 44 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.6P PS=2.4U M653 9 44 44 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.6P PS=2.4U M654 9 44 44 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.6P PS=2.4U M655 9 44 44 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.6P PS=2.4U M656 9 44 44 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.6P PS=2.4U M657 9 44 44 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.6P PS=2.4U M658 44 44 9 10 PMOS W=0.8U L=0.4U + AD=0.6P PD=2.4U AS=0.3P PS=3.0U M659 44 44 9 10 PMOS W=0.8U L=0.4U
223
+ AD=0.6P PD=2.4U AS=0.3P PS=3.0U M660 44 44 9 10 PMOS W=0.8U L=0.4U + AD=0.6P PD=2.4U AS=0.3P PS=3.0U M661 44 44 9 10 PMOS W=0.8U L=0.4U + AD=0.6P PD=2.4U AS=0.3P PS=3.0U M662 44 44 9 10 PMOS W=0.8U L=0.4U + AD=0.6P PD=2.4U AS=0.3P PS=3.0U M663 44 44 9 10 PMOS W=0.8U L=0.4U + AD=0.6P PD=2.4U AS=0.3P PS=3.0U M664 44 44 9 10 PMOS W=0.8U L=0.4U + AD=0.6P PD=2.4U AS=0.3P PS=3.0U M665 44 44 9 10 PMOS W=0.8U L=0.4U + AD=0.6P PD=2.4U AS=0.3P PS=3.0U M666 44 44 9 10 PMOS W=0.8U L=0.4U + AD=0.6P PD=2.4U AS=0.3P PS=3.0U M667 44 44 9 10 PMOS W=0.8U L=0.4U + AD=0.6P PD=2.4U AS=0.3P PS=3.0U M668 44 44 9 10 PMOS W=0.8U L=0.4U + AD=0.6P PD=2.4U AS=0.3P PS=3.0U M669 44 44 9 10 PMOS W=0.8U L=0.4U + AD=0.6P PD=2.4U AS=0.3P PS=3.0U M670 9 44 44 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.6P PS=2.4U M671 9 44 44 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.6P PS=2.4U M672 9 44 44 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.6P PS=2.4U M673 9 44 44 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.6P PS=2.4U M674 9 44 44 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.6P PS=2.4U M675 9 44 44 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.6P PS=2.4U M676 9 44 44 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.6P PS=2.4U M677 9 44 44 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.6P PS=2.4U M678 9 44 44 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.6P PS=2.4U M679 9 44 44 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.6P PS=2.4U M680 9 44 44 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.6P PS=2.4U M681 9 44 44 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.6P PS=2.4U M682 40 11 16 3 NMOS W=6.4U L=0.4U + AD=0.0P PD=28.5U AS=0.0P PS=21.8U M683 40 14 17 3 NMOS W=6.4U L=0.4U + AD=0.0P PD=28.5U AS=0.0P PS=21.8U M684 4 49 38 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=3.5U M685 4 49 38 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=3.5U M686 4 49 38 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=3.5U M687 4 49 38 3 NMOS W=0.8U L=0.4U
+ AD=0.0P PD=2.8U AS=0.0P PS=3.5U M688 4 49 38 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=3.5U M689 4 49 38 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=3.5U M690 4 49 21 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=4.0U M691 4 49 21 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=4.0U M692 4 49 21 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=4.0U M693 4 49 39 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=3.5U M694 4 49 39 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=3.5U M695 4 49 39 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=3.5U M696 4 49 39 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=3.5U M697 4 49 39 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=3.5U M698 4 49 39 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=3.5U M699 4 49 24 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=4.0U M700 4 49 24 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=4.0U M701 4 49 24 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=4.0U M702 4 49 41 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=3.5U M703 4 49 41 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=3.5U M704 4 49 41 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=3.5U M705 4 49 41 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=3.5U M706 4 49 41 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=3.5U M707 4 49 41 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=3.5U M708 4 49 27 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=4.0U M709 4 49 27 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=4.0U M710 4 49 27 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=4.0U M711 4 49 42 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=3.5U M712 4 49 42 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=3.5U M713 4 49 42 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=3.5U M714 4 49 42 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=3.5U M715 4 49 42 3 NMOS W=0.8U L=0.4U
224
+ AD=0.0P PD=2.8U AS=0.0P PS=3.5U M716 4 49 42 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=3.5U M717 4 49 30 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=4.0U M718 4 49 30 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=4.0U M719 4 49 30 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=4.0U M720 4 49 46 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=3.5U M721 4 49 46 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=3.5U M722 4 49 46 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=3.5U M723 4 49 46 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=3.5U M724 4 49 46 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=3.5U M725 4 49 46 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=3.5U M726 4 49 33 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=4.0U M727 4 49 33 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=4.0U M728 4 49 33 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=4.0U M729 45 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.1U AS=0.0P PS=2.8U M730 45 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.1U AS=0.0P PS=2.8U M731 45 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.1U AS=0.0P PS=2.8U M732 45 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.1U AS=0.0P PS=2.8U M733 45 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.1U AS=0.0P PS=2.8U M734 45 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.1U AS=0.0P PS=2.8U M735 45 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.1U AS=0.0P PS=2.8U M736 45 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.1U AS=0.0P PS=2.8U M737 45 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.1U AS=0.0P PS=2.8U M738 9 50 51 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.2P PS=2.7U M739 51 50 9 10 PMOS W=0.8U L=0.4U + AD=0.2P PD=2.7U AS=0.3P PS=3.0U M740 9 50 51 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.2P PS=2.7U M741 51 50 9 10 PMOS W=0.8U L=0.4U + AD=0.2P PD=2.7U AS=0.3P PS=3.0U M742 9 50 51 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.2P PS=2.7U M743 52 51 51 3 NMOS W=0.8U L=0.4U
+ AD=0.0P PD=5.1U AS=0.0P PS=4.6U M744 52 51 51 3 NMOS W=1.0U L=0.4U + AD=0.0P PD=6.4U AS=0.0P PS=5.8U M745 52 51 51 3 NMOS W=1.0U L=0.4U + AD=0.0P PD=6.4U AS=0.0P PS=5.8U M746 52 51 51 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=5.1U AS=0.0P PS=4.6U M747 38 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.5U AS=0.0P PS=2.8U M748 38 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.5U AS=0.0P PS=2.8U M749 38 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.5U AS=0.0P PS=2.8U M750 38 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.5U AS=0.0P PS=2.8U M751 38 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.5U AS=0.0P PS=2.8U M752 38 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.5U AS=0.0P PS=2.8U M753 39 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.5U AS=0.0P PS=2.8U M754 39 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.5U AS=0.0P PS=2.8U M755 39 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.5U AS=0.0P PS=2.8U M756 39 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.5U AS=0.0P PS=2.8U M757 39 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.5U AS=0.0P PS=2.8U M758 39 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.5U AS=0.0P PS=2.8U M759 41 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.5U AS=0.0P PS=2.8U M760 41 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.5U AS=0.0P PS=2.8U M761 41 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.5U AS=0.0P PS=2.8U M762 41 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.5U AS=0.0P PS=2.8U M763 41 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.5U AS=0.0P PS=2.8U M764 41 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.5U AS=0.0P PS=2.8U M765 42 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.5U AS=0.0P PS=2.8U M766 42 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.5U AS=0.0P PS=2.8U M767 42 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.5U AS=0.0P PS=2.8U M768 42 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.5U AS=0.0P PS=2.8U M769 42 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.5U AS=0.0P PS=2.8U M770 42 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.5U AS=0.0P PS=2.8U M771 46 49 4 3 NMOS W=0.8U L=0.4U
225
+ AD=0.0P PD=3.5U AS=0.0P PS=2.8U M772 46 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.5U AS=0.0P PS=2.8U M773 46 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.5U AS=0.0P PS=2.8U M774 46 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.5U AS=0.0P PS=2.8U M775 46 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.5U AS=0.0P PS=2.8U M776 46 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.5U AS=0.0P PS=2.8U M777 4 49 45 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=3.1U M778 4 49 45 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=3.1U M779 4 49 45 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=3.1U M780 4 49 45 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=3.1U M781 4 49 45 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=3.1U M782 4 49 45 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=3.1U M783 4 49 45 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=3.1U M784 4 49 45 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=3.1U M785 4 49 45 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=3.1U M786 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M787 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M788 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M789 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M790 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M791 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M792 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M793 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M794 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M795 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M796 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M797 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M798 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M799 37 49 4 3 NMOS W=0.8U L=0.4U
+ AD=0.0P PD=2.8U AS=0.0P PS=2.8U M800 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M801 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M802 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M803 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M804 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M805 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M806 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M807 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M808 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M809 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M810 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M811 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M812 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M813 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M814 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M815 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M816 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M817 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M818 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M819 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M820 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M821 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M822 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M823 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M824 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M825 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M826 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M827 48 49 4 3 NMOS W=0.8U L=0.4U
226
+ AD=0.0P PD=2.8U AS=0.0P PS=2.8U M828 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M829 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M830 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M831 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M832 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M833 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M834 52 51 34 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=5.1U AS=0.0P PS=3.6U M835 52 51 34 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=5.1U AS=0.0P PS=3.6U M836 52 51 34 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=5.1U AS=0.0P PS=3.6U M837 52 51 34 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=5.1U AS=0.0P PS=3.6U M838 52 51 34 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=5.1U AS=0.0P PS=3.6U M839 52 51 34 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=5.1U AS=0.0P PS=3.6U M840 52 51 34 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=5.1U AS=0.0P PS=3.6U M841 52 51 34 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=5.1U AS=0.0P PS=3.6U M842 52 51 40 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=5.1U AS=0.0P PS=3.6U M843 52 51 40 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=5.1U AS=0.0P PS=3.6U M844 52 51 40 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=5.1U AS=0.0P PS=3.6U M845 52 51 40 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=5.1U AS=0.0P PS=3.6U M846 52 51 40 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=5.1U AS=0.0P PS=3.6U M847 52 51 40 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=5.1U AS=0.0P PS=3.6U M848 52 51 40 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=5.1U AS=0.0P PS=3.6U M849 52 51 40 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=5.1U AS=0.0P PS=3.6U M850 9 50 51 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.2P PS=2.7U M851 51 50 9 10 PMOS W=0.8U L=0.4U + AD=0.2P PD=2.7U AS=0.3P PS=3.0U M852 9 50 51 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.2P PS=2.7U M853 51 50 9 10 PMOS W=0.8U L=0.4U + AD=0.2P PD=2.7U AS=0.3P PS=3.0U M854 9 50 51 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.2P PS=2.7U M855 51 51 52 3 NMOS W=0.8U L=0.4U
+ AD=0.0P PD=4.6U AS=0.0P PS=5.1U M856 51 51 52 3 NMOS W=1.0U L=0.4U + AD=0.0P PD=5.8U AS=0.0P PS=6.4U M857 51 51 52 3 NMOS W=1.0U L=0.4U + AD=0.0P PD=5.8U AS=0.0P PS=6.4U M858 51 51 52 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=4.6U AS=0.0P PS=5.1U M859 4 49 38 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=3.5U M860 4 49 38 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=3.5U M861 4 49 38 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=3.5U M862 4 49 38 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=3.5U M863 4 49 38 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=3.5U M864 4 49 38 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=3.5U M865 4 49 39 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=3.5U M866 4 49 39 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=3.5U M867 4 49 39 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=3.5U M868 4 49 39 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=3.5U M869 4 49 39 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=3.5U M870 4 49 39 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=3.5U M871 4 49 41 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=3.5U M872 4 49 41 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=3.5U M873 4 49 41 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=3.5U M874 4 49 41 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=3.5U M875 4 49 41 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=3.5U M876 4 49 41 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=3.5U M877 4 49 42 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=3.5U M878 4 49 42 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=3.5U M879 4 49 42 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=3.5U M880 4 49 42 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=3.5U M881 4 49 42 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=3.5U M882 4 49 42 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=3.5U M883 4 49 46 3 NMOS W=0.8U L=0.4U
227
+ AD=0.0P PD=2.8U AS=0.0P PS=3.5U M884 4 49 46 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=3.5U M885 4 49 46 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=3.5U M886 4 49 46 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=3.5U M887 4 49 46 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=3.5U M888 4 49 46 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=3.5U M889 45 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.1U AS=0.0P PS=2.8U M890 45 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.1U AS=0.0P PS=2.8U M891 45 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.1U AS=0.0P PS=2.8U M892 45 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.1U AS=0.0P PS=2.8U M893 45 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.1U AS=0.0P PS=2.8U M894 45 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.1U AS=0.0P PS=2.8U M895 45 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.1U AS=0.0P PS=2.8U M896 45 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.1U AS=0.0P PS=2.8U M897 45 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.1U AS=0.0P PS=2.8U M898 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M899 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M900 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M901 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M902 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M903 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M904 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M905 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M906 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M907 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M908 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M909 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M910 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M911 4 49 37 3 NMOS W=0.8U L=0.4U
+ AD=0.0P PD=2.8U AS=0.0P PS=2.8U M912 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M913 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M914 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M915 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M916 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M917 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M918 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M919 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M920 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M921 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M922 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M923 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M924 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M925 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M926 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M927 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M928 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M929 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M930 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M931 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M932 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M933 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M934 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M935 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M936 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M937 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M938 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M939 4 49 48 3 NMOS W=0.8U L=0.4U
228
+ AD=0.0P PD=2.8U AS=0.0P PS=2.8U M940 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M941 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M942 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M943 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M944 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M945 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M946 34 51 52 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.6U AS=0.0P PS=5.1U M947 34 51 52 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.6U AS=0.0P PS=5.1U M948 34 51 52 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.6U AS=0.0P PS=5.1U M949 34 51 52 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.6U AS=0.0P PS=5.1U M950 34 51 52 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.6U AS=0.0P PS=5.1U M951 34 51 52 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.6U AS=0.0P PS=5.1U M952 34 51 52 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.6U AS=0.0P PS=5.1U M953 34 51 52 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.6U AS=0.0P PS=5.1U M954 40 51 52 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.6U AS=0.0P PS=5.1U M955 40 51 52 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.6U AS=0.0P PS=5.1U M956 40 51 52 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.6U AS=0.0P PS=5.1U M957 40 51 52 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.6U AS=0.0P PS=5.1U M958 40 51 52 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.6U AS=0.0P PS=5.1U M959 40 51 52 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.6U AS=0.0P PS=5.1U M960 40 51 52 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.6U AS=0.0P PS=5.1U M961 40 51 52 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.6U AS=0.0P PS=5.1U M962 9 50 51 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.2P PS=2.7U M963 51 50 9 10 PMOS W=0.8U L=0.4U + AD=0.2P PD=2.7U AS=0.3P PS=3.0U M964 9 50 51 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.2P PS=2.7U M965 51 50 9 10 PMOS W=0.8U L=0.4U + AD=0.2P PD=2.7U AS=0.3P PS=3.0U M966 9 50 51 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.2P PS=2.7U M967 52 51 51 3 NMOS W=0.8U L=0.4U
+ AD=0.0P PD=5.1U AS=0.0P PS=4.6U M968 52 51 51 3 NMOS W=1.0U L=0.4U + AD=0.0P PD=6.4U AS=0.0P PS=5.8U M969 52 51 51 3 NMOS W=1.0U L=0.4U + AD=0.0P PD=6.4U AS=0.0P PS=5.8U M970 52 51 51 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=5.1U AS=0.0P PS=4.6U M971 52 51 34 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=5.1U AS=0.0P PS=3.6U M972 52 51 34 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=5.1U AS=0.0P PS=3.6U M973 52 51 34 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=5.1U AS=0.0P PS=3.6U M974 52 51 34 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=5.1U AS=0.0P PS=3.6U M975 52 51 34 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=5.1U AS=0.0P PS=3.6U M976 52 51 34 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=5.1U AS=0.0P PS=3.6U M977 52 51 34 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=5.1U AS=0.0P PS=3.6U M978 52 51 34 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=5.1U AS=0.0P PS=3.6U M979 52 51 40 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=5.1U AS=0.0P PS=3.6U M980 52 51 40 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=5.1U AS=0.0P PS=3.6U M981 52 51 40 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=5.1U AS=0.0P PS=3.6U M982 52 51 40 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=5.1U AS=0.0P PS=3.6U M983 52 51 40 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=5.1U AS=0.0P PS=3.6U M984 52 51 40 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=5.1U AS=0.0P PS=3.6U M985 52 51 40 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=5.1U AS=0.0P PS=3.6U M986 52 51 40 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=5.1U AS=0.0P PS=3.6U M987 9 50 51 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.2P PS=2.7U M988 51 50 9 10 PMOS W=0.8U L=0.4U + AD=0.2P PD=2.7U AS=0.3P PS=3.0U M989 9 50 51 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.2P PS=2.7U M990 51 50 9 10 PMOS W=0.8U L=0.4U + AD=0.2P PD=2.7U AS=0.3P PS=3.0U M991 9 50 51 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.2P PS=2.7U M992 51 51 52 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=4.6U AS=0.0P PS=5.1U M993 51 51 52 3 NMOS W=1.0U L=0.4U + AD=0.0P PD=5.8U AS=0.0P PS=6.4U M994 51 51 52 3 NMOS W=1.0U L=0.4U + AD=0.0P PD=5.8U AS=0.0P PS=6.4U M995 51 51 52 3 NMOS W=0.8U L=0.4U
229
+ AD=0.0P PD=4.6U AS=0.0P PS=5.1U M996 34 51 52 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.6U AS=0.0P PS=5.1U M997 34 51 52 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.6U AS=0.0P PS=5.1U M998 34 51 52 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.6U AS=0.0P PS=5.1U M999 34 51 52 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.6U AS=0.0P PS=5.1U M1000 34 51 52 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.6U AS=0.0P PS=5.1U M1001 34 51 52 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.6U AS=0.0P PS=5.1U M1002 34 51 52 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.6U AS=0.0P PS=5.1U M1003 34 51 52 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.6U AS=0.0P PS=5.1U M1004 40 51 52 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.6U AS=0.0P PS=5.1U M1005 40 51 52 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.6U AS=0.0P PS=5.1U M1006 40 51 52 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.6U AS=0.0P PS=5.1U M1007 40 51 52 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.6U AS=0.0P PS=5.1U M1008 40 51 52 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.6U AS=0.0P PS=5.1U M1009 40 51 52 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.6U AS=0.0P PS=5.1U M1010 40 51 52 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.6U AS=0.0P PS=5.1U M1011 40 51 52 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=3.6U AS=0.0P PS=5.1U M1012 4 49 45 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=3.1U M1013 4 49 45 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=3.1U M1014 4 49 45 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=3.1U M1015 4 49 45 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=3.1U M1016 4 49 45 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=3.1U M1017 4 49 45 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=3.1U M1018 4 49 45 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=3.1U M1019 4 49 45 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=3.1U M1020 4 49 45 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=3.1U M1021 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1022 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1023 37 49 4 3 NMOS W=0.8U L=0.4U
+ AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1024 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1025 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1026 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1027 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1028 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1029 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1030 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1031 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1032 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1033 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1034 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1035 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1036 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1037 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1038 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1039 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1040 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1041 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1042 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1043 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1044 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1045 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1046 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1047 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1048 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1049 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1050 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1051 48 49 4 3 NMOS W=0.8U L=0.4U
230
+ AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1052 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1053 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1054 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1055 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1056 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1057 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1058 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1059 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1060 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1061 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1062 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1063 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1064 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1065 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1066 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1067 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1068 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1069 9 50 51 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.2P PS=2.7U M1070 51 50 9 10 PMOS W=0.8U L=0.4U + AD=0.2P PD=2.7U AS=0.3P PS=3.0U M1071 9 50 51 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.2P PS=2.7U M1072 51 50 9 10 PMOS W=0.8U L=0.4U + AD=0.2P PD=2.7U AS=0.3P PS=3.0U M1073 9 50 51 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.2P PS=2.7U M1074 52 51 51 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=5.1U AS=0.0P PS=4.6U M1075 52 51 51 3 NMOS W=1.0U L=0.4U + AD=0.0P PD=6.4U AS=0.0P PS=5.8U M1076 52 51 51 3 NMOS W=1.0U L=0.4U + AD=0.0P PD=6.4U AS=0.0P PS=5.8U M1077 52 51 51 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=5.1U AS=0.0P PS=4.6U M1078 52 51 34 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=5.1U AS=0.0P PS=3.6U M1079 52 51 34 3 NMOS W=0.8U L=0.4U
+ AD=0.0P PD=5.1U AS=0.0P PS=3.6U M1080 52 51 34 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=5.1U AS=0.0P PS=3.6U M1081 52 51 34 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=5.1U AS=0.0P PS=3.6U M1082 52 51 34 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=5.1U AS=0.0P PS=3.6U M1083 52 51 34 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=5.1U AS=0.0P PS=3.6U M1084 52 51 34 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=5.1U AS=0.0P PS=3.6U M1085 52 51 34 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=5.1U AS=0.0P PS=3.6U M1086 52 51 40 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=5.1U AS=0.0P PS=3.6U M1087 52 51 40 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=5.1U AS=0.0P PS=3.6U M1088 52 51 40 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=5.1U AS=0.0P PS=3.6U M1089 52 51 40 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=5.1U AS=0.0P PS=3.6U M1090 52 51 40 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=5.1U AS=0.0P PS=3.6U M1091 52 51 40 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=5.1U AS=0.0P PS=3.6U M1092 52 51 40 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=5.1U AS=0.0P PS=3.6U M1093 52 51 40 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=5.1U AS=0.0P PS=3.6U M1094 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1095 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1096 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1097 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1098 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1099 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1100 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1101 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1102 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1103 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1104 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1105 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1106 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1107 4 49 37 3 NMOS W=0.8U L=0.4U
231
+ AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1108 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1109 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1110 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1111 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1112 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1113 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1114 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1115 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1116 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1117 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1118 4 49 8 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.6U M1119 4 49 8 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.6U M1120 4 49 8 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.6U M1121 4 49 8 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.6U M1122 4 49 8 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.6U M1123 4 49 8 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.6U M1124 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1125 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1126 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1127 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1128 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1129 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1130 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1131 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1132 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1133 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1134 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1135 4 49 48 3 NMOS W=0.8U L=0.4U
+ AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1136 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1137 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1138 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1139 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1140 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1141 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1142 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1143 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1144 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1145 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1146 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1147 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1148 4 49 44 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.6U M1149 4 49 44 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.6U M1150 4 49 44 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.6U M1151 4 49 44 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.6U M1152 4 49 44 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.6U M1153 4 49 44 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.6U M1154 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1155 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1156 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1157 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1158 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1159 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1160 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1161 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1162 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1163 37 49 4 3 NMOS W=0.8U L=0.4U
232
+ AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1164 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1165 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1166 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1167 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1168 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1169 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1170 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1171 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1172 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1173 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1174 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1175 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1176 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1177 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1178 8 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.6U AS=0.0P PS=2.8U M1179 8 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.6U AS=0.0P PS=2.8U M1180 8 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.6U AS=0.0P PS=2.8U M1181 8 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.6U AS=0.0P PS=2.8U M1182 8 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.6U AS=0.0P PS=2.8U M1183 8 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.6U AS=0.0P PS=2.8U M1184 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1185 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1186 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1187 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1188 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1189 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1190 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1191 48 49 4 3 NMOS W=0.8U L=0.4U
+ AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1192 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1193 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1194 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1195 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1196 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1197 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1198 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1199 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1200 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1201 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1202 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1203 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1204 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1205 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1206 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1207 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1208 44 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.6U AS=0.0P PS=2.8U M1209 44 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.6U AS=0.0P PS=2.8U M1210 44 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.6U AS=0.0P PS=2.8U M1211 44 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.6U AS=0.0P PS=2.8U M1212 44 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.6U AS=0.0P PS=2.8U M1213 44 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.6U AS=0.0P PS=2.8U M1214 9 50 51 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.2P PS=2.7U M1215 51 50 9 10 PMOS W=0.8U L=0.4U + AD=0.2P PD=2.7U AS=0.3P PS=3.0U M1216 9 50 51 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.2P PS=2.7U M1217 51 50 9 10 PMOS W=0.8U L=0.4U + AD=0.2P PD=2.7U AS=0.3P PS=3.0U M1218 9 50 51 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.2P PS=2.7U M1219 4 49 37 3 NMOS W=0.8U L=0.4U
233
+ AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1220 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1221 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1222 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1223 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1224 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1225 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1226 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1227 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1228 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1229 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1230 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1231 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1232 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1233 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1234 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1235 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1236 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1237 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1238 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1239 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1240 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1241 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1242 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1243 4 49 8 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.6U M1244 4 49 8 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.6U M1245 4 49 8 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.6U M1246 4 49 8 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.6U M1247 4 49 8 3 NMOS W=0.8U L=0.4U
+ AD=0.0P PD=2.8U AS=0.0P PS=2.6U M1248 4 49 8 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.6U M1249 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1250 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1251 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1252 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1253 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1254 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1255 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1256 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1257 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1258 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1259 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1260 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1261 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1262 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1263 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1264 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1265 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1266 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1267 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1268 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1269 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1270 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1271 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1272 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1273 4 49 44 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.6U M1274 4 49 44 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.6U M1275 4 49 44 3 NMOS W=0.8U L=0.4U
234
+ AD=0.0P PD=2.8U AS=0.0P PS=2.6U M1276 4 49 44 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.6U M1277 4 49 44 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.6U M1278 4 49 44 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.6U M1279 9 50 51 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.2P PS=2.7U M1280 51 50 9 10 PMOS W=0.8U L=0.4U + AD=0.2P PD=2.7U AS=0.3P PS=3.0U M1281 9 50 51 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.2P PS=2.7U M1282 51 50 9 10 PMOS W=0.8U L=0.4U + AD=0.2P PD=2.7U AS=0.3P PS=3.0U M1283 9 50 51 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.2P PS=2.7U M1284 9 50 51 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.2P PS=2.7U M1285 51 50 9 10 PMOS W=0.8U L=0.4U + AD=0.2P PD=2.7U AS=0.3P PS=3.0U M1286 9 50 51 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.2P PS=2.7U M1287 51 50 9 10 PMOS W=0.8U L=0.4U + AD=0.2P PD=2.7U AS=0.3P PS=3.0U M1288 9 50 51 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.2P PS=2.7U M1289 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1290 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1291 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1292 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1293 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1294 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1295 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1296 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1297 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1298 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1299 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1300 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1301 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1302 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1303 37 49 4 3 NMOS W=0.8U L=0.4U
+ AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1304 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1305 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1306 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1307 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1308 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1309 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1310 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1311 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1312 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1313 8 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.6U AS=0.0P PS=2.8U M1314 8 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.6U AS=0.0P PS=2.8U M1315 8 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.6U AS=0.0P PS=2.8U M1316 8 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.6U AS=0.0P PS=2.8U M1317 8 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.6U AS=0.0P PS=2.8U M1318 8 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.6U AS=0.0P PS=2.8U M1319 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1320 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1321 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1322 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1323 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1324 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1325 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1326 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1327 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1328 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1329 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1330 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1331 48 49 4 3 NMOS W=0.8U L=0.4U
235
+ AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1332 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1333 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1334 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1335 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1336 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1337 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1338 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1339 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1340 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1341 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1342 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1343 44 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.6U AS=0.0P PS=2.8U M1344 44 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.6U AS=0.0P PS=2.8U M1345 44 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.6U AS=0.0P PS=2.8U M1346 44 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.6U AS=0.0P PS=2.8U M1347 44 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.6U AS=0.0P PS=2.8U M1348 44 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.6U AS=0.0P PS=2.8U M1349 49 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.4U AS=0.0P PS=2.8U M1350 49 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.4U AS=0.0P PS=2.8U M1351 49 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.4U AS=0.0P PS=2.8U M1352 49 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.4U AS=0.0P PS=2.8U M1353 49 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.4U AS=0.0P PS=2.8U M1354 49 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.4U AS=0.0P PS=2.8U M1355 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1356 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1357 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1358 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1359 4 49 37 3 NMOS W=0.8U L=0.4U
+ AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1360 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1361 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1362 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1363 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1364 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1365 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1366 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1367 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1368 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1369 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1370 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1371 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1372 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1373 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1374 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1375 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1376 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1377 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1378 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1379 4 49 8 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.6U M1380 4 49 8 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.6U M1381 4 49 8 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.6U M1382 4 49 8 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.6U M1383 4 49 8 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.6U M1384 4 49 8 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.6U M1385 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1386 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1387 4 49 48 3 NMOS W=0.8U L=0.4U
236
+ AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1388 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1389 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1390 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1391 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1392 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1393 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1394 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1395 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1396 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1397 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1398 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1399 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1400 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1401 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1402 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1403 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1404 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1405 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1406 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1407 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1408 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1409 4 49 44 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.6U M1410 4 49 44 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.6U M1411 4 49 44 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.6U M1412 4 49 44 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.6U M1413 4 49 44 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.6U M1414 4 49 44 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.6U M1415 4 49 49 3 NMOS W=0.8U L=0.4U
+ AD=0.0P PD=2.8U AS=0.0P PS=2.4U M1416 4 49 49 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.4U M1417 4 49 49 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.4U M1418 4 49 49 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.4U M1419 4 49 49 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.4U M1420 4 49 49 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.4U M1421 9 50 51 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.2P PS=2.7U M1422 51 50 9 10 PMOS W=0.8U L=0.4U + AD=0.2P PD=2.7U AS=0.3P PS=3.0U M1423 9 50 51 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.2P PS=2.7U M1424 51 50 9 10 PMOS W=0.8U L=0.4U + AD=0.2P PD=2.7U AS=0.3P PS=3.0U M1425 9 50 51 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.2P PS=2.7U M1426 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1427 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1428 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1429 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1430 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1431 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1432 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1433 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1434 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1435 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1436 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1437 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1438 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1439 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1440 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1441 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1442 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1443 37 49 4 3 NMOS W=0.8U L=0.4U
237
+ AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1444 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1445 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1446 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1447 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1448 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1449 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1450 8 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.6U AS=0.0P PS=2.8U M1451 8 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.6U AS=0.0P PS=2.8U M1452 8 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.6U AS=0.0P PS=2.8U M1453 8 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.6U AS=0.0P PS=2.8U M1454 8 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.6U AS=0.0P PS=2.8U M1455 8 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.6U AS=0.0P PS=2.8U M1456 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1457 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1458 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1459 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1460 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1461 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1462 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1463 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1464 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1465 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1466 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1467 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1468 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1469 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1470 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1471 48 49 4 3 NMOS W=0.8U L=0.4U
+ AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1472 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1473 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1474 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1475 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1476 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1477 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1478 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1479 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1480 44 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.6U AS=0.0P PS=2.8U M1481 44 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.6U AS=0.0P PS=2.8U M1482 44 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.6U AS=0.0P PS=2.8U M1483 44 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.6U AS=0.0P PS=2.8U M1484 44 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.6U AS=0.0P PS=2.8U M1485 44 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.6U AS=0.0P PS=2.8U M1486 49 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.4U AS=0.0P PS=2.8U M1487 49 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.4U AS=0.0P PS=2.8U M1488 49 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.4U AS=0.0P PS=2.8U M1489 49 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.4U AS=0.0P PS=2.8U M1490 49 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.4U AS=0.0P PS=2.8U M1491 49 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.4U AS=0.0P PS=2.8U M1492 9 50 51 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.2P PS=2.7U M1493 51 50 9 10 PMOS W=0.8U L=0.4U + AD=0.2P PD=2.7U AS=0.3P PS=3.0U M1494 9 50 51 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.2P PS=2.7U M1495 51 50 9 10 PMOS W=0.8U L=0.4U + AD=0.2P PD=2.7U AS=0.3P PS=3.0U M1496 9 50 51 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.2P PS=2.7U M1497 50 53 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.9U AS=0.0P PS=2.8U M1498 4 53 50 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.9U M1499 50 53 4 3 NMOS W=0.8U L=0.4U
238
+ AD=0.0P PD=2.9U AS=0.0P PS=2.8U M1500 9 50 51 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.2P PS=2.7U M1501 51 50 9 10 PMOS W=0.8U L=0.4U + AD=0.2P PD=2.7U AS=0.3P PS=3.0U M1502 9 50 51 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.2P PS=2.7U M1503 51 50 9 10 PMOS W=0.8U L=0.4U + AD=0.2P PD=2.7U AS=0.3P PS=3.0U M1504 9 50 51 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.2P PS=2.7U M1505 50 53 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.9U AS=0.0P PS=2.8U M1506 4 53 50 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.9U M1507 50 53 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.9U AS=0.0P PS=2.8U M1508 9 50 51 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.2P PS=2.7U M1509 51 50 9 10 PMOS W=0.8U L=0.4U + AD=0.2P PD=2.7U AS=0.3P PS=3.0U M1510 9 50 51 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.2P PS=2.7U M1511 51 50 9 10 PMOS W=0.8U L=0.4U + AD=0.2P PD=2.7U AS=0.3P PS=3.0U M1512 9 50 51 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.2P PS=2.7U M1513 50 53 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.9U AS=0.0P PS=2.8U M1514 4 53 50 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.9U M1515 50 53 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.9U AS=0.0P PS=2.8U M1516 9 50 51 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.2P PS=2.7U M1517 51 50 9 10 PMOS W=0.8U L=0.4U + AD=0.2P PD=2.7U AS=0.3P PS=3.0U M1518 9 50 51 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.2P PS=2.7U M1519 51 50 9 10 PMOS W=0.8U L=0.4U + AD=0.2P PD=2.7U AS=0.3P PS=3.0U M1520 9 50 51 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.2P PS=2.7U M1521 50 53 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.9U AS=0.0P PS=2.8U M1522 4 53 50 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.9U M1523 50 53 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.9U AS=0.0P PS=2.8U M1524 9 50 51 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.2P PS=2.7U M1525 51 50 9 10 PMOS W=0.8U L=0.4U + AD=0.2P PD=2.7U AS=0.3P PS=3.0U M1526 9 50 51 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.2P PS=2.7U M1527 51 50 9 10 PMOS W=0.8U L=0.4U
+ AD=0.2P PD=2.7U AS=0.3P PS=3.0U M1528 9 50 51 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.2P PS=2.7U M1529 50 53 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.9U AS=0.0P PS=2.8U M1530 4 53 50 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.9U M1531 50 53 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.9U AS=0.0P PS=2.8U M1532 9 50 51 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.2P PS=2.7U M1533 51 50 9 10 PMOS W=0.8U L=0.4U + AD=0.2P PD=2.7U AS=0.3P PS=3.0U M1534 9 50 51 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.2P PS=2.7U M1535 51 50 9 10 PMOS W=0.8U L=0.4U + AD=0.2P PD=2.7U AS=0.3P PS=3.0U M1536 9 50 51 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.2P PS=2.7U M1537 50 53 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.9U AS=0.0P PS=2.8U M1538 4 53 50 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.9U M1539 50 53 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.9U AS=0.0P PS=2.8U M1540 4 53 53 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.4U M1541 53 53 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.4U AS=0.0P PS=2.8U M1542 9 50 50 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.5P PS=2.7U M1543 50 50 9 10 PMOS W=0.8U L=0.4U + AD=0.5P PD=2.7U AS=0.3P PS=3.0U M1544 9 50 50 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.5P PS=2.7U M1545 50 50 9 10 PMOS W=0.8U L=0.4U + AD=0.5P PD=2.7U AS=0.3P PS=3.0U M1546 9 50 50 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.5P PS=2.7U M1547 4 53 53 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.4U M1548 53 53 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.4U AS=0.0P PS=2.8U M1549 9 50 50 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.5P PS=2.7U M1550 50 50 9 10 PMOS W=0.8U L=0.4U + AD=0.5P PD=2.7U AS=0.3P PS=3.0U M1551 9 50 50 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.5P PS=2.7U M1552 50 50 9 10 PMOS W=0.8U L=0.4U + AD=0.5P PD=2.7U AS=0.3P PS=3.0U M1553 9 50 50 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.5P PS=2.7U M1554 4 53 53 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.4U M1555 53 53 4 3 NMOS W=0.8U L=0.4U
239
+ AD=0.0P PD=2.4U AS=0.0P PS=2.8U M1556 49 54 9 10 PMOS W=0.8U L=0.4U + AD=0.2P PD=2.7U AS=0.3P PS=3.0U M1557 9 54 49 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.2P PS=2.7U M1558 49 54 9 10 PMOS W=0.8U L=0.4U + AD=0.2P PD=2.7U AS=0.3P PS=3.0U M1559 9 54 49 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.2P PS=2.7U M1560 49 54 9 10 PMOS W=0.8U L=0.4U + AD=0.2P PD=2.7U AS=0.3P PS=3.0U M1561 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1562 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1563 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1564 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1565 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1566 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1567 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1568 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1569 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1570 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1571 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1572 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1573 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1574 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1575 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1576 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1577 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1578 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1579 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1580 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1581 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1582 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1583 4 49 37 3 NMOS W=0.8U L=0.4U
+ AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1584 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1585 4 49 8 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.6U M1586 4 49 8 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.6U M1587 4 49 8 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.6U M1588 4 49 8 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.6U M1589 4 49 8 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.6U M1590 4 49 8 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.6U M1591 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1592 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1593 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1594 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1595 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1596 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1597 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1598 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1599 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1600 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1601 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1602 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1603 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1604 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1605 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1606 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1607 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1608 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1609 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1610 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1611 4 49 48 3 NMOS W=0.8U L=0.4U
240
+ AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1612 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1613 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1614 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1615 4 49 44 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.6U M1616 4 49 44 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.6U M1617 4 49 44 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.6U M1618 4 49 44 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.6U M1619 4 49 44 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.6U M1620 4 49 44 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.6U M1621 4 49 49 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.4U M1622 4 49 49 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.4U M1623 4 49 49 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.4U M1624 4 49 49 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.4U M1625 4 49 49 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.4U M1626 4 49 49 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.4U M1627 49 54 9 10 PMOS W=0.8U L=0.4U + AD=0.2P PD=2.7U AS=0.3P PS=3.0U M1628 9 54 49 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.2P PS=2.7U M1629 49 54 9 10 PMOS W=0.8U L=0.4U + AD=0.2P PD=2.7U AS=0.3P PS=3.0U M1630 9 54 49 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.2P PS=2.7U M1631 49 54 9 10 PMOS W=0.8U L=0.4U + AD=0.2P PD=2.7U AS=0.3P PS=3.0U M1632 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1633 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1634 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1635 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1636 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1637 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1638 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1639 37 49 4 3 NMOS W=0.8U L=0.4U
+ AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1640 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1641 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1642 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1643 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1644 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1645 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1646 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1647 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1648 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1649 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1650 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1651 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1652 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1653 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1654 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1655 37 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1656 8 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.6U AS=0.0P PS=2.8U M1657 8 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.6U AS=0.0P PS=2.8U M1658 8 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.6U AS=0.0P PS=2.8U M1659 8 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.6U AS=0.0P PS=2.8U M1660 8 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.6U AS=0.0P PS=2.8U M1661 8 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.6U AS=0.0P PS=2.8U M1662 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1663 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1664 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1665 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1666 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1667 48 49 4 3 NMOS W=0.8U L=0.4U
241
+ AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1668 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1669 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1670 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1671 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1672 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1673 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1674 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1675 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1676 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1677 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1678 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1679 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1680 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1681 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1682 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1683 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1684 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1685 48 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1686 44 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.6U AS=0.0P PS=2.8U M1687 44 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.6U AS=0.0P PS=2.8U M1688 44 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.6U AS=0.0P PS=2.8U M1689 44 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.6U AS=0.0P PS=2.8U M1690 44 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.6U AS=0.0P PS=2.8U M1691 44 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.6U AS=0.0P PS=2.8U M1692 49 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.4U AS=0.0P PS=2.8U M1693 49 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.4U AS=0.0P PS=2.8U M1694 49 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.4U AS=0.0P PS=2.8U M1695 49 49 4 3 NMOS W=0.8U L=0.4U
+ AD=0.0P PD=2.4U AS=0.0P PS=2.8U M1696 49 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.4U AS=0.0P PS=2.8U M1697 49 49 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.4U AS=0.0P PS=2.8U M1698 49 54 9 10 PMOS W=0.8U L=0.4U + AD=0.2P PD=2.7U AS=0.3P PS=3.0U M1699 9 54 49 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.2P PS=2.7U M1700 49 54 9 10 PMOS W=0.8U L=0.4U + AD=0.2P PD=2.7U AS=0.3P PS=3.0U M1701 9 54 49 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.2P PS=2.7U M1702 49 54 9 10 PMOS W=0.8U L=0.4U + AD=0.2P PD=2.7U AS=0.3P PS=3.0U M1703 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1704 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1705 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1706 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1707 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1708 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1709 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1710 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1711 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1712 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1713 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1714 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1715 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1716 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1717 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1718 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1719 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1720 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1721 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1722 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1723 4 49 37 3 NMOS W=0.8U L=0.4U
242
+ AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1724 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1725 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1726 4 49 37 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1727 4 49 8 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.6U M1728 4 49 8 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.6U M1729 4 49 8 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.6U M1730 4 49 8 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.6U M1731 4 49 8 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.6U M1732 4 49 8 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.6U M1733 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1734 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1735 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1736 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1737 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1738 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1739 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1740 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1741 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1742 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1743 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1744 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1745 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1746 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1747 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1748 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1749 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1750 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1751 4 49 48 3 NMOS W=0.8U L=0.4U
+ AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1752 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1753 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1754 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1755 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1756 4 49 48 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.8U M1757 4 49 44 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.6U M1758 4 49 44 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.6U M1759 4 49 44 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.6U M1760 4 49 44 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.6U M1761 4 49 44 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.6U M1762 4 49 44 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.6U M1763 4 49 49 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.4U M1764 4 49 49 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.4U M1765 4 49 49 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.4U M1766 4 49 49 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.4U M1767 4 49 49 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.4U M1768 4 49 49 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.4U M1769 49 54 9 10 PMOS W=0.8U L=0.4U + AD=0.2P PD=2.7U AS=0.3P PS=3.0U M1770 9 54 49 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.2P PS=2.7U M1771 49 54 9 10 PMOS W=0.8U L=0.4U + AD=0.2P PD=2.7U AS=0.3P PS=3.0U M1772 9 54 49 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.2P PS=2.7U M1773 49 54 9 10 PMOS W=0.8U L=0.4U + AD=0.2P PD=2.7U AS=0.3P PS=3.0U M1774 49 54 9 10 PMOS W=0.8U L=0.4U + AD=0.2P PD=2.7U AS=0.3P PS=3.0U M1775 9 54 49 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.2P PS=2.7U M1776 49 54 9 10 PMOS W=0.8U L=0.4U + AD=0.2P PD=2.7U AS=0.3P PS=3.0U M1777 9 54 49 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.2P PS=2.7U M1778 49 54 9 10 PMOS W=0.8U L=0.4U + AD=0.2P PD=2.7U AS=0.3P PS=3.0U M1779 49 54 9 10 PMOS W=0.8U L=0.4U
243
+ AD=0.2P PD=2.7U AS=0.3P PS=3.0U M1780 9 54 49 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.2P PS=2.7U M1781 49 54 9 10 PMOS W=0.8U L=0.4U + AD=0.2P PD=2.7U AS=0.3P PS=3.0U M1782 9 54 49 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.2P PS=2.7U M1783 49 54 9 10 PMOS W=0.8U L=0.4U + AD=0.2P PD=2.7U AS=0.3P PS=3.0U M1784 49 54 9 10 PMOS W=0.8U L=0.4U + AD=0.2P PD=2.7U AS=0.3P PS=3.0U M1785 9 54 49 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.2P PS=2.7U M1786 49 54 9 10 PMOS W=0.8U L=0.4U + AD=0.2P PD=2.7U AS=0.3P PS=3.0U M1787 9 54 49 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.2P PS=2.7U M1788 49 54 9 10 PMOS W=0.8U L=0.4U + AD=0.2P PD=2.7U AS=0.3P PS=3.0U M1789 49 54 9 10 PMOS W=0.8U L=0.4U + AD=0.2P PD=2.7U AS=0.3P PS=3.0U M1790 9 54 49 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.2P PS=2.7U M1791 49 54 9 10 PMOS W=0.8U L=0.4U + AD=0.2P PD=2.7U AS=0.3P PS=3.0U M1792 9 54 49 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.2P PS=2.7U M1793 49 54 9 10 PMOS W=0.8U L=0.4U + AD=0.2P PD=2.7U AS=0.3P PS=3.0U M1794 49 54 9 10 PMOS W=0.8U L=0.4U + AD=0.2P PD=2.7U AS=0.3P PS=3.0U M1795 9 54 49 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.2P PS=2.7U M1796 49 54 9 10 PMOS W=0.8U L=0.4U + AD=0.2P PD=2.7U AS=0.3P PS=3.0U M1797 9 54 49 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.2P PS=2.7U M1798 49 54 9 10 PMOS W=0.8U L=0.4U + AD=0.2P PD=2.7U AS=0.3P PS=3.0U M1799 9 50 50 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.5P PS=2.7U M1800 50 50 9 10 PMOS W=0.8U L=0.4U + AD=0.5P PD=2.7U AS=0.3P PS=3.0U M1801 9 50 50 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.5P PS=2.7U M1802 50 50 9 10 PMOS W=0.8U L=0.4U + AD=0.5P PD=2.7U AS=0.3P PS=3.0U M1803 9 50 50 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.5P PS=2.7U M1804 9 50 50 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.5P PS=2.7U M1805 50 50 9 10 PMOS W=0.8U L=0.4U + AD=0.5P PD=2.7U AS=0.3P PS=3.0U M1806 9 50 50 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.5P PS=2.7U M1807 50 50 9 10 PMOS W=0.8U L=0.4U
+ AD=0.5P PD=2.7U AS=0.3P PS=3.0U M1808 9 50 50 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.5P PS=2.7U M1809 4 55 54 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.9U M1810 54 55 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.9U AS=0.0P PS=2.8U M1811 4 55 54 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.9U M1812 49 54 9 10 PMOS W=0.8U L=0.4U + AD=0.2P PD=2.7U AS=0.3P PS=3.0U M1813 9 54 49 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.2P PS=2.7U M1814 49 54 9 10 PMOS W=0.8U L=0.4U + AD=0.2P PD=2.7U AS=0.3P PS=3.0U M1815 9 54 49 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.2P PS=2.7U M1816 49 54 9 10 PMOS W=0.8U L=0.4U + AD=0.2P PD=2.7U AS=0.3P PS=3.0U M1817 4 55 54 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.9U M1818 54 55 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.9U AS=0.0P PS=2.8U M1819 4 55 54 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.9U M1820 49 54 9 10 PMOS W=0.8U L=0.4U + AD=0.2P PD=2.7U AS=0.3P PS=3.0U M1821 9 54 49 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.2P PS=2.7U M1822 49 54 9 10 PMOS W=0.8U L=0.4U + AD=0.2P PD=2.7U AS=0.3P PS=3.0U M1823 9 54 49 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.2P PS=2.7U M1824 49 54 9 10 PMOS W=0.8U L=0.4U + AD=0.2P PD=2.7U AS=0.3P PS=3.0U M1825 4 55 54 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.9U M1826 54 55 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.9U AS=0.0P PS=2.8U M1827 4 55 54 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.9U M1828 49 54 9 10 PMOS W=0.8U L=0.4U + AD=0.2P PD=2.7U AS=0.3P PS=3.0U M1829 9 54 49 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.2P PS=2.7U M1830 49 54 9 10 PMOS W=0.8U L=0.4U + AD=0.2P PD=2.7U AS=0.3P PS=3.0U M1831 9 54 49 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.2P PS=2.7U M1832 49 54 9 10 PMOS W=0.8U L=0.4U + AD=0.2P PD=2.7U AS=0.3P PS=3.0U M1833 4 55 54 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.9U M1834 54 55 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.9U AS=0.0P PS=2.8U M1835 4 55 54 3 NMOS W=0.8U L=0.4U
244
+ AD=0.0P PD=2.8U AS=0.0P PS=2.9U M1836 49 54 9 10 PMOS W=0.8U L=0.4U + AD=0.2P PD=2.7U AS=0.3P PS=3.0U M1837 9 54 49 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.2P PS=2.7U M1838 49 54 9 10 PMOS W=0.8U L=0.4U + AD=0.2P PD=2.7U AS=0.3P PS=3.0U M1839 9 54 49 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.2P PS=2.7U M1840 49 54 9 10 PMOS W=0.8U L=0.4U + AD=0.2P PD=2.7U AS=0.3P PS=3.0U M1841 4 55 54 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.9U M1842 54 55 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.9U AS=0.0P PS=2.8U M1843 4 55 54 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.9U M1844 49 54 9 10 PMOS W=0.8U L=0.4U + AD=0.2P PD=2.7U AS=0.3P PS=3.0U M1845 9 54 49 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.2P PS=2.7U M1846 49 54 9 10 PMOS W=0.8U L=0.4U + AD=0.2P PD=2.7U AS=0.3P PS=3.0U M1847 9 54 49 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.2P PS=2.7U M1848 49 54 9 10 PMOS W=0.8U L=0.4U + AD=0.2P PD=2.7U AS=0.3P PS=3.0U M1849 4 55 54 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.9U M1850 54 55 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.9U AS=0.0P PS=2.8U M1851 4 55 54 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.9U M1852 49 54 9 10 PMOS W=0.8U L=0.4U + AD=0.2P PD=2.7U AS=0.3P PS=3.0U M1853 9 54 49 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.2P PS=2.7U M1854 49 54 9 10 PMOS W=0.8U L=0.4U + AD=0.2P PD=2.7U AS=0.3P PS=3.0U M1855 9 54 49 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.2P PS=2.7U M1856 49 54 9 10 PMOS W=0.8U L=0.4U + AD=0.2P PD=2.7U AS=0.3P PS=3.0U M1857 4 55 55 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.4U M1858 55 55 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.4U AS=0.0P PS=2.8U M1859 54 54 9 10 PMOS W=0.8U L=0.4U + AD=0.5P PD=2.7U AS=0.3P PS=3.0U M1860 9 54 54 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.5P PS=2.7U M1861 54 54 9 10 PMOS W=0.8U L=0.4U + AD=0.5P PD=2.7U AS=0.3P PS=3.0U M1862 9 54 54 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.5P PS=2.7U M1863 54 54 9 10 PMOS W=0.8U L=0.4U
+ AD=0.5P PD=2.7U AS=0.3P PS=3.0U M1864 4 55 55 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.4U M1865 55 55 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.4U AS=0.0P PS=2.8U M1866 54 54 9 10 PMOS W=0.8U L=0.4U + AD=0.5P PD=2.7U AS=0.3P PS=3.0U M1867 9 54 54 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.5P PS=2.7U M1868 54 54 9 10 PMOS W=0.8U L=0.4U + AD=0.5P PD=2.7U AS=0.3P PS=3.0U M1869 9 54 54 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.5P PS=2.7U M1870 54 54 9 10 PMOS W=0.8U L=0.4U + AD=0.5P PD=2.7U AS=0.3P PS=3.0U M1871 4 55 55 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.8U AS=0.0P PS=2.4U M1872 55 55 4 3 NMOS W=0.8U L=0.4U + AD=0.0P PD=2.4U AS=0.0P PS=2.8U M1873 54 54 9 10 PMOS W=0.8U L=0.4U + AD=0.5P PD=2.7U AS=0.3P PS=3.0U M1874 9 54 54 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.5P PS=2.7U M1875 54 54 9 10 PMOS W=0.8U L=0.4U + AD=0.5P PD=2.7U AS=0.3P PS=3.0U M1876 9 54 54 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.5P PS=2.7U M1877 54 54 9 10 PMOS W=0.8U L=0.4U + AD=0.5P PD=2.7U AS=0.3P PS=3.0U M1878 54 54 9 10 PMOS W=0.8U L=0.4U + AD=0.5P PD=2.7U AS=0.3P PS=3.0U M1879 9 54 54 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.5P PS=2.7U M1880 54 54 9 10 PMOS W=0.8U L=0.4U + AD=0.5P PD=2.7U AS=0.3P PS=3.0U M1881 9 54 54 10 PMOS W=0.8U L=0.4U + AD=0.3P PD=3.0U AS=0.5P PS=2.7U M1882 54 54 9 10 PMOS W=0.8U L=0.4U + AD=0.5P PD=2.7U AS=0.3P PS=3.0U C1 43 4 8.2F C2 9 32 8.5F C3 9 30 1.6F C4 7 18 34.0F C5 47 9 75.9F C6 50 4 15.0F C7 4 13 160.2F C8 51 34 3.1F C9 9 29 8.5F C10 41 4 13.2F C11 9 24 1.5F C12 4 21 3.7F C13 14 34 3.3F C14 6 5 6.4F C15 4 8 50.6F C16 45 4 27.5F
245
C17 9 26 11.2F C18 4 52 2.5F C19 22 23 2.2F C20 13 11 1.9F C21 9 19 10.5F C22 16 52 3.0F C23 9 7 81.7F C24 14 17 1.1F C25 41 20 2.9F C26 42 4 12.1F C27 54 9 11.3F C28 1 4 5.4F C29 9 23 3.2F C30 4 30 3.7F C31 44 9 38.7F C32 31 32 4.2F C33 38 4 10.9F C34 2 1 6.4F C35 9 4 1255.1F C36 53 4 3.5F C37 49 9 52.5F C38 9 33 1.6F C39 4 24 2.5F C40 20 22 4.4F C41 46 4 13.8F C42 47 43 34.0F C43 9 31 10.5F C44 9 27 1.6F C45 13 14 2.2F C46 43 9 81.7F C47 28 29 4.2F C48 48 4 178.8F C49 49 48 1.1F C50 4 7 8.2F C51 51 52 2.0F C52 9 28 10.5F C53 39 4 12.8F C54 9 20 8.5F C55 4 37 178.8F C56 49 37 1.1F C57 50 9 11.3F C58 54 4 15.0F C59 40 34 3.8F C60 4 5 5.4F C61 9 25 2.3F C62 44 4 50.6F C63 9 21 1.6F C64 11 34 2.2F C65 19 20 4.2F C66 25 26 2.3F C67 9 8 38.7F C68 49 4 85.3F C69 4 33 3.7F C70 9 18 75.9F C71 51 9 51.9F C72 55 4 3.5F
C73 9 22 8.6F C74 4 27 2.9F C75 40 0 9.2F C76 23 0 2.7F C77 28 0 5.8F C78 29 0 5.9F C79 18 0 28.1F C80 7 0 30.0F C81 47 0 25.4F C82 43 0 27.2F C83 13 0 79.8F C84 12 0 8.1F C85 15 0 8.1F C86 11 0 9.8F C87 14 0 9.9F C88 4 0 1667.5F C89 19 0 5.9F C90 37 0 53.7F C91 9 0 345.1F C92 5 0 5.5F C93 1 0 5.5F C94 2 0 7.1F C95 6 0 6.9F C96 39 0 6.0F C97 55 0 9.2F C98 35 0 5.1F C99 36 0 5.4F C100 41 0 6.0F C101 21 0 8.5F C102 31 0 5.7F C103 32 0 5.8F C104 53 0 9.2F C105 45 0 9.3F C106 44 0 86.9F C107 52 0 40.6F C108 46 0 5.8F C109 16 0 9.2F C110 17 0 8.2F C111 42 0 5.8F C112 26 0 6.1F C113 22 0 7.8F C114 20 0 8.1F C115 33 0 8.5F C116 51 0 48.6F C117 48 0 53.7F C118 54 0 38.2F C119 49 0 308.1F C120 27 0 8.5F C121 30 0 8.5F C122 25 0 2.6F C123 38 0 5.8F C124 34 0 13.2F C125 24 0 8.4F C126 50 0 38.2F C127 8 0 86.9F
246
*** Node Listing for subckt: FRONT_POST3_SIM ** 0 Node 0 is the global ground node ** 1 a_3282_1590# ** 2 Voffset1 ** 3 GND! ** 4 Vss_gm ** 5 a_3382_1590# ** 6 Voffset2 ** 7 out4 ** 8 a_3990_1439# ** 9 Vdd_gm ** 10 Vdd! ** 11 midin1 ** 12 Iin1 ** 13 Vdd_cmAmp ** 14 midin2 ** 15 Iin2 ** 16 cmAmpout1 ** 17 cmAmpout2 ** 18 out3 ** 19 out1_1stage ** 20 out2_1stage ** 21 a_3235_1440# ** 22 offsetout2 ** 23 a_3300_1436# ** 24 a_3338_1440# ** 25 a_3388_1500# ** 26 offsetout1 ** 27 a_3438_1440# ** 28 out1 ** 29 out2 ** 30 a_3547_1440# ** 31 Bufferin1 ** 32 Bufferin2 ** 33 a_3647_1440# ** 34 Com_in ** 35 Bufferout1 ** 36 Bufferout2 ** 37 a_3801_1429# ** 38 a_3179_1385# ** 39 a_3283_1385# ** 40 Com_load ** 41 a_3387_1385# ** 42 a_3491_1385# ** 43 out6 ** 44 a_4343_1439# ** 45 a_3693_1375# ** 46 a_3591_1385# ** 47 out5 ** 48 a_4154_1429# ** 49 IbiasN_gm ** 50 a_2835_1195# ** 51 IbiasN_cm ** 52 Vss_cmAmp ** 53 IcmFromDac
** 54 a_4529_1170# ** 55 IgmFromDac .END
247
Appendix 2.2.4. NSC Transimpedance Optical Receiver SPICE Input
Control File
***** Differential Amplifier Simulation ***** .options ACCURATE post list .temp 25 100 .param I_1=-8u I_2=8u I_0=0u bps=1.25n slope=0.001n Vdd! 10 0 1.65v Vgnd! 3 0 -1.65v *********************************** Vdd_cmamp 13 0 1.65v Vss_cmamp 52 0 -1.65v Vdd_gm 9 0 1.65v Vss_gm 4 0 -1.65v ************************************ IbiasN_cm 0 53 70uA IbiasN_gm 0 55 60uA *C_in 0 12 1.0p V_in 981 12 0v I2 0 15 ac 1 Iamp_in 0 981 ac 1 pwl + (0ns,'I_1') ('2*bps-slope','I_1') + ('2*bps','I_2') ('9*bps','I_2') + ('9*bps+slope','I_1') ('10*bps','I_1') + ('10*bps+slope','I_2') ('11*bps','I_2') + ('11*bps+slope','I_1') ('18*bps','I_1') + ('18*bps+slope','I_2') ('19*bps','I_2') + ('19*bps+slope','I_1') ('20*bps','I_1') + ('20*bps+slope','I_2') ('22*bps','I_2') + ('22*bps+slope','I_1') ('23*bps','I_1') + ('23*bps+slope','I_2') ('24*bps','I_2') + ('24*bps+slope','I_1') ('26*bps','I_1') + ('26*bps+slope','I_2') ('28*bps','I_2') + ,R Voffset1 2 0 dc 342.3mV Voffset2 6 0 dc 330mV Vdum 999 0 pulse 0 1 0n '3*bps-slope/100000' 'slope/100000' 0n '3*bps' Rout1 43 0 50 Rout2 47 0 50 .include 'nsc035bsim3_typ.lib' .tran .01n 100n
248
ac Dec 1000 1mega 10giga .noise V(16) Iamp_in 10000 .plot noise onoise .dc IVoffset1 45u 60u .1u .include 'FRONT_POST3_SIM.spice' .op .end
249
Appendix 2.3 Mathcad Simulation for ISI Effect
This simulation shows FDDI codes with the worst case (3 zeros) low frequencies
up t t s, if t t s< 0, 1, dn t t s, if t t s< 0, 1,
p5 t t s, up t t s 0, dn t t s 1, up t t s 2, dn t t s 3,up t t s 4, dn t t s 5, up t t s 6, dn t t s 7,+
...
up t t s 8, dn t t s 9,+...
clk t( ) p5 t 0,( ) p5 t 10,( ) p5 t 20,( ) p5 t 30,( ) p5 t 40,( ) p5 t 50,( )
I c11111u t t s, up t t s 1, dn t t s 3, up t t s 5, dn t t s 7, up t t s 9,
I c11111d t t s, dn t t s 1, up t t s 3, dn t t s 5, up t t s 7, dn t t s 9,
3 c10101u t t s, up t t s 1, dn t t s 5, up t t s 9,
T c01101u t t s, up t t s 3, dn t t s 5, up t t s 9,
T c01101d t t s, dn t t s 3, up t t s 5, dn t t s 9,
J c11000u t t s, up t t s 1, dn t t s 3,
K c10001u t t s, up t t s 1, dn t t s 9,
8 c10010u t t s, up t t s 1, dn t t s 7, FDDI code names givenTypical FDDI packet is(approx 16 I symbols)JK(data)TTc10010d t t s, dn t t s 1, up t t s 7,
1 c01001u t t s, up t t s 3, dn t t s 9,
c01001d t t s, dn t t s 3, up t t s 9,
4 c01010u t t s, up t t s 3, dn t t s 7,
c01010d t t s, dn t t s 3, up t t s 7,
2 c10100u t t s, up t t s 1, dn t t s 5,
7 c01111u t t s, up t t s 3, dn t t s 5, up t t s 7, dn t t s 9,
sig1 t( ) c11111u t 1,( ) c11111d t 11,( ) c11000u t 21,( ) c10001u t 31,( )c01101u t 41,( ) c01101d t 51,( )+
... This is IIJKTT(3 zeros)
sig2 t( ) c10010u t 1,( ) c01001u t 11,( ) c01010u t 21,( ) c10010u t 31,( )c01001u t 41,( ) c01010u t 51,( )+
... This is 814814(2 zeros)
sig t( ) c10100u t 1,( ) c01111u t 11,( ) c01010u t 21,( ) c10100u t 31,( )c01001u t 41,( ) c10010u t 51,( )+
... This is 274213(3 zeros)
tp t o p t step. sigv p sig t p sig1 t p 61 0.5 fsig fft sigv( )
filt f( ) 1
1 1 f.
pole
clkv p clk tpsweepv p0
tp
tclk t( ) d
filtv p2 filt t p2 ffsig p2 filtv p2 fsig p2.
sigiv ifft ffsig( ) filti ifft filtv( )
The filter cutoffs are at max*9/8 and max*1.25/8
62.5 pole8
. 78.125= zero 2 pole 10 62.5 zero.
815.625=62.5 pole
8.
1250.625=
if fsig p2 0> fsig p2, 0.01,
if filtv p2 0> filtv p2, 0.01,
1
if p2520. 0> p2
520., 0.1,
0.1 1 10 1001 .10 3
0.01
0.1
1
10
t step14
t end 128 t o 0 stepst end t o
t stepp 0 steps 1.. p2 0 steps
2.. steps
21 255=
steps 512=
20 40 60 80 100 120 140
0.5
0
0.5
FDDI codeBand Passed FDDI CodeZero Crossing
250
APPENDIX III
HSPICE TRANSIENT SIMULATION RESULT
Appendix 3.1. Low Impedance Open Loop Optical Receiver
This simulation results are transient response of low impedance open loop optical
receiver at 480Mbps and 622Mbps. The simulations are performed at different optical
powers and different input capacitances.
251
Figure Appedix 3-1: Transient Response to 2µA Input Current with 0.1pF Input Capacitance at 480Mbps
Figure Appedix 3-2: Transient Response to 2µA Input Current with 0.5pF Input Capacitance at 480Mbps
252
Figure Appedix 3-3: Transient Response to 2µA Input Current with 1.0pF Input Capacitance at 480Mbps
Figure Appedix 3-4: Transient Response to 4µA Input Current with 0.1pF Input Capacitance at 480Mbps
253
Figure Appedix 3-5: Transient Response to 4µA Input Current with 0.5pF Input Capacitance at 480Mbps
Figure Appedix 3-6: Transient Response to 4µA Input Current with 1.0pF Input Capacitance at 480Mbps
254
Figure Appedix 3-7: Transient Response to 8µA Input Current with 0.1pF Input Capacitance at 480Mbps
Figure Appedix 3-8: Transient Response to 8µA Input Current with 0.5pF Input Capacitance at 480Mbps
255
Figure Appedix 3-9: Transient Response to 8µA Input Current with 1.0pF Input Capacitance at 480Mbps
Figure Appedix 3-10: Transient Response to 16µA Input Current with 0.1pF Input Capacitance at 480Mbps
256
Figure Appedix 3-11: Transient Response to 16µA Input Current with 0.5pF Input Capacitance at 480Mbps
Figure Appedix 3-12: Transient Response to 16µA Input Current with 1.0pF Input Capacitance at 480Mbps
257
Figure Appedix 3-13: Transient Response to 2µA Input Current with 0.1pF Input Capacitance at 622Mbps
Figure Appedix 3-14: Transient Response to 2µA Input Current with 0.5pF Input Capacitance at 622Mbps
258
Figure Appedix 3-15: Transient Response to 2µA Input Current with 1.0pF Input Capacitance at 622Mbps
Figure Appedix 3-16: Transient Response to 4µA Input Current with 0.1pF Input Capacitance at 622Mbps
259
Figure Appedix 3-17: Transient Response to 4µA Input Current with 0.5pF Input Capacitance at 622Mbps
Figure Appedix 3-18: Transient Response to 4µA Input Current with 1.0pF Input Capacitance at 622Mbps
260
Figure Appedix 3-19: Transient Response to 8µA Input Current with 0.1pF Input Capacitance at 622Mbps
Figure Appedix 3-20: Transient Response to 8µA Input Current with 0.5pF Input Capacitance at 622Mbps
261
Figure Appedix 3-21: Transient Response to 8µA Input Current with 1.0pF Input Capacitance at 622Mbps
Figure Appedix 3-22: Transient Response to 16µA Input Current with 0.1pF Input Capacitance at 622Mbps
262
Figure Appedix 3-23: Transient Response to 16µA Input Current with 0.5pF Input Capacitance at 622Mbps
Figure Appedix 3-24: Transient Response to 16µA Input Current with 1.0pF Input Capacitance at 622Mbps
263
Appendix 3.2. Transimpedance type Optical Receiver
This simulation results are transient response of low impedance open loop optical
receiver at 800Mbps and 1Gbps. The simulations are performed at different optical
powers and different input capacitances.
264
Figure Appedix 3-25: Transient Response to 2uA Input Current with 0.1pF input Capacitance at 800Mbps
Figure Appedix 3-26: Transient Response to 2uA Input Current with 0.5pF input Capacitance at 800Mbps
265
Figure Appedix 3-27: Transient Response to 2uA Input Current with 1.0pF input Capacitance at 800Mbps
Figure Appedix 3-28: Transient Response to 4µA Input Current with 0.1pF input Capacitance at 800Mbps
266
Figure Appedix 3-29: Transient Response to 4µA Input Current with 0.5pF input Capacitance at 800Mbps
Figure Appedix 3-30: Transient Response to 4µA Input Current with 1.0pF input Capacitance at 800Mbps
267
Figure Appedix 3-31: Transient Response to 8µA Input Current with 0.1pF input Capacitance at 800Mbps
Figure Appedix 3-32: Transient Response to 8µA Input Current with 0.5pF input Capacitance at 800Mbps
268
Figure Appedix 3-33: Transient Response to 8µA Input Current with 1.0pF input Capacitance at 800Mbps
Figure Appedix 3-34: Transient Response to 16µA Input Current with 0.1pF input Capacitance at 800Mbps
269
Figure Appedix 3-35: Transient Response to 16µA Input Current with 0.5pF input Capacitance at 800Mbps
Figure Appedix 3-36: Transient Response to 16µA Input Current with 1.0pF input Capacitance at 800Mbps
270
Figure Appedix 3-37: Transient Response to 2µA Input Current with 0.1pF input Capacitance at 1Gbps
Figure Appedix 3-38: Transient Response to 2µA Input Current with 0.5pF input Capacitance at 1Gbps
271
Figure Appedix 3-39: Transient Response to 2µA Input Current with 1.0pF input Capacitance at 1Gbps
Figure Appedix 3-40: Transient Response to 4µA Input Current with 0.1pF input Capacitance at 1Gbps
272
Figure Appedix 3-41: Transient Response to 4µA Input Current with 0.5pF input Capacitance at 1Gbps
Figure Appedix 3-42: Transient Response to 4µA Input Current with 1.0pF input Capacitance at 1Gbps
273
Figure Appedix 3-43: Transient Response to 8µA Input Current with 0.1pF input Capacitance at 1Gbps
Figure Appedix 3-44: Transient Response to 8µA Input Current with 0.5pF input Capacitance at 1Gbps
274
Figure Appedix 3-45: Transient Response to 8µA Input Current with 1.0pF input Capacitance at 1Gbps
Figure Appedix 3-46: Transient Response to 16µA Input Current with 0.1pF input Capacitance at 1Gbps
275
Figure Appedix 3-47 Transient Response to 16µA Input Current with 0.5pF input Capacitance at 1Gbps
Figure Appedix 3-48 Transient Response to 16µA Input Current with 1.0pF input Capacitance at 1Gbps
276
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VITA
Jae Joon Chang was born and grew up in Seoul, Korea on November 4th, 1969.
He is the second son of Jiyoul Chang and Boyoung Kim and happily married to Yoonah
Kim.
From 1989 to 1995, Mr. Chang attended Hanyang University, Seoul, Korea,
where he received a Bachelor of Science degree in Electrical Engineering. He also served
in Korean army for 2 years during this time.
He came to United States in June 1995 and entered graduate school in Georgia
Institute of Technology in October. He joined High Speed Signal Processing Group,
headed by Dr. Martin A. Brooke, his Ph.D. advisor at the same time. And he has been
working as a research assistant until now. He has received a Master of Science in
Electrical Engineering at Georgia Institute of Technology in 1997 and currently he’s
pursuing his Doctoral degree in the same area.
His research interest includes high-speed CMOS optical receiver circuit and
system designs, passive component-free clock recovery and PLL circuit design, system
simulation and optimization techniques, and noise analysis and characterization in Mixed
Signal Processing Chip.