CMOS RF Integrated Circuits at 5 GHz and Beyond

CMOS RF Integrated Circuits at 5 GHzand Beyond

THOMAS H. LEE, MEMBER, IEEE,AND S. SIMON WONG, FELLOW, IEEE

A strong demand for wireless products, an insatiable thirst forspectrum that pushes carrier frequencies ever upward, and the con-stant quest for higher performance at lower power and cost, haverecently driven the development of radio frequency integrated cir-cuit (RF IC) technology in unprecedented ways. These pressures arestimulating novel solutions that allow RF ICs to enjoy more of thebenefits of Moore’s law than has been the case in the past. In addi-tion to regular raw transistor speed increases, the growing numberof interconnect layers allows the realization of improved inductors,capacitors, and transmission lines. A deeper understanding of noiseat both the device and circuit level has improved the performance oflow noise amplifiers (LNAs) and oscillators. Finally, an appropriateraiding of circuit ideas dating back to the vacuum tube era enablesexcellent performance, even when working close to the limits of atechnology.

This paper surveys some of these developments in the contextof low-power RF CMOS technology, with a focus on an illustra-tive implementation of a low-power 5-GHz wireless LAN receiverin 0.25-�m CMOS. Thanks to these recent advances in passivecomponents and active circuits, the blocks comprising the receiverconsume a total of approximately 37 mW. These blocks includean image-reject LNA, image-reject downconverter, and a completefrequency synthesizer. The overall noise figure is 5 dB, and theinput-referred third-order intercept (IIP3) is�2 dBm. To under-score that 5 GHz does not represent an upper bound by any means,this paper concludes with a look at active circuits that function be-yond 15–20 GHz, and a characterization of on-chip transmissionlines up to 50 GHz, all in the context of how scaling is expected toshape future developments.

Keywords—CMOS, HIPERLAN, LAN, radio, receiver, RF IC,transceiver, transmitter, wireless LAN.

I. INTRODUCTION

The remarkable explosive growth in personal wirelesscommunications continues to stimulate advances on multiplefronts. Unrelenting demand for simultaneous improvementsin performance, cost, and power consumption compelsengineers to circumscribe the design space with muchgreater refinement than in the past. This imperative is feltmost acutely in the design of CMOS RF integrated circuits(RF ICs), where the inferiority of both active and passive

Manuscript received December 31, 1999; revised July 14, 2000.The authors are with the Center for Integrated Systems, Stanford Uni-

versity, Stanford, CA 94305-4070 USA (e-mail: [email protected];[email protected]).

Publisher Item Identifier S 0018-9219(00)09131-3.

devices forces designers to work harder to achieve a givenlevel of performance. While this paper, therefore, focuseson CMOS implementations, nearly all of the ideas presentedhere apply to realizations in other technologies.

This paper begins with an enumeration of the attributesand limitations of CMOS as a medium in which to build RFICs, with an emphasis on the quality of realizable passivecomponents. A discussion of the design of two critical RFbuilding blocks, low noise amplifiers (LNAs) and oscillators,follows. An illustrative 5-GHz receiver design example thenties together many of the ideas presented earlier, and revealsno fundamental limitations that would prevent operation atfrequencies well in excess of 5 GHz as scaling continuesalong expected trajectories.

II. CMOS AS A RADIO-FREQUENCYTECHNOLOGY

As is well appreciated, conformance with Moore’s lawregularly delivers faster and smaller transistors, with those ofthe 0.18- m generation of CMOS (now ramping into volumeproduction) exhibiting peak values in excess of 50 GHz.1

Although this reliable doubling of transistor speed everythree years goes a long way toward offsetting the otherwiseinferior device physics of CMOS (e.g., worse com-pared to bipolars, worse mobility relative to GaAs), RF cir-cuits have demands beyond the mere availability of tran-sistors with high . Among these are low noise, high lin-earity, and, in particular, good passive components (capac-itors and inductors). Unfortunately, these RF essentials arelargely irrelevant in the context of digital ICs, and it is thelatter that has driven, and continues to dictate, CMOS tech-nology evolution. It has been necessary to develop numerousworkarounds to build RF ICs beyond 5 GHz in a medium thathas suffered, thus, from benign neglect. We consider first theissue of passive components, and then examine RF-relevanttransistor properties.

A. On-Chip Inductors

In contrast with ordinary digital circuits, passive compo-nents are necessary adjuncts to most RF circuits. Inductors

1Practical linear circuits typically operate devices at some fraction of thepeak value.

0018–9219/00$10.00 © 2000 IEEE

1560 PROCEEDINGS OF THE IEEE, VOL. 88, NO. 10, OCTOBER 2000

Fig. 1. Typical planar spiral inductor.

in particular are critical components in oscillators and othertuned circuits. Although bond wires or package pins can be,and have been, used to make good inductors (with induc-tances on the order of 1 nH/mm), there remains a questionof predictability and manufacturing variability.

A highly predictable and repeatable alternative is to em-ploy planar spiral geometries (Fig. 1), since these are definedby photolithographic processes.

Increasing their attractiveness are recently developed ana-lytical formulas for inductance. These formulas have provensufficiently accurate to obviate the need for electromagneticfield solvers, or algorithmic methods (such as Greenhouse’smethod [2]) in most cases. At the same time, the formulas arerelatively simple, possessing a common form for a variety offrequently used geometries

(1)

wherepermeability;number of turns;arithmetic mean of the inner and outer diameters;a measure of inductor “hollowness,” called the fillfactor:

(2)

The various coefficients are functions of geometry, withvalues given by Table I.

These formulas are usually accurate to within 2%–3%.This attribute, combined with their simplicity, enables andencourages engineers to iterate their designs in search of anoptimum. For example, the innermost turns of a spiral do notcontribute much to the inductance, but can contribute sig-nificant series resistance. These observations have led to thecommon practice of removing the innermost turns to improveperformance. Quite often, then, the best inductors tend besomewhat hollow, with fill factors frequently within 50% ofapproximately 0.5. Because, as we shall see, an on-chip in-ductor brings with it so many parasitics whose relative promi-nence is a function of factors such as frequency, inductance

Table 1Coefficients for Inductance Formula

Fig. 2. Model for planar spiral inductor (eddy current loss notdirectly represented).

value, and substrate characteristics, no single, universally op-timum geometry exists. Fortunately, finding the particularoptimum for a given set of conditions is greatly facilitatedby the simplified inductance formulas.

Unfortunately, CMOS realizations of spiral inductorssuffer from dissipative mechanisms beyond simple con-ductor loss. Achievable values are frequently in the rangeof 5–10, owing to a combination of thin conductors and adissipative silicon substrate. The latter is particularly trou-blesome, for there are two separate mechanisms of substrateloss, each of which contributes to degradation of inductorquality factor. The first may be termed capacitive-currentinduced loss (see Fig. 2) [3].

As seen in the figure, a planar spiral inductor has a substan-tial parasitic capacitance, , between it and the top surfaceof the substrate, because the insulating oxide is thin (typi-cally on the order of 1 m per layer). At high frequencies, thecurrent flows through this capacitance and into the lossy sub-strate (modeled here as a simple parallel network). Theresulting dissipation adds a real component to the imaginary

LEE AND WONG: CMOS RF INTEGRATED CIRCUITS AT 5 GHz AND BEYOND 1561

Fig. 3. Patterned ground shield.

inductive impedance, degrading the quality factor. Relativeto other loss mechanisms, this component can be important atfrequencies where the skin depth exceeds the substrate thick-ness, loosely speaking. As a rough calibration, the skin depthis 5 mm for 10- cm material at 1 GHz. Given that substratethicknesses typically range within a factor of two of approx-imately 500 m, we see that this component of loss may beimportant for lightly doped substrates at low frequencies. Itis fortunate that this loss mechanism can be suppressed to agreat extent by using a grounded electrostatic shield betweenthe inductor and the substrate (Fig. 3) [1].

This patterned ground shield (PGS) functions by creatingwhat is in effect a low-loss pseudosubstrate. The currentsflowing through this capacitance now flow into the less dissi-pative PGS instead of the substrate. Because the PGS may beconstructed out of highly conductive materials (e.g., heavilydoped polysilicon or metal), dissipation by this loss mech-anism can be reduced to very small levels. In some cases,the of resonators built with PGS-enhanced inductors canimprove by a factor of two. The PGS additionally providesa welcome measure of isolation that can be of great benefitin mixed-signal applications, in particular [1]. However, thePGS does increase the parasitic capacitance, an undesired ef-fect that must be accommodated in design. In resonators oroscillators, the parasitic capacitance can often be absorbedinto the network.

A solid ground shield cannot be used, for image currentsinduced in it by the main spiral would set up magnetic fieldsthat would tend to cancel those produced by the spiral proper,resulting in a significant reduction in overall inductance andan increase in loss. The situation is exactly analogous to atransformer whose secondary turn has been short-circuited.To prevent this problem, slots must be cut in the shield tointerrupt the current flow.

As frequencies or substrate doping levels increase towhere the skin depth is comparable to, or smaller than, thesubstrate thickness, image currents (eddy currents) return asa loss mechanism, even in the absence of a solid shield. Inthis case, it is the flow of induced currents in the substratethat causes the problem. This magnetically induced loss is

Fig. 4. Simple model of eddy current loss (other parasitics notshown).

equivalent to transformer action between a (lossy) primary(the main inductance) and a lossy secondary (the imageinductance, terminated in a resistive load), as shown inFig. 4.

The loss in the secondary is fully equivalent to a suitablyadjusted loss in the primary circuit. Recent analytical mod-eling reveals that this effective reflected resistance is approx-imately proportional to thecubeof the inductor diameter [3].Typical engineering practice has been to use generous di-mensions to reduce conductor loss, a strategy that is mostsuccessful when substrate effects may be largely ignored (asis generally the case with GaAs, for example). However,the dramatic sensitivity to layout dimensions of this type ofloss in heavily doped silicon immediately suggests the useof smaller diameters than has been traditional, trading in-creased conductor loss for decreased eddy current loss. Fol-lowing this prescription can yield particularly striking im-provements in quality factor at high frequencies in technolo-gies with heavily doped substrates. These improvements maybe compounded further by exploiting multilevel metalliza-tion to build vertical solenoids in those applications that cantolerate a large turn-to-turn parasitic capacitance.

Through judicious size reduction, and perhaps the use ofa PGS, the former perhaps augmented by exploitation of theever-increasing number of available metal layers, it is pos-sible to realize inductors whose quality factors (e.g.,10or more) are adequate for a great many applications in themid-GHz range of frequencies, even when built over heavilydoped substrates (e.g., 10 mcm, where the skin depth be-comes 50 m at 10 GHz).

B. Fixed Capacitors

Substrate effects are also a problem for realizing RF capac-itors. The most linear capacitors are metal-insulator-metal(MIM) structures, but ordinary parallel-plate capacitors al-ways involve the substrate as an unwanted extra plate (Fig. 5).The lossy parasitic capacitance thus formed is often nearlyequal to the main capacitance. Additionally, process technol-ogists do not reduce the vertical plate spacing as transistor di-mensions shrink, precisely because digital circuit designerscannot tolerate large increases in wiring capacitance fromgeneration to generation. As a consequence, a given valueof parallel-plate capacitance tends to consume a fixed area,independent of process generation. Thus, while transistorsshrink, such capacitors occupy an increasingly large fractionof the total die area.

Because it is the lateral dimensions that are improved witheach advance in photolithography, capacitance structures thatexploit lateral, instead of vertical, flux fortunately do scale


Fig. 5. Conventional parallel plate capacitor.

Fig. 6. Lateral-flux capacitor (comb-type).

as desired. Such lateral flux capacitors (LFCs) take advan-tage of the fact that the allowed spacing between adjacentmetal lines is now smaller than the vertical spacing betweeninterconnect layers, so the capacitance between adjacent con-ductors is appreciable (and growing with each generation).Furthermore, the more lateral flux contributes to the total ca-pacitance, the smaller the bottom plate parasitic capacitancebecomes. Both comb structures (Fig. 6) and more elaboratefractal geometries have been used to implement lateral fluxcapacitors (Fig. 7) [7]. Capacitance boost factors of an orderof magnitude (relative to parallel plate structures) will soonbe feasible, providing an option with capacitance density in-termediate between vertical structures and MOSFET gate ca-pacitances [7].

Another important figure of merit is the -frequencyproduct, and values of 100–200 GHz are readily achievable.Fractal LFCs have the additional attribute that no extra effortis required to distribute current flow in quasi-random direc-tions, thus reducing self-inductance. As a result, satisfactoryoperation is possible up to very high frequencies (e.g., tensof gigahertz).

C. Varactors

The ability to tune is essential for operation over a rangeof frequencies, and also to accommodate manufacturing tol-erances. In discrete RF circuits, a PN diode (frequently hy-perabruptly doped) is generally used as a tuning capacitor.Although standard PN junction diodes can be built out of asource/drain diffusion and n- (or p-) well, the high well re-sistivity typically degrades to undesirably low levels. An-other option is to use the gate capacitance of a standard en-hancement-mode MOSFET, exploiting the change in capac-itance as the gate bias varies from well below threshold towell above threshold.

A minor modification to the standard MOS varactor resultsin substantial improvements in. By replacing, for example,the source/drain diffusions of a PMOS transistor with the

diffusions of an NMOS device, one can construct a MOS

Fig. 7. Lateral-flux capacitor (fractal-type).

Fig. 8. Accumulation-mode MOS capacitor.

capacitor that may be operated in the accumulation mode(Fig. 8).

Fabrication of this structure requires no fundamentalchanges to the process flow (only a design rule adjustment).Such a device’s capacitance exhibits a large change nearthe flatband voltage. Typically, achievable capacitancetuning ranges approach 2:1. Operation in the accumulationmode can be advantageous because of the lowered channelresistance that attends operation in this regime. As a result,large -frequency products (e.g., in excess of 100 GHz) areachievable with current processes, and continue to improveas technology scales [4].

III. MOSFETS AT GIGAHERTZ FREQUENCIES

Another impediment to RF IC design in CMOS has beenthe lack of good device models. In particular, most modelscurrently in use were originally developed for low-frequencyapplications, and fail to predict noise and input impedancecorrectly at radio frequencies. Both of these problems aretraceable to nonquasi-static device behavior that becomes in-creasingly prominent as frequency increases. A rather com-plete treatment of nonquasi-static behavior may be found in[6, Ch. 9], and a simplified device model in [7].

A finite carrier transit velocity implies that signals undergoa phase shift in traversing from source to drain. A fixed timedelay represents an ever-increasing phase shift as frequencyincreases. Assuming that the entire gate may still be treated asa unipotential capacitor plate, the presence of phase-shifted


Fig. 9. Modified gate circuit of MOSFET model.

potentials underneath it causes a departure from the quadra-ture relationship that prevails at low frequencies betweengate voltage and gate current. The normally capacitive gateimpedance, therefore, acquires an increasingly resistivecharacter as frequency increases. It is important to emphasizethat the origin of this resistive component is distinct from theuse of nonsuperconductive gate electrode material.

This resistance has several important consequences. Itcauses the power gain of a MOSFET to be finite becausea source driving the gate sees a dissipative load instead ofa pure capacitance. This resistance must also be taken intoaccount in the design of any amplifier intended to producea specified input impedance (e.g., 50). In addition, thedissipation generates thermal noise that appears at the gateterminal, and any proper design of an LNA must accommo-date this noise. These effects are not correctly captured inthe present generation of public-domain device models, soad hocaccommodation of these phenomena is currently nec-essary for accurate simulation of noise and input impedance.Fortunately, this situation is temporary, for greatly improvedRF-compatible models are being developed [12].

Work by van der Ziel and others has shown that these ef-fects may be modeled with the use of a frequency-dependentconductance in shunt with the gate-source port [8], [9]

(3)

where is the gate-source capacitance and is thedrain-source conductance at zero drain-source voltage. Inolder formulations, the latter parameter is replaced by,the transconductance. In long-channel devices, these twoconductances are the same. However, in the short-channelregime, they diverge in value, and should be used.

This shunt gate conductance not only affects power gainand input impedance, it also generates noise (Fig. 9). De-tailed considerations reveal that one may treat the conduc-tance as generating a thermally noisy gate current whosespectral density is

(4)

where is a technology- and bias-dependent constant (gen-erally in the range of 2–5 for modern devices) chosen to pro-duce agreement with experiment [11].

From (3) and (4), the gate current noise is seen to be non-white. A simple Norton-to-Thévenin transformation of thegate network can be employed to produce a seriesequiv-alent whose noisevoltageis white [10]. Both representationsare correct, of course, and the choice of which to use is madeon the basis of considerations such as computational conve-nience or pedagogy.

Fig. 10. Inductively degenerated single-ended LNA.

IV. L OW-NOISE AMPLIFIER DESIGN AT GIGAHERTZ

FREQUENCIES

The noisy gate current just described is in addition tothe noisy drain current that existing models already pos-sess. These two currents fundamentally share a commonorigin—fluctuating channel charge—so they are partiallycorrelated. The presence of two noise sources with partialcorrelation complicates LNA design. Compounding thedifficulty is the frequent necessity to produce a specified realimpedance (such as 50), using a device which naturallypresents a largely capacitive gate impedance.

The impedance matching problem is best solved throughthe use of inductive degeneration in series with the sourceterminal of the MOSFET. In a fundamental sense, induc-tive degeneration functions by exploiting an effect very sim-ilar to nonquasi-static phenomena. The inductor causes anadditional phase lag between applied gate voltage and theflow of device current, rotating the impedance phasor towardmore real values. This effect was first appreciated explicitlyin the context of vacuum tubes by Strutt and van der Ziel,as reported in these PROCEEDINGSin 1938 [13], with furtherelucidation by Valley and Wallman ten years later [14]. Ithas since been exploited in numerous technologies, rangingfrom bipolar to GaAs and now CMOS. Producing a real inputimpedance this way is desirable because it is accomplishedthrough the use of a lossless and, hence, noiseless inductance.

As seen in Fig. 10, an additional inductance in se-ries with the gate terminal is often employed to cancel anyresidual capacitive reactance at the frequency of operation.The circuit is thus tuned and, therefore, inherently narrow-band. Nevertheless, practical bandwidths are large enough toaccommodate considerable component variation.

An important difference between discrete and integratedcircuit design is the freedom enjoyed by the designer to se-lect a device size to produce some optimum. One procedureto exploit this freedom reveals that the optimum product ofdevice width and operating frequency is very approximately500- m GHz, assuming that the source degeneration induc-tance is chosen to produce a 50-impedance level [15]. Theexistence of an optimum is the result of the presence of thetwo incompletely correlated noise sources. A very narrow de-vice has a small capacitance, and, therefore, requires a large


total inductance to produce resonance. The individual reac-tive impedances are, therefore, large, so that the noisy gatecurrents can generate relatively large input noise voltages.

The noise performance of an amplifier employing a verywide device, on the other hand, is not sensitive to noisy gatecurrent but, for a given fixed drain bias current, suffers fromlow owing to the low device current density. Noise is,thus, relatively more prominent compared with signal at theoutput. In between these two extremes lies an optimum.

With this particular choice of device width, and with cer-tain assumptions of device parameter values, the amplifiernoise factor may be expressed approximately as [15]

(5)

where is the drain noise counterpart of. The general formof this equation is perhaps more important here than the pre-cise value of the various constants. From this equation, wecan expect continuing improvements in noise figure as tech-nologyscales, since continues to increase.Fortunately, thecoefficient in front of the factor does not increase dra-matically as devices scale, despite early fears that this wouldbe the case. Using a typical value of 3.5 for, the device-lim-ited noise figure becomes a quite respectable 1.0 dB if device

is ten times the operating frequency. Practical LNA noisefigures will generally be somewhat larger because of the exis-tence of other noise sources (e.g., inductor loss), but this cal-culation nonetheless underscores the dramatic improvementsdelivered by continued scaling. These improvements may beused to obtain some combination of decreased noise and de-creased power consumption at higher operating frequency.

As a final comment on CMOS LNAs, scaling bestowsan additional benefit: linearity. The most prominent short-channel effect is saturation of carrier velocity. This satura-tion causes a departure from square-law behavior, with thetransconductance approaching a constant value. This con-stancy endows short-channel devices with excellent linearity.Hence, although MOSFETs suffer from inferior -per-unitcurrent (relative to bipolar transistors), improved linearityhelps offset that deficiency. Ifdynamic range-per-unit cur-rent is used instead as a figure of merit, the gap in perfor-mance between MOSFETs and bipolars narrows consider-ably. In many demanding wireless applications, this figure ofmerit is indeed more relevant than simply transconductanceper milliampere.

V. OSCILLATOR PHASE NOISE

Oscillators are another critical transceiver building block.Modern communications systems demand oscillators with anexceptional degree of spectral purity to prevent interferencewith other users, and otherwise to accommodate a crowdedspectrum. The two primary departures from spectral purityare broad-band noise and discrete tones (spurious or “spurs”).The origins of the latter have been much better understoodthan the former, as have been ways to mitigate them.

Until recently, there was no quantitatively correct theorythat explained precisely how circuit noise corrupts an

Fig. 11. LosslessLC resonator and impulse excitation.

Fig. 12. Response ofLC circuit to impulse injected at twodifferent times.

oscillator’s spectrum, although valuable qualitative insightshave guided oscillator design for several decades [16]. Chiefamong these insights are that maximizing both carrier powerand resonator are highly desirable. A more completeunderstanding emerges when one recognizes that oscillatorsmay be treated as periodically time-varying systems whosenoise-to-output phase relationships are well approximatedas linear. In contrast with the linear time-invariant (LTI)models that preceded it, the linear time-variant (LTV) noisemodel is capable of quantitatively accurate noise predictionsboth near the carrier frequency and far from it.

The LTV model provides two additional insights beyondthose provided by older LTI models. One is that the easewith which an oscillator’s phase is perturbed is not constantthroughout a cycle. A related idea is that the power spectraldensity of the noise sources within an oscillator may alsovary throughout a cycle. The second important insight is thatwaveform symmetry can have a strong effect on the noiseproperties of an oscillator [17]. Exploitation of these newinsights permits a suppression of the notoriously highnoise of CMOS transistors.

Although a detailed derivation of the LTV model is beyondthe scope of this article, its essential features may be readilyunderstood by examining the impulse response of a simpleabstraction: a pure resonator (Fig. 11).

Let us assume that the resonator was given some initialenergy long ago, and has been oscillating ever since. Thetank voltage after the impulse depends very much on whenthe impulse occurs.

In the left waveform of Fig. 12, the impulse happens to co-incide with a resonator voltage maximum. The superpositionof the background oscillation and the response to the impulseresults in a discontinuous jump in amplitude, but there is nochange in the timing of the zero crossings. By contrast, theright-hand waveform shows that little amplitude shift resultswhen the impulse is injected near a zero crossing. However, apersistent phase shiftdoesresult. This simple example showsthe essential time-varying nature of an oscillator.

Having shown that time invariance fails to hold, we still in-voke linearity in the following restricted, but profoundly im-portant, sense: We expect noise sources to be extremely small


Fig. 13. Examples of waveforms and ISFs for (a)LC oscillatorand (b) ring oscillator.

in strength relative to the carrier, for if this were not so, theoscillator would not be worth analyzing. Hence, for any prac-tical oscillator, there must be a linear relationship betweeninput noise and output phase. This statement holds even inthe presence of the strong nonlinearities necessary for ampli-tude stabilization in all real oscillators. It is essential to keepin mind that linear relationships may exist among certain vari-ables at the same time that nonlinear ones exist among others.

Linearity of the noise-to-phase transfer function then im-plies that we may bring to bear on the problem of all the pow-erful tools of linear system theory. Superposition holds, andthe system is then completely characterized by the impulseresponse. The difference here is that an LTV system has animpulse response that is a function of two arguments: the mo-ment of observation (just as in the LTI impulse response), andthe moment of injection.

From Fig. 12, not only do we see that the amount of phaseshift due to an impulse is a function of injection time, but alsothat whatever phase shift results persists for all time. That is,an impulsive input produces a step change in phase, and wemay express the impulse response in general as follows:

(6)

where is the maximum resonator charge swing, and, known as the impulse sensitivity function (ISF),

encodes information about the sensitivity of an oscillator’sphase to perturbations injected at phase. Representativeshapes of the ISF are in Fig. 13.

The example recapitulates the foregoing discussion,and shows that the most sensitive moments are the zero cross-ings of the oscillation waveform, a sensitivity shared by thering oscillator. An important difference is that the oscil-lator can be arranged to inject energy at the least sensitivemoments. By contrast, a ring oscillator inherently injects en-ergy at the most sensitive times, helping to explain why ringoscillators exhibit poor phase noise.

Even though the time-varying sensitivity of oscillators hasnot been widely appreciated until recently, it has neverthe-less been exploited for decades. The Colpitts oscillator, forexample, is a widely used topology (see Fig. 14).

A capacitive voltage divider provides positive feedback tothe transistor, and also resonates with an inductor to set the

Fig. 14. Colpitts oscillator (simplified).

Fig. 15. Incremental tank voltage, drain current, and drain noisefor Colpitts oscillator.

oscillation frequency. Representative waveforms for the Col-pitts oscillator are in Fig. 15.

As can be seen, the transistor operates discontinuously (inClass C mode), delivering narrow pulses of current near thetank voltage maxima, which are the least sensitive moments.The drain current noise waveform, shown on the bottom ofFig. 15, is correlated with the drain current. Because devicenoise, thus, injects into the oscillator at the least sensitivetimes, the spectral purity of the output can be excellent. En-gineers, noting this good performance, have converged onthe Colpitts without quite fully understanding why. The LTVmodel provides an explanation [18]. Of the infinite ways inwhich an active element could restore energy to a dissipativeresonator to sustain oscillation, the least obtrusive way to doso is impulsively, at instants where the ISF has a minimumvalue. Such an insight is fundamentally unavailable from LTImodels, which necessarily treat all instants as equals. TheColpitts oscillator approximates the desired behavior well.

The LTV model also suggests a powerful way to sup-press a problem that afflicts conventional MOSFET- (andMESFET-) based oscillators: upconversion of devicenoise. It has been observed for quite some time that oscil-lators built with devices that exhibit large amounts ofnoise tend to produce outputs with significant amounts ofnoise in the vicinity of the carrier. Evidently, some mech-anism causes low-frequency noise to translate upward infrequency so that it ends up near the carrier. Such “close-in”


Fig. 16. Simplified schematic of the doubly symmetric oscillator.

Fig. 17. Die micrograph of doubly symmetric oscillator.

noise is particularly objectionable because it can allowadjacent channel interference to leak through a conventionalsuperheterodyne receiver.

The precise mechanism by which this upconversion occursis difficult to understand without an LTV model. It is impor-tant to understand that, unlike an LTI system, in which anexcitation at one frequency produces a response at that samefrequency, an LTV system can have excitation and responseat different frequencies. The LTV oscillator noise model re-veals that waveform symmetry controls the amount ofnoise upconversion, thus, suggesting a method for compen-sating for the inferior device noise.

A topology that exploits this new understanding is thedoubly symmetric oscillator. Although the topology itself isnot new, an understanding of its potential for suppression of

noise upconversion is. The circuit is doubly symmetricbecause it possesses both left-right and top-bottom symmetry(see Figs. 16 and 17).

Each cross-coupled pair synthesizes a negative resistancefor cancelling the loss of the tank. Additionally, thepmos-to-nmos width ratio is adjusted to maintain a sym-metric rise and fall time on each half-circuit output (here,symmetry is defined in the sense that the average value ofthe ISF is made to equal zero). This circuit has demonstratedattenuation of noise effects of orders of magnitude

Fig. 18. Block diagram of 5-GHz receiver.

[17]. Thanks to this suppression through symmetry, a phasenoise of 121 dBc/Hz at a 600-kHz offset from a 1.8-GHzcarrier has been achieved in a 0.25-m CMOS technologywith an expenditure of 6 mW of power. The fully integratedoscillator nearly meets GSM1800 specifications at thispower level, and successfully complies with specificationwith a modest increase in dissipation.

It should be noted that this performance is obtained withon-chip inductors of less than optimal design. Improved in-ductors, plus scaled transistors, will permit some combina-tion of lower noise, higher operating frequency, and lowerpower consumption.

The LTV model powerfully refutes arguments that tech-nologies with inferior noise are automatically precludedfrom use in oscillators intended for high-performance appli-cations. As a result, CMOS is now a credible medium inwhich to build oscillators. Undoubtedly, the LTV model willstimulate the design of still better oscillators (and not only inCMOS) as the full import of its implications becomes widelyunderstood.

VI. I LLUSTRATIVE LOW-POWER 5-GHz RECEIVER

To tie together many of the ideas presented in the pre-ceding sections, we now examine a 5-GHz receiver intendedfor wireless LAN applications. The target specifications arechosen to comply with the requirements of the EuropeanHIPERLAN system, whose frequency range overlaps partof the 300-MHz-wide unlicensed national information in-frastructure (UNII) U.S. spectrum allocation. The generous23.5-MHz channel spacings support extremely high data ratecommunications.

The receiver is a conventional low-IF superheterodyne,employing a Weaver architecture for rejection of the imagesignal [19] (see Fig. 18).

As is well known, it is difficult to obtain more than approx-imately 30–40 dB of image cancellation as a result of com-monly encountered levels of phase and amplitude mismatch.This design augments the image rejection by an additional 12dB by integrating a tracking notch filter with the LNA [22].

The noise figure requirements are rather modest forHIPERLAN receivers. For a predetection SNR of 12 dB,the overall noise figure needs to be below 14 dB. This noise


Fig. 19. LNA with integral tracking image-reject filter.

Fig. 20. Simplified half-circuit of LNA/notch filter combination.

figure is readily achievable at low power consumption. Atthe same time, a dense deployment of LAN nodes can resultin a challenging interference environment. Correspondingly,a highly linear receiver is necessary to accommodate inter-ferers that may be as strong as20 dBm at the receiver.

An LNA that possesses the necessary attributes is shownin Fig. 19.

The circuit in the top half of the figure is a differential ver-sion of the inductively degenerated cascode LNA discussedearlier. The bottom circuit is a tunable reactive network thatemploys accumulation-mode varactors. The function of thisnetwork is to produce a low impedance at the image fre-quency, thereby shunting the signal away from the cascodingtransistors of the LNA. A small amount of negative resis-tance, provided by cross-coupled transistors M5 and M6,compensates for the loss in the spiral inductors and, thus,helps deepen the notch. The operation of the notch filteris best understood with the simplified half-circuit shown inFig. 20.

Here, the impedance marked cancels the parasitic ca-pacitance at the drain of M1 at the desired signal frequency,and also produces a low impedance at the frequency of the

Fig. 21. Frequency synthesizer block diagram.

Fig. 22. Resonant frequency divider schematic.

undesired image signal. A PLL-based tracking loop assuresthat the notch is produced at the correct frequency, indepen-dent of process variations. The PLL locks the VCO to theimage frequency. The VCO and the notch filter are madetopologically identical and share a common control voltage.Tuning the VCO to the image frequency then also tunes thenotch circuit to the image as well. Thus, the error in notchlocation is sensitive only to component mismatches, whichare readily made negligibly small.

The complete image-reject differential LNA, includingthe PLL, consumes about 12.4 mW in a 0.25-m CMOStechnology. It is completely integrated with the exception ofa single external matching network at the input. The noisefigure of the LNA alone is 4.8 dB, and exhibits a2-dBminput-referred third-order intercept.

In keeping with the philosophy of minimizing powerwhile still functioning well at 5 GHz, the frequency syn-thesizer employs an unconventional frequency divider inits first stage. An ordinary flip-flop-based divide-by-twoconsumes substantial power when operating at 5 GHz, andin this technology, operation could not even be guaranteedover all process corners. To assure reliable operation andreduce power at the same time, a resonant frequency divideris used. Injection-locked oscillators have a long history,having been used in the sweep synchronization circuits of


Fig. 23. Coplanar transmission line.

television receivers for decades until the advent of PLLs.Here, the frequency of a free-running oscillator is perturbedby an injected synchronizing signal. These two signals neednot be of the same frequency, and in the present design,synchronization at a 2:1 frequency ratio is obtained.

The block diagram for the synthesizer is shown in Fig. 21.The synthesizer’s overall architecture is conventional,

with the exception of that first divider stage. The block la-beled “tracking ILFD” is the voltage-controlled differentialinjection-locked frequency divider. Details of the divider areshown in Fig. 22.

The divider consists of a conventional oscillator (herecomprising M1, M2 and the drain network) that istuned to 2.5 GHz. In oscillation, the node marked “Vx”has a strong spectral component at twice this frequency.Injecting a signal at 5 GHz into this node can effect sub-stantial control over the oscillator, causing synchronizationto occur at a precise 2:1 frequency ratio. Because of the useof a resonant tank, the power consumed by the circuit ismuch lower than that of ordinary flip-flop-based dividers.In the particular example shown, the power consumptionof the divide-by-two circuit is less than 1 mW at 5 GHz[23]. The power consumption is still below 3.8 mW for thecombination of the main synthesizer VCO and the divider,underscoring the power reduction that attends the use ofresonant circuits.

The VCOILFD derives its tuning control voltage from thatof the main VCO. The center frequencies of the two blocks,thus, track one another, thereby extending the frequencyrange over which lock may be maintained.

The rest of the synthesizer consumes considerably morepower because resonant techniques are not as readily appliedin the lower-frequency portions of the circuit. The completesynthesizer consumes 25 mW, and permits the receiver totune to all eight channels located within the lower 200-MHzportion of the UNII allocation. The image-reject front endand synthesizer together, thus, consume 37 mW. This powerconsumption is considerably lower than has been reportedfor similar receivers in other technologies. This achievement

is an example of how acknowledgment of inferior physicsforces the invention of a compensating innovation.

VII. CIRCUITS BEYOND 5 GHz

Almost as a mantra, it has been intoned that continuedscaling delivers faster transistors, so limits on the frequencyof operation are likely to result from a scaling failure else-where. In particular, passive component quality beyond 5GHz is very much an open question, but there are some en-couraging data points.

On-chip transmission lines in silicon technologies have thesame problem as do planar spirals: the substrate, explainingwhy microstrip is perhaps not a good choice in silicon [24].The solution is also similar to that for spirals: try to preventfields from entering the substrate in the first place. In thecase of transmission lines, a good choice is to use a coplanarstructure with somewhat unusually narrow geometries. Thestrong edge coupling tends to concentrate the electric field,thereby reducing its excursion into the substrate (Fig. 23).The reduction in substrate loss compensates for the increasein conductor loss.

With appropriate sizing, and through exploitation of manymetal layers (or, more significantly, thicker total insulationbetween line and substrate), signal attenuations as low as 0.3dB/mm at 50 GHz have been demonstrated with conductordimensions and spacings corresponding to CMOS technolo-gies to be deployed in the near future [25]. This value iscomparable to the best of those achieved in any IC tech-nology, and, therefore, should not pose a serious limit. Fur-thermore, other passive components, such as inductors, ca-pacitors, and resonators, can be constructed out of transmis-sion lines. The line attenuation factors imply thatvaluesof these other components will not suffer a precipitous dropwith frequency, so it appears that passive components withacceptable quality will continue to be available well beyond5 GHz [25].

As closing demonstrations that suggest we have not yet hithard limits on the frequency of operation, we present a four-


Fig. 24. Four-stage distributed amplifier (schematic and die photo).

Fig. 25. Distributed oscillator (schematic and die photo).

stage traveling wave amplifier, built in a 0.18-m technology,with a unity gain frequency of 23 GHz (Fig. 24) [26].

Feeding the output back to the input of a distributed ampli-fier creates an oscillator whose output frequency is 17 GHz(Fig. 25).

Significant harmonic energy exists at 34 GHz and even at50 GHz, and resonators could select one or more of theseharmonics for use elsewhere. Although these circuits maynot represent immediately practical circuits, they serve both

as valuable milestones of present achievements and as guide-posts for the future.

VIII. SUMMARY AND CONCLUSION

Faster transistors will compound the recent achievementsin improved passive elements and better circuits. Betterperformance and lower power will be possible at the lowerfrequencies, and higher frequency operation will become


progressively more accessible over time. The experimental5-GHz LAN receiver demonstrates what can be accom-plished with existing technology, and suggests what couldbe done in the future.

Inductors and capacitors of a quality consistent withoperation at 5 GHz and above are available without processmodifications, and the noise of amplifiers and oscillators isbetter understood now than ever before. Interconnect qualityis seen to be adequate for RF circuits approaching mil-limeter-wave frequencies, and circuit idioms appropriate forextremely high-frequency operation have already demon-strated their usefulness in the 15–25-GHz frequency range.As long as technology continues to scale, performancerecords will be broken with great regularity, and the wirelessrevolution will continue apace.

ACKNOWLEDGMENT

The work described in this paper is largely due to the ef-forts of many students, past and present. The authors wish toacknowledge, in particular, the contributions of Prof. A. Ha-jimiri (oscillator phase noise), B. Kleveland (50-GHz inter-connect), Dr. S. S. Mohan (inductor modeling), H. R. Rategh(injection-locked 5-GHz synthesizer), H. Samavati (image-reject LNA), Dr. D. K. Shaeffer (LNA theory), and Dr. C. P.Yue (patterned ground shield).

REFERENCES

[1] C. P. Yue and S. S. Wong, “On-chip spiral inductors with patternedground shields for Si-based RF ICs,” presented at theDig. Tech. Pa-pers, 1997 VLSI Circuits Symp., June 1997.

[2] H. M. Greenhouse, “Design of planar rectangular microelectronicinductors,”IEEE Trans. Parts, Hybrids, Packag., vol. PHP-10, pp.101–109, June 1974.

[3] S. S. Mohan, “The design, modeling and optimization of on-chip in-ductor and transformer circuits,” Ph.D. dissertation, Stanford Univ.,Stanford, CA, 1999.

[4] H. Samavatiet al., “Fractal capacitors,”IEEE J. Solid-State Circuits,vol. 33, pp. 256–257, Dec. 1998.

[5] T. Soorapanthet al., “Analysis and optimization of accumula-tion-mode varactor for RF ICs,” presented at theDig. Tech. Papers,1998 VLSI Circuits Symp., June 1998.

[6] Y. P. Tsividis, Operation and Modeling of the MOS Tran-sistor. New York: McGraw-Hill, 1987.

[7] T. H. Lee,The Design of CMOS Radio-Frequency Integrated Cir-cuits. Cambridge, U.K.: Cambridge Univ. Press, 1998.

[8] A. van der Ziel, “Gate noise in field effect transistors at moderatelyhigh frequencies,”Proc. IRE, vol. 51, pp. 461–467, Mar. 1963.

[9] , Noise in Solid State Devices and Circuits. New York: Wiley,1986.

[10] F. M. Klaassen and J. Prins, “Noise of field-effect transistors at veryhigh frequencies,”IEEE Trans. Electron Devices, vol. ED-16, pp.952–957, 1969.

[11] D. K. Shaeffer and T. H. Lee, “A 1.5 V, 1.5 GHz CMOS low-noiseamplifier,” IEEE J. Solid-State Circuits, vol. 32, pp. 745–759, May1997.

[12] C. Enz and Y. Cheng, “MOS transistor modeling for RF IC design,”IEEE J. Solid-State Circuits, vol. 35, pp. 186–201, Feb. 2000.

[13] M. J. O. Strutt and A. van der Ziel, “The causes for the increase ofthe admittances of modern high-frequency amplifier tubes on shortwaves,”Proc. IRE, vol. 26, pp. 1011–1032, Aug. 1938.

[14] G. Valley and H. Wallman,Vacuum Tube Amplifiers, ser. MIT Radi-ation Laboratory. New York: McGraw-Hill, 1948, vol. 18.

[15] D. K. Shaeffer and T. H. Lee,The Design and Implementation ofLow-Power CMOS Radios. Norwell, MA: Kluwer, 1999.

[16] D. B. Leeson, “A simple model of feedback oscillator noise spec-trum,” Proc. IEEE, vol. 54, pp. 329–330, Feb. 1966.

[17] A. Hajimiri and T. Lee, “A general theory of phase noise in electricaloscillators,”IEEE J. Solid-State Circuits, vol. 33, pp. 179–194, Feb.1998.

[18] , The Design of Low-Noise Oscillators. Norwell, MA:Kluwer, 1999.

[19] D. K. Weaver Jr., “A third method of generation and detection ofsingle-sideband signals,”Proc. IRE, vol. 44, pp. 1703–1705, June1956.

[20] J. Craninckx and M. Steyaert, “A 1.8 GHz CMOS low-phase-noisevoltage-controlled oscillator with prescaler,”IEEE J. Solid-StateCircuits, vol. 30, pp. 1474–1482, Dec. 1995.

[21] A. Hajimiri and T. Lee, “Design issues in CMOS differentialLCoscillators,”IEEE J. Solid-State Circuits, vol. 34, May 1999.

[22] H. Samavati, H. Rategh, and T. Lee, “A 12.4 mW CMOS front-endfor a 5 GHz wireless-LAN receiver,” presented at theDig. Tech. Pa-pers, 1999 VLSI Circuits Symp., June 1999.

[23] H. Rategh, H. Samavati, and T. Lee, “A 5 GHz, 32 mW CMOSfrequency synthesizer with an injection-locked frequency divider,”presented at theDig. Tech. Papers, 1999 VLSI Circuits Symp., June1999.

[24] H. Hasegawa, M. Furukawa, and H. Yanai, “Properties of microstripline on Si-SiO system,”IEEE Trans. Microwave Theory Tech., vol.MTT-19, pp. 869–881, Nov. 1971.

[25] B. Kleveland, T. Lee, and S. Wong, “50-GHz interconnect designin standard silicon technology,” presented at theIEEE MTT-S Int.Microwave Symp., June 1998.

[26] B. Klevelandet al., “Monolithic CMOS distributed amplifier andoscillator,” ISSCC Dig. Tech. Papers, Feb. 1999.

Thomas H. Lee (Member, IEEE) receivedthe S.B., S.M., and Sc.D. degrees in electricalengineering from the Massachusetts Instituteof Technology, Cambridge, in 1983, 1985, and1990, respectively.

He joined Analog Devices in 1990, wherehe was primarily engaged in the design ofhigh-speed clock recovery devices. In 1992,he joined Rambus Inc., Mountain View, CAwhere he developed high-speed analog circuitryfor 500-Mb/s CMOS DRAMs. He has also

contributed to the development of PLLs in the StrongARM, Alpha, andK6/K7 microprocessors. Since 1994, he has been an Assistant Professorof Electrical Engineering at Stanford University, Stanford, CA, where hisresearch focus has been on gigahertz-speed wireline and wireless integratedcircuits built in conventional silicon technologies, particularly CMOS. Heis a Distinguished Lecturer of both the IEEE Solid-State Circuits Societyand Microwave Society. He holds 13 U.S. patents and is the author ofa textbook,The Design of CMOS Radio-Frequency Integrated Circuits(Cambridge, U.K.: Cambridge Univ. Press, 1998), and is a coauthor of twoadditional books on RF circuit design. He is also a cofounder of MatrixSemiconductor.

Dr. Lee has twice received the “Best Paper” award at the InternationalSolid-State Circuits Conference, was coauthor of a “Best Student Paper” atISSCC, received the “Best Paper” award at CICC, and is a recipient of aPackard Foundation Fellowship.

S. Simon Wong (Fellow, IEEE) received theB.E.E. and B.M.E degrees from the Universityof Minnesota, Minneapolis, in 1975 and 1976,respectively, and the M.S. and Ph.D. degreesfrom the University of California, Berkeley, in1978 and 1983, respectively.

From 1978 to 1980, he was with NationalSemiconductor Corporation designing MOSdynamic memories. From 1980 to 1985, he waswith Hewlett-Packard Laboratories, workingon advanced MOS technologies. From 1985 to

1988, he was an Assistant Professor at the School of Electrical Engineering,Cornell University, Ithaca, NY. In 1988, he joined Stanford University,Stanford, CA, where he is now Professor of Electrical Engineering. Hisresearch interests include high-performance device structures, advancedinterconnection technologies, and multichip modules. His current researchconcentrates on interconnect technologies and high-frequency modeling ofinterconnect networks.


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CMOS RF Integrated Circuits at 5 GHz and Beyond