Cmos Rf Modeling,Characterization and Applications

ected Topics in Electronics and Systei

OS RF MODELING, CHARACTERIZATION AND APPLICATIONS

CMOS RF MODELING, CHARACTERIZATION AND APPLICATIONS

SELECTED TOPICS IN ELECTRONICS AND SYSTEMS

Editor-in-Chief: M. S. Shur

Published Vol. 6: Low Power VLSI Design and Technology

eds. G. Yeap and F. Najm

Vol. 7: Current Trends in Optical Amplifiers and Their Applications ed. T. P. Lee

Vol. 8: Current Research and Developments in Optical Fiber Communications in China eds. Q.-M. Wang and T. P. Lee

Vol. 9: Signal Compression: Coding of Speech, Audio, Text, Image and Video ed. N. Jayant

Vol. 10: Emerging Optoelectronic Technologies and Applications ed. Y.-H. Lo

Vol. 11: High Speed Semiconductor Lasers ed. S. A. Gurevich

Vol. 12: Current Research on Optical Materials, Devices and Systems in Taiwan eds. S. Chi and T. P. Lee

Vol. 13: High Speed Circuits for Lightwave Communications ed. K.-C. Wang

Vol. 14: Quantum-Based Electronics and Devices eds. M. Dutta and M. A. Stroscio

Vol. 15: Silicon and Beyond eds. M. S. Shur and T. A. Fjeldly

Vol. 16: Advances in Semiconductor Lasers and Applications to Optoelectronics eds. M. Dutta and M. A. Stroscio

Vol. 17: Frontiers in Electronics: From Materials to Systems eds. Y. S. Park, S. Luryi, M. S. Shur, J. M. Xu and A. Zaslavsky

Vol. 18: Sensitive Skin eds. V. Lumelsky, Michael S. Shur and S. Wagner

Vol. 19: Advances in Surface Acoustic Wave Technology, Systems and Applications (Two volumes), volume 1 eds. C. C. W. Ruppel and T. A. Fjeldly

Vol. 20: Advances in Surface Acoustic Wave Technology, Systems and Applications (Two volumes), volume 2 eds. C. C. W. Ruppel and T. A. Fjeldly

Vol. 21: High Speed Integrated Circuit Technology, Towards 100 GHz Logic ed. M. Rodwell

Vol. 22: Topics in High Field Transport in Semiconductors eds. K. F. Brennan and P. P. Ruden

Vol. 23: Oxide Reliability: A Summary of Silicon Oxide Wearout, Breakdown, and Reliability ed. D. J. Dumin

Selected Topics in Electronics and Systems - Vol. 24


Editors

M. Jamal Deen McMaster University, Canada

Tor A. Fjeldly Norwegian University of Science and Technology, Norway

, © World Scientific !• New Jersey • London • Singapore • Hong Kong

Published by

World Scientific Publishing Co. Pte. Ltd.

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Copyright © 2002 by World Scientific Publishing Co. Pte. Ltd.

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PREFACE


M.JAMALDEEN Department of Electrical and Computer Engineering

McMaster University, Hamilton, Ontario, Canada L8S 4K1

TOR A. FJELDLY UniK - Center for Technology at Kjeller,

Norwegian University of Science and Technology, N-2027 Kjeller, Norway

The rapid evolution of semiconductor electronics technology is fueled by a never-ending demand for better performance at reduced cost, combined with a fierce global competition. For CMOS technology, this evolution is often measured in generations of three years, the time it takes for manufactured memory capacity to be increased by a factor of four and for logic circuit density to increase by a factor of between two and three. Technologically, this trend is made possible by a downscaling of transistor feature size (i.e., gate length) by a factor of two per two generations. Traditionally, the high-frequency properties of silicon MOSFETs have been considered inferior to other technologies, including silicon bipolar transistors and transistors based on III-V materials such as gallium arsenide. However, the CMOS technology has now reached a state of evolution, in terms of both frequency and noise, where it is becoming a serious contender for radio frequency (RF) applications in the GHz range. Cut-off frequencies of about 50 GHz have been reported for 0.18 urn CMOS technology, and are expected to reach about 100 GHz when the feature size shrinks to 100 nm within a few years. This translates into CMOS circuit operating frequencies well into the GHz range, which covers the frequency range of many of the popular wireless products today, such as cell phones, GPS (Global Positioning System), and Bluetooth. Of course, the great interest in RF CMOS comes the obvious advantages of CMOS technology in terms of production cost, high-level integration, and the ability to combine digital, analog and RF circuits on the same chip.

Circuit design is an integral part of electronics technology, as important as the fabrication itself. Advances in the fabrication process always pose new challenges to the circuit designers. In order to be able to take full advantage of the new technology, the designers need to update their CAD (Computer Aided Design) tools with precise

V

vi Preface

descriptions of the new devices in terms of models that can be implemented into circuit simulators. To be able to scale the devices for different operations, the models must be physics based to account for the complex dependence of the device properties on dimensions and other processing variables. The model parameters are derived from measurements and characterization of the devices. For RF CMOS, both the modeling and the characterization are challenging tasks that will be especially emphasized in this volume. Next follows a survey of the six contributions included in the first issue.

Reliable measurements are a prerequisite for any sensible work on device modeling, especially so for high frequencies where the subtleties of the device behavior are plentiful. In the first chapter of this volume, F. Sischka and T. Gneiting discuss a wide range of issues related to RF MOSFET measurements, most of which also apply to RF device characterization in general. A thorough discussion of S-parameters, Smith charts, polar plots, network analyzer measurements, de-embedding techniques, and MOSFET test structures are included, and may serve as a valuable high-level tutorial on the subject of RF measurements.

In the second chapter, M. Je, I. Kwon, H. Shin, and K. Lee discuss MOSFET modeling and parameter extraction for RF applications. They review several existing techniques, many of which are based on earlier work on three-terminal III-V devices, and examine the problems and shortcomings encountered in adapting these techniques to RF MOSFETs. The fact that the MOSFET is a four-terminal device and that the silicon substrate is lossy represent major challenges. The authors emphasize the importance of using charge conserving models, especially in conjunction with parameter extraction. They also present a new four-terminal modeling approach for handling RF MOSFETs. Finally, many of the remaining challenges in RF CMOS modeling and parameter extraction are discussed.

RF MOSFET modeling is also the topic of the third chapter by Y. Cheng. Equivalent circuits representing both intrinsic and extrinsic components in a MOSFET are analyzed to obtain physics-based RF models. Procedures for parameter extraction are also discussed. The analysis emphasizes the importance of certain capacitive and resistive components at high frequencies, in particular, the polysilicon gate resistance, the distributed channel resistance, and the components associated with the lossy substrate. An RF MOSFET model based on BSIM3v3 is presented, and good correspondence is obtained with experimental data obtained for different device geometries. Non-quasi-static effects are discussed in conjunction with this model. The modeling of flicker noise and thermal noise, and existing challenges in this area, are also discussed as part of this presentation.

The fourth chapter by C.-C. Chen and M. J. Deen is dedicated to RF CMOS noise characterization and modeling. From small-signal models, such as some of those discussed above, it may be difficult to find analytical expressions for the fundamental noise parameters. As an alternative, the authors present techniques for calculating the noise parameters numerically. De-embedding techniques for extraction of RF MOSFET noise parameters and scattering parameters from experiments are also presented in detail, along with procedures for obtaining the frequency and bias dependencies of the extracted

Preface vii

noise sources. Finally, this chapter includes some considerations for design of low-noise circuits, and a comparison of different noise models reported in the literature.

Silicon-on-insulator (SOI) CMOS technology offers exceptional advantages in terms of low-power/low-voltage applications in digital as well as in RF and microwave circuits. In the fifth chapter, D. Flandre, J.-P. Raskin, and D. Vanhoenacker-Janvier present many aspects of the SOI CMOS technology, including SOI materials, devices and circuits, MOSFET properties, passive elements, and last but not least, the RF and microwave modeling and characterization of SOI MOSFETs. A fully developed SOI MOSFET macro model valid from DC to RF is presented, which includes transmission line effects related to both the gate and the channel. Comparisons with experiments show that this model is accurate up to 40 GHz for feature sizes down to 0.16 urn. Some examples of RF SOI CMOS applications are also presented.

CMOS operating frequencies in the GHz range have been achieved through the down-scaling of device feature sizes into deep sub-micrometer dimensions. However, this has not come without penalties. Among these are the deleterious effects of hot carrier transport, brought on by a concomitant increase in the MOSFET channel electric field. The high field problem is, of course, rooted in the need for keeping the supply voltages relatively high to maintain high speed and reduce the subthreshold leakage current. Basically, the hot-electron effects lead to device degradation and, hence, represent a serious reliability problem. In the sixth chapter on RF CMOS reliability, S. Naseh and M. J. Deen consider the important issues of hot-carrier effects, and illustrate them by experimental results and simulations.

viii Preface

M. Jamal Deen is professor of Electrical and Computer Engineering at McMaster University. He also holds the Canada Research Chair in

? •tSU't' Information Technology. He has also been professor of Engineering ; 'N ', Science at Simon Fraser University since 1993. Previously, he was

"" ""* & with the CNRS Laboratory of Physics of Semiconductors Devices - (LPCS), Grenoble (Visiting Scientist, summer 1998), faculty of Elec-* trical Engineering (ECTM Lab), Delft University of Technology

(Visiting Professor, summer 1997); Herzberg Institute of Astrophysics, National Research Council, Ottawa (Visiting Scientist, summer 1986); and Lehigh University, Bethlehem, Pennsylvania (Assistant Professor, 1985-86). His industrial experience includes a one-year visiting scientist position (1992-93) with the Device Technology Group, Northern Telecom, Ottawa, and several years of consulting and joint research with Northern Telecom, Bell Northern Research, Conexant, D&V Electronics, IBM, Mitel, National Semiconductor and Rockwell Semiconductor Systems.

Dr. Deen holds the Ph.D. and M.S. degrees from Case Western Reserve University, Cleveland, Ohio, U.S.A. in Electrical Engineering and Applied Physics, and the B.Sc. degree from the University of Guyana, Guyana, S. America in Physics/Mathematics. As an undergraduate student, he won the Dr. Irving Adler's Prize for the best graduating mathematics student, and the Chancellor's Medal for the second best graduating student in the University in 1978. He was also a Fulbright Scholar from 1980 to 1982, an American Vacuum Society Scholar from 1983 to 1984, an NSERC Senior Industrial Fellow in 1993. He was given a Reward of Recognition Award, Silicon Technology Division, Northern Telecom in 1993, and won the IEEE 1993 Outstanding Branch Councillor and Advisor Award for Canada. Most recently, he was awarded a Canada Research Chair in Information Technology at McMaster University. Dr. Deen is a member of Eta Kappa Nu (the Electrical Engineering Honor Society, U.S.A) and the Electrochemical Society, a life member of die American Physical Society, and a Senior Member of the IEEE. Dr. Deen is also Editor, IEEE Transactions on Electron Devices; Executive Editor, Fluctuation and Noise Letters; and Member, Editorial Board, Interface — An Electrochemical Society Publication. Dr. Deen is the co-editor of six books or conference proceedings and the co-author of thirteen book chapters and one encyclopedia article. He has authored or co-authored more than 220 peer-reviewed scientific papers, 68 conference abstracts and extended abstracts, and 48 commissioned technical reports. He is also named an inventor in five patents.

Preface ix

Tor A. Fjeldly received the M. Sc. degree in physics from the Norwegian Institute of Technology, 1967, and the Ph.D. degree from Brown University, Providence, RI, in 1972. From 1972 to 1994, he was with Max-Planck-Institute for Solid State Physics in Stuttgart, Germany. From 1974 to 1983, he worked as a Senior Scientist at the SINTEF research organization in Norway. Since 1983, he has been on the faculty of the Norwegian University of Science and Technology

(NTNU), where he is a Professor of Electrical Engineering. He is presently with NTNU's Center for Technology at Kjeller, Norway. He was Head of the Department of Physical Electronics at NTNU, and he also served as an Associate Dean of the Faculty of Electrical Engineering and Telecommunication. From 1990 to 1997, he held the position of Visiting Professor at the Department of Electrical Engineering, University of Virginia, Charlottesville, VA, and from 1997 he has been Visiting Professor at the Electrical, Computer and Systems Engineering Department, Rensselaer Polytechnic Institute, Troy, NY. His research interests have included fundamental studies of semiconductors and other solids, development of solid-state chemical sensors, electron transport in semiconductors, modeling and simulation of semiconductor devices, and circuit simulation. He has written about 150 scientific papers, several book chapters, and is a co-author of the books Semiconductor Device Modeling for VLSI (Englewood Cliffs, NJ: Prentice Hall, 1993) and Introduction to Device Modeling and Circuit Simulation (New York, NY: Wiley & Sons, 1998). He is also a co-developer of the circuit simulator AIM-Spice. Since 1998, he has been a Co-Editor-in-Chief of the International Journal of High Speed Electronics and Systems, Singapore. Dr. Fjeldly is a Fellow of IEEE and a member of the Norwegian Academy of Technical Sciences, the American Physical Society, the European Physical Society and the Norwegian Society of Chartered Engineers.

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CONTENTS

Preface v M. J. Deen and T. A. Fjeldly

RF MOS Measurements 1 F. Sischka and T. Gneiting

MOSFET Modeling and Parameter Extraction for RF IC's 67 M. Je, I. Kwon, H. Shin, and K. Lee

MOSFET Modeling for RF IC Design 121 Y. Cheng

RF CMOS Noise Characterization and Modeling 199 C.-H. Chen and M. J. Deen

SOI CMOS Transistors for RF and Microwave Applications 273 D. Flandre, J.-P. Raskin, and D. Vanhoenacker-Janvier

RF CMOS Reliability 363 S. Naseh and M. J. Deen

International Journal of High Speed Electronics and Systems, Vol. 11, No. 4 (2001) 887-951 © World Scientific Publishing Company

RF MOS MEASUREMENTS

FRANZ SISCHKA Agilent Technologies GmbH, Munich, Germany

THOMAS GNEITING admos, Frickenhausen, Germany

The trend to higher integration and higher transmission speed challenges modeling engineers to develop accurate device models up to the Gigahertz range. An absolute prerequisite for achieving this goal are reliable measurements, which have to be checked for data consistency and plausibility. This is especially true for RF data, and also for checking and verifying the applied de-embedding techniques. If this is not the case, RF modeling can become quite time consuming, with a lot of guesswork and ad-hoc judgements, and, basically, frustrating and not correct. If, however, the underlying measurements are flawless and consistent, and provided the applied the models are understood well, RF modeling becomes very effective and provides accurate design kits which will satisfy the chip designer's main goal: right the fist time.

1 Characterizing Devices From DC To High Frequencies

While the characterization of electronic components in the DC domain is relatively simple and only requires a voltmeter and an amperemeter, the frequency performance of the device is affected by magnitude dependence and phase shift of the currents and voltages. Furthermore, nonlinearities will lead to a spectrum of frequencies, although the device is only stimulated with a single, sine frequency. Last not least, inevitable capacitive and inductive parasitics, with values close to those of the very device under test (DUT), will contribute to the measurements and degrade the measured performance of the 'inner' DUT. [1,2]

In this paper, we will go step by step through the individual characterization issues and develop measurement strategies which will provide the base of accurate device modeling.

2 DC Measurements As A Prerequisite For RF Setups

Large signal modeling of a nonlinear component always begins with the characterization of its DC performance. Instead of power supplies, DC parametric analyzers with source-monitor-unit plugins (SMU) are applied. This allows to fully characterize the DUT (device under test) from fempto-Ampere up to its maximum current, and in all four i-v quadrants. I.e. forward and reverse currents and voltages, are measured with the same SMU unit.

l

888 F. Sischka & T. Gneiting

Usually, in case of a transistor, all 4 terminals (including substrate) are connected to individual SMUs in order to avoid recabling during the forward and reverse measurements.

SMUs apply a Kelvin measurement to avoid parasitic series resistances. This measurement procedure, also known as the four-wire method, consists of a stimulating line (Force) with a second one in parallel (Sense) for every pin of the DUT. Fig. 1 illustrates this. Ohmic losses on the Force line are eliminated by the main operational amplifier (OpAmpl) in voltage follower mode. This means this OpAmpl output will exhibit a somewhat higher voltage than the desired test voltage at the DUT, because the test current generates some ohmic losses along the Force line. The Sense line, connected to the minus input of the OpAmpl, assures that the DUT is biased with exactly the desired test voltage.

SMU OpAmp2

* L

d OpAmpl

I desired I voltage

Ohmic Losses ± •AM/v^-

r -r F External Shielding

Inner Shielding

Force

Dielectric Losses Sense

Test Potential

Measurement Instrument

Metering Lines

Fig. 1: The principle of Kelvin measurements (C) Copyright 2001 by Franz Sischka, Agilent Technologies, Munich

While this method compensates the DC errors, it does not cover dynamic measurement problems. For example, to avoid external electro-magnetic influences, both the Force and Sense cables are shielded. Such cable shieldings exhibit parasitic capacitances. Due to charging problems, these capacitances will affect the measurement speed and accuracy of our Kelvin measurement.

As a simple example: assume we want to measure the reverse characteristics of a semiconductor diode. This means we need measure very low currents. Before the voltage steps to, e.g. -20 V, the quiescent voltage at the diode is zero. That is, the cable capacitors are not charged. When the negative voltage step occurs, these capacitances have to be charged, and the required current is provided by the OpAmpl. This could lead to either a mis-measurement (DUT current plus charging current) or a delay in the triggering of the actual current measurement (by some intelligent firmware in our measurement).

To solve this problem, an extra inner shielding is applied between the hot metering lines and the outer cable shielding, called 'Guard'. This extra shielding is connected to a separate,

2

RF MOS Measurements 889

second 0pAmp2 which follows exactly the value of the desired test voltage. Now it is this auxiliary OpAmp2 which supplies the charging current for the test cables, while the main Op Amp 1 can start current measurements independently of this charging problem. That is, the inner measurement loop does not see the charging problem any more.

Of course the point where Force and Sense are tied together must be as close as possible to the DUT. In case they aren't connected, an internal lOkOhm resistor at the . of the SMU acts as the Kelvin point. Another important fact is that the Guard comae i should never be connected to Force or Sense. Otherwise, the inner loop OpAmpl of the SMU would measure the DUT current plus the charging current of the auxiliary, second OpAmp2!

In order to maintain the DC measurement accuracy, SMUs perform periodically an auto-calibration. This means that the SMU disconnects its outputs from the DUT, measures possible offset voltages and currents and corrects it. This type of calibration does not require any action from the user.

See publications [3] and [4] for details.

3 Capacitance Measurements At 1MHz

As discussed in the previous chapter, the DC voltages and currents can be measured directly. The calibration is periodically auto-executed by the instrument.

After such a DC characterization, modeling engineers usually perform a so-called CV (capacitance versus voltage) measurement in order to characterize the device capacitances at a standard frequency of 1MHz. This frequency is high enough to allow a resolution down to a few fempto-Ampere (provided shielded probes are applied for e.g. on-wafer measurements), yet still low enough to neglect second order parasitics like resistors in series with the capacitors, or like inductances. For such CV measurements, the DC-bias is swept, a test frequency (1MHz) is applied to the DUT, and the instrument calculates the capacitance between the 2 pins of the DUT from the magnitude and phase of the device voltage and current.

For CV meters, an auto-balancing method is typically applied. Fig. 2 depicts the simplified measurement scheme. The DUT is inserted in the feedback loop of an operational amplifier, and the system is stimulated with a 1MHz sine signal plus a DC bias. The feedback resistor R is precisely known, and the complex voltages VI and Vdut are measured. From the formula given in Fig. 2, the capacitance of the DUT can be calculated, assuming an equivalent schematic of either a resistor in series with the capacitor, or, commonly for modeling, a capacitor in parallel with a resistor (which is the bias-dependent diode resistance for example).

3


CV meter applying the auto-balancing method

DUT

V V

Zx R

sine frequency + DC bias

Hint: LOW potential is virtual ground !

Fig.2: schematic measurement principle of a CV meter (C) Copyright 2001 by Franz Sischka, Agilent Technologies, Munich

Again, test cables and fixtures contribute and affect the device characterization. Here, the measurement calibration consists of unconnecting the DUT, assuming an ideal OPEN condition and measuring the cables and their OPEN parasitics. The corresponding capacitance is then automatically subtracted from the subsequent DUT measurement.

Note: If we are interested in the inner DUT's CV curves, i.e. without its surrounding test pads capacitances, we need to connect to an OPEN dummy structure during CV meter calibration. Such an OPEN dummy consists of all connection pads, lines to the DUT etc, but without the inner DUT itself. See Figures 34 and 46 for examples.

When characterizing the capacitances of transistors, the open 3rd transistor terminal can be connected to the shielding potential, eliminating the effect of the unwanted capacitor. See Fig. 3, and also publication [5] for details.

taffies w ©53®

QOSH

Measurement of CDG

With the auto-balancing method, connecting the Source to the cable shielding potential, eliminates the effect of CGS

Fig. 3: measuring transistor capacitances with a CV meter (C) Copyright 2001 by Franz Sischka, Agilent Technologies, Munich

4


4 From Y-, Z-, And H-Parameters To S-Parameters

While the CV measurement is considered as a specific two-pin test condition, the situation changes for frequencies above 100MHz. The modeling device is now operated under its originally intended environment conditions: DC bias is applied to all the pins, and an additional small-signal RF excitation is applied. Now, the sine currents and voltages at all pins of the DUT are to be measured, with magnitude and phase.

A natural choice for such characterizations would be Z-, Y- or H-parameters from linear two-port theory. These two-port parameters can be used to completely describe the electrical behavior of our device (or network), including any source and load conditions. For such parameters, we have to measure the voltage or current as a function of frequency and bias at the ports of the device. At high frequencies, however, it is very hard to measure voltage and current at the device ports. One cannot simply connect a voltmeter or current probe and get accurate measurements due to the impedance of the probes themselves and the difficulty to place the probes at the desired positions. Furthermore we have to apply either (AC-wise) OPEN or SHORT circuits as part of the Z-, Y- or H-parameter measurement. Active devices may oscillate or self-destruct with such terminations.

4.1 Introducing S-Parameters

Clearly, some other way of characterizing high-frequency networks is required that doesn't have these drawbacks. That is why scattering or S-parameters were developed. These parameters relate to familiar measurements such as gain, loss, and reflection coefficient. They are relatively simple to measure, and do not require connection of undesirable loads to the DUT. Different to Y and Z, however, they relate to the traveling waves that are scattered or reflected when a network is inserted into a transmission line of a certain characteristic impedance ZO.

The measured S-parameters of multiple devices can be cascaded to predict overall system performance. S-parameters are readily used in both linear and nonlinear CAE circuit simulation tools, and Z-, Y- or H-parameters can be derived from S-parameters when necessary.

To help with becoming familiar with linear S-parameters, we want to give a short example on characterizing components using power measurements, the lightwave analogy for Transmission and Reflection. Since a circuit described by S-parameters can be thought of like inserted into a uniform characteristic impedance (ZO) environment, we can compare S-parameters to reflection and transmission of an optical lens, surrounded at both sides by air. When light interacts with a lens, as in the photograph of Fig. 4, part of the light incident on the eyeglasses is reflected while the rest is transmitted. The amounts reflected and transmitted are characterized by optical reflection and transmission coefficients. By performing such a measurement, your optician is able to characterize your eyeglasses completely.

5


Fig. 4: reflection and transmission with eyeglasses (C) Copyright 2001 by Franz Sischka, Agilent Technologies, Munich

Similarly, scattering parameters are measures of reflection and transmission of voltage waves through a two-port electrical network, inserted into a uniform characteristic impedance environment.

Definition of S-parameters Referring once again to the spectacles examples from above, i.e. power-wise, the S-parameters are defined as:

with

Pi I

I ajl2

ibjl2

I2 i i2

I—22 I ,

2\ f *

§2 I |2

J

power wave traveling towards the two-port gate

power wave reflected back from the two-port gate

and

I S n I 2

I S i 2 l 2

IS.21I2

I S 2 2 I 2

power reflected from portl

power transmitted from portl to port2

power transmitted from port2 to portl

power reflected from port2

This means that S-parameters relate traveling waves (power) to a two-port's (DUT) reflection and transmission behavior. Since the two-port is imbedded in a characteristic impedance of ZO, these 'waves' can be interpreted in terms of normalized voltage or current amplitudes. This is sketched below.

6


la,!2 -

lb, I2 « -

Zh

t W t * [ ._ ,

Starting with power

P=v*i

normalized toZo

V*V

3)

f iiin'niiii a,

gives normalized amplitudes for voltage and current

V • * 1-7

= I JZc - VP =

^ -o

In other words, we can convert the power towards the two-port into a normalized voltage amplitude of

towards _ twoport

VZo" (1)

and the power away from the two-port can be interpreted in terms of voltages like

L. away _ from _ twoport

See Fig. 5 for details.

(2)

Fig. 5: S-parameter definition (C) Copyright 2001 by Franz Sischka, Agilent Technologies, Munich

7


Looking at the S-parameter coefficients individually, we have:

0 _ b1 v reflected at portl

211 £1 Vtowards portl

Q _ b 2 _ v ou t of port2 —21

^1 ^towards portl

(3)

Sl l and S21 are determined by measuring the magnitude and phase of the incident, reflected and transmitted signals when the output is terminated in a perfect ZO load. This condition guarantees that a2 is zero. Sl l is equivalent to the input complex reflection coefficient or impedance of the DUT, and S21 is the forward complex transmission coefficient.

Likewise, by placing the source at port 2 and terminating port 1 in a perfect load (making al zero), S22 and S12 measurements can be made. S22 is equivalent to the output complex reflection coefficient or output impedance of the DUT, and S12 is the reverse complex transmission coefficient.

The accuracy of S-parameter measurements depends greatly on how good a termination we apply to the port not being stimulated. Anything other than a perfect load will result in al or a2 not being zero (which violates the definition for S-parameters). When the DUT is connected to the test ports of a network analyzer and we don't account for imperfect test port match, we have not done a very good job satisfying the condition of a perfect termination. For this reason, two-port calibration, which corrects for source and load match, is very important for accurate S-parameter measurements.

In order to become more familiar with S-parameters, we will now discuss some specific S-parameter values.

SllandS22 value interpretation

-1 0

+1

all voltage amplitudes towards the twoport are inverted and reflected impedance matching, no reflections at all (50 Q) voltage amplitudes are reflected (infinite Q.)

(Oil)

The magnitude of Sl l and S22 is always less than 1. Otherwise, it would represent a negative ohmic resistor (!).

On the other hand, the magnitude of S21 (transfer characteristics) respectively S12 (reverse) can exceed the value of 1 in the case of active amplification. Also, the starting


points of S21 and S12 can be positive or negative. If they are negative, there is a phase inversion. As an example, S21 of a transistor starts usually at about S21 = -2 ...-10. This means signal amplification within the ZO environment and phase inversion.

S21andS12

magnitude

0 0...+1

+1 >+1

interpretation

no signal transmission at all input signal is damped in the Z0 environment unity gain signal transmission in the ZO environment input signal is amplified in the ZO environment

The numbering convention for S-parameters is that the first number following the S is the port at which energy emerges, and the second number is the port at which energy enters. So S21 is a measure of power emerging from Port 2 as a result of applying an RF stimulus to Port 1.

4.2 Smith Chart And Polar Plot

The Smith chart for Sxx

What makes Sxx-parameters especially interesting for modeling, is that S11 and S22 can be interpreted as complex input or output resistances of the two-port. That's why they are usually plotted in a Smith chart. NOTE: do not forget that included in Sxx is the termination at the opposite side of the two-port, usually ZO !!

The Smith chart is a transformation of the complex impedance plane R into the complex reflection coefficient T (rho) , following the formula:

r ^ R - Z 0 ~ R + zo (1)

with the system's characteristic impedance ZO = 50 Q.

This means that the right half of the complex impedance plane R is transformed into a circle in the r-domain. The circle radius is '1' (see Fig. 6).

9


R

j50 Ohm

50 Ohm

R-50

r = R + 50

Fig. 6: the relationship between Sxx and the complex impedance of a two-port. (C) Copyright 2001 by Franz Sischka, Agilent Technologies, Munich

On the other hand, using a network analyzer with a characteristic system impedance of ZO, the parameter S11 is equal to

S „ = 2 . ^ - 1 v01 (2)

where vl is the complex voltage at port 1 and vOl the stimulating AC source voltage (which is typically normalized to 'I'). Fig. 7 depicts the corresponding circuit schematic.

ZO twoport

V01 V1

ZO

Fig. 7: about the definition of SI 1 (S22 is analogous) (C) Copyright 2001 by Franz Sischka, Agilent Technologies, Munich

Under the assumption that R is the complex input resistance at port 1 and ZO is the system impedance, we get using eq.(2) and the resistive divider formula for Fig. 7:

S n = 2--=— - 1 = = R-ZO

»11 R + ZO R + ZO

And this is the reflection coefficient T from(l)!!

10


NOTE: see also the chapter called 'Calculating S-Parameters From Complex Voltages' further down.

After all, if the reflection coefficient T resp. Sj j or S22 is known, we get for the complex

resistor R: i + r 1+s-n

R = ZO • —-=• = ZO • 1 — , with usually ZO = 50 Q 1-T 1-S 11

This explains how we can get the complex input/output resistance of a two-port directly from S11 or S22, if we plot these S-parameters in a Smith chart.

Let's go back to Fig. 6 and consolidate this context a little further: it shows a square with the corners (0/0)Q, (50/0)Q, (50/j50)Q and (0/j50)ii in the complex impedance plane and its equivalent in the Smith chart with ZO=50£2. Please watch the angel-preserving property of this transform (rectangles stay rectangles close to their origins). Also watch how the positive and negative imaginary axis of the R plane is transformed into the Smith chart domain ( T ), and where (50/j50)Q is located in the Smith chart. Also verify that the center of the Smith chart represents ZO, i.e. for ZO = 50Q, the center of the Smith chart is (50/j0)Q.

This allows us to make the following statements: > Sxx on the real axis represent ohmic resistors > Sxx above the real axis represent inductive impedances > Sxx below the real axis represent capacitive impedances > Sxx curves in the Smith chart turn clock-wise with increasing frequency.

Fig. 8 depicts this graphically.

<*»**&tt0>

— K>

CD ED

Fig. 8: Location of ohmic, inductive and capacitive components in the Smith chart

(C) Copyright 2001 by Franz Sischka, Agilent Technologies, Munich

11


As an example for interpreting Smith charts, Fig. 9a shows the Sl l plot of a bipolar

transistor. In this case, the locus curve stars with S l l = 1 = ° ° * Z Q at low frequencies

corresponding to Rgg '+ R^j0(je + beta*Rr£. For increasing frequencies, the curves then

turn into the lower half-plane of the Smith chart, the capacitive region. Here, the Cgg

shorts R(jiode' anc* beta = 1- F° r infinite frequency, when the capacitors represent ideal

shorts, the end point of S] j lies on the middle axis, i.e. the input impedance is completely

ohmic, representing Rgg> + Rr£- Since Rgg> is bias dependent, and decreasing with

increasing iB, the end points of the curves represent this bias-dependency.

NOTE: For incrementing frequency, the Sxx locus curves turn always clockwise!

Fig. 9b shows the Sl l curve of a capacitor located between the two ports of the network analyzer (NWA). The capacitor represents an OPEN for DC, thus S11 = 1 = °°*Z0. For highest frequencies, it behaves like a SHORT, and we see the 50 Q of the opposite port2 (!). The transition between the DC point and infinite frequency follows a circle, and the increasing frequency turns the curve again clockwise.

S11

Fig. 9a: Si i of a transistor with increasing Base current iB. (C) Copyright 2001 by Franz Sischka, Agilent Technologies, Munich

12


-F i™ e CI

Fig. 9b: Si of a capacitor between port 1 and port 2

7%e PoZar diagram for Sxy

Fig.10: The polar diagram for S12 and S21 (C) Copyright 2001 by Franz Sischka, Agilent Technologies, Munich

The S21 parameter represents the power transmission from port 1 to port 2, if the two-port is inserted into a matching network with characteristic impedance Z0 of e.g. 50 Q. This means, if no signal is transmitted, then S21=0 (located in the center of the polar plot). If the signal is transmitted, then MAG(S21)>0. The magnitude of the S21 curve will be below T for damping between the port 1 and port 2, and above 1' for amplification. If the phase is inverted, we are basically in the left half-plane of the polar plot (REAL[S21]<0).

Like with the Smith chart, all S21 and S12 curves turn clock-wise with increasing frequency.

As an example, Fig. 11a shows the S21 plot of a bipolar transistor, and Fig. l i b of a capacitor between port 1 and port 2. While the transistor starts with REAL(S21) < -1 at low frequencies (voltage amplification in a 50 £2 system, plus phase inversion), its curves tend towards S21=0 for highest frequencies (no voltage transmission, the transistor capacitances short all voltage transmission). Since the current amplification 6 is bias

13


depending, the start point of the S21 curve at lowest frequencies reflects this 6(iB) dependency: more 6 for higher iB, i.e. more amplification magnitude with S21 for higher iB too.

For the capacitor in Fig. l ib , it's just the opposite: no power transmission for lowest frequencies, but an ideal short (S21=l) for highest frequencies.

T—i—i—I—r

0 - 6 . 0 - 4 . 0 - 2 . 0 0 . 0 2 . 0

R E R L C E + 0 ]

Fig. 11a: S21 of a transistor with varying Base current iB. (C) Copyright 2001 by Franz Sischka, Agilent Technologies, Munich

Ld

m •;, - 0 . 5

RECRU CEC+-0D

Fig. 1 lb: S21 of a capacitor between port 1 and port 2 (C) Copyright 2001 by Franz Sischka, Agilent Technologies, Munich

14


4.3 Useful Notes On S-Parameter Properties

S12 = S21for linear, passive circuits As can be derived from the theory, the Sxy-parameters for passive circuits are equal.

MAG(Sxy) <1 for passive circuits. If an active device exhibits power amplification in the Z0 environment, then MAG(Sxy) > 1

Simple R-L-C circuits have S-parameter curves following half-circles An L-C resonator is an overlay of two half-circles, i.e. represents a full circle. Delay lines appear like phase shifters.

All S-parameter curves turn clock-wise with increasing frequency. Because the Sxx parameters, displayed in a Smith chart, can be linked to a locus curve in the complex impedance plane, the Smith chart curve index increment can be related to frequency. It is clear that in the impedance plane, the locus curve for an inductor follows jcoL, i.e. the locus curve starts at '0' and then goes upward. Referring to the Smith chart transformation, this upgoing refers to following a circle, starting at T = -l , and ending at r = +1. I.e. this curve turns clockwise with increasing frequency.

For a capacitor, it is just similar: in the impedance plane, a 1/jcoC comes from minus infinity towards '0' for highest frequency. In the Smith chart, this corresponds to a half-circle, starting at T = +1, and ending at T = -1, again turning clock-wise.

Similar considerations can be applied to prove that also for the Sxy paramters, the locus curves in a polar diagram also turn clockwise.

Generally speaking, if a measured curve turns counter-clockwise, even only for a frequency sub-range, we have a underlying measurement problem, most possibly a calibration problem. On the other hand, if such a counter-clockwise turning happens for a de-embedded curve, and the not de-embedded curve looked ok (all clock-wise), we have a over-de-embedding problem.

4.4 Multiport S-Parameters

The number of multiport parameters for a given device is equal to the square of the number of ports. For example, a two-port device has four S-parameters. Like with Z-, Y- or H-parameters , multiport S-parameters can be obtained by overlying two-port measurements with the not used ports terminated accordingly. For S-parameters, this means a termination by the characteristic impedance Z0.

In order to transform e.g. Common-Emitter S-Parameters to Common-Base, we will now consider 3-Port S-Parameters. Provided a certain port is connected to ground, we are then able to evaluate the conversion formulas.

15


Converting from 3-PORT to 2-PORT Provided that the device under test is connected with Z0 (e.g. 50 Q) to all its 3 ports, the 3-pole network S-parameters are defined as:

b1=S11 a, + S12 a2+S1 3 a3

b2 = o21 at + o22 a2 + o23 a3

^3 = S31 * a, + S32 * a2 + S33 a3 ^

If port 3 is connected to ground, we get for the corresponding reflection coefficient F^

| \=^2. = -1

Thus we get the 2-port network parameters from the 3-port ones as: (2)

s „

S21 -

s1 3 1+

s 3 1

° 3 1

S33

°23

1+S 33

S ° 1 3 ° 3 2 19 — " '12

Ono —

I + S33 O9o O ' 23 32

'22 1+S 33

'O V " J

(3)

Converting from 2-PORT to 1-PORT Such a conversion is required if a component has been measured in two-port mode, and some of its components characteristics might be affected by the characteristic impedance of the opposite VNA port. An example is the calculation of the quality factor of a spiral inductor directly out of S-parameters.

In this case, we refer to equation. (3) from above and obtain:

^ 1 1 1port — ^ 1 1 S12 S 2 1

1 + S22

From that, we apply the basic S,, 0 R conversion, mentioned in the above chapter on

Smith charts,

R = Z0-1 + S 11

1-S 11

and obtain for the input impedance at Port 1

16


7 _ y * ' + Sn_ipor t ^-11_1port ~ *-0

1-Sn. 1port

From this, we can obtain the requested 1-Port characteristic like the Q factor of a spiral inductor

QJMAG(Z1 1 1 p o r t )

REAL(Z111port)

Converting from 2-PORT to 3-PORT Using the matrix in (3), we can also calculate the 3-port S-parameters out of 2-port parameters.

We know that: 3 2-Sj j=1 for i=i,2,3 i=1

and 3 £^=1 for j = i 2 3

i=1 So we can calculate the 3-port S-parameters out of the 2-port ones, with Index T (Two-port Measurement):

s s i j T i=1,2

C _ J=1.2

° 3 3 ~ 4 - 1 SijT 1=1.2 1=1,2

^32 - p U~S12T ~"S2 2 T)

^23 = z U - S 2 1 T - S 2 2 T )

O O , ^23 + ^ 3 2 ^ 2 2 — ^ZZl ^

^>31 = ' ~~ S 3 3

S13 = 1 - S23

S12 = 1 - S 2 2

S11 = 1 _ S 2 i

S2i =1 - S2 2

1+S33

~~ S32

~~ S33 _ s 3 2 ~ ^ 3 1

_ ^ 2 3

17


Once these 3-port S-parameters are known, they can be used to calculate the common-Base or common-Collector 2-port S-parameters of a bipolar transistor etc.

4.5 Calculating S-Parameters From Complex Voltages

Measurementwise, S-parameters refer to the backreflected and transmitted RF power of a component under RF excitation. Most SPICE simulators, however, do not feature S-parameter simulations. But they can simulate complex voltages/currents vs. fireq. Therefore, instead of the missing feature, a method to calculate S-parameters from complex voltages can be applied.

As it was mentioned before, S-parameters can be interpreted in terms of voltage at the DUT in a Z0 environment. The following sketch gives an explanation about how to calculate them for a given two-port (DUT), imbedded in an external circuit, which itself represents the characteristic impedance. In order to get the required complex forward and reverse voltages Vi, V0i, V2, V02 (to satisfy the equations (1) .. (4) of Fig. 12), a single SPICE simulation containing twice the embedded DUT is performed.

Zl = Z2 = Z0, e.g.ZO = 5012

Z 1 twoport

V01 V2

S 1 1 = 2 * - l - - 1 v01

§21=2* ^ 2 _

V01

(1)

(2)

Zl = Z2 = Z0, e.g.ZO = 50 Q

twoport yo

Zl VI VQ2

18


S - 2 * - ^ --12 ~ V^

v 0 2

(3) V ,

S 2 2 = 2 * ^ - - 1 v02 ( 4 )

Fig. 12: calculating S-parameters out of SPICE simulations (C) Copyright 2001 by Franz Sischka, Agilent Technologies, Munich

For details please refer to publications [6] to [8].

5 Network Analyzer Measurements

After the introduction to the S-parameters, it is time to consider how to measure them. A network analyzer (NWA), also called vector network analyzer (VNA), is applied. This instrument measures S-parameter vectors, i.e. the magnitude and phase, of all four S-parameters of a two-port. This is particularly important for device modeling, because there are also instruments available, which are called network analyzers, but rather are impedance analyzers, and which allow only to perform so-called 1-port measurements. However, a full two-port measurement is the important feature, because only in this case are we able to convert the measured S-parameters to Y- and Z-parameters etc., what is a requirement for de-embedding.

When applying network analyzers for S-parameter measurements, it is important to remember that we measure linear circuit performance and circuit performance for a given frequency, ignoring harmonics.

On the other hand, network analyzers can also be applied to specific non-linear measurements, e.g. sweeping the RF power, measuring the transfer characteristics and evaluating for example the ldB compression point of amplifiers. In this case, however, signal distortion happens and harmonic frequencies show up. On the other hand, when using a NWA, always the base frequency and its transfer compression are measured. Therefore, if we are interested in the modeling of device nonlinearities, we should apply a spectrum analyzer after the conventional DC-CV-NWA modeling, and use harmonic balance simulation to model the RF-power dependent spectrum. Alternatively, one of the currently introduced commercial nonlinear NWAs can be used as well.

In the following, we will refer to linear network analyzers.

5.1 Network Analyzer Measurement Principle

A two-port network analyzer measures the power transmission and reflection in magnitude and phase at two locations, port 1 and port 2.

19


It basically consists of a wobbled, high frequency signal generator (RF synthesizer), an S-parameter test set to acquire the input and reflected power at the DUT for both ports, and a control and display unit (mainframe), see Fig. 13 below.

signal flow K hpib

portl

© ©

Network Analyzer Mainframe

RF Synthesizer

s-Parameter Testset

port2

test device DUT

Fig. 13: vector network analyzer components (C) Copyright 2001 by Franz Sischka, Agilent Technologies, Munich

For the measurement, the DUT is connected between the two ports. The RF synthesizer signal is fed into the S-parameter testset and applied alternately to port 1 and port 2. Measured is the signal of that specific frequency reflected back from the DUT to port 1, the signal transmitted from port 1 to port 2, and then, when the RF signal is applied to port 2, the reverse behavior.

The S-parameter testset.

The block diagram of Fig. 14 shows the core of this meter combination, the S-parameter testset. The RF Input source at the top, connected to the RF synthesizer, provides the stimulus power. The PIN switch directs the signal to either a forward or a reverse S-parameter measurement. Directional couplers then detect the injected and reflected power of the DUT. The detected signals are downcoverted into IF signals for further analysis in the NWA mainframe, where all the 4 signals are digitized and signal processed in order to give the S-parameters.

Note the signal naming: R: reference signal, A: reflected signal at port 1, B: transmitted signal from port 1 to port 2

20


in 5 o

I i is tl o 9 9 V 9

LO.V7 IF. H h

AAAA

in 2 X o X

PIN SWITCH A

20dB

20dB

R 0-90dB ^ ^

X

0-90dB

V ^

^ J"h <^) -^Â^

A B

6dB 2MB

0-90dB 20dB

6dB

PIN SWITCH

PIN SWITCH

I PUT

J Fig. 14: Block diagram of the S-parameter testset (4-sampler).

R: reference signal A: reflected signal at port 1 B: transmitted signal from port 1 to port 2


4-sampler vs. 3-sampler network analyzers

There are two main S-parameter testset principles: 3-sampler and 4-sampler, see Fig. 15. In case of a 3-sampler, the reference signal is coupled-out before the PIN switch. Therefore, the switching errors are not included in the calibration.

For a 4-sampler VNA, however, where the reference signals are detected after the switch to the two ports, a better calibration can be performed, including all error terms. Usually, this is important for frequencies above ~20GHz. Also, with the 4-sampler VNA, the user has complete freedom with regard to his own calibration techniques and does not need to use simplified procedures.

21


Source I . >

A n—

Portl

fe Transfer switcn

3Vfc -cr-

Port2

Fig. 15: principle of a 3-sampler and a 4-sampler VNA. (C) Copyright 2001 by Franz Sischka, Agilent Technologies, Munich

Note: in both cases, the signal power at the reference port R should not be too small. Otherwise, the downconverter might have phase locking problems. The NWA error message reads in this case: "phase lock lost".

5.2 Network Analyzer With DC Bias

In order to measure S-parameter of active components, the operating point (DC bias) must be set. This is performed with AC/DC bias TEEs. Such components consist basically of a big inductor (to feed the DC bias) and a big capacitor (to feed the HF signal), see Fig. 16.

DC IN

coax toSMU

DC & HF OUT

Fig. 16: bias TEE to couple DC bias and HF signal (C) Copyright 2001 by Franz Sischka, Agilent Technologies, Munich

22


Since the applied DC bias inductor is not ideal, but also exhibits some ohmic DC losses, the voltage at the DUT (transistor, diode etc.) will not be identical to the one set up at the DC supply, i.e. the SMU. In order to compensate these DC bias losses, the ohmic loss must be carefully characterized by a separated measurement with the bias TEE's output shorted, and must be added as auxiliary test circuit to the model circuit of the DUT. As a rule of thumb, the ohmic losses are about ~2Q.

For a SPICE simulator, the additional circuit is:

.SUBCKT bsim_n_DC_bias 1=G 2=D Rbiasl 1 11 2 Cbiasl 1 11 1 Rbias2 2 22 2 Cbias2 2 22 1 Xtransistor 22 11 0 0 bsim *this is a subcircuit call .ENDS

Please note that in order to not affect the high frequency simulations, shunt capacitors Cbiasx are added to short the Rbiasx effects for the S-parameter simulations. With this additional circuit, the modeling simulation will perform corresponding to the measurement environment. Otherwise, if these resistors are not taken into account with the simulation, the simulated DC bias conditions will be different from the ones measured during the S-parameter measurements, what is best seen if the S21 simulations do not match the measurement data at lowest frequencies.

Please note that these DC bias losses are not included in any NWA calibration. A NWA calibration refers to the NWA frequency range of e.g. 50MHz .. 50GHz and not to the DC !

In most network analyzers, these bias-TEEs are included in the the S-parameter testset, and the DC_IN is accessible by a coax connector at the rear panel. Fig. 17 sketches the required connections for this case.

Note: In order to connect the DC-Analyzer Triax cables to the Coax inputs of the NWA's S-parameter testset, Triax-to-Coax converters have to be applied. Make sure these converters leave the middle shield of the Triax cable open, i.e. unconnected !

23


DC Source/ |ojrj Monitor 113 sU

Synthesized Sweeper

" » » » « •

DC bias

® RF ®

OUT

i_r

Vector Network Analyzer

S-parameter Test Set with internal bias TEEs

control software 1C-CAP

Fig. 17: VNA measurements using the internal DC bias feedthrough of the S-parameter testset. (C) Copyright 2001 by Franz Sischka, Agilent Technologies, Munich

If we want to avoid the ohmic losses of the NWA's internal bias TEE, we can also apply the previously mentioned force-sense DC biasing externally (Kelvin measurements), and include a voltage sense line up to the very DUT. As a consequence, this means using double bias-TEE for each port of the NWA. Such a commercial external bias TEE is depicted in Fig. 18.

FORCE

2xtriax toSMU

SENSE

DC & HF_OUT

Fig. 18: using external bias TEEs allows to apply Kelvin DC biasing also with network analyzer measurements (C) Copyright 2001 by Franz Sischka, Agilent Technologies, Munich

24


The corresponding measurement setup is shown in Fig. 19. Two external bias TEEs are applied between the two DUT connections and the network analyzer ports. This setup then allows to get rid of possible ESD (electrostatic discharge) protection shunt resistors at the NWA ports (typically 1MQ), and, of course, of the internal bias TEE inductor choke resistor. With such a measurement setup, keep in mind to not connect the guard shield of the triax Kelvin cables. Also, these Kelvin bias TEEs should be placed as close as possible to the DUT.

Vector Network Analyzer

Synthesized Sweeper

DC Source/ Monitor

| S-parameter I Test Set

External Bias TEEs

Force

DC bias

Fig. 19: VNA measurements with external force-sense DC bias supply (C) Copyright 2001 by Franz Sischka, Agilent Technologies, Munich

5.3 Network Analyzer Calibration

A considerable challenge in S-parameter VNA measurements is to define exactly where the measurement system ends and the DUT begins. This location is called 'reference plane'. This means, all error contributions, inside the VNA and in the cables up to this reference plane, have to be calibrated out. The point is, especially compared to CV measurements, that the calibration standards are no longer ideal, and also contribute themselves to the total calibration process.

What is a 12-term error correction

As can be seen in Fig. 20, there are 6 error contribution terms in forward direction, related to the characterizing signals R, A and B of the NWA:

Directivity: cross-talk of the power splitter in the NWA testset Crosstalk: cross-talk inside the S-parameter test set, overlying the DUT Source Mismatch: multiple reflections due to impedance mismatch

of cables and connectors Load Mismatch: the same for the opposite port

25


Reflection Tracking A/R: Transmission Tracking A/R:

frequency dependence of signal path R->A same for signal path R->B

For the reverse calibration, another 6 error terms add up to a total of 12 terms. The procedure to get rid of these 12 terms is called the 12-term error correction.

power splitter

AC source

5 5 source load

mimmatch mismatch

Fig. 20: the 12 error contributions for S-parameter measurements with a VNA (C) Copyright 2001 by Franz Sischka, Agilent Technologies, Munich

H(f)'

frequency res|

reflection transiuis*

V ' f

tracking (A/R) ion tracking (BM)

Network analyzer calibration with standards like SOLT, TRL, LRM etc. There are many different calibration techniques for network analyzers. Such are Short-Open-Load-Thru (SOLT), Thru-Reflection-Load (TRL) or Load-Refection-Match (LRM) and the associated error correction calculations. For the different calibration procedures, specific known standard terminations have to be measured.

Note: for 3-sampler NWAs, specific simplified applied. They are called TLR* and LRM*.

TRL and LRM calibrations have to be

Although there are many publications on the pros and contras of the different calibration methods, the SOLT is most commonly used for on-wafer measurements of silicon devices. One of the reasons is that due to the electrical losses of silicon, microstrip standards as required for LRM and TRL are difficult to manufacture on the wafer. Another reason for using SOLT is that this calibration is a wide-band calibration and not limited to a frequency band.

In case of a SOLT calibration, and for on-wafer measurements using Ground-Signal-Ground (GSG) coplanar probes, Figures 21 and 22 depict the corresponding test structures,

26


which are usually available on a RF-high-performance ceramic substrate, including accurate description of the non-idealities of these standards.

Fig. 21: calibration substrates (C) Copyright Cascade Microtech

OPEN

V , — if ^

: -At IB Probes in the air

SHORT THRU

Fig. 22: details of SOLT calibration structures for on-wafer measurements (C) Copyright 2001 by Franz Sischka, Agilent Technologies, Munich

Some notes about these calibration standards: While in the case of the CV meter, the calibration corrects for a single, ideal offset capacitor, a NWA calibration relates to cal standards (OPEN, SHORT, LOAD, THRU etc.) from a calkit. These cal standards do not represent ideal standards. They represent the real, existing standard, including its nonidealities! It means that a SHORT is not an ideal SHORT, but instead represents rather a small inductance. The same applies to the THRU, which has a non-ideal delay time. The OPEN corresponds rather to a capacitor than to an ideal OPEN. Therefore, these non-idealities of the G-S-G probes have to be entered into the NWA before calibration. This is called 'entering' or 'modifying the calkit'.

27


While this procedure refers to the non-idealities of the calibration standards, i.e. the termination of the NWA cables during calibration, the subsequent calibration is based on this information and then related to the selected frequency range, the RF power, the averaging of the NWA etc. After it has been performed, the correction terms are stored in the calset of the NWA. In other words, the 12-term error vectors are 'filled up'.

Afterwards, when the measurement is performed, the raw measured data arrays will be corrected inside the NWA, using a correction technique related to the selected calibration method, and referring to the specified calset. Finally, this corrected measurement result is transferred into the modeling software and displayed there.

Therefore, after the calibration, a re-measurement of the OPEN will not represent an ideal open, but instead exactly those parasitic components as described in the documentation of the OPEN. In the same way, a THRU shows up after calibration with its real delay time, and a SHORT represents its inductive behavior!

This fact leads to a simple calibration verification procedure:

5.4 NWA Calibration Verification

Of course, the best calibration verification is to measure a golden device. However, this is not available for on-wafer device modeling. Otherwise, if we remeasure all the calibration standards, i.e. the OPEN, SHORT, LOAD and THRU on the ISS ceramic calibration substrate, and check the result against SPICE simulations of the calibration standard specification netlists, we obtain a very clear picture of the calibration quality. This is because these standards of the ISS substrate are carefully specified by the manufacturer (calkit data!).

CalKit data for Cascade G-S-G probes: Pitch C-Open/fF L-Short/pH L-Termination/pH 100 -9.3 2.4 -3.5 125 -9.5 3.6 -2.6 150 -9.7 4.8 -1.7 The THRU delay time is always lps.

When all 4 standards exhibit an excellent fit between measurement and simulated model, we can assume a correct calibration of the NWA.

Note: This calibration verification can also be applied to check the quality of an older calibration.

28


5.5 Conditions For Efficient NWA Measurements

In order to make efficient network analyzer measurements, it is recommendable to perform log sweeps instead of linear ones. Usually, 10 data points per frequency decade are fully sufficient for obtaining clean S-parameter plots. Also, use the same frequencies for all measurements. This simplifies de-embedding later. Last not least, to avoid non-linearities during the measurements, keep the RF power levels smaller compared to the DC bias power level.

For transistor modeling, measure S-parameters for all DC bias conditions, perform just one single de-embedding to these data (see further below) and then store them into a data file. Then, by individually reading sub-data out of this file related to e.g. transistor input resistor modeling (frequency sweep for specific DC bias conditions) or transit time modeling (one fixed frequency at the -20dB/dec slope of MAG(H21)), we do not need to re-measure, but simple read from that data file. This saves a lot of calibration time and de-embedding manipulations. Last not least, after the model parameter set has been finally obtained, we can read back all the de-embedded data for all DC bias conditions and compare these curves with the simulation result of the final parameter set. A plot showing the relative vector errors between measured and simulated data allows then to clearly identify the quality of the model fit and to identify operating conditions with best and worst fit.

5.6 Linear Versus Non-Linear RF Performance

So far, we introduced the S-parameters and compared them to the other two-port parameters like Y or Z, into which they also can be converted. This means, S-parameters are small signal parameters by definition. In other words, for a transistor as an example, the S-parameters do not reflect non-linear amplification phenomena like compression etc.

In general, two-port parameters of non-linear components like transistors or diodes vary as a function of input power. However, for RF signal powers which are small compared to the DC bias power, this non-linearity can be neglected, and linear operation can be assumed. In the case of a bipolar or MOS transistor, this is generally true for RF input signals at the Base or Gate lower than -30dBm, and Collector or Drain DC currents above 1mA.

NOTE: a smart way to check the max. tolerable RF signal power is explained further down in this chapter.

Applying too high RF signals leads to signal distortion and thus to harmonics.

When applying a too high RF signal during S-parameter measurements of a network analyzer (NWA), the Kirchhoff law is affected. Since the NWA only measures the base frequencies and ignores the harmonics, the Kirchhoff statement that 'the sum of all currents, at all frequencies, into a node is zero' is violated ! Therefore, it is absolutely important to verify small-signal conditions for the diodes and transistors during NWA measurements.

29


Again, keep in mind that when the S-parameters become RF-power dependent, harmonics occur, see Fig. 23. In order to characterize these harmonic frequencies, a spectrum analyzer or a non-linear network analyzer should be applied! Simulation-wise, SPlCE simulators have to be replaced by harmonic balance simulators. And your modeling software, as the interface between measurements and simulator, should support this !

large signal, non-linear RF: voltage/current vectors for each harmonic frequency

:8v i I .a,

small signal: S-parameters tf freq

If 5.

c <0

1 :

f

/

1 L

t / ^ ^ - - - - ^ ^ ' ^ f r e q

DC bias DC bias

Fig. 23: Applying too much RF power to non-linear devices like transistors generates h a r m o n i c s (C) Copyright 2001 by Franz Sischka, Agilent Technologies, Munich

An absolute prerequisite for using two-port matrices is the linear, time invariant behavior of the circuit. Only in this case, matrix conversions like for example for de-embedding, are possible! Nonlinear high-frequency measurements cannot be de-embedded by Y- and Z-matrix subtractions!

Selecting the right RF power for nonlinear devices before starting calibration

When measuring S-parameters of nonlinear devices with a network analyzer, it must be assured that these devices operate in small-signal, linear mode. Otherwise, the high frequency test signals will no longer be sinusoidal, and the occurrence of harmonics will lead to wrong S-parameter measurements and shifted DC bias conditions.

A smart method to check the correct port power settings is like this: When measuring a DC output characteristics and calculating the output resistor 'Rout' from of it, the resulting curve is very sensitive. Therefore, we can use this plot to identify possible effects of too big an AC power applied to the transistor. This means, we measure the DC output characteristics, and let the NWA perform measurements untriggered, in continuous mode, i.e. unsynchronized to the DC measurement. Then, we increase the Port power manually (decrease port attenuations) until we see an effect on the next 'Rout' measurement. We then know the maximum allowed RF power for the S-parameter measurements of this device! The plot in Fig. 24 reflects such a test. The disturbed curve happens when tpo much RF power is applied to the transistor.

30


Rout M2

Vd/V

Fig. 24: Measuring the DC Rout resistance of a MOS transistor: with an accurate RF power level and with a too big RF power level.


What if: characterizing a transistor at higher RF signal levels where it behaves nonlinear

If you need to characterize e.g. a power RF transistor at signal levels where distortion occurs, and where the Kirchhoff law is not fulfilled for the data measured by the NWA, it is absolutely mandatory to replace the linear SPICE S-parameter simulation by a nonlinear harmonic balance simulation. Only with this kind of simulation, we can emulate the conditions of the power RF transistor measurement. From the simulation data of harmonic balance, we then calculate the S-parameters of the base frequency and compare these S-parameters with those obtained from the NWA measurements. Only in this case the obtained model parameters will be correct for the power RF transistor !

Conclusions: If the DUT behaves non-linearly:

- signal compression occurs - harmonics show up - the DC operating point may be shifted - loadlines and transfer curves become dynamic, i.e. RF-power dependent - matrix conversions are no longer possible - de-embedding (see further below) is no longer valid.

For further details related to the topics of this chapter see publications [9] to [18].

31


5.7 Pulsed S-Parameter Measurements

When measuring a transistor, the DC measurements are usually performed in fast sweep mode, i.e. pretty fast in time. On the other hand, when performing the biased RF measurements (network analyzer), the underlying DC bias has to be kept constant during the whole frequency sweep, incremented and again kept constant for the next frequency sweep. Therefore, due to self-heating of the transistor, the RF measurements may have been performed at completely different chip temperatures than the DC measurements. And while the possibly cooler DC measurement curves served to extract the DC model parameters, we may run into problems when extracting the remaining RF parameters, which may refer to hotter measurement conditions. And this can be one of the explanations if the measured and simulated S21 curves do not match at lowest frequencies.

To avoid this, isothermal measurements have to be performed. There are fully configured pulsed network analyzer systems available on the market, like the Agilent 85124A. Such systems allow lus pulsed measurements from DC up to 40GHz. Fig. 25 gives an overview of the system, and Fig. 26 depicts the applied pulse scheme.

RF synthesizer

IC-CAP control software

network analyzer

LO synthesizer

bias pulser 1

O

Pulse Generator, acting as a trigger for the whole system

Fig. 25: block diagram of the Agilent 85124A pulsed measurement system from DC to m i c r o w a v e s (C) Copyright 2001 by Franz Siscbka, Agilent Technologies, Munich

In this case, the modeling procedure is as follows: > perform a full device measurement characterization at e.g. 25'C in pulsed mode, DC

and S-parameters. > extract all temperature-independent model parameters (conventionally) > perform another pulsed measurement for DC and S-parameters at the other

32


temperatures, e.g. -25'C and +75'C and extract the temperature parameters (e.g. XTI and XTB for the Gummel-Poon model) perform a conventional, non-pulsed measurement. The deviation from the pulsed measurement of above is then due to self-heating, modeled by an extra thermal pin of the model. This pin is connected to an equivalent schematic consisting of a thermal resistor (radiation) and a thermal capacitor (self-heating), which is fed by a 'thermal' current. This current is proportional to the dissipated power in the device. The modeling is then performed by tuning the thermal network model parameters Rth and Cth.

Gate/Base DC bias

Drain/Collector DC bias

Gate pulse width = HFpulsewidth + 2T1 + 2T2

Drain pulse width = HFpulsewidth + 2T2

Fig. 26: Pulse timing of the measurement system in Fig. 25 (C) Copyright 2001 by Franz Sischka, Agilent Technologies, Munich

33


6 Extending The Measurement Plane To The Transistor: De-embedding

After having performed a network analyzer calibration, the calibration plane is located at the ends of the NWA cables. The device itself, however, needs to be connected to this calibration plane. In the case of a packaged device, S-parameter measurements would now include the test fixture, the package and the very inner DUT. For on-wafer device characterization, using e.g. ground-signal-ground probes (GSG), the test pads (where the probes touch down) degrade the performance of the very inner DUT by their layout specific capacitive and inductive pad parasitics. In order to extend the calibration plane to either the beginning of the package, or the inner DUT, these outer parasitic effects have to be stripped off. This is called de-embedding.

A brief example on how de-embedding returns the real, inner DUT perfonnance without its degradation due to the measurement environment is given in Fig. 27. We can clearly see how the transistor cutoff frequency fT is degraded due to these parasitics.

CE+a: inner transistor performance. > : i i i i.

degraded transit frequency

due to package effects J I 1 1 1 I—! 1 1 !_

G 5 0 . 0 7 0 0 . 0 7 5 0 . 0 8 0 0 . 0 8 5 0 . 0 9 0 0 . 0

C E : - 3 J vBE

Fig. 27: f-p of a transistor before and after de-embedding (C) Copyright 2001 by Franz Sischka, Agilent Technologies, Munich

6.1 A De-Embedding tutorial

If we are going to model a transistor mounted to a chip carrier, this carrier will distort the performance of the inner transistor. Yet, the chip carrier can be described widi series inductors of the bond wires and the parallel capacitors of the pads (Fig. 28).

34


via

via

Fig. 28: chip carrier of a bipolar transistor case and its parasitic components (C) Copyright 2001 by Franz Sischka, Agilent Technologies, Munich

By rearranging the schematic components of Fig. 28, we obtain a simplified equivalent schematic as given in Fig. 29.

•C12

S — ° total —

° 11 total

s V 21total

s ^ l j 12 total

° 22 total J

pinl

C13

I

pin2

C23

L3

pin3 I Fig. 29: The equivalent schematic of the chip carrier for high frequencies.


In order to strip off the parasitic components from the outside towards the inner DUT, Fig. 30 depicts the corresponding de-embedding procedure.

35


HP5

i ^T J Jc2:

r T J _ pin3 _ ^ subtract the Y matrix

of parallel capacitances

pinl

ET of subtract the Z matrix

the series inductors

pinl pin2

T Fig.30: Stripping off the chip carrier parasitics in order to obtain the performance of the inner t r a n s i s t o r (C) Copyright 2001 by Franz Sischka, Agilent Technologies, Munich

The step-by-step procedure for this de-embedding:

We have measured the S-parameters Sjotai of the transistor and its carrier. We assume that the carrier has been modeled already.

Following our assumption of having parallel capacitors as 'outer' parasitic components, we transform the S-parameters to Y, because a Y matrix represents a PI structure of components. A simple subtraction will de-embed the parasitic capacitor effects, see Fig. 31.

Y = ( Y n - j n ( C 1 3 + C 1 2 ) Y12+jQC I2

Y21+jQC12

pinl

L1 !

Y 2 2 - j ^ (C 2 3 + C12)y

c pin2

L3

pin3

Fig. 31: The remaining equivalent schematic of fig. 30 after the de-embedding of the Capac i tors (C) Copyright 2001 by Franz Sischka, Agilent Technologies, Munich

36


Now, the new 'outer' parasitic components are the two inductors, which are in series with the chip connections. Series parasitics can be easily eliminated by subtracting a Z matrix. Therefore, we transform the resulting Y-parameters from above into Z-parameters and subtract the inductors, see Fig. 32.

z = (Zu-\Cl(L,+L3) Z 1 2 - jQL 3

Z21 - jftl_3 Z22 - jQL3

pinl B pin2

pin3

Fig. 32: The remaining equivalent schematic of Fig. 31 after the de-embedding of the series inductors (C) Copyright 2001 by Franz Sischka, Agilent Technologies, Munich

These Z-parameters are finally transformed back into S-parameters which now describe exclusively the performance of the 'inner' chip.

chip ° 1 letup

^°21chip

°12chip

Q lJ22chipy

Note: de-embedding by complete Y matrix (OPEN) and Z matrix (SHORT) subtractions can be applied as well, provided it has been assured that

there are no hidden series components present for Y-matrix subtractions (mixed cross-talk represented by chains of C-L-C-L etc.).

there are no hidden parallel components present for Z-matrix subtractions related to a two-step de-embedding:

for on-wafer measurements (OPEN -> SHORT sequence): the SHORT has been de-embedded from the OPEN dummy

for packaged measurements (SHORT -> OPEN sequence): the OPEN has been de-embedded from the SHORT dummy

there are no hidden delay line effects present when subtracting Y- or Z-matrices

37


6.2 Two-Port Matrix Properties And Manipulations For De-Embedding

Before we begin, first some terms and definitions on serial and parallel circuits:

Series circuit Parallel circuit .

Impedance Z = ylR2 +X2 Admittance Y -1/Z-jG +B Resistance R Conductance G=l/R Reactance X Susceptance B=l/X Immittance: A general term for both impedance and admittance, used when the distinction is irrelevant.

With this in mind, we are now ready for the two-port matrix signal flow definitions:

1. H matrix relating voltages and currents of a two-port

(vA 'hl l h l 2 \

h21 h22 on

2. Z matrix relating voltages and currents of a two-port

(vn (zll zl2^ ( iH z21 z22

38

RF MOS

3. Y matrix relating voltages and currents of a two-port

l i2J fy11 y1 2 \ y21 y22

(v\\

12

4. A matrix relating voltages and currents of a two-port

(\\\ fall al2^ fv2^

il a21 a22 V J V J 12

5. S matrix relating to traveling waves at a two-port

fbI) l b 2 J

fsll sl2^ (dl\

s21 s22

39


6. K matrix relating to traveling waves at a two-port

| b l j fkll \L\2\ (bl\

*

vk21 k22

Matrix Conversions

Since all these matrices refer to linear, small-signal signal theory, they can be converted into each other. Here some useful examples:

H to Y conversion

To convert a H matrix into its Y equivalent, we just have to rearrange the matrix equations. The H matrix has the form

^vH fhll hl2^ f i O * h21 h22 v i 2y v j K"h

and the target Y matrix

' iO fyll yl2Y/vn y21 y22 v i2y v- j vv 2y

The vl dependency, i.e. the first line in the H matrix, can be solved for il:

1 , hl2 „ il = vl v2

"•*• * " I i , what is already the first line of the Y matrix.

We insert this result into the second line of the H matrix in order to replace the il dependency

•o h 2 1 H i2 = v1 +

h11 h22 - ^ l h12

h11 \i2

40


With det(h)=h11h22-h12h21

we can rearrange and yield

.„ h 2 1 , det(h) . i2 = vl + — — v 2

hl l h l l

what finally gives the relationship between the y and h parameters:

( y i i y12>l y21 y22 hl l

1 • h l 2

h21 det(h)

Y to Z and ZtoY conversions:

The conversion of the Y to the Z parameters is, related to the special definition of these two matrices, very simple. Starting with the resistance matrix form

(v) = (z )*( i ) »

we can solve it for ( i ) by multiplying to the left side with ( z ) , the inverse matrix of ( z ).

(z)-(v)=(zr(z)*(i) (zr(v)=(i)

or

Comparing this result with the definition of the y matrix, we get finally

(z ) -=(y)

and correspondingly

(y)-'=(z)

Note: remember the matrix inversion scheme:

fa bV1 1 ( d -b\ c d ad - cb - c

with ad - cb = det( matrix)

41


StoH conversion

Important note: S-parameter conversion into other matrices by simply multiplying with e.g. ZO = 50 Q are only o.k. if the characteristic impedance ZO is *not* frequency dependent! This is important for low-impedance silicon substrates !!!

h „ = _ ( 1 + S11)-(1 + S 2 2 ) - S 1 2 S 2 1

11 ( 1 - S 1 I ) ( 1 + S 2 2 )+S 1 2 S 2 1

2 s 1 2 h12 =

( 1 - S 1 1 ) - ( 1 + S 2 2 )+S 1 2 S 2 1

h ~ 2 s 2 i 21 (1-Sn)-(1 + S22)+S12s21

_ (1~S11JV~S22/~S12S21 2 2 ( 1 - S H ) ( 1 + S 2 2 ) + S 1 2 S 2 1

* ZO

/ ZO

6.3 De-embedding Techniques

In this chapter, we discuss the matrix properties and manipulation schemes relevant for de-embedding.

De-embedding of serial parasitics (Z-matrix)

Adding of Z-matrices corresponds to adding of serial impedances to a DUT. On the other hand, provided these parasitic matrices are known, we can calculate the Z-matrix of the inner DUT by subtracting them from the Z-matrix of the total measurement.

Adding of Z-matrices:

o — "parasl

hi UT

"paras2

42


Ztotal = ZParasl + ZDUT + ZParas2

The individual Z-matrices of the series parasitic components are:

Z_paras1 Z_paras2

JParas1

Paras2

fA

1° (c lc

°1 BJ c l cj

Adding these matrices of parasitic components gives:

Zparas = ZParasl + ZParas2

Z_paras or:

(A + C C } Paras

V = z TEE C B + C

what is the matrix of a TEE structure (!!).

How to proceed with the de-embedding of series parasitics: Once the parasitic components A, B and C are known, they can be stripped-off by subtracting the Z-matrix Z ^ ^ = ZTEE of a TEE structure from the measured data Ztotal. We obtain:

ZDUT = Ztotal - ZParasl - ZParas2 = Ztotal - Zparas

43


De-embedding of parallel parasitics (Y-matrix)

Inversely to the adding of Z-matrices above, the adding of Y-matrices corresponds to adding of parallel admittances to a DUT. Again, provided this parasitic Y-matrix is know, we can calculate the Y-matrix of the inner DUT by subtracting Yparas from Y ^ , i.e. the Y-matrix of the total measurement.

Adding of Y-matrices:

YDUT

Y paras

Ytotal = YDUT + YParas

The Y-matrix of the parallel parasitics is:

rA + B -B

-B C + B please watch the signs !

Y paras

= Y, PI

How to proceed with the de-embedding of parallel parasitics: Once the parallel parasitic components A, B and C are known, they can be stripped-off by simply subtracting the Y matrix Yparas = Yw of a PI structure from the measured data Y ^ and we obtain:

YDUT = Ytotal - YParas

44


De-embedding of lossless delay lines (S-matrix)

&"

* )

coplanar

," s+

microstrip

Assumption: we are in the S-parameter domain and have the device-under-test (DUT) imbedded between two lossless delay lines:

with a: forward wave b: reflected wave

Then, the S-parameter matrix is valid and it is

W = si l t o t a l * a l + 8 1 ^ ^ * 8 2 b2 = s21 t o t a l*al+s22 t o t a l*a2

a1 b1

Delay TD1

lossless

Delay TD2

lossless The delay matrices are represented by the S-parameter matrices:

f °TD1 ~~

0 e (-j*2PI*f*TDl)

(-j»2W*f*TDl)^

a2 b2

° T D 2 —

f 0 e(-j*2PI«fTD2)>\

,(-j*2PI»f*TD2) Q

How to proceed with the de-embedding of lossless delay lines: Provided we know the delay times TDl and TD2, we can use the 'port shift' properties of S-parameter multiplications (shift of reference planes), and obtain:

45


'S11n,rr S12 ^ f 'DUT -DUT

S21, DUT S22, DUT

01 -i * pj-2Plf 2TD1 0 1 'total e S12total*exp j2Plf (TD1+TD2)\

S21 total exp j2Plf (TD1+TD2) 9 9 ? * pvnJ-2PI-«-2TD2

° " t o t a l e x P

with: f : frequency TD1: delay time at port 1, TD2: delay time at port 2

De-embedding applying the ABC-matrix

By definition, ABC matrices are best suited to describe a chain of two-ports. This feature makes them an ideal starting point for parasitics de-embedding related to measurement conditions where we have considerably long connection lines to the device, and a separation into parallel and serial parasitics cannot be achieved. I.e. situations where the parasitic components are more distributed than lumped. ABC matrix de-embedding can be applied for example to packaged or insertable devices like a connector etc.. It can also be applied to special on-wafer components line spiral inductors, which occupy a large area on the chip and whose parasitics are therefore distributed.

For a classical ABC matrix de-embedding, let's start with an example of a packaged device. Besides the test fixture for the DUT, which consists basically of a substrate with a strip line for each port of the DUT, we also need a special test structure to characterize these strip lines.

This means we need another strip line on the same substrate like the test fixture, and this strip line is exactly as long as the strip lines of the test fixture. See the sketch below.

(L - AL)/2

Ajine

—location 7 of the DUT

AJine

AL

auxiliary fixture to characterize AJine

test fixture to measure the DUT

With the assumption that the A j m e ABC matrix is identical to the connection strip lines of

the test fixture, the total performance of the device-under-test (DUT) including the test fixture can be expressed in A matrices as:

46


Atotal = Aline * ADUT * Aline

or solved for the DUT ABC matrix AQJJT; :

A _ A - l * A * A _ 1

•^ DUT ~ " • line ** total ^ line

How to proceed:

The measured S-parameters S. î are converted to At t aj . The same applies to the

measured S j m parameters. Then the matrix calculation from above is applied in order to

obtain the de-embedded AQTJX-

As a special case, the ABC matrix can be applied to de-embedding from lossy delay lines. First, we have to define the ABC matrix A j m e of a strip line, with:

ZO characteristic impedance of the strip line y propagation coefficient of the line ct loss B or TD phase shift resp. delay time of the strip line,

r , lossless line Y (freq)- L = |a(freq) + j • B(freq) J • L ~ j • B(f) • L = j • 2PI • freq • TD

Note: roughly TD=10ps per mm strip line can be assumed on a ceramic substrate.

In case of a lossy line, we calculate first for every frequency point [i] the auxiliary term:

aux[i] = (j2 * PI * freqlij * oc + j * 2 * P I * f req[i] * p)* L

and in case of a lossless line (ct=0), we calculate first:

aux[i]=j*2*PI*freq[i]*p*L or

aux[i]=j*2*PI*freq[i]*TD

which gives for the ABC matrix of the delay line (per frequency point index i):

cosh(aux[i]) ZO*sinh(aux[i]p Aline 10 = —-sinh(aux[i]) cosh(aux)[i]

This matrix is then introduced in the ACB matrix de-embedding formula A DUT = A|j"ne * A t o t a | * AjTne, and we can calculate the de-embed matrix ArjTjj.

47


Note: in case of a lossless delay line, the formula simplifies to

( cos(p*l_) ZO*sin(P*L)^

with

Mine lossless [i] = -^s in (p*L) cos(p*L)

p = coVCL and ZO = J—

6.4 De-Embedding The OPEN Dummy Device

The most simple, but very often used de-embedding method is the simple de-embedding from an OPEN device. The underlying prerequisite for this method is, however, that all the circuit components of the OPEN dummy structure can be represented exclusively by lumped circuit components only which are altogether in parallel with the DUT. Only in this case, the well-known Y-matrix subtraction method Y_DUT = Yjxrtal - Y_OPEN can be applied. Fig. 33 depicts this condition.

Y DUT

^^•^rDUT^^H infflHHn,t.,.-'M~ • • • • • ilHIMiiij L"

- parallel-v. / parasitic;:

Y_parallel

Fig. 33: For OPEN dummy device de-embedding using Y-matrix subtraction, the OPEN subcircuit has to be completely in parallel with the DUT.


In order to successfully applying this Y-matrix subtraction, this prerequisite condition of parallel parasitics has to be verified. Otherwise, the de-embedded curves of the inner DUT may look ok, but they may be wrong.

The best way to check this is to model the open. If we are able to achieve a fit with a sub-circuit consisting of lumped devices which can be interpreted as being completely in

48


parallel with the DUT, (independent of how complex the inner structure of this sub-circuit is !), we can be sure to perform a correct OPEN de-embedding.

Fig. 34 shows an OPEN dummy layout, and its S-parameter performance. Referring to the physical layout given in Fig. 35, we can assume a simple RC TEE structure for low frequencies. For higher frequencies, also crosstalk between the ground-signal-ground GSG contact pads of the dummy and coupling across the pads from port 1 to port 2 comes into play. See Fig. 34 and components CIO, RIO, C12, C20 and R20, where the resirtors again represent the losses of the silicon substrate. This effect happens usually for frequencies above -10 GHz, and can be seen in the S-parameter measurements as a deviation from the low-frequency half-circles. See the typical measured S-parameters in Fig. 34. Of course, this 2nd order high-frequency dependency varies with the layout of the OPEN and also with the wafer process.

OPEN DUMMY

R £ « » CE-33

Fig. 34: Modeling the OPEN dummy device (C) Copyright 2001 by Franz Sischka, Agilent Technologies, Munich

49


Fig. 35: physical representation of the OPEN dummy structure for low frequencies (C) Copyright 2001 by Franz Sischka, Agilent Technologies, Munich

If we did not require e.g. inductors to model the OPEN dummy, or other components which can be assumed to be in series with the inner DUT, we can now perform the de-embedding. The measured S-parameters of the OPEN and the total DUT are transformed to Y-parameters and then, the Y-parameters from the OPEN are subtracted from the total DUT's Y-parameters.

De-embed from Open: •DUT = ^Total - Y 0 p w i

Convert to S: SD U T ~ S ( Y Q U T )

6.5 De-embedding The OPEN And The SHORT Dummy Device

A method to also strip off the series parasitic influence from the measured data is to de-embed the inner DUT from both the OPEN and SHORT dummy device. The idea behind this method is, that the electrical behavior of the pads around the DUT can be described by a combination of exclusively parallel (OPEN) and exclusively serial (SHORT) circuit elements as described in Fig. 36.

50


SERIAL PARASITICA

; i Di : ,_ i -' . ' •-* t

r i V*y" ' :

• ; ) * — c

c

i.. • • - , 7 ^ - ^

i s f - M 1 * )

I'AHALLEL PARAS!TICS

• r-i'Hi'u!

Fig. 36: For OPEN and SHORT dummy device de-embedding using Y- and Z-matrix subtraction, the OPEN subcircuit has to be completely in parallel with the DUT, and the SHORT subcircuit completely in series with the DUT.


Once the two-port matrices of the serial and parallel parasitic elements are known, they can be subtracted very easily from the total measurement data set. To determine these matrices, the S-parameters of the OPEN and the SHORT dummy test structure are used.

51


OPEN DUMMY:

o 1 o

o-

PARALIEL PAOASITICS

Y pu*!let i — I D -

SHORT DUMMY:

o •

SERIAL PARASITICS

. o

._—o-; ' ^ T * • • • » " ^ • i ,

--«•?! "••J1."" v i » i l -• rv-1

{seies i;

• O < I SHORT

^feaih1

Ziwi ' s t 2\

! PARALLEL PARASITICS i - . •

"j . . . . . Y parftUet

Fig. 37: Y- and Z-matrix components of me OPEN and the SHORT dummy device (C) Copyright 2001 by Franz Sischka, Agilent Technologies, Munich

Looking at Fig. 37, the schematic of the SHORT dummy device, it is clear, how the matrices of the serial and parallel parasitic elements can be determined:

52


parallel elements:

the S-to-Y converted S-parameters of the OPEN dummy give the Y-parameters of the parallel elements.

serial elements:

the Z-parameters of the serial elements can be determined from the SHORT dummy when the Y-parameters of the parallel elements are known and de-embedded.

SHORT DUMMY layout

1

.J ZJ Z]

equivalent circuit R1 L1 L2

°-W—MYT*—|—rrrrrr R2

Rp1

•AAA-o

Rp2

R3

' L3

Sxx

Sxy

. fWCF*„ CE—33

Fig. 38: Modeling the SHORT dummy device, de-embedded from the OPEN (C) Copyright 2001 by Franz Sischka, Agilent Technologies, Munich

53


With this pre-assumption, the de-embedding can be performed following these matrix operations:

De-embed from Open:

• Short/Open " 'Short " 'Open

Convert fo Zs

^Short/Open ~ MT$|,ort/0|Mit}

De-embed from Short: Zour = Z D U T / 0 p o n - Zshoit/Op»n

Convert fo S: S D U T = S(Z D U T )

In a first step, the influence of the parallel parasitic elements is removed from both the SHORT and the device under test (DUT). This is done by subtracting the Y-parameters of the OPEN from the Y-parameters of the SHORT and DUT. In the following step, the resulting Y-parameters are converted to Z-parameters and in this representation, the influence of the serial parasitic elements is removed by subtracting the de-embedded Z-parameters of die SHORT from the de-embedded Z-parameters of the DUT. The resulting Z-parameters of the DUT are then finally converted back to S-parameters.

6.6 Verifying The De-Embedding

Verifying the de-embedding procedure is very important before applying it to the very DUT, i.e. die transistor etc. Wimout this step, errors or problems with the de-embedding will result in distortions of the inner, de-embedded device, and, thus, to a wrong device model. This is especially true when de-embedding the complete Y and Z matrices of the OPEN and SHORT dummy.

Therefore, it is suggested to - model every dummy structure in order to verify its de-embedding prerequisites

and to - verify the de-embedding witii a well-known 'golden device'

before applying it to the modeling DUT.

This means: - After the OPEN and (if available/required) SHORT dummy measurements

have been modeled,

54


- and it is assured that circuit components of the OPEN are all in parallel with the DUT, - and the circuit components of the SHORT can be interpreted as being completely in series

with the DUT, we can check the de-embedding procedure with a known 'golden device'.

In practice, however, the problem is the availability of such a 'golden device'. Provided we have a THRU dummy, we can use this device for a verification of the de-embedding procedure. The idea is that the THRU should look like a simple delay line, with a certain characteristic impedance ZO, and a delay time TD. Additionally, the delay line can be lossy. In any case, the model parameters must represent physical meaningful values, and the de-embedded trace must be simple without resonances etc. Just a simple delay line! Fig. 39 depicts such a dummy device layout, the measurement and the simple model.

THRU DUMMY

Fig. 39: measurement result and model of a THRU dummy, de-embedded from both, the OPEN and SHORT (with the SHORT itself de-embeded from the OPEN).


6.7 Over- And Under-De-Embedding

If under-de-embedding occurred, i.e. we de-embed 'not enough parasitics', the traces of the de-embedded device will not be 'turned back' sufficiently, se Fig. 40. The de-embedding error will add up to the inner device and make its model useless. Unfortunately, this effect is usually not directly visible from inspections of the data.

55


The better recognizable effect, however, is over-de-embedding. If this happens, the de-embedded DUT curves will 'turn backwards' for higher frequencies or show some other non-physical effects. They may even turn outside the Smith chart!

un-deembedded DUT deembedded DUT

under deembedded

correctly deembedded

over deembedded

Fig. 40: under and over de-embedding effect (C) Copyright 2001 by Franz Sischka, Agilent Technologies, Munich

7 Checking RF Measurement Data Consistency

For a successful device modeling, it is very important to check the RF measurement results before proceeding with the parameter extraction. Without going into the details, here some checkpoints:

> Check for the DC bias losses due to the resistors in the bias TEEs. > check the contact resistance of the RF probes to the aluminum pads on the wafer. > check the RF-signal power if it is low enough for measuring linear S-parameters. > DC bias currents from S-parameters measurements must match the DC curves,

otherwise either self-heating, too much RF-signal, or oscillation etc. may have occurred.

> compare S-parameters (by Y-matrix conversion) against the CV curves. > every de-embedding step must make the signal look more ideal. > check if there are enough DC bias conditions available for transit time modeling.

56


8 Test Structures For MOS Transistors

This paragraph gives some information about the physical layout of:

• high frequency transistors as used in integrated CMOS circuits • test structures to measure these transistors • dummy structures to eliminate the influence of the parasitic pads from the real

transistor behavior

8.1 Pad Layout Suggestions For A Uniform DC And S-Parameter Test Stucture

Fig. 41 gives and idea, how a uniform transistor layout could look like to cover both, high-resolution DC current and also S-parameter measurements.

Source and Bulk are shorted by the probes!

S-par Fig. 41: Uniform layout suggestion for DC and S-parameter measurements of transistors


For DC measurements, a low-current resolution is required down to sub-pico-Amperes. This can best be achieved using special shielded DC needles, and connecting these needles directly to the DC analyzer.

It is not recommended to measure DC through the S-parameter testset of the network analyzer.

For S-parameter measurements, a good grounding is essential, and ground loops must be avoided. Therefore, the Bulk and Substrate contacts are reliably connected to Ground when the GSG probes (Ground-Signal-Ground) are connected to the above layout.

57


If an individual DC bias is required for the Bulk or Substrate contact, it is recommended to use GS probes (Ground-Signal), and to use a 3rd GS probe to bias the 3rd DC contact.

Using a 3rd GS probe for the DC contact and not a DC needle reduces possible device oscillation considerably.

to Bulk SMU

S-par with individual DC bias

Fig. 42: Layout suggestion for S-parameter measurements and individual DC bias for Bulk or Substrate, using Ground-Signal probes.


NOTE: the distance between the centers of the pads is called pitch. Typical pitches for on-wafer transistor modeling is about or below lOOum.

8.2 Layout For High Frequency MOS Transistors

Depending on the target application, there are different layout schemes possible for RF MOS transistors [20]. These layouts depend on the application in RF circuits. Fig. 43 depicts three basic possibilities for a layout of such devices.

58


RF transistorl design

Top view Device geometry

one single

transistor gate d ra in

3 d ra in

I gate, p-Si

source 0 v ia

metal

1 Gate 1 Drain 1 Source

n parallel

transistors gate

idrain H source O via

• gate, p-Si CZ~~J> metal

3 Gates 3 Drains 3 Sources

multi finger

transistors

gate

o

o ^1

^^^Bmm •2 drain

I gate, p-Si

I s o u r c e Q via

„ metal

6 Gates 3 Drains 4 Sources

Fig. 43: Test structures for S-parameter measurements. (C) Copyright 2001 Thomas Gneiting, admos, Frickenhausen, Germany

The use of one of these designs depends on the functionality of the transistor in the designed circuit. However, most designs are using the multi finger transistor approach. It is very compact and because of a minimization of parasitic capacitance due to shared drain/source regions, it provides the best RF performance (e.g. cut-off frequency fT).

A detailed layout of such a multi finger transistor is given in Fig. 44 below. The gate fingers are contacted from both sides to minimize the gate resistance which results in a better high frequency noise behavior.

59


M d r a i n H s o u r c e Q v i a §§ g a t e , p -S i c;— metal

Fig. 44: Layout of a multi finger transistor. (C) Copyright 2001 ThomasGneiting, admos, Frickenhausen, Germany

Test devices should be designed so that they can drive enough current to get a reasonable gain for the measurement with the network analyzer. E.g. using a 'normal' short device with W/L = 10um/0.5um would result in a small starting value of IS21I = 0.2. Such small RF signal levels can be affected by the measurement noise and therefore become distorted. A multi-finger device with 6 gates, 3 drain and 4 source areas would exhibit a higher gain of about IS21I = 1.0 with much less measurement resolution problems.

Fig. 45 finally depicts a three-dimensional representation of such a multi-finger MOS transistor. It is interesting to note how 'high' the metal planes are relative to the active silicon area and that the size of the transistor itself is very small compared to the size of the pads.

60


Fig. 45: High frequency MOS transistor layout. (C) Copyright 2001 ThomasGneiting, admos, Frickenhausen, Germany

For more information see publication [20].

8.3 Additional dummy structures for de-embedding

The pre requisite for a correct de-embedding is that certain test structures are available on a wafer together with the device under test (DUT) itself. Depending on the selected de-embedding method, an OPEN and SHORT dummy structure is required and must be measured. For the proposed de-embedding verification from above, also a THROUGH dummy structure is necessary. The principle layouts of these structures are given in Figures 46 - 48. These layouts are for Ground-Signal-Ground Probes (GSG).

61

948 F. Sisckka & T. Gneiting

OPEN DUMMY

cal.plane after de-embedding

Fig. 46: Layout of an OPEN dummy structure. (C) Copyright 2001 Thomas Gneiting, admos, Frickenhausen, Germany

SHORT DUMMY


Fig. 47: Layout of a SHORT dummy structure. (C) Copyright 2001 Thomas Gneiting, admos, Frickenhausen, Germany

62


THRU DUMMY


strip line of the THRU which has to be modeled

and what must be representable by a simple SPICE stripline !!

Fig.48: Layout of a THRU dummy structure. (C) Copyright 2001 Thomas Gneiting, admos, Frickenhausen, Germany

9 Conclusions

"The modeling of electronic devices in the Gigahertz range can be troublesome, requiring a lot of guesswork and ad-hoc judgements..."

These statements are certainly true if the device engineer does not have a thorough knowledge about the models he is applying, the effects involved in the RF characterization measurements and if he has not tested and verified the RF measurement conditions.

On the other hand, if he is well aware of

- the features of his measurement equipment (e.g. specifications and instrument calibration),

- the limitations of the applied measurements (e.g. device self-heating due to the applied DC power levels),

- the boundary conditions during characterization (e.g. small RF power levels for network analyzer measurements)

- the performance of the RF test fixture or the on-wafer RF probes (e.g. contact resistance, ground loops etc.)

63


- the quality of his RF dummy structures (e.g. verification using a THRU dummy on the wafer),

- and permanent checking of data consistency (e.g. bias conditions for S-parameter measurements identical to the DC only measurements),

RF device modeling is a very clean and reproducible science.

This chapter attempted to illustrate the main issues of these modeling pre-considerations. During the daily RF modeling work, it was found that once these issues are satisfyingly resolved and the data are consistent and o.k., reliable and accurate device models can be obtained.

In order to make a thorough modeling job, it is clear that the modeling engineer has to know the selected device models. But without a clear picture of the basics, i.e. the underlying measurements and their quality, he might easily end up with phrases like the ones above!

However, and underlining once again, this can be avoided when giving some extra thoughts to the measurement and characterization of the modeling devices.

References

[1] F.Sischka, "Device Modeling and Measurement for RF Systems", VLSI conference proceedings 1999, Lisbon, Kluwer Academics.

[2] F.Sischka, "RF Measurements And Modeling with Special Emphasis on Test Structures", Tutorial Short Course at the ICMTS 2000 Conference, Monterey, CA.

[3] Agilent 4155B/4156B Product Note No. 3: "Prober Connection Guide", Agilent Technologies Literature Number 5966-4185E, 1998

[4] "Ultra Low Current dc Characterization of MOSFETs at the Wafer Level", Agilent Technologies Application Note 4156-1, 1/1998, Lit.Nr. 5963-2014E

[5]..Hiroshi Haruta, "Agilent Technologies Impedance Measurement Handbook", 2nd edition, Agilent Technologies product number 5950-3000

[6] R.W.Anderson, "S-Parameter Techniques for Faster, More Accurate Network Design", Agilent Technologies Application Note 95-1, PN 5952-1130. This is a reprint of the article in the Feb, 1967 Hewlett-Packard Journal, vol.18, no.6

[7] _Understanding the Fundamental Principles of Vector Network Analysis, Agilent Technologies Application Note 1287-1

64


[8] P. van Wijnen, "On the Characterization and Optimization of High-Speed Silicon Bipolar Transistors", PhD Thesis University of Delft, 1992, published 1995 by Cascade Microtech, Inc., Beaverton, Oregon

[9] Paul Schmitz, "Vector Measurements of High Frequency Networks", Hewlett-Packard, Publication HP5958-0387, April 1989

[10] Agilent Technologies Application Notes 1287-1: "Understanding the Fundamental Principles of Vector Network Analyzers", Pub.No. 5965-7710E, 1997

[11] Agilent Technologies Application Notes 1287-2: "Exploring the Architectures of Network Analyzers", Pub.No 5965-7708E, 1997

[12] Agilent Technologies Application Notes 1287-4: "Network Analyzer Measurements: Filter and Amplifier Examples", Pub.No5965-7710E, 1997

[13] "Hewlett-Packard 1997 Back to Basics Seminar", D.Ballo, Network Analyzer Basics, Pub.No. 5965-7917E

[14] Hewlett-Packard Application Note 8510-5A: "Specifying Calibration Standards for the HP8510 Network Analyzer", Publication HP5956-4352, February 1997

[15] Cascade Microtech, "Microwave Wafer Probe Calibration Constants", HP8510 Network Analyzer Input Instruction Manual, 1990

[16] Cascade Microtech Application Note: "On Wafer Vector Network Analyzer Calibration and Measurements", 1997, Pub Name PYRPROBE-0597

[17] Cascade Microtech Application Note: "Layout Rules for GHz Probing", 1992, Pub.Name LAYOUT19

[18] CascadeMicrotech Technical Brief: "A Guide to Better Vector Network Analyzer Calibrations for Probe-Tip Measurements"

[19] F.Sischka, "IC-CAP Modeling Reference", Agilent Technologies publ.no.85190-90109, May 2000

[20] T. Gneiting, "Documentation of the BSIM3v3 Modeling Package", HP Part No. 85190-90082, October 1998, included in: IC-CAP Modeling Software Documentation, Agilent Technologies Prod.Nr. 85199D

65

http://publ.no.85



MOSFET MODELING AND

PARAMETER EXTRACTION FORRFIC'S

MINKYU JE, ICKJIN KWON, HYUNGCHEOL SHIN, AND KWYRO LEE

Dept. ofEECS, KAIST Also with MICROS Research Center, KAIST

373-1 Kusong, Yusung, Taejon, 305-701, Korea E-mail:krlee@ee. kaist. ac. kr

After reviewing the basic concept and general strategies, we have examined a variety of examples of modeling and parameter extraction methods for RF MOSFET's. Modeling and parameter extraction techniques popular in III-V FET modeling were reviewed and recent efforts to model the RF MOSFET and extract the model parameters were examined in light of the differences between the MOSFET and the III-V FET. A very simple and accurate parameter extraction method studied in our laboratory for three-terminal modeling considering charge conservation is also introduced. Our works have two important implications. One is that the consideration for charge conservation is important not only for accurate device modeling and circuit simulation but even more for proper parameter extraction. Another is that one accurate large-signal /- V model is enough to be used for DC, low-frequency analog, as well as RF circuit simulation. Four-terminal modeling based on new equivalent circuits to address the high-frequency effects arising in a MOSFET is very complicated and not practical for CAD applications, even without considering the substrate coupling terms. As a temporary alternative, the macro-modeling approach is examined with various examples.

1. Introduction

Until recently, most RF circuits and systems have been implemented with either compound semiconductor transistors, such as GaAs MESFETs, HEMTs, HBTs, or silicon BJTs. The microwave properties of silicon MOSFET's were inferior to those of other high-frequency transistors. However, over time the continuous down-scaling of the CMOS technology has made it a candidate for RF applications." As shown in Table 1, the 0.\&-/jm CMOS technology easily available today exhibits nearly 50 GHz offT (cut-off frequency) and fmax (maximum oscillation frequency), and 0.35 dB of NFml„ (minimum noise figure) at 2-GHz operation frequency.5 These figures indicate excellent potential of the current CMOS technology for RF applications operating at several GHz. As the channel length of a MOSFET shrinks to 100 nm, the/?- of the device comes to about 100 GHz.

67

954 M. Je, I. Kwon, H. Shin & K. Lee

Table 1. RF characteristics of n-MOSFET's with decreasing channel lengths.5

Gate Length, L [nm]

MGHz]

fmox [GHZ]

NFmin [dB] @ 2 GHz

250

33

41

0.5

180

49

47

0.35

140

70

51

0.23

120

84

52

0.2

100

112

60

0.15

In addition to its sufficient potential, the CMOS technology is very attractive as an RF technology because CMOS provides such advantages as low cost, high-level integration, and easy access over other technologies. Above all, using the CMOS technology it becomes possible to integrate RF circuits, low-frequency analog circuits, and digital circuits in a single chip, which makes an ultimate one-chip system. This strength of the CMOS technology has resulted in a large amount of research directed toward replacing the conventional high-frequency transistors in RF circuits with RF MOSFET's and integrating the RF front-ends into a single chip.6*

However, differences between the RF MOSFET and conventional high-frequency transistors make the proper modeling of RF MOSFET complicated and difficult and, in turn, prevent the successful development of robust commercial RF circuits using CMOS technology. There are two major differences: one is related to the substrate material and the other arises from the device structure of the MOSFET's. These differences complicate not only the device modeling but also the implementation of the integrated RF CMOS circuits.

1.1. Large and lossy parasitic components due to the semi-conducting rather than semi-insulating nature of the silicon substrate

The MOSFET's are fabricated on a silicon substrate. Silicon is a semi-conducting material rather than a semi-insulating material like gallium-arsenide. As shown in Table 2, the resistivity of silicon is much lower than that of gallium-arsenide, especially for the practical case. Essentially, the intrinsic resistivity of silicon is smaller than that of gallium-arsenide due to more plentiful carriers in the intrinsic condition. Adding to this, in a practical CMOS process, the silicon substrate is typically doped to have the carrier concentration ranging from about 1015

cm3 to about 1018 cm3, which corresponds to the resistivity of 0.01 ~ 10 ohm-cm. The resistivity value of the silicon substrate is closely related to the ease of device fabrication. In the CMOS process, it is not easy to maintain either p-type or n-type substrate in a high resistivity condition.

68

MOSFET Modeling and Parameter Extraction for RF IC's 955

Table 2. Electrical properties of Si and GaAs at 300 °K.

Properties

Dielectric constant

Substrate resistivity

• Ultimate intrinsic resistivity

• Practical resistivity range

Thermal conductivity

Si

11.7

2.3 x 105ohmcm

0.01 ~ 10 ohmcm

\.SW/cm-°C

GaAs

13.1

108 ohmcm

108 ohm-cm

0.46 W/cm-°C

The lower resistivity of the silicon substrate results in larger and lossier parasitics related to the substrate. The performance of the integrated CMOS RF circuits is often dominated by these parasitics, not by intrinsic MOSFET's. The substrate parasitics have an important effect on the characteristics and performance of RF CMOS circuits in several aspects, which can be summarized as follow:

A. On MOSFET's

In RF MOSFET's, the influence of the distributed substrate resistance becomes significant as the operation frequency increases.815 At low frequencies, the impedance of the junction capacitance is so large that the substrate resistance may not be seen from the drain terminal. However, with increasing frequency, the impedance of the junction capacitance reduces and the effects of the substrate resistance start to be seen. At high frequencies, combined with the fact that the MOSFET is a four-terminal device, the signals in RF MOSFET's are coupled through the substrate R-C network in a complex way. The substrate signal coupling mainly affects the small-signal output characteristics, which are important for RF design. This will be discussed in detail in section 3.2.

B. On passive circuit elements

The semi-conducting substrate also affects the performance of the passive circuit elements such as inductors and capacitors, and makes the modeling of the passive elements complicated.1'1-21

Above all, the energy dissipation through the ohmic loss of the silicon substrate significantly degrades the performance of the on-chip inductors, which is one of the most important components for RF IC's."" The lack of an accurate model for on-chip inductors presents one of the most challenging problems for silicon RF IC designers.""

C. On interconnection elements

On lossy substrates, complex signal propagation characteristics are exhibited along the interconnection lines and thus it is much harder to model the interconnection lines on the silicon

69


substrate."24 For the typical resistivity of the silicon substrate, as the operation frequency increases, a transition from the "slow-wave" propagation mode (no electric field in the substrate) to the "dielectric quasi-TEM" propagation mode (electric field in the substrate) occurs. Furthermore, a longitudinal current component is induced in the silicon substrate by the magnetic field.

D. On bonding/probing pads The bonding/probing pads on the silicon substrate constitute considerable parasitics. Most of the loss is associated with the coupling from the signal pads to ground pads that originates from the pad-to-substrate capacitance and the semi-conducting nature of the silicon substrate.25 The S-parameters of the pads have a strong dependence on the substrate resistivity.26 Besides, the substrate carried coupling between the input pad/lead and the output pad/lead is significant.27

All of these parasitics should be carefully considered not only for the actual circuit but also for de-embedding to obtain the accurate characteristics of the intrinsic MOSFET.

E. On signal/noise coupling in mixed-signal IC's As various kinds of circuit blocks are integrated on a single-chip, such as digital, analog, and RF circuitry, the signal and noise coupling between blocks through the semi-conducting substrate becomes an important issue for successful system design.18" For example, the great amount of harmonics in the switching noise generated from the digital block may be coupled to the adjacent RF block whose signal level is very weak, to significantly degrade the signal-to-noise ratio of the system. Thus, an efficient isolation technique preventing the substrate coupling should be devised. Also, accurate substrate coupling models that can be incorporated into the circuit simulator are required for the accurate simulation of the designed circuits.

2.2. Three-port/four-terminal rather than a two-port/three-terminal device

The conventional high-frequency FET's have three terminals: a gate, a source, and a drain. Bipolar transistors are also three-terminal devices, having an emitter, a base, and a collector as their terminals. However, the MOSFET has a fourth terminal, the "body", as shown in Fig. 1. The body is doped opposite to the source/drain regions to isolate these two regions by reverse-biased p-n junctions. For reliable operation of a MOSFET, the body terminal should be connected to a certain terminal with a fixed potential. It is typically connected to ground (the lowest potential used in the circuit) for an n-MOSFET and Vdd (the highest potential used in the circuit) for a p-MOSFET to prevent the source/drain junctions from being forward-biased in any case.

70


Fig. 1. Simplified cross-section of a MOSFET.

The basic concept of FET operation is to control the current flow between the source and the drain by adjusting the voltage applied to the gate terminal. The carriers - electrons for an n-MOSFET and holes for a p-MOSFET - start from the source where they have a higher potential energy and move through the channel region below the gate and sink into the drain where they have a lower potential energy. The number of carriers participating in a current flow is controlled by the field induced from the gate voltage. In a MOSFET, the change in the body potential can also cause the change in the number of channel carriers. This control mechanism by body voltage is very similar to that by gate voltage, although the body voltage is much less efficient than the gate voltage in controlling the current flow. Thus the MOSFET is essentially a four-terminal device.

In many cases, the source and the body of the MOSFET are tied together. Even for this configuration, however, a MOSFET cannot be treated as a three-terminal device because the potential of the intrinsic body node (Fig. 1), which can affect the device operation, is neither the same as the (extrinsic) body terminal nor as the source. With DC excitations, the intrinsic body potential is the same as the extrinsic one, which is also identical to the source terminal. However, with AC excitations, the AC body current becomes significant as the excitation frequency increases. The distributed R-C network composed of the depletion capacitances and the substrate resistances, and the AC current flowing through this R-C network directly coupled from gate, drain, and source terminals make the potentials of the extrinsic body and the intrinsic body different.

It is much more difficult to explain and predict the behavior of the four-terminal device than that of the three-terminal device. A three-terminal device can be treated as a two-port network, where four complex numbers (eight real numbers) are enough to characterize the device. However, nine complex numbers (eighteen real numbers) are required to characterize a four-terminal device. The complexity increase due to this difference is significant. The high-frequency modeling and parameter extraction is even more difficult considering the signal coupling between various terminals through the substrate. In addition, the measurement of the four-terminal device is harder to perform and more time-consuming. Additional DC /-K curves are needed to characterize the effects of the body terminal in DC operation, and, ideally a three-port S-parameter measurement is needed to fully characterize the small-signal behaviors of the four-terminal device at high frequencies in AC operation. However, there is no established

71


measurement technique to perform an on-wafer three-port ^-parameter measurement. Even if three-port measurement is possible, the number of measurement ports is increased and there are many more bias combinations for the AC characteristics to consider; thus the measurement becomes much more time-consuming. As a result, the data handling and the parameter extraction procedure become very complicated.

1.3. Difficulties in CMOS RF modeling/parameter extraction

As discussed above, the modeling and the parameter extraction of RF MOSFET's are different from and more difficult than those of conventional high frequency transistors mainly due to the lossy silicon substrate and the four-terminal device structure of MOSFET's. The difficulties can be summarized as follows:

• A more complicated model with a larger number of parameters is required to describe the behavior of the four-terminal MOSFET. • The parasitic components for both active and passive devices as well as for pads and interconnection lines, originating from the semi-conducting substrate, should be included and the effects of signal coupling through the substrate parasitics should be considered properly. • The lossy silicon substrate causes large parasitics of the probing pads and interconnection lines. Accurate measurement and careful de-embedding of these parasitics should be performed using well-designed de-embedding fixtures to obtain the real characteristics of intrinsic MOSFET's. • An on-wafer three-port S-parameter measurement technique has not yet been well-established, although it is needed to obtain full small-signal characteristics of four-terminal MOSFET's. Until now, the well-established two-port measurement has been used to characterize MOSFET's, which gives insufficient information to model the four-terminal device. • The measurement of three-port/four-terminal devices requires more measurement points and longer time, and produces a large amount of data. • The manipulation of the large amount of data and the extraction of a large number of model parameters are difficult and time-consuming.

Despite these problems, intensive efforts have been spent in the field of MOSFET modeling and parameter extraction, and partial solutions have been exhibited. In the next section, we will introduce basic strategies for RF modeling and parameter extraction of two-port networks. Then, in section 3, various three-terminal models and parameter extraction methods for conventional high-frequency transistors and RF MOSFET's, including the work we performed recently, are extensively described. We briefly comment on four-terminal MOSFET modeling and parameter extraction in section 4, followed by conclusion.

72

MOSFET Modeling and Parameter Extraction for RF IG's 959

2. RF Modeling Approaches and Parameter Extraction Strategies for Two-Port Network

At high frequencies above about 1 GHz, S-parameter measurement is the easiest and the most reliable way to measure the network characteristics of a certain functional block. A great number of models and corresponding parameter extraction methods from S-parameter measurement data have been proposed for various kinds of two-port networks such as passive devices20 and transistors.™1 In this section, we will discuss the concept and useful interpretations of S-parameters in section 2.1; the basics of modeling and parameter extraction in section 2.2; adequate modeling and parameter extraction strategies for linear/reciprocal and nonlinear/nonreciprocal two-port networks in sections 2.3 and 2.4, respectively; and, finally, requirements for RF FET modeling in section 2.5.

2.2. Physical, mathematical, and engineering interpretations of S-parameters for circuit design and measurement

An Alport device can be represented in many ways. At low frequency, this is usually done by Z, Y, or H matrices. This is because it is easier to force or measure terminal voltage (or current) with open (or short) circuit. However, there are many problems with this at high frequency. Firstly, accurate high frequency measuring of voltage or current is very hard. In addition, an active device may oscillate or self-destruct with open or shorted connections. Secondly, the voltage or current depends on the cable length, which is always needed to connect a DUT (device under test) and a measurement system. This is equivalent to saying that they are position dependent along the cable. Thirdly, it is not easy to achieve truly open/short termination at high frequency.

On the other hand, terminating the port with a cable of characteristic impedance ZQ is much easier. Instead of voltage or current, it is physically and mathematically much easier to work with power (or equivalent voltage) waves propagating into and being reflected from or transmitted through the device. Note that this propagating equivalent voltage wave is position invariant along the cable. Moreover, incident power is fully absorbed, or equivalently there is no reflected power, when the cable corresponding to the force/measure port is terminated by Z0. S-parameters, or scattering parameters in an Alport network are defined as the complex reflection coefficients at each port and complex transmission coefficients of the equivalent voltage wave between each pair of ports. An Alport network has A/2 S-parameters, among which N parameters indicate the reflection coefficients and the remaining N2-N parameters, the transmission coefficients."

The S-parameter measurement technique overcomes all of the above drawbacks in characterizing high-frequency networks." The S-parameters relate to familiar measurements such as gain, loss, and the reflection coefficient. The measured S-parameters of multiple devices can be cascaded to predict overall system performance. They are analytically convenient for CAD programs and flow-graph analysis, and mathematically, H, Y, and Z- parameters can be derived from S-parameters when necessary. It should be noted, however, that S-parameters are measured with a particular Z0-system, i.e., 50 O. For example, S2| is the forward gain when terminal 2 is terminated by Z0. This gives insight for a hybrid circuit but not for an integrated

73


circuit, because usually the output impedance for the former is matched to Z0, while it is very far from Z0 for the latter. Thus S2\ can be interpreted as the rough gain of the device only when its input/output impedance level is around ZQ.

2.2. Basic concepts of modeling and parameter extraction

Only when both a proper model and a good set of model parameters are used together, can we obtain accurate and meaningful circuit simulation results. Thus, it is important to develop both a mathematically well-conditioned model to effectively describe the device characteristics and its associated parameter extraction method to find the correct parameter set. The model and the extracted parameter set should be able not only to fit the measured data well but also to predict the correct device behavior under conditions where no measurement is made. Because a correct and efficient parameter extraction is as important as the model itself, we should carefully consider the parameter extraction strategy and method at the same time as when the model is developed.

Prior to discussion of the practical modeling and parameter extraction strategies, we should explain modeling and parameter extraction. Most of the device models have their own equivalent circuits, which consist of resistances, capacitances, inductances, voltage-controlled current sources, and so on. This equivalent circuit, having the proper values for each circuit element, generates the device characteristics, or predictions. The value of each element in the equivalent circuit is determined either by examining the data table for table models or by solving the physical or empirical equations for physical models. The model parameters indicate either the values of elements themselves for the table model or the physical and empirical constants and coefficients that appear in the equations describing the behavior of elements for the physical model.

In the case of the table model, developing the model of a certain device means that we construct the equivalent circuit that can explain the device behavior in the operation region of interest and devise an appropriate interpolation scheme that can give values of elements when the device does not operate at measurement points. Sometimes, the equivalent circuit of the table model may not be physical, but just mathematical and the element values may be just measured 5-parameter values themselves like the Root model.,4*' The set of measurement conditions should be carefully designed to efficiently cover the whole range in which the device operates. On the other hand, in the case of the physical model, modeling implies constructing the equivalent circuit and formulating the suitable equations that are solved for the element values when the device operating conditions are given. When we extract the model parameters of the physical model, we first extract the element values that fit the measurement data under various conditions, and then find the best values of the constants and coefficients in the equations that describe the characteristics of elements in the operation range of interest. Parameter extraction is not needed for some simple physical models because all of the element values can be calculated from the physical equations without extracting the constants and coefficients experimentally if the process parameters and the device geometries are given.

With a physical understanding of the device operation, we can construct the equivalent

74


circuit by choosing and arranging the proper elements. We may further develop the set of equations, each of which describes the behavior of each element. All of the elements and all of the constants and coefficients in the equations must ideally have the corresponding physical origins. However, some of them may be added by empirical experience to enhance the model accuracy. Note that with increasing the number of elements (and/or constants and coefficients), the model accuracy may be improved, but it scarifies the computational efficiency and complicates the parameter extraction. A good model should give satisfactory predictions within the target error tolerance with a minimum number of elements, constants, and coefficients. If the model is physically correct and the model parameters are extracted well, the values of the elements such as resistances, capacitances, and inductances should usually be frequency-independent by definition. However, like the current source, transconductance and conductance with non-quasi-static"M or frequency-dispersion40-" characteristics, some elements may be frequency dependent.

We assume that the S-parameter measurement is made to extract the model parameters and the measurement at one discrete bias-frequency generates A" independent S-parameters. Since S-parameters are complex numbers, each S-parameter has a real part and an imaginary part, or magnitude and phase, ^measurement data is obtained for one set of S-parameter measurement. If we make measurements at / discrete frequency points without changing bias voltages, 1XY measurement data are generated. The parameter extraction is simply the procedure to find the best set of model parameters fitting the measurement data set. In principle, 1XY data points can be exactly fitted using 1XY independent elements. However, the number of the elements in the practical equivalent circuit is usually and should be much less than 2XY, and it is impossible to model all of the detailed physical phenomena. Besides, there always exist measurement errors. Due to these reasons, the model predictions cannot fit the measurement data perfectly. Thus, the best set of parameters does not give an exact fitting of the measurement data but best approximates it with minimum error under certain criteria.

There are various methods to obtain the best set of model parameters and the methods can be classified into three categories: optimization-based approach,'2-" decomposition-based approach,4'-" and direct extraction:4"50

A. Optimization-based approach We assume that the properties of the model are accurately represented with its K

characteristics. Let p = [Pi,P2,- • ;PN]Z RN be the vector of model parameters to be extracted,

y' =LVj'>J;2'''"'>.>v']e RM > ' = 1,2,- -.AT , the vector of model performance of the i-th

characteristics, and zl =[zt',z2',--,zM']e RM , i = \,2,---,K , the vector of measured

performance of the »'-th characteristics. A general device model of the i-th characteristic can be

written as y' = y'{p). Given the known device model y' = y'{p) for all i"s, pointwise error

of the model can be defined as ej'(p) = y]'(p)-zj'{p), i = \,2,---,K, j = \,2,---,M . Given

a set of weights W = [w, vv2>- • -,wM]e RM , i = 1,2,- • ,K, a scalar measure of partial model

75


accuracy is assumed as

under the well-known least squares criterion. The global optimization is to find the parameter vectors p^ e R" that minimize the total error function e(p) given as

e(p) = ie'(p). (2)

Various optimization techniques, such as a gradient-based Levenberg-Marquardt algorithm," a simulated annealing algorithm," and a simulated diffusion algorithm," are used to solve the given optimization problem, like (2). It is generally believed that global optimization is needed to extract the "best" set of parameters to fit the measured performances. However, it is also the most problematic one. The false convergence to a local minimum is frequent if the initial approximations to model parameters are not sufficiently accurate, and substantial computing resources might be needed. This approach cannot provide any intuition to model users.

B. Decomposition-based approach Detailed knowledge of model functions is used to design measurements and transform data in such a way as to make the error functions e'(p) in (1) dependent only on a small subset of model parameters. If the parameter subset for different characteristics were disjoint, K independent regressions could be used instead of the global optimization problem or minimization of (2). Furthermore, simplifications of the model in properly selected parts of the characteristics are typically employed, resulting in reduction of the extraction problem to a sequence of some simple curve fittings. The advantage is a simple and fast extraction (with model simplification). Model users can also get some sense of the relationships between parameter values and generated model characteristics. However, because interactions between characteristics are ignored, quality of total fit suffers. Additional model simplifications reduce accuracy even further.

C. Direct parameter extraction For some simple models with a relatively small number of parameters, an adequate set of parameters can be solved analytically. In many cases, like the decomposition-based approach, the model is simplified and solved to obtain the model parameters in the selected parts of the characteristics. Direct parameter extraction requires that the analytical expressions are formulated for a particular model based on the separation of model parameters and a few selected parts of the characteristics. The extracted results from direct parameter extraction are sensitive to the device models. Obviously, the measurement accuracy of the selected data points must be very high to reduce the extraction errors. The accuracy of the model with directly extracted parameters may not be the "best." In addition, the development cost involved in such an approach is high. However, the extraction procedure is very straightforward and needs very short computation time. The greatest virtue of this approach is to give users a useful intuition

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during the parameter extraction.

In practice, the above three approaches are properly combined according to the features of the model. We can easily find cases where the decomposition-based successive curve fitting method and the direct extraction method are used together. Even if the decomposition-based method and/or direct extraction method are sufficient to extract the parameters, often the global optimization step is followed to enhance the model accuracy.

2.3. Modeling and parameter extraction strategies for a linear/reciprocal two-port network

We will focus on the modeling and parameter extraction strategies for linear/reciprocal two-port networks in this section. Most of the passive devices can be treated as linear networks under normal conditions, or when too high voltage is not applied and too large current doesn't flow through the devices. A linear network doesn't have dependence on the applied bias voltages. On the other hand, a passive device is a reciprocal network because no amplifying activity takes place. Thus, most passive devices are modeled as linear and reciprocal networks in practice. The equivalent circuit of the linear/reciprocal device consists of linear/reciprocal passive elements, such as resistances, inductances, and capacitances. There is no transconductance and no transcapacitance because of the reciprocal characteristics and the passive elements in the equivalent circuit have no or negligible bias dependence because of the linear characteristics. For the linear network, there is no distinction between a small-signal model and a large-signal model. If the model is physically correct and the model parameters are extracted well, the values of the elements should usually be frequency-independent and bias-independent as the ideal resistances, inductances, and capacitances show neither frequency dependence nor bias dependence. In the physical model, the equations should not be functions of bias voltages or operation frequencies but of process parameters and geometric parameters of the passive devices only.

The operation of passive devices is relatively simple although some parasitic components must be considered adequately. In addition, the number of significant technology parameters for passive devices is smaller than those of transistors and technology parameters, including the substrate doping concentration, are much simpler for passive devices than for transistors. As a result, there are only a few elements in the equivalent circuit, and the physical modeling based on equations is relatively easy. In most cases, parameters can be extracted directly or by using very simple curve fitting such as linear regression. For convenience, a simple optimization technique might be used without severe convergence problems.

To characterize a passive device, S-parameter measurements are also made to extract the model parameters and evaluate the model accuracy. Due to the linear characteristics, however, the 5-parameter measurements at only one bias point sweeping the frequency is sufficient. The measurements generate four J-parameters - Sn, Sn, S2\, and S22 - as functions of frequency. Making a distinction between the real part and the imaginary part of each S-parameter, or the magnitude and the phase of each J-parameter, results in eight measured characteristics.

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However, considering that 5,2 and S2i of the reciprocal network have the same value due to reciprocity," the number of independent measurement characteristics reduces to six. These characteristics, or the converted characteristics in the form of//, Y, or Z-parameters, are used to evaluate the model performance and extract parameters.

As an example of passive device modeling and parameter extraction, we will briefly review the model and parameter extraction method for silicon on-chip spiral inductors presented in a paper by Yue and Wong:'8

Example. Modeling and parameter extraction for a silicon on-chip spiral inductor."

4"Bfc :

M S -M4--

¥2 • M2

(a) Layout of a square-type spiral inductor.

:S m m m ; i-V3

L Oxide

Silicon substrate B

(b) Cross-section along A-B.

Fig. 2. Layout and cross-section of a typical on-chip spiral inductor.

The on-chip inductors are fabricated using a microstrip transmission line wound in a spiral. In addition to the rectangular geometry as shown in Fig. 2, octagonal and circular geometries are also widely used to implement microstrip spiral inductors. Figure 2(b) shows a cross-sectional view of the square-type spiral inductor. Multiple metal layers are often stacked and connected together through via to reduce the ohmic loss resulting from the resistivity of the metal line. A metal layer passing under the spiral is used to access the inner port (point B in Fig. 2(a)) of the inductor. Note that a lower-level metal (Ml) is not used in Fig. 2. By including Ml,

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we can decrease the coupling to the lossy substrate, which significantly degrades the inductor performance at high frequencies.

Although the inductor is a device intended for storing magnetic field energy, inevitably parasitic resistances dissipate energy through ohmic loss, lowering the inductor quality factor Q appreciably. In addition, the parasitic capacitance limits the operating frequency of the integrated inductor drastically. Since these counter-productive parasitics limit the inductor performance, it is very important to include and model them accurately, as well as to predict the inductance value correctly. The physical model of a spiral inductor on silicon is v ~g. 3. The inductance and resistance of the spiral and underpass are represented oy aie series inductance, Ls, and the series resistance, Rs, respectively. The overlap between the spiral and the underpass allows direct capacitive coupling between the two terminals of the inductor. This feed-through path is modeled by the series capacitance, Cs. The oxide capacitance between the spiral and the silicon substrate is modeled by COT. The capacitance and resistance of the silicon substrate are modeled by C$i and Rsi-

1c c£ ..

Fig. 3. The lumped physical model of a spiral inductor on silicon."

Ls can be calculated as a sum of all the self and mutual inductances. The self inductance of a line with a rectangular cross-section and the mutual inductance between two parallel lines can be calculated from geometric parameters of lines using adequate formulas summarized by Graver." Based on Graver's formulas, Greenhouse developed an algorithm for computing the inductance of planar rectangular spirals." The Greenhouse method states that the overall inductance of a spiral can be computed by summing the self inductance of each wire segment and the positive and negative mutual inductance between all possible line segment pairs.

When a conductor is subjected to a time-varying magnetic field, the eddy current effect occurs. Eddy currents manifest themselves as skin and proximity effects. In the case of the skin effect, the time-varying field due to the current flow in a conductor induces eddy currents in the conductor itself. The proximity effect takes place when a conductor is under the influence of a time-varying field produced by a nearby conductor carrying a time-varying current. The skin-effect eddy current and the proximity-effect eddy current superimpose to form the total eddy current distribution. Regardless of the induction mechanism, eddy currents reduce the net current flow in the conductor and hence increase the AC resistance. The series resistance of each line segment caused by the skin effect can be expressed as

79


W-ttf (3)

where p, /, and w represent the resistivity, the length, and the width of the line, respectively, t^ denotes the effective thickness of the line and is defined as

teff=S-(\-e-"5) (4)

where t is the thickness of the line and 5 is the skin depth, which is a function of frequency. Thus, in fact, Rs depends upon frequency. Despite that the skin effect is more severe than the proximity effect in typical cases, if we want to include the resistance resulting from the proximity effect, it can be computed using a numerical electromagnetic field solver and added XoRs.

Based on the inductor's structure, both the crosstalk between adjacent turns and the overlap between the spiral and underpass contribute to Cs. However, since the adjacent turns are almost equipotential, the effect of the crosstalk capacitance is negligible. Therefore, for most practical inductors, it is sufficient to model Cs as the sum of all overlap capacitances, which is equal to

..2 S„

Cs=n-w< ^ — (5) t0x,M2-M3

where n is the number of overlaps and taxMi-Mi is the oxide thickness between the spiral and the underpass. eox denotes the oxide permittivity.

In this model, a MOS microstrip structure is modeled by a three-element network comprised of CM, Rs,, and CSi. Cox represents the oxide capacitance, whereas RSi and Q, represent the silicon substrate resistance and capacitance, respectively. The physical origin of RSi is the silicon conductivity, which is predominately determined by the majority carrier concentration. CSi models the high-frequency capacitive effects occurring in the semiconductor and its value increases with frequency. The substrate capacitance and resistance are approximately proportional to the area occupied by the inductor and can be approximated by

Cox=yl-W^, (6)

CSi=\-l-wCsub, (7)

and

Rsi=, 2r (8)

'•W-Gsub

where Csub and Gsub are capacitance and conductance per unit area for the silicon substrate. The factor of two accounts for the fact that the substrate parasitics are assumed to be distributed equally at the two ends of the inductor. Csub and Gsub are functions of the substrate doping and are extracted from measurement results using a simple optimization technique.

With all the extracted parameter values, the small-signal characteristics of the equivalent circuit can be simulated using a CAD tool such as SPICE, and then compared to the measured results. For inductors, the quality factor calculated from the 5-parameters should also be

80


verified to validate the developed model and parameter extraction procedure. The on-chip spiral inductor on the silicon substrate is one of the most complicated passive devices. We should consider and model the electromagnetic phenomena dominating the device operation correctly. We have reviewed an example" for this topic. The equivalent circuit composed of elements having their own physical origins was developed and the parameter values were extracted using several equations, a simple optimization, and a numerical solver, if it were needed.

2.4. Modeling and parameter extraction strategies for a nonlinear/nonreciprocal two-port FET

Conventional RF FET's have been modeled as nonlinear/nonreciprocal two-port networks. The characteristics of FETs exhibit strong dependence on bias as it is intended to: for example, as the gate voltage increases and comes to exceed a certain threshold value, significant current starts to run through the channel. Thus, a FET is a nonlinear network and both a small-signal model and a large-signal model are needed to completely describe the device operation. The most important aspects of the FET features are amplification and switching operation. The amplification occurring in the FET implies that the FET must be a nonreciprocal network and thus needs transconductances and transcapacitances in its small-signal equivalent circuit. The transconductance represents the amplifying activity itself and the transcapacitance represents the phenomenon where the charge between two given nodes in the active device is controlled not only by the voltages across the two nodes but also by the voltages applied at other nodes, which is unlike the operation of a passive capacitor such as a simple parallel plate capacitor. The transcapacitance is indispensable in guaranteeing charge conservation, especially when the transient behavior of the FET is simulated.57*0 More about this will be discussed in 3-1.

The device physics of FETs is not simple and a large number of process parameters and geometric parameters affect the operation. The equivalent circuit requires numeruous elements to describe the device behavior accurately and it is hard to develop equation-based physical models that provide sufficiently accurate predictions. Usually, the equations are augmented by several empirical constants or functional terms. Furthermore, for high-frequency application of the FET model, phenomena such as non-quasi-static effects and frequency dispersion effects must be modeled correctly. The modeling of these effects results in frequency-dependent elements" "•" in the frequency domain description, or equivalently, elements with delayed response in the time domain description. The amount of the delay is often represented by a time constant"" or numerically determined by solving partial differential equations."

For most of the conventional RF FET models, the S-parameters are measured sweeping frequency and used to extract small-signal parameters. Since the FET has bias dependence, the S-parameter measurements are made at a set of bias points that effectively covers the operation region of interest and parameters are extracted at each bias point. The S-parameter measurements at each bias point generate four S-parameter characteristics - S,u S\2, S2I, and S22

- varying with frequency. No pair of these characteristics is identical when the device is on and operates in an active mode, while S,2 and S2, coincides when the device is off and passive.

The elements in the equivalent circuit can be divided into two groups: the extrinsic parasitic

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elements and the intrinsic ones. The extrinsic elements are not related to the intrinsic FET operation, whereas the intrinsic elements represent the active operation of the intrinsic FET. For example, the interconnection parasitics and overlap capacitances are the extrinsic elements and the transconductance and gate capacitances are intrinsic ones. The different nature of the extrinsic elements and the intrinsic elements is often used to extract parameters more easily. The extrinsic elements have no or negligible bias dependence while the intrinsic elements have strong bias dependence. Taking advantage of this difference, it is common practice to apply zero drain bias to the FET,6' where the behavior of the intrinsic FET is much simpler. This cold-FET method reduces the number of elements and the values of the remaining extrinsic elements can be extracted without difficulties. With the values of the extrinsic elements determined, then parameters related to the intrinsic FET are extracted to complete the parameter extraction. When the parameter values at an arbitrary bias point are needed during a simulation, the values are obtained using proper interpolation functions such as a polynomial function or a spline function. Also an interpolation function connecting the small-signal measurement data points is integrated to generate the large-signal parameters." Although a lot of parameters are extracted from the S-parameters, sometimes DC I-V characteristics are also measured to extract the DC-related parameters."

Until recently, somewhat different approaches have been applied to model MOSFET's and to extract MOSFET parameters until recently. This is because the MOSFET is a four-terminal, or three-port device and thus the approach used for the III-V FET could not be effective, on one hand, and because the high-frequency characteristics have not been as important for MOSFET's as for III-V FET's, on the other hand. It was only a few years ago that the high-frequency modeling of the MOSFET began to generate extensive interest. The modeling of MOSFET's has been mainly focused on the DC I-V and low-frequency C-V characteristics, and thus most MOSFET models are based on complicated large-signal equations describing the drain current and charge at each terminal - gate, drain, source, and body - as functions of terminal voltages.63

While the equations stem from the MOSFET device physics basically, many empirical constants, coefficients, and functional terms enhance the performance of the model equations. Typically, the DC I-V and low-frequency C-V characteristics are measured and a fairly complex extraction sequence follows to obtain reasonably good fitting to the measurement data. The extraction routine consists of decomposition-based extraction steps followed by global optimization steps with multiple targets to refine the model performance.6* Recently, as the high-frequency modeling of MOSFET's attracts growing interest, new approaches are being applied to MOSFET modeling and parameter extraction.

In this section we have discussed the basic strategies of modeling and parameter extraction for FET's. We will review actual examples to make the concepts more tangible in sections 3 and 4, with emphasis on the modeling and parameter extraction of RF MOSFET's, or new approaches. Before examining the modeling examples, the requirements for successful RF FET modeling will be discussed to elucidate RF FET modeling.

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2.5. Requirements for RF FET modeling

The requirements for RF FET modeling should be considered from several points of view: Which measurement method is the most reliable at high frequencies? What performances are important and should be predicted accurately in RF circuit and system design? What conditions should be satisfied to guarantee a robust and efficient circuit simulation?

As mentioned previously, S-parameter measurements are the only practical method to characterize the high-frequency performance of devices, circuits, and systems. Thus a RF model and its parameter extraction scheme had better be based on a small-signal model because the S-parameter measurement is a small-signal measurement. Note that by the S-parameter measurement one obtains / ' (= dl/dV) and C (= dQ/dV) at the frequencies of interest. Making an accurate measurement and using the results for parameter extraction is desirable for successful modeling without doubt.

Table 3. Required quantities for RF circuit design.

LNA

• Bias ( / ) • Gain(/', C) • Linearity (I",I'",C) • Thermal noise

Mixer

• Bias(/) • Conversion gain (7",C)

• Linearity

( / " " , C )

Oscillator

• Bias (7)

• Oscillation frequency

( / \ C ) • Oscillation amplitude ( / " , / " ' , £ ) • Phase noise (///"noise)

Power Amp.

• Bias (I) • Gain(/', C)

• Linearity (I'",C)

Table 3 shows the list of quantities that a successful RF FET model must predict accurately for the important building blocks of RF systems, which indicates that RF models should be able to simulate /, /', /", and / '" very accurately. This is an extremely challenging task. Compared with low frequency analog circuits, a RF system requires much better accuracy of higher harmonics. Besides, the most efficient RF simulation is based on harmonic balance. Thus RF circuit simulation needs much higher-order continuity to improve numerical accuracy as well as simulation convergence speed. It can be easily inferred that starting from / ' modeling/extraction with the help of S-parameter measurement and then constructing /, /", and / '" is a more efficient way than starting from modeling and extraction of / itself. Because / should be uniquely determined for a given Vgs, Vds bias condition, where Vgs is the gate-to-source voltage and V& is the drain-to-source voltage, respectively, all of the / ' are not independent. Similarly, we measure C (=Q") first then extract parameters and construct Q. As all / ' are not independent, so are Q', such that Q is uniquely determined at a given bias condition. This is needed for charge conservation.

One of the very important requirements for FET modeling and parameter extraction is that charge conservation is absolutely required for accuracy and simulation convergence. To accomplish this, we should model the current and charge of FET's as path-independent

83


quantities.57 In other words, after controlling voltages are allowed to vary and then return to their original values, the values of the current and charge should remain unchanged regardless of the variation history. Details on the charge conservation will be discussed in the next section.

3. Three-Terminal RF MOSFET Modeling and Parameter Extraction Examples

As mentioned in 1.2, a MOSFET is a four-terminal device rather than a three-terminal device, unlike other RF FET's. In spite of this fact, in many works, the MOSFET has been modeled as a three-terminal device in the RF range. A three-terminal modeling approach makes the problem quite simple and there are good solutions to this simplified problem devised for conventional III-V FET's already. One wants to use the well-established RF modeling and parameter extraction methods for the conventional III-V FET's. The source and the body terminals of a MOSFET are tied together in many applications, and the MOSFET configured in this way can be handled as a three-terminal device without large errors. In this section, we will examine and discuss the three-terminal modeling approach of RF MOSFET's after the III-V FET modeling/parameter extraction techniques are introduced.

3.1. Brief review of small- and large-signal modeling and parameter extraction techniques for III-V FET's

The differences between III-V FET models and MOSFET models result from the fact that III-V FET's were originally modeled for high-frequency applications whereas in the past MOSFET models were intended to simulate digital circuits and low-frequency analog circuits. Thus, in studies on III-V FET modeling/parameter extraction, high-frequency modeling issues such as de-embedding of pads and interconnection parasitics, non-quasi-static effects, and nonlinear characteristics including high-order harmonics have been intensively addressed for a long time. Many techniques were developed to address the high-frequency modeling and parameter extraction problems efficiently, and unique features of III-V models were formed during the process.

For MOSFET's, physical models that describe the device behavior with a set of equations have mostly been based on large-signal model. This is because it provides the necessary accuracy as well as computation efficiency required by the digital and low-frequency analog VLSI. In contrast to this, it is not difficult to find table models for III-V FET's containing a collection of small-signal measurement data for later retrieval. Actually, the Root model, one of the most widely accepted III-V FET models, is a table-model. There are several reasons why the table models have been applied to III-V FET circuit simulation extensively. The table model can provide quite accurate predictions required for high frequency circuit design without a complete understanding of the physical mechanisms of problematic issues such as non-quasi-static effect, nonlinear characteristics, and frequency dispersion effect, especially for III-V FET's. This is possible because the table model is basically based on measurement; thus, if measurements are made carefully and proper data handling is guaranteed, relatively accurate modeling results can be obtained.

84


Another reason to use table models for III-V FET's is that in many cases, the simulation of RF circuits with III-V FET's has been performed using a harmonic balance simulator, which simulates the circuit performance in the frequency-domain. This harmonic balance simulation is most efficient in simulating circuits including components that have frequency-dependent characteristics. The modeling approach using a set of data measured varying frequency is a very natural one considering the harmonic balance simulation. The other type of circuit simulators are time-domain circuit simulation programs such as SPICE, which has been very popular for MOSFET circuit simulations. For this type of simulation, equation-based physical modeling is a natural approach because the equations can give the current value at each branch as a function of node voltages varying with times. There also exist several III-V FET models for the time-domain simulation such as the Curtice model," the Staz model,66 the Materka model,6' and TriQuint's own model (TOM),68 all of which are based on physical and empirical equations. Popular models for MOSFET's include the BSIM3v3 model,6' the MOS Model 9,6' and the Enz-Krummenacher-Vittoz (EKV) model.™

Although table models can provide accurate results for high-frequency circuit simulation, they have problems and shortcomings. In table models, interpolation functions are used to generate continuous data at points between measurement data points. The continuity of the measured characteristics is guaranteed by using interpolation, but the first-order and higher-order derivatives of the characteristics might not be continuous if a proper interpolation function is not chosen. Discontinuities increase the time to converge and even make the simulation fail to converge. Furthermore, because the measurements always contain some errors, the numerical integration of the measured data to find the current or charge values might cause a charge non-conservation problem. However, the most important disadvantage of the table model is that the model is not predictive. This is simply because the table model is not based on device physics. The table model is only valid for devices under the same conditions as the device on which actual measurements were made. Performance of devices with different dimensions or technology parameters cannot be predicted effectively. Thus, all devices with different dimensions used in the circuit should be measured and it is practically impossible to analyze the yield of IC's accounting for process variations.

We will now examine examples of RF III-V FET models and parameter extraction methods. The conventional small-signal equivalent circuit for III-V FET and its well-known parameter-extraction method will be introduced, and the principles of nonlinear active device modeling studied by Root and Hughes will be reviewed with a resulting physical/empirical model topology.

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6 o - ' r n

Fig. 4. Conventional small-signal equivalent circuit of a 1H-V FET.

The conventional small-signal equivalent circuit of a III-V FET is shown in Fig. 4. Dambrine, Cappy, Heliodore, and Playez have suggested an efficient method to determine the parameters of this equivalent circuit directly from the measured 5-parameters." Basically, this equivalent circuit can be divided into two parts:

• the intrinsic elements, gm, gjs, Cgs, Cg<t, C(ts, Rh and r, which are functions of the biasing conditions; • the extrinsic elements, Lg, Rg, Cra, Ls, Rs, Rd, C^, and Llt, which are independent of the biasing conditions.

First, they determine the extrinsic elements from the measurement data at special conditions (at cold-FET) and de-embed the extrinsic elements to obtain the K-matrix of the intrinsic device only. Then, from the K-matrix, the intrinsic element values are extracted. A more detailed account of the procedure is as follows.

A. Determination of the series parasitic elements The S-parameter measurements at zero drain bias voltage can be used for the evaluation of

device parasitics because the equivalent circuit is much simpler. Figure 5 represents the equivalent circuit when zero drain bias is applied. Rc is the channel resistance under the gate and Zdy = Rdy // Cdy is the distributed equivalent impedance of the Schottky barrier. As the gate current increases with increasing gate voltage, Rdy decreases and Cdy increases, but the exponential behavior of Rdy versus Vgs is the dominant factor. Consequently, for a sufficiently large gate current, the capacitive effect of the gate disappears and Zdy comes close to Rdy, which can be written as

nkT Zdy » Rdy =

1'* (9)

where n is the ideality factor, k the Boltzmann constant, T the temperature, and /„ the DC gate

86


current. In addition, the influence of the CK and Cpd parasitic capacitances is negligible and consequently the extrinsic Z-parameters are simply determined by adding the parasitic resistances Rs, Rg, Rd and inductances Lg, Ls, Ld to the intrinsic Z-parameters. In this bias condition, the Z-parameters of a cold FET are expressed as

Zu=R,+Rt+^. + ^ . + j<0(L,+Lg)

Rr nkT . . Z12 =Z2I =RS + -*- + —+ JQ>LS

2 ql,

Z22=Rs+Rd+Rc+ja)(Ls+Ld)

(10)

(ID

(12)

|-r,nr>-^vw-r

Fig. 5. Small-signal equivalent circuit of a cold FET.71

The series parasitic elements can be extracted using these expressions. Ls can be extracted from Im(Zl2), Lg from Im(Zn), and Ld from In^Z^). In addition, the linear extrapolation of the plot Re(Zn) versus \llg to the ordinate gives the value of Rs + Rg + RJ3. Therefore the Z-parameters' real parts provide three relations between the four unknowns, R„ Rg, Rd, and Rc. At this step, an additional relation is needed to separate the four unknowns. This additional relation can be the value of the sum Rs + Rd determined by the conventional method using the real part of Z22 and the concept of channel opening factor," the value of Rg provided from the resistance measurement, the values of Rs and Rd provided by DC measurement, or the value of Rc if the channel technological parameters are known. Therefore, the determination of the four parameters, Rs, Rg, Rd, and Rc, does not constitute a real problem since some redundant relations are available in most cases.

87

974 M. Je, I. Kwon, Hr Shin & K. Lee

B. Determination of the shunt parasitic elements

Intrinsic device

Fig. 6. Small-signal equivalent circuit of a cold FET at gate voltage lower than the pinch off voltage.71

At zero drain bias and for a gate voltage lower than the pinch-off voltage Vp, the intrinsic capacitance (i.e., under the gate) cancels, as does the channel conductance. Under these biasing conditions, the FET equivalent circuit is shown in Fig. 6. In this figure, Cb represents the fringing capacitance due to the depleted layer extension at each side of the gate. For frequencies up to a few giga-hertz, the resistances and inductances have no influence on the imaginary part of the /-parameters, which can be written

lm{Yu) = MCpg+2Cb) (13)

Im(yI2) = Im(y2I) = -yfflCA (14)

Im(y22) = yo»(C/x/+CA). (15)

Thus, the three unknowns, Ch, Cpg, and C^, can be calculated using (13)—(15).

C. Determination of the intrinsic Y-matrix The remaining problem is to determine the y-matrix of the intrinsic device from experimental data. When all the extrinsic elements are known through the previous steps A and B, the following procedure can be used to solve this problem:

(a) transformation of the as-measured S-parameters to impedance (Z) parameters and subtraction of Lg and L,t that are series elements; (b) transformation of Z to /-parameters and subtraction of Cpg and C^ that are in parallel; (c) transformation of Yto Z-parameters and subtraction of Rg, Rs, Ls, Rd that are in series; (d) transformation of Zto y-parameters that correspond to the desired matrix.

Therefore, the determination of the intrinsic admittance matrix can be carried out using some simple matrix manipulations with the known values of extrinsic elements.

88


D. Extraction of the intrinsic elements

Since the intrinsic device exhibits a n topology, it is convenient to use the admittance (Y) parameters to characterize its electrical properties. These parameters are

a>2R<Cj (C \ ' (16) Yu= l-S—rja

11 D

Cgs • r

V u J

Yl2=-jcoCgd (17)

X21= i+mcgs -J(oC*d (18)

Y22=gds+J<»(Cds+Cgd) (19)

with

D = l + a>2Cgs2/?,2.

For a typical device, the term o^C^R? is less than 0.01 at low frequency (< 5 GHz) and D = 1 constitutes a good approximation. In addition, assuming CDT« 1, we have

r n = « 2 * , . C g J2 + M C g s + C g r f ) (20)

Yl2=-jwCgd (21)

>2i = *« - M e * + g,„ (*,Cgs + r)) (22)

1 ' ! ! = ? . + > ( C A + C j l / ) . (23)

Expressions (20)-(23) show that the intrinsic small-signal elements can be deduced from the Y-parameters as follows: Cgli from Yn, Cgs and /J, from Yu,gm and rfrom Y2X, and lastly, gds and Crfs from y22-

Through steps A to A all the elements of the FET shown in Fig. 4 are extracted in a direct manner. This method is now well known and has been widely used to extract small-signal parameters of III-V FET's with or without modifications. The extraction of small-signal model parameters is used in the generation and verification of large signal models. The equivalent circuit and parameter extraction procedure introduced above are only for small-signal modeling. For obtaining the corresponding large-signal model, additional large-signal model construction method should be devised. However, as the equivalent circuit in Fig. 4 does not contain a complete set of intrinsic capacitances for charge conservation, we cannot build a successful large-signal model guaranteeing the charge conservation from this small-signal model. Note that in this work, all the parasitics including Cw and Cpj are extracted without using separate test fixtures. However, it is also common practice to determine and de-embed pad parasitic elements using separate patterns: open and short patterns for the two-step method," and open, short, and thru patterns for the three-step method."

Root and Hughes are the pioneers who addressed the possible problems of equivalent circuits such as that shown in Fig. 4 and presented the principles of nonlinear active device modeling for circuit simulation in SPICE and harmonic balance programs, motivated by an examination of three common problems of standard nonlinear GaAs MESFET models." Here

89


we will focus on the first and second problems and their solutions, which introduce the concepts of a voltage controlled charge source (VCQS) and a transcapacitance. These concepts are so important that we review the original ideas of Root and Hughes here.

The first problem is that simulations done in large-signal analysis don't fit the measured imaginary parts of the v-parameters versus bias. On the other hand, good fits to the measurements can be obtained in linear (small-signal) analysis. The solution is to use nonlinear VCQS elements in place of two-terminal capacitors in the nonlinear model. A VCQS is a reactive analogue of the familiar voltage controlled current source. This improves the accuracy and convergence properties of the large signal reactive FET model. Linearizing the resulting equations produces an accurate small-signal model, consistent with the large-signal simulations in the appropriate limit. Linearizing a VCQS element produces another unfamiliar quantity, the transcapacitance. A transcapacitance is a reactive analogue of a transconductance.

G O

SO ( ^ OD

I*

Fig. 7. Voltage controlled current source element.

The nodal equations solved by SPICE in transient (large-signal) analysis are given in (24). There are similar equations, written in the frequency domain, which characterize the harmonic balance based circuit simulators." It is possible in principle to formulate active device models starting directly from the quantities of (24). However, it is often much easier to begin from basic nonlinear elements, and use them as building blocks to construct full models.76

Ii{V\{t\--;VN{t)) + -Qi{V,(t),--;VN{t)) = Q, i = \,--,N where N = number of nodes. (24) at

Corresponding to each of the terms of the left hand side of (24), there is a nonlinear branch element which we consider. The first is a familiar element, the voltage controlled current source (VCCS). It defines a branch current as a nonlinear function of one or more controlling voltages. A schematic of a three-terminal VCCS element is given in Fig. 7. This example can be considered the most elementary nonlinear model of a FET. The model drain-source current Ids

depends on the gate-source voltage Vgs as well as the drain-source voltage Vds.

Ifi'UiVr'V*) (25)

A nonlinear element related to the second term on the left hand side of (24) is the VCQS. It is a multi-terminal reactive analogue of a VCCS. The VCQS defines a branch charge as a nonlinear function of one or more controlling voltages. The branch current is defined to be the total time derivative of the charge. A schematic of a three-terminal VCQS element is given in Fig. 8. The charge associated with the gate-source branch Qgs depends on the gate-source voltage Vgs and also on the drain-source voltage V^ as given in (26). This is a generalization of

90


the familiar two-terminal capacitor, where the charge associated with a branch depends only on the single voltage difference across the element. The branch current of a VCQS element is defined, in (27), by the total time derivative of the charge. The associated reference direction for current to flow is chosen to be from the positive to the negative sign of the symbol in Fig. 8. Notice that the gate-source branch current of this element has a term proportional to the time derivative of the drain-source voltage. The coefficient of proportionality cQsJdVds is a'so a function of Vgs and Vds. This is called a transcapacitance Cm, which is a reactive analogue of the transconductance.

Qgs=Qgs(vgs,vds)

jVCQS = d_Q _ ' gs - i. « g s

dQgs dVgs dQg* dVds

df

= c„

dv„ dt dvH, dt

dt

gs

•+c„ dKis dt

(26)

(27)

G Q

o„©

SO OD

Fig. 8. Voltage controlled charge source element.

The model current /rfs of the VCCS nonlinear element of Fig. 7 is plotted versus the two controlling bias voltages Vgs and Vds in Fig. 9. Ids describes a two-dimensional surface. The slope of the Ids surface in the direction parallel to the Vgs axis defines the model transconductance gm(Vgs, V&). The slope of this surface in the direction parallel to the V^ axis defines the model conductance gds(Vgs> V<b)- These relations are given in (28) and (29). The model current, conductance, and transconductance depend only on the controlling voltages, with no explicit time or frequency dependence.

gm(Vgs>Yds) = -dI"s

BV. (28)

gs

gds(Vgs,V*) = 2Lt dV,

(29) ds

91


Fig. 9. Model current /* vs. two controlling bias voltages V& and V&.

Taking the partial derivative of (28) with respect to Vds, and noting 82L dlL

w*wv dV0,dV, gsurds

we obtain a relationship between the model conductance and model transconductance given in (30). A mathematically equivalent statement (derived using Stokes's Theorem) is given by (31). The indicated contour is any closed loop on the surface defining the model current Jds.

5K„, dV„

< j k Wv. V* )dVgs + gds (Vgs, Vds )dVds ]= 0

(30)

(31)

A key consequence of (30) and (31) is that the model conductance gaJi,Vgs, Vds) and the model transconductance gm(Vg$, Krfs) are not independent functions of bias! Extraction of model gm and gds separately versus bias, which is standard practice in linear analysis, can result in a path-dependent model Ids. That is, the right hand side of (31) may be different from zero.

A nonzero result for the right hand side of (31) represents the net (positive or negative) current supplied by the VCCS to the circuit after its controlling voltages are allowed to vary and then return to their original values. This is not a problem in small-signal analysis, where the bias point remains fixed, but it is extremely dangerous in large-signal analysis. Disaster can result in large-signal simulations even if the right hand side of (31) is only slightly different from zero. Under the conditions of large signal periodic input waveforms, the FET model controlling voltages can traverse closed loops in voltage space at the rate of billions of times a second (at microwave frequencies). The error (excess current) generated with each loop traversal accumulates, ultimately becoming large enough to cause the simulation to crash, or else cause a spurious result, such as a runaway voltage on a capacitor plate elsewhere in the circuit. The two properties of path independence and time (frequency) independence of current modeled by VCCS element are hallmarks of a network variable.

Exactly the same considerations apply to the network variable charge as applied to the network variable current. The model charge Qgs of the VCQS nonlinear element of Fig. 8 is

92


plotted versus the two controlling bias voltages Vgs and Vj, in Fig. 10. Qgs describes a two-dimensional surface. The slope of this surface in the direction parallel to the Vgs axis defines the model capacitance Cgs(Vgs, Vds). The slope of the Qgs surface in the direction parallel to the V& axis defines the model transcapacitance Cm(Vgs, Vds). This is precisely the quantity we met in (27).

Fig. 10. Model charge Q^ vs. two controlling bias voltages VJS and V&.

The statement of path independence of the model charge is given in (32). An equivalent statement is given by (33). Mathematically, (32) and (33) show that Cgs(Vgs, Vds) and Cm(Vgs, Vds) are components of a conservative vector field.

h* (Vs. •V* )dVss + Cm (Vgs, Vds )dVds ] = 0 #

8Ces dC„

dV„ dV„

(32)

(33) ds "• gs

Again the important point is that the model capacitance and model transcapacitance are not independent functions of bias! Specifying the model capacitances and transcapacitances separately versus bias can result in a path-dependent model Qgs. That is, the right hand side of (32) may be different from zero. Such a situation can result in the same fatal errors as described for the VCCS case.

The transient (large-signal) analysis simulations don't fit the ^-parameters versus bias data well. On the other hand, good fits to the measurements can be obtained by using a simple AC (small-signal) model. However, the poor fit to the data in the transient analysis (TA) mode means the TA and AC simulations are inconsistent. Such inconsistencies mean AC simulations over a wide range of bias, no matter how accurate, cannot be used to reliably extrapolate the true large signal model performance.

The solution to this problem is to start directly from three-terminal VCQS elements such as Qgs(Vg$, Vds) and QgdiVg,, Vds). Despite the innocent appearance of capacitor symbols in the equivalent circuit of the FET model, the intrinsic capacitors are not two-terminal capacitors. A two-terminal capacitor has a capacitance (and also a charge) that depends only on the single

93


voltage difference between the terminals. However, the intrinsic capacitors and charges in FET's depend on two voltage differences. The consistency between TA and AC modes can now be guaranteed by taking the AC admittance matrix to be given by the linearized TA equations.

G O

9ds

(a)

SO-

G o

9ds -JvW-

• © • 9m

(b)

-OD

Fig. 11. Time delay implementation in linear analysis: (a) using a frequency dependent element (b) using a transcapacitance.

The second problem is that large-signal FET models do not simulate time delays of the FET. In linear analysis, time delays are typically introduced via the multiplicative frequency dependent factor gme~J°". In a linear FET model, this factor often appears with the transconductance element at the output. The key point is that in linear analysis only, quantities such as conductances and transconductances can be assigned arbitrary frequency dependences. The objective is to try to represent time delays, at least approximately, using the nonlinear elements. We can start from the standard expression gme'i<aT and perform the sequence of operations indicated in (34). The real and imaginary parts are separated, and the frequency dependence of each term is then approximated in the limit COT« 1. For low enough frequencies, the original complex frequency dependent transconductance is equivalent to two elements in parallel, a real frequency independent transconductance gm and a real frequency independent transcapacitance C r

8me'Jm ~ Sm COSCOT - jgm sin cor

= gm + JeoCT w h e r e Q =-gmT. (34)

Under these conditions, we may redraw the linear equivalent circuit of Fig 11(a) as shown in Fig. 11(b). The transcapacitance is the coefficient of proportionality between the out-of-phase current in the drain-source branch and the applied gate-source voltages. The value of the transcapacitance Cr is just -g„ r. This expression is independent of frequency, but it does depend on bias. However, the situation illustrated in Fig. 11(b) is not acceptable for nonlinear analysis as it now stands. The existence of a bias dependent transcapacitance without a corresponding parallel capacitance will generally violate the path independence of the network variable charge. The solution of the problem is again obtained by using a VCQS element in the drain-source branch. This is shown in Fig. 12. The functional form of the charge associated with the

94


nonlinear VCQS element can be obtained, starting from the transcapacitance C£Vgs, V^), by solving an "exact" ordinary differential equation. Then, the transcapacitance associated with a VCQS element between the source and the drain provides a reactive output current proportional to the time derivative of the gate voltage. This current approximates the effect of the delay.

G 0

delay

Fig. 12. Time delay implementation using VCQS for large-signal analysis.

Figure 13 show the large-signal equivalent circuit used for physical or empirical FET models." As Root and Hughes stressed, the circuit includes nonlinear VCQS elements to guarantee charge conservation, give a good fit to the measured /-parameters, and properly model the effects of time delay. The VCCS elements and VCQS elements represent the active operation of the intrinsic device and the extrinsic series parasitics are accounted for using linear resistances and inductances. This equivalent circuit can be used with physical equations or empirical equations describing the nonlinear active element values.

So—r*"rv-vw- A/W-'v,r*—OD

Fig. 13. Large-signal equivalent circuit for physical and empirical FET models.77

We believe that there is no question that RF MOSFET modeling should be based on the

95

982 M. Je, I. Kwon, H. Shin & K. lee

large signal model as shown in Fig. 13. As discussed earlier, current MOSFET models such as BSIM3v363 is basically large signal one. Therefore, we do not have to worry about conservation laws shown in (30) and (33), as far as circuit simulation is concerned. However, these conditions, i.e., the concept of transcapacitance, should still be carefully considered in parameter extraction. This is the focus of this section and will be extensively discussed in 3.3.

3.2. Parameter extraction using conventional three-terminal RF MOSFET models without intrinsic body terminal

Intrinsic device

t=k © ft»e*"v

r is

9d, -rc< 'd«

•VW>- -OD

Fig. 14. Conventional small-signal equivalent circuit model for a silicon MOSFET.78

Figure 14 shows one of the most popular MOSFET equivalent circuit used to extract small-signal parameters of a RF MOSFET.'8 It is very similar to the schematic for III-V FET's shown in Fig. 4. The distributed channel resistance /?, was omitted and the MOSFET was regarded as a simple three-terminal device. As previously mentioned, the cold-FET method with forward-biased gate has been widely used to extract the series extrinsic elements for III-V FET's. However, this cold-FET method cannot be applicable to silicon MOSFET's, because the gate is DC-isolated from the remainder of the device. As a modified approach for silicon MOSFET's, Lovelace, Costa, and Camilleri extracted the parasitic resistances from 5-parameters at Vgs = Vds

= 0 V.n This bias condition causes the contribution of the transconductance gm and the output conductance gds to become zero. Conversion of the measured zero-bias 5-parameters into real components of an equivalent Z-parameter network yields the parasitic resistance values as follow:

MZu) = Rg+Rs (35)

Re(Z12) = Re(Z21) = * s (36)

Re(Z22 ) = Rd+Rs. (37)

With knowledge of the parasitic resistance parameters, the intrinsic Z-parameters can be

96


obtained by subtracting the series resistances from the measured Z-parameters and then, converted to the intrinsic y-parameters. The intrinsic model elements can be extracted directly using a procedure very similar to that suggested in Ref. 71. Parameters for the intrinsic small-signal model as a function of the intrinsic y-parameters are shown below:

Im(y,2) cgd - •

CO

C _lm(Yu) + lm(Yn)

gs CO

_lm(y22) + Im(y,2) CO

gds=Re(Y22)

8, = |V tan"

T = -

im(y2,-y l2) Re(y2l-y12)

(38)

(39)

(40)

(41)

(42)

(43)

Based on this parameter extraction approach, Biber, et al. constructed a nonlinear large-signal model for RF MOSFET's.7' They proposed new equations for the nonlinear capacitances. To simplify the implementation, the DC drain current equation of the EKV model was used while accuracy for RF simulation was achieved by adding new capacitance equations with the model program code. The combination of the DC and RF parts of the model predicts the nonlinear high-frequency performance over a wide range of the operating bias points.

Fig. 15. Small-signal equivalent circuit used for the extraction of the linear intrinsic elements."

Small-signal on-wafer 5-parameters are measured for a MOSFET at various bias points. The extrinsic elements from probing pads are de-embedded using the three-step method.74 The small-sipal elements including intrinsic ones are determined by direct extraction from this de-

97


embedded data.'8 The small-signal equivalent circuit used is shown in Fig. 15. The output conductance is modeled in two parts: \/Rds and the \IZdsoul. The MRds models the low-frequency output conductance while the high-frequency output impedance is dominated by CdsU C^, and R<tsu which combine to form Zdsoul. Once the equivalent circuit element values of the linear model are known, the next step is to find the best set of constants and coefficients of the capacitance equations that fit the extracted capacitances over all bias points. The equation used for Cgs is of the following form: Cgs=Cgs0 +Ctll{A,+B,mh[C,(Vg,-VT)]}{D,+Et[l + tanh(yg, -Vds)]tanh(FsVds-GsVgs)}

(44) where Cgs0 is a bias independent capacitance, VT is the threshold voltage, and Cgjl is a scaling factor, As, Bs, C„ Ds, E„ Fs, and Gs are all fitting parameters to match this equation to the measured data. The pararmeters As, Bs, and C, fit the major curvature as a function of gate-source voltage, while Ds, Es, Fs, and Gs fit the drain-source dependence. The fitting parameters are optimized by minimizing the mean square error. The same fitting procedure is repeated for the gate-drain capacitance. The equation used for Cgd is of the following form:

Cgd = Cgd0 + Cgdl {Ad + Bd tanh[C„ (-Vds + DdVgs) - VT]} (45)

where Cgd0 and Cgdx are a bias independent capacitance and a scaling factor, respectively, while Ad, Bd, Cd, and Dd are fitting parameters. The linear parameter extraction results, especially the capacitances, are inputted to the nonlinear modeling process along with the DC current equations of the nonlinear SPICE model. The combination of these elements yields a model for the nonlinear RF performance of a transistor.

The simulations of the implemented nonlinear RF MOSFET model have shown fairly good agreement with the measurements in linear analysis over a wide range of bias points and in two-tone intermodulation analysis. However, a fairly large difference was seen in the output reflection (S12). This difference is attributed to the absence of a proper substrate parasitic modeling. Although Zdsou, could possibly have been used to fit S22 at high frequencies, unfortunately, Zdsml was used for modeling the frequency dispersion effect, or the variation of output conductance at low frequencies as observed in IH-V FET's.

Moreover, the small-signal equivalent circuits used in Refs. 78 and 79 don't have a complete set of active capacitances including transcapacitances and thus, the transient simulation with the constructed large-signal model suffers from inaccurate results and convergence problem due to the path-dependent charge quantities. Also the ways of implementing time delay in Refs. 78 and 79 using the multiplicative term e'jaT and Rj/Ru are not compatible with large-signal modeling."

Figure 16 shows the small-signal equivalent circuit proposed by Sung, Bendix, and Das."0

This model considered the substrate resistance as a lumped element connected to the bottom of the drain junction capacitance Q so that it can fit measured Y22 or S22 more accurately. Cg and Cds represent the overlap and fringing effects and also include the effects of the gate and drain probing pad, respectively. The resistances /?, and Rdg are the effective channel resistances. ym

includes both the transit time and the RC delay terms with the fraction of their contribution adjusted by the coefficients kx and k2, respectively, which depend on the biasing condition. ym is

98


expressed as

y* gm* -j<°Tokt

(46) \+j(OT0k2

As pointed out above in this section,7"-7'^ and R/Rdg used for considering time delay effects are useful only for small-signal analysis.

60—rrrt—VW-

Intrinsic device C9d Rdg

-\\—-VW^

vm\^<v ymv, •©

• v w — f * ^ — O D

-1- c,,

Fig. 16. Small-signal equivalent circuit.80

The drain and source series resistances are determined from the extrapolation of equivalent channel resistance to zero channel length using an array of devices with varying channel lengths, whereas the gate series resistance is calculated from the polysilicon sheet resistance. The series inductances are determined by fitting the imaginary parts of Zit, Zn, and Z^x. The Cds is measured on a dummy device structure using only contact pads and is de-embedded from the measured data.

After de-embedding the extrinsic elements, the intrinsic ^-parameters can be written as follow:

^ _ / g £ L _ J(0cdg \+jcoCgiRi

g \ + jwCdgRdg * i i =" (47)

r>2=-

^21 =

\ + jaCgdRdg

8n -JO>TJ<-\ J<oCdg

1 + jaCglRi 1 + j(0Tok2 1 + jwCd R, dg dg

'22 \+a>2Cd

2Rsub(Rsub+Rds)+ja)CdRds , jccCgd

Rds+a)2c/R sub *Vs \ + jwCgdrdg

(48)

(49)

(50)

99


Note that Cdg was distinguished from Cgd according to the difference in signal excitation. Cgd * Cdg because the intrinsic capacitances in the active device are not reciprocal. The use of non-reciprocal capacitances is theoretically equivalent to the use of transcapacitances (i.e., Cm = Cdg

- Cgd)-W Although the equivalent circuit in Fig. 16 doesn't seem to implement a complete set of capacitances, the charge conservation can be guaranteed by using non-reciprocal capacitances in linear equations when the resulting small-signal model is used to build a large-signal model. However, the above equations are too complex to be useful for direct extraction of parameters, and thus a curve fitting approach was used."0

In practice, the simulated output characteristics using this model show fairly good agreement with the measured ones. However, there is no intrinsic body node in Fig. 16. In the source-body tied MOSFET, the node that is tied with the source is not the intrinsic body, but the extrinsic body. Thus, even for the source-body tied configuration, the circuit elements associated with the body, such as body small signal transconductance gmb and gate-body intrinsic capacitance Cgby do not really disappear. Strictly speaking, without these elements and the intrinsic body node, various substrate-related signal coupling that becomes more important at higher frequencies (> 10 GHz) cannot be explained.'-'2 On the other hand, without the intrinsic body node, the substrate parasitics cannot be modeled physically. The Rsub connected in series with the drain junction capacitance in Fig. 16 may be just enough to fit the measured K22 or S22

up to about 10 GHz, but its location in the equivalent circuit is not physically correct.81-82 As a result, it is difficult to make the value of Rsub in this model be scalable and predictable from the technology parameters. Above all, all the models examined in this section are three-terminal models, and thus their application is limited to a specific circuit configuration.

3.3. KAIST three-terminal model with simple and accurate parameter extraction technique

Drain

6 Source

Fig. 17. Small-signal equivalent circuit of a three-terminal MOSFET model without an intrinsic body node.

We have proposed a simple and accurate parameter extraction method for a small-signal MOSFET model including the substrate-related parameters and a complete set of non-reciprocal capacitors.83 This work focuses on a charge-conserving and physical small signal equivalent

100


circuit of the RF MOSFET and an accurate parameter extraction approach by K-parameter analysis from measured S-parameters.

The small signal equivalent circuit of a three-terminal MOSFET model is shown in Fig. 17. Non-reciprocal capacitance and substrate-related parameters are included in the model. In a three-terminal configuration, the source-to-body junction capacitance Cjs and the source-to-body spreading resistance Rsubs can be excluded if the intrinsic body node is assumed to be short-circuited to the source directly. This approximation makes a simple direct extraction of all the elements possible. However, Cjd and Rsubd extracted with this assumption do not provide physically correct values, although they provide excellent fit of Y-n up to 10 GHz, as pointed out in 3.2.80 Four intrinsic capacitances, Cgs, Cgd, Cdg and Csd, are required for the three-terminal model. The overlap capacitances are merged with the correspondent intrinsic capacitances. Cgd

and Cdg are the two non-reciprocal capacitance components for the three-terminal model.57*0 The capacitive effect of the drain voltage on the gate charge is represented by Cgd, and the capacitive effect of the gate voltage on the drain charge is represented by Cdg. In general, Cdg is different from Cgd. C„ = Cdg - Cgd is a transcapacitance representing the different effect of the gate and the drain on each other in terms of charging currents, just as gm is a transconductance representing the different effect of these two terminals on each other in terms of transport currents. If Cgd and Cdg are set to be equal, as in most conventional models, large error can be introduced since charge conservation does not hold. In the AC simulation, the transcapacitance has to be included for accurate prediction of the transadmittances v

2i and Yn. Without the non-reciprocal gate-drain capacitance, it is impossible to model I m ^ i ) and I m ^ u ) accurately at the same time. In the case of a four-terminal model with a separate substrate terminal, a similar approach can be extended by including other non-reciprocal capacitances. The resistance Rg

represents the effective gate resistance that consists of the distributed channel resistance and the gate electrode resistance." These effects are approximated by a single effective lumped gate resistance, as shown in the equivalent circuit of the MOSFET shown in Fig. 17.

Direct extraction using a linear regression approach is performed by K-parameter analysis on the equivalent circuit of the MOSFET for high frequency operation. In our approach, an optimization process, which may have uncertainties in obtaining physical parameters, is not required. The small-signal equivalent circuit shown in Fig. 17 can be analyzed in terms of Y-parameters as follow:

ja>(Cgs + Cgd) a>2 (Cgs + Cgd )2 Rg + ja>(Cgs + Cgd)

" \+MCgs+Cgd)Rg \+<o2{Cgs+Cgd)2Rg

2

y - jwCgd _ - a>2Cgd (Cgs + Cgd )Rg - jwCgd

12 \+jco{Cgs+Cgd)Rg \+a>2{Cgs+Cgd)2Rg

2

1 + MCgs + Cgd )Rg 1 + ja(Cgs + Cgd )Rg

8 m -°>2Cdg(Cgs +Cgd)Rg -jccCdg-jcogmRg{Cgs+Cgd)

l + a,2(Cgs+Cgd?Rg2

Yix

101


y22 -_gds + *** +j(oCsd +jwCgd +-2CMCgd+Cm) + jagmCgdRg

\+jojCjdRsubd gd l+jo>(Cgs+Cgd)Rg

= g d j + **» +j(oCsd +jaCgd +"'C*C**«+**•<**« ** \ + jcoCjdRsubd

gd \ + joj{Cgs+Cgd)Rg

, <°2cjd2Rsubd , ^ 2 c g d c d g R g + o>2gmR2

gcgd (cgs + c g d ) 8ds \+OJ

2CJd2Rsubd

2 \+co2{Cgs+Cgd)2Rg

2

J^Jd _, • s* ^ • . J<»gmRgCgd -ja>3CgdCdg(Cgs +Cgd)R2g

. 2 / " 2 D 2 s" « a u^.,^r j .r \2i

(54) For operation frequency up to 10 GHz, by using the assumption that a2 (Cgs + Cgd)

2 Rg2 « 1, the

K-parameters can be approximated as follows:

y,, * w2 (Cgs +Cgd)2Rg+ jo>(Cgs + Cgd) (55)

Yl2 * -w2Cgd(Cgs + Cgd)Rg - jcoCgd (56)

»2i * 8m ~0}2Cdg{Cgs +Cgd)Rg -jwCdg -jojgmRg(Cgs+Cgd) (57)

>-22 * * * +,°)C2*2S:bd

1^2CgdCdgRg + a>2gmR2

gCgd(Cgs +Cgd) \+a> Cjd Rsuhd

JWCjd + jaCsd + jcoCgd + jcogmRgCgd - ja>>CgdCdg(Cgs + Cgd)R2g.

i , 2 ^ 2 D 2 l + O) CJd Rsubd

(58) The validity of the assumption that a} (Cgs + Cgd)

2 Rg2 « 1 will be checked after each

parameter is extracted. All the components of the equivalent circuit are extracted by the Y-parameter analysis and analytical equations are derived from real and imaginary parts of the Y-parameters. gm is obtained from the -intercept of Re(K21) versus of and gds is extracted from the ^-intercept of Re(y22) versus of, at the low frequency range. Rg, Cgd, Cgs and Cdg can be obtained by (61H74).

gm=Re(r2.)Uo <59>

/?g=Re(yn)/(Im(Kn))2 (61)

Cgd=-\miXxl)loj (62)

Cgs=(lm(Yn) + lm(Yn))/co (63)

Cdg =-lm(Y2l)/o>-gmRg(Cgs+Cgd) (64)

For the extraction of substrate components Rsuhd and Cjd, Ysub is first defined as follows:

ysub = hi ~gds ~<o2CgdCdgRg -co2gmR2gCgd{Cgs +Cgd)

102


-jaC* -ja>Cgd -jagmRgCgd + ja>3CgdCdg(Cgs +Cgd)R2g

°>1Cid2Rsubd _+_ JaCjd

\ + a>2Cjd2Rsubd

2 \+m2CjdlRsubd

Kubd »s obtained from the slope of the relationship for a2/Re(Ysub) vs. a? by (66).

CO

R * d U ) • = co2R subd + 2 D

Cjd is obtained from the following.

Cjd 03 Rsubd

[Mrsub) as

r _ im(y22) c,

-o>2Rsubd2

-1/2

Finally, Csrf is obtained from (58) as

C

<o - l + « 2 C y ( /2 / ? J u W

2 'grf -yrf

-s-V* ^ V * ^ + c * * ) * *

(65)

(66)

(67)

(68)

1.4-

r rn s

0.6 J

W/L

X

= 100 / 0.35 1V,V„

1 »

=2V

1 —

S l ° P e : R . u . » d = 1 9 1 n

-

<o2[x1021rad2]

Fig. 18. RmU was determined from slope of of/V.e(Yab) as a function of of-.

The proposed direct extraction method was applied to determine the parameters of test

devices, which were multi-fingered n-MOSFET fabricated by 0.35 nm technology. S-

parameters are measured in the common source-substrate configuration using on-wafer RF

probes and a HP 8510C vector network analyzer. Before the extraction process, parasitic

components of input and output pads have to be removed. To remove on-wafer pad parasitics, a

de-embedding technique was carried out by subtracting y-parameters of the open pad structure

from F-parameters of the measured device. The parameter extraction has been performed for an

n-MOSFET with 100-nm width having twenty-unit gate fingers. All the small signal parameters

were extracted using (59) - (68). A transconductance gm of 16.6 mS was obtained from the^-

intercept of Re(y2i) versus of and a conductance gds of 0.31 mS was extracted from the

103


intercept of Re(y22) versus or, at the low frequency range. a?/Re(Ysub) is linearly proportional to of and Rsubd of 191 i2 was determined from the slope, as shown in Fig. 18.

o o c 8 5 & O

140

120

100

80

60

40

20

0

W/L= 100/0.35 . V = 1V,V » 2 V

a n - i c o o o ^ '

70

60

50

4 0 „

a 30 —

a?

20

10 4 6 8

Frequency [GHz]

10 12

Fig. 19. Frequency dependence of the extracted parameters for an n-MOSFET having 100 fan width and biased to Vg, = 1 V and Vis -2V.

In Fig. 19, the frequency dependence of extracted parameters such as Rg, Cgd, Cgs, Cdg> CJd

and Cjrf at Vgs = 1 Kand Vds =2 Fare shown. The results show that the extracted parameters remain almost constant with frequency. This verifies that those components are frequency-independent and the proposed extraction method is accurate and reliable. Due to the non-reciprocity, Qg is larger than Cgd as it should be. For the extracted parameter values, o? (Cgs + Cgd)2 Rg2 is calculated to be 0.055 even at 10 GHz, which is much smaller than one. This verifies the validity of using the assumption in simplifying (51)—(54) to (55H58).

ImfY,,] o

0 2 4 6 8 10 Frequency [GHz]

(a)

E ^ > •

0.0-

•0.5 •

-1 .0 -

-1 .5 -

-2 .0 -

-2 .5 -

-3 .0 -

^ A „ A 0 n _ a _ i "

o Maasurod Propoaad Modal

W / L - 100/0.35 V • 1 V, V, • 2 V

" • * - « - « * _ R " Y J "

^ ^ ^ ^ ^ o ^ ^ "

^> -

V

l m I Y J . •

2 4 6 t 10

Frequency [GHz]

(b)

104


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o Manured Proposed Modal

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I 1 r'-' — i — • j

' " [ Y J p ^

» / Re[YJ

2 4 6 8

Frequency [GHz]

(d)

Fig. 20. The 1 Vand VV

measured(symbol) and modeled(line) results of Y-parameters for the n-MOSFET biased to Vg,= • 2 V: (a) Yn, (b) YI2/ (c) Yn, (d) Y22. The frequency range is from 0.5 GHz to 10.5 GHz.

In Fig. 20, the calculated results for y-parameters obtained by using the equivalent circuit shown in Fig. 17 with extracted values are compared with the measured data for Vgs = 1 V and Vds = 2 V. It shows that the simulation result matched well with the measurement without any optimization after parameter extraction. The non-reciprocal capacitances Cgd and Cdg contribute to match the imaginary parts of YX2 and Y2\. Excluding transcapacitance could result in a significant error on the imaginary part of Y:, at high frequencies. The substrate coupling significantly contributes to the real part of the output admittance Y22 at high frequency. The total error" between measured and simulated /-parameters of the proposed model is only 0.4 %.

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(a)

10'-

10'-

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• - • "

•—• •

— 1 1 — ' 1 1

— « —

1 '

r ••

•

<W

:

R

—. •

1 1 1

1.5 2.0 2.5

V„[V]

(b)

3.5

Fig. 21. The gate-bias dependence of small signal parameters for an n-MOSFET having 100 ftm width and biased to ]/&= 2 V: (a) capacitances, (b) R8 and Ru,u-

In Fig. 21, gate bias dependence of the extracted small-signal parameters for the n-MOSFET biased to Vds = 2 V is shown. The gate bias dependence of extracted capacitances is

105

992 M. Je, I. Kwon, H. Shin & K, Lee

shown in Fig. 21(a). Cgs and Cgd are composed of the intrinsic components Cgsi and Cgdi and the overlap components Cgso and Cgd0. In the saturation region, the intrinsic capacitances Cgdi and Csd are almost zero because the drain voltage does not influence the device charges. The total gate-to-drain capacitance Cgd is dominated by the overlap capacitance Cgdo. As the gate bias increases for constant Vds, Cgd and Cdg increase due to increase of the intrinsic capacitance. Cgs

and Cm increase with Vgs near the threshold voltage at the onset of the strong inversion region and are almost constant in the strong inversion saturation region. The extracted Rg and Rsubd

with gate bias are shown in Fig. 21(b) and they are almost constant with gate bias in the strong inversion region.

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100

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- » B-

—I ' 1 r~

fl

—•

( r -

—• •—

subd

m

-

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(b)

Fig. 22. The drain-bias dependence of small signal parameters for an n-MOSFET having 100 fan width and biased to Vjs= 2 V: (a) capacitances, (b) Rs and /?»«.

In Fig. 22, drain-bias dependence of the extracted small-signal parameters for the n-MOSFET biased to Vgs= 2V\s shown. The drain-bias dependence of the extracted capacitances are shown in Fig. 22(a). The vertical line at Vds = 0.81 Kis the boundary between the linear and saturation regions. When the transistor is biased in the linear region with low Vds, the intrinsic behavior of the transistor becomes symmetric in terms of drain and source. Thus the intrinsic capacitances Cgsi and Cgdi are almost the same at V^ = 0 V. In Fig. 22(a), the difference between Cgs and Cgd at Vds = 0 Vis due to the parasitic Cgb which is included in the Cgs. Cgb of the gate contact pad component and the poly-to-well capacitance in the field oxide become the major parts of the parasitic capacitance. At V& = 0 V, Cdg is the same as Cgd and Cm = 0. Cm increases with J^ in the linear region and is almost constant for high Vds in the saturation region. Csd

becomes negative in the linear region because the raising the drain voltage will increase the effective reverse bias at the drain end and will cause the magnitude of the inversion layer charges to decrease. In the saturation region for higher Vds, the gate-to-drain capacitance Cgd is almost the same as Cgdo. The extracted capacitance parameters correctly model the bias dependence of intrinsic capacitance. Because the conventional C-V measurements using large C-V test structure are less sensitive to extraction of small capacitance values in short-channel

106


RF MOSFET's, measuring S-parameters of the RF MOSFET in the high frequency GHz range is a better alternative. The proposed parameter extraction method can be applied to accurate intrinsic capacitance modeling at GHz operation. The extracted Rg and RsuM with drain bias are shown in Fig. 22(b) and they are almost constant with drain bias.

20 -

(0

W/L* 100/0.35 V * - 2 V — — — _

/ • Extraction rwult

DC inm urwmnt

/

i . .a *—' *•" \ <* —t — . 1 ' i •>

On,

-

8*.

W/Ls 100/0.35 V. - 2 V

E _? 20

2

• Extraction raault DC measurement

(a)

Fig. 23. gm and g& extracted from the S-parameter measurement and those obtained from DC measurement: (a) varying the gate bias for Vis = 2V, (b) varying the drain bias for Vg, = 2 V.

In Fig. 23, gm and gds extracted from the S-parameter measurement and those obtained from DC measurement are compared. Extracted gm and gds as a function of Vgs with gate bias for Vds

-2 V are shown in Fig. 23(a), and extracted gm and g* as a function of Vj, with drain bias for Vgs = 2 V are shown in Fig. 23(b). They match very well with each other, verifying the validity of the equivalent circuit and the extraction method. The extraction results correctly modeled the bias dependence of gm and && in the linear and saturation regions. Figure 23 shows that RF conductance data agree well with those from derivatives of measured DC I-V characteristics. This has very important implications, that a large-signal model for I-V characteristics is accurate enough to be used for DC, low-frequency analog, as well as RF circuit simulations.

4. Four-Terminal RF MOSFET Modeling and Parameter Extraction

We have examined several trials to model the RF MOSFET as a three-terminal device. As mentioned previously, the three-terminal models are only valid for devices with source-body tied configuration and the complex signal coupling through the intrinsic body node cannot be described. To overcome these important limitations, four-terminal modeling of the RF MOSFET is required as essentially it is a four-terminal device. In this chapter, four-terminal modeling examples will be reviewed.

107


4.1. Equivalent-circuit-based modeling approaches

1 OB

Fig. 24. Complete small-signal model for a four-terminal intrinsic MOSFET proposed by Bagheri and Tsividis.37

In Ref. 37, Bagheri and Tsividis presented a four-terminal physical model of a MOSFET with the equivalent circuit shown in Fig. 24. It includes a "transmission-line effect" which is another name for the non-quasi-static effect, and its parameters are given by functions of terminal voltages, process parameters, and device geometry. The parameters vary continuously in value with bias from strong, through moderate to weak inversion. The equations were derived for the long-channel device using a charge-sheet approximation. Two differential equations -the current transport and charge continuity equations -with appropriate boundary conditions were solved using iterative methods for obtaining the small-signal terminal currents. In general, each terminal current has the form of a power series numerator over a common denominator series. From this result, the small-signal /-parameters can be calculated using the definition

L Y»P = v

fr (69)

K=O,y*0

where the subscripts a, fl, and y can stand for drain (d), gate (g), and substrate (b). The Y-parameters that were evaluated and truncated to second order in Ref. 37 are shown below.

1 + jcoa{ Ygs = -J®0*

Ygd = -JvCgd

hs = -JoCbs

YM = -J*"0, bd'

D(ja>)

1 + jcoa2

D(jco)

1 + j coai

D{ja>)

1 + jcoa2

(70)

(71)

(72)

(73)

108


igb -JoC. «*" D(jo>)

*m Sti \-jcoa4-U<») as

'mb &mb

Ysd = Sd

D(jco)

\-jcM6-U'a>)2a7

D(Ja) 1

(74)

(75)

(76)

(77)

^ = 0 (78)

D(jco) = 1 + jabx + (ja)1 b2 (79)

The quantities ah i = 1,2, •••, 7 and b},j = 1, 2 are calculated from terminal voltages, process parameters, and device geometry. As one can see from the detailed description of the quantities," the formulations are very complex. This complexity prohibits intuitive insight into the non-quasi-static effect and makes the model unattractive for CAD application. Note that this physical model is valid only for long-channel MOSFET's and appropriate parasitic elements should be added to be accurate in RF circuit simulations.

Go-

i ^ i > ?

D O

^gb " j b

HI </W-

HI i/W-

Y v

=FC^ 4=°.

&bd Cbd

m ©

-VvV 1 | -

. 'mhât

-OB

6 S

Fig. 25. Second-order high frequency equivalent circuit for the intrinsic MOSFET proposed by Vandeloo and Sansen.s5

Figure 25 shows another four-terminal high frequency equivalent circuit for the intrinsic MOSFET. Starting from the solution of a set of differential equations, which describe the channel current, Vandeloo and Sansen proposed this model." This model is a special case of the general model obtained by Bagheri and Tsividis shown in Fig. 24. The resistances in series with the capacitances in Fig. 25 represent the inertia of the charge configuration, which produces

109


time delay for the charges to reach their steady-state values when the applied voltages vary. In Ref. 85, the circuit elements were extracted by fitting the measured /-parameters rather than calculated using physical equations. For extraction, the theoretical expressions of the sixteen /-parameters - Ytj, i = 1, 2, 3, 4, j = 1, 2, 3, 4 - were derived from the equivalent circuit. The numbers in the subscripts refer to the terminals of the MOSFET: 1 denotes the gate, 2 the drain, 3 the bulk, and 4 the source. For example, Y\ \ is written as

Y = Ja>(Cgsl + Cgs2) + (ja>)2 Cg5lCgs2Rgs2

1 + jo(RgslCgsi + RgsiCgs2 + Rgs2Cgs2) + (jco)2 Cgs]Cg52RgslRgs2

+ jccCgd + jcoCgd m

1 + jeoRgdCgd 1 + jcoRgdCgd

Then, the S-parameter measurement was made to obtain the real /-parameters obtained through a conversion process. The transistor was connected to a two-port S-parameter test set and the transistor configuration was changed during the measurement to fully characterize the four-terminal characteristics in terms of sixteen S-parameters. In the first measurement, the gate was defined as port 1 and the drain as port 2. Four S-parameters were measured at a given DC bias point. Next, the measurement configuration was changed: the bulk was connected to port 1, while the source was connected to port 2. A second set of four S-parameters was measured at the same DC bias. The eight measured S-parameters were converted mathematically to Y-parameters. The eight /-parameters, obtained as a function of the frequency, are thus: /,,, Yi2, Yiu Yii< /»» Zj4» ^43. Y**- The missing /-parameters were calculated. It is obvious from the network theorem that six independent linear relations exist between all the /-parameters. To find the eight missing parameters, two extra equations are thus needed. The first relation used is the measurement of the admittance parameter /42, which is equal to the output impedance. For the second relation, a special property of the MOSFET was used. Considering the model of Fig. 25, it is obvious that Y]} equals K31. This relationship was used as the last equation. The missing /-parameters were then calculated by using the relations: X / = 0 • The final result of the

measurement and calculation is thus a three-dimensional matrix of N by 4 by 4 elements {N is the number of frequency points). This three-dimensional matrix of measured data was fitted against the theoretical model. The fitting process is built up of two parts:

(1) The measured data are fitted against a general transfer function with p poles and z zeros (p and z ranges from 1 to 3). (2) The poles and zeros from the theoretical expression are fitted against the poles and zeros extracted at step (1) by adjusting values of the equivalent circuit elements.

Through this process the optimum set of parameter values was obtained, resulting in a very good match between the measured and modeled /-parameters. Although this work proposed a small-signal measurement process for the four-terminal MOSFET and a parameter extraction procedure using the measured data, the measurement requires much effort and the extraction procedure is too complicated due to the complicated theoretical /-parameter expressions of the four-terminal equivalent circuit. In addition, the model did not account for the effects of substrate coupling and thus some of the extracted parameter values are physically incorrect. If

110


the substrate parasitics were also included in the equivalent circuit and their effects were properly considered, the formulations and extraction procedure would become even more complicated.

4.Z Macro-modeling approaches

The complexity of high-frequency four-terminal MOSFET modeling, as examined in the previous section, led to the macro-modeling approach. This approach makes use of a commercially available MOSFET model core such as the BSIM3v3, MOS model 9, or the EKV model with lumped-element equivalent circuit extensions. The model core and lumped-elements compose a sub-circuit representing a RF MOSFET. Several works adopting the macro-modeling approach have been reported.10"'3 Most of them commonly use a gate resistance. The non-quasi-static effect and the distributed gate electrode resistance are modeled as this lumped gate resistance. This solution is attractive since this resistance also models the gate-induced thermal noise efficiently." Recent lumped-element extensions for RF have incorporated the effect of the substrate as an external network with the commercial model core. These network approaches are summarized in Fig. 26. Note that the models shown in Fig. 26 represent the intrinsic part of the MOSFET excluding extrinsic series elements in the source and the drain. The substrate models of Refs. 11 and 13 are similar with the exception of additional capacitance in parallel with substrate resistances for the model of Ref. 13. The substrate model of Ref. 10 is more complicated than those of Refs. 11 and 12 and requires a complex parameter extraction procedure. If Rsub2 = RSttbi = oo in the network of Fig. 26(a), then this model reduces to that of Fig. 26(b). In a similar way, if Rsubl = R,ubi = 0 in Fig. 26(a), the model of Ref. 12 reduces to that of Ref. II with the junction capacitances enclosed in the model core. One common feature in the models of Refs. 10 and 11 is the use of extrinsic capacitances to account for the drain-to-body/source-to-body junction capacitances. They did this because the body-side ends of the two junction capacitances implemented in the core are hard-wired. Note that the model of Ref. 11 does not allow coupling of the signals through the gmb and Cgb due to the absence of the intrinsic body node. This coupling is important for both Y12 and Y2\ at high frequencies.12

D O

*» G o-

H I - - ^ W — I

E " / • »

(a)

111


D Q

€ 6 S

-OB

HI—vw—

(b)

D Q

G. r t O «W- i- t s -o- ->W——OB.

6 S

(c)

Fig. 26. (a) Sub-circuit model of Ref. 10, (b) sub-circuit model of Ref. 11, (c) sub-circuit model of Ref. 12.

Usually, model parameters of the core in sub-circuit models are extracted with DC /-Kand low-frequency C-V measurement data using the same procedure used in commercial models. Then the extraction of the lumped-elements is executed using measured S-parameters at a given DC bias condition. The Rg has a great influence on the real part of Yu or the phase of Yu and the substrate network affects the real part of Y22 or the phase of Y22 most significantly. Thus the Rg is extracted from Re(yn) or Phased) and the substrate-related elements are determined from Re(y22) or Phase(v

22) directly or using a curve fitting technique. When the used model core does not provide the bias-dependent overlap capacitances, external Cgs0 and Cgd0 can be added between the gate and source/drain terminals of the core to describe the bias dependence of the overlap capacitance, which is especially important in a short-channel LDD MOSFET."2

These external capacitances also allow one to correct for the inaccuracies of the intrinsic capacitances appearing for short-channel devices. The best values of the additional capacitances are found in fitting the modeled Im(v,i) and Im(y12) against the measured ones. Note that the

112


accuracy of lm(Yl2) generated from the sub-circuit model mainly relies on the transcapacitance value modeled in the core and cannot be adjusted by just adding external passive components.

The sub-circuit models that we have reviewed seem to be a successful compromise between accuracy and model complexity or computational efficiency. These models, accompanied by an appropriate parameter extraction process, show fairly good agreement with the measured small-signal parameters. However, these sub-circuit models cannot overcome some limitations inherent in the MOSFET model used as a core. The accuracy of g„ and g^ predicted by commercial models has improved significantly, but is not yet sufficient, especially for RF circuit simulation where the higher order derivatives of the current should be smooth and correct. How accurately the commercial MOSFET models simulate the nonlinear characteristics of the RF circuits has not been verified. There also remain errors in predicting the intrinsic C-V characteristics of short-channel devices. These intrinsic problems cannot be cured using extrinsic sub-circuit extensions. Also, note that scalable physical modeling of the added extrinsic elements is required for the sub-circuit model to be scalable and predictive as a whole.

5. Conclusions

We have examined a variety of examples of modeling and parameter extraction methods for RF MOSFET's after reviewing the basic concept and general strategies. Modeling and parameter extraction techniques popular in III-V FET modeling were reviewed and recent efforts to model the RF MOSFET and extract the model parameters were examined in light of the differences between the MOSFET and the III-V FET. We have found that the differences - the lossy silicon substrate and the four-terminal properties of a MOSFET - resulted in major difficulties of RF MOSFET modeling and parameter extraction. We have also discussed several works which attempt to successfully apply the established methodology for III-V FET's to MOSFET's with proper modifications, along with the shortcomings and limitations of this three-terminal modeling approach. A very simple and accurate parameter extraction method studied in our laboratory for three-terminal modeling considering charge conservation was also introduced. Our works have two important implications. One is that the consideration for charge conservation is important not only for accurate device modeling and circuit simulation but even more for proper parameter extraction. Another is that one accurate large-signal l-V model is enough to be used for DC, low-frequency analog, as well as RF circuit simulation. Four-terminal modeling based on new equivalent circuits to address the high-frequency effects arising in a MOSFET was found to be very complicated and not practical for CAD applications, even without considering the substrate coupling terms. As a temporary alternative, the macro-modeling approach has been examined with various examples.

There still remain many challenges in RF MOSFET modeling and parameter extraction, especially to satisfy the tough requirements in the coming future concerning applications at higher frequencies: The Q-V model accuracy for the short-channel device should be enhanced and more precise modeling of l-V, especially in the moderate inversion region is required. Furthermore, the model accuracy of the high-order derivatives of currents and charges should be improved because it is critical for correct nonlinear simulation of RF circuits as well as

113


computational efficiency. More careful implementation of the non-quasi-static effect is also needed. Scalable and physical model development for the substrate network is necessary to keep the virtue of scalable and predictive nature of the MOSFET model at the RF range. There has been much effort to overcome these challenges. With a continuous effort, more successful modeling schemes and parameter extraction strategies will appear in the near future and they will greatly accelerate the growth of the RF CMOS market. As a final comment, it should be emphasized that the challenges mentioned cannot be solved only in terms of modeling itself. As the operation frequency increases, the parameter extraction technique becomes more important. Even with the same modeling scheme, significant improvements can be achieved by developing a better parameter extraction procedure or more accurate measurement techniques.

Acknowledgements This work was supported by MICROS research center, Silvaco International, and the

National Program for Tera-Level Nano-Devices through MOST. The authors also would like to appreciate useful comments by Prof. Tor Fjeldly at Norwegian Univ. of Science and Technology.

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42. P. Yang and P. Chatterjee, "An optimal parameter extraction program for MOSFET models," IEEE Trans. Electron Devices, vol. ED-30, Sep. 1983,1214-1219.

43. T. Sakurai, B. Lin, and A. R. Newton, "Fast simulated diffusion: an optimization algorithm for multiminimum problems and its application to MOSFET model parameter extraction," IEEE Trans. Computer-Aided Design, vol. 11, no. 2, Feb. 1992,228-234.

44. Y H. Hu and S. W. Pan, "SaPOSM: an optimization method applied to parameter extraction of MOSFET models," IEEE Trans. Computer-Aided Design, vol. 12, no. 10, Oct. 1993,1481-1487.

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47. J. W. Bandler, S. H. Chen, S. Ye, and Q-J. Zhang, "Integrated model parameter extraction using large-scale optimization concepts," IEEE Trans. Microwave Theory and Techniques, vol. 36, no. 12, Dec. 1988, 1626--1638.

48. H. P. Tuinhout, S. Swaving, J. J. M. Joosten, "A fully analytical MOSFET model parameter extraction approach," IEEE Int. Conf. Microelectronic Test Structures, vol. 1, no. 1, 1988, 79-84.

49. P. R. Karlsson and K. O. Jeppson, "A direct extraction algorithm for a submicron MOS transistor mode," IEEE Int. Conf. Microelectronic Test Structures, vol. 6, 1993, 157-162.

50. S. Minehane, S. Healy, P. O'Sillivan, K. McCarthy, A. Mathewson, and B. Mason, "Direct BSIM3v3 parameter extraction for hot-carrier reliability simulation of n-channel LDD MOSFETs," IEEE Int. Symp. Physical and Failure Analysis of Integrated Circuits, 1997, 133-139.

51. D. W. Marquardt, "An algorithm for least squares estimation of nonlinear parameters," J. SIAM, vol. 11, 1963,431-441.

52. S. Kirkpatrick, C. D. Gelatt, Jr. and M. P. Vecchi, "Optimization by simulated annealing," Science, vol. 220, May 1983,671-680.

53. S. Geman and C-R. Hwang, "Diffusions for global optimization," SIAM J. Control and Optimization,

vol. 24, no. 5, Sep. 1986,1031 -1043.

54. D. M. Pozar, Microwave Engineering, 2nd ed., John Willey & Sons, 1998.

55. F. W. Grover, Inductance Calculations, New York, NY: Van Nostrand, 1962.

56. H. M. Greenhouse, "Design of planar rectangular microelectronic inductors," IEEE Trans. Parts, Hybrids, and Packaging, vol. PHP-10, June 1974, 101-109.

57. D. E. Root and B. Hughes, "Principles of nonlinear active device modeling for circuit simulation," ARFTG Conf., 1988,3-26.

58. D. E. Ward and R. W. Dutton, "A charge-oriented model for MOS transistor capacitances," IEEE J.

Solid-State Circuits, vol. SC-13, no. 5, Oct. 1978, 703-707.

59. P. Yang, B. D. Epler, and P. K. Chatterjee, "An investigation of the charge conservation problem for

MOSFET circuit simulation," IEEE J. Solid-State Circuits, vol. SC-18, no. 1, Feb. 1983.

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60. Y. Tsividis, The operation and Modeling of the MOS Transistor, 2nd ed., McGraw-Hill, 1999.

61. F. Diamant and M. Laviron, "Measurement of the extrinsic series elements of a microwave MESFET under zero current condition," European Microwave Conf., 1982,451 —456.

62. R. R. Daniels, A. T. Yang, and J. P. Harrang, "A universal large/small signal 3-terminal FET model using a nonquasi-static charge-based approach," IEEE Trans. Electron Devices, vol. 40. . ;i. 1993, 1723-1729.

63. BSIM3v3.2 MOSFET Model User's Manual, Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA 94720.

64. UTMOST HI Extractions Manual, Vol. 1, Silvaco International, CA 94054.

65. W. R. Curtice, "A MESFET model for use in the design of GaAs integrated circuits," IEEE Trans. Microwave Theory and Techniques, vol. MTT-28, no. 5, May 1980,448—456.

66. H. Staz, P. Newman, I. W. Smith, R. A. Pucel, and H. A. Haus, "GaAs FET device and circuit simulation in SPICE," IEEE Trans. Electron Devices, vol. ED-34, no. 2, 1987,160-169.

67. T. Kacprzak and A. Materka, "Compact dc model of GaAs FET's for large-signal computer calculation," IEEE J. Solic-State Circuits, vol. SC-18, no. 2, Apr. 1983,211-213.

68. A. J. McCamant, G. D. McCormack, and D. H. Smith, "An improved GaAs MESFET model for Spice," IEEE Trans. Microwave Theory and Techniques, vol. MTT-38, no. 6, June 1990, 822-824.

69. Sematech "Compact model workshop", Austin, Texas, Mar. 1995.

70. C. C. Enz, F. Krummenacher, and E. A. Vittoz, "An analytical MOS transistor model valid in all regions of operation and dedicated to low-voltage and low-current applications," Analog Integrated Circuits and Systems Processing Journal, vol. 8, 1995, 83—114.

71. G. Dambrine, A. Cappy, F. Heliodore, and E. Playez, "A new method for determining the FET small-signal equivalent circuit," IEEE Trans. Microwave Theory and Techniques, vol. 36, no. 7, July 1988, 1151-1159.

72. P. L. Hower and N. G Bechtel, "Current saturation and small-signal characteristics of GaAs field effect transistors," IEEE Trans. Electron Devices, vol. ED-20, Mar. 1973,213-220.

73. M. C. A. M. Koolen, J. A. M. Geelen and M. P. J. G Versleijen, "An improved de-embedding techniques for on-wafer high-frequency characterization," IEEE Bipolar Circuits and Technology Meeting,

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1991,188-191.

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75. K. Kundert and A. Sangiovanni-Vincentelli, "Simulation of nonlinear circuits in the frequency domain," IEEE Trans. Computer-Aided Design, vol. CAD-5, no. 4, Oct. 1986.

76. L. Chua, "Device modeling via basic nonlinear circuit elements," IEEE Trans. Circuits and Systems, vol. CAS-27, no. 11, Nov. 1980.

77. Advanced Design System 1.5 User's Manual - Circuit Components: Nonlinear Devices, Agilent Technologies, Dec. 2000.

78. D. Lovelace, J. Costa, and N. Camilleri, "Extracting small-signal model parameters of silicon MOSFET transistors," IEEE Microwave Theory and Techniques Symp., 1994, 865-868.

79. C. E. Biber, M. L. Schmatz, T. Morf, U. Lott, and W. Bachtold, "A nonlinear microwave MOSFET model for Spice simulators," IEEE Trans. Microwave Theory and Techniques, vol. 46, no. 5, May 1998, 604-610.

80. R. Sung, P. Bendix, and M. B. Das, "Extraction of high-frequency equivalent circuit parameters of submicron gate-length MOSFET's," IEEE Trans. Electron Devices, vol. 45, no. 8, Aug. 1998,1769-1775.

81. S. H-M. Jen, C. C. Enz, D. R. Pehlke, Schroter, and B. J. Sheu, "Accurate modeling and parameter extraction for MOS transistors valid up to 10 GHz," IEEE Trans. Electron Devices, vol. 46, no. 11, Nov. 1999,2217-2227.

82. C. C. Enz and Y. Cheng, "MOS transistor modeling for RF IC design," IEEE Trans. Solid-State Circuits, vol. 35, no. 2, Feb. 2000, 186-201.

83. Ickjin Kwon, Minkyu Je, Kwyro Lee, and Hyungcheol Shin, "A new small signal modeling of RF MOSFETs including charge conservation capacitances," European Solid-State Circuit Conf., 2000, 296— 299.

84. X. Jin, J-J Ou, C-H. Chen, W. Liu, J. Deen, P. R. Gray, and C. Hu, "An effective gate resistance model for CMOS RF and noise modeling," Int. Electron Devices Meeting, 1998,961-964.

85. P. J. V. Vandeloo and W. M. C. Sansen, "Modeling of the MOS transistor for high frequency analog design," IEEE Trans. Computer-Aided-Design, vol. 8, no. 7, July 1989,713-723.

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MOSFET MODELING FOR RF IC DESIGN

YUHUA CHENG

Conexant Systems, Newport Beach, CA 92660, USA

High frequency (HF) AC and noise modeling of MOSFETs for radio frequency (RF) integrated circuit

(IC) design is discussed. Equivalent circuits representing both intrinsic and extrinsic components in a

MOSFET are analyzed to obtain a physics-based RF model. Modeling of the intrinsic device and the

extrinsic components is discussed by accounting for the important physical effects at both DC and HF.

Based m the Y-parameter analysis of the equivalent circuit model, procedures of the HF model

parameter extraction are also developed. With the discussed approaches, a sub-circuit RF model

incorporating the modeling of parasitics is presented. This model is compared with the measured data

for both y parameter and fT characteristics. Good model accuracy is achieved against the measurements

for a 0.25um RF CMOS technology. The non-quasi-static (NQS) modeling issue has also been discussed

by using the BSlM3v3 based RF model to predict the HF characteristics of devices with serious NQS

effects. Further, noise modeling issues are discussed by analyzing the theoretical and experimental

results in both the flicker noise and thermal noise modeling. Modeling efforts to incorporate new

physical effects are needed to predict better the flicker noise characteristics in today's MOSFETs. A

detailed analysis of the HF noise parameters has been conducted to establish the relationship between

the noise parameters preferred by circuit designers and obtained by HF noise measurement. Analytical

calculation of the noise parameters has also been discussed to understand the noise characteristics

with/without some parasitic components such as gate and substrate resistances as well as the influence of

the induced gate noise. The HF noise predictivities of several HF noise models are also examined with

the measured data. The results show that the BSIM3v3 based RF model can predict the channel thermal

noise better than the other models.

1. Introduction

1.1. General review of the RF performance of MOSFETs

With fast growth in the radio-frequency (RF) wireless communications market, the demand

for high performance but low cost RF solutions is rising. The common perception is that

silicon CMOS is suitable for digital applications while other technologies such as silicon

bipolar and III-V material based processes are suitable for high frequency (HF)

applications. However, advances in CMOS fabrications have resulted in deep submicron

transistors with higher transit frequencies and lower noise figures. RF designers have

already started to explore the use of CMOS technology in RF circuits. In Table 1, the RF

performance of several generation of CMOS technologies are listed,' where, for a 0.25|im

technology^- is around 30GHz, and is in the 50GHz range for a 0.18pm process and even

higher for a more advanced technology. Actually, literature on more attractive device

performance to RF applications than those listed in Table 1.1 has been reported recently.2

This advanced performance of MOSFETs is attractive for HF circuit design in view of a

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1008 Y. Cheng

system-on-a-chip realization, where digital, mixed-signal base-band and HF transceiver blocks would be integrated on a single chip. Besides the ability to integrate RF circuits with other analog and logic circuits with the intention to reduce cost by eliminating the sometimes expensive packaging, other advantages offered by silicon CMOS technologies are also interesting, such as the low cost due to the volume of wafers processed and low power consumption feature of MOSFETs, which makes it suitable for portable applications. For example, silicon MOSFET circuit can operate at voltages as low as IV, and still have room to improve.

Table 1 RF performances of MOSFETs in different technology generations.

Year

L (um)

/T-(GHZ)

/„,,(GHz)

NFmi„ (dB)

1995

0.25

33

41

0.5

1997

0.18

49

47

0.35

1999

0.14

70

51

0.23

2001

0.12

84

52

0.2

2003

0.1

112

60

0.15

Although the above picture might change in the future with decreasing MCM packaging cost and due to many still existing problems of a single-chip solution, such as substrate high frequency coupling, synchronized design cycle time for digital and HF blocks as well as increased cost for RF-suitable deep-submicron processes, exploration of the suitability of CMOS for RF application is a very useful task,3 as further development such as silicon-on-insulator and other novel structures will improve the performance of silicon-based CMOS devices in general compared to III-V material based solutions.4

1.2. The importance of the modeling at HF

Time to market is one of the key factors for a product to have profit margin and market shares. For RF products, time to market and design cycle reduction depend greatly on the capability of the design environment to predict circuit performance accurately using simulation. To have an efficient design environment, design tools with accurate models for devices and interconnect parasitics are essential. It has been known that for analog and RF applications the accuracy of circuit simulation is strongly determined by device models. Accurate device models become crucial to predict the circuit performance correctly.

In most of the commercially available circuit simulators, MOS transistor models have been originally developed for digital and low frequency analog circuit design,5,6

which focus on the dc drain current, conductances, and intrinsic charge/capacitance behavior up to the megahertz range. However, as the operating frequency increases to the gigahertz range, the importance of the extrinsic components rivals that of the intrinsic counter-parts. Therefore, a RF model with the consideration of the HF behavior of both intrinsic and extrinsic components in MOSFETs is extremely important to achieve accurate

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MOSFET Modeling for RF IC Design 1009

and predictive results in simulation of a designed circuit. Next we discuss some examples to show the necessity of the MOSFET HF modeling for RF applications.

So far, most compact MOSFET models do not include the gate resistance RG. However, the thermal noise contributed by the gate resistance should be considered as MOS transistors approach gigahertz frequencies, and the RC effect at the gate should be well modeled since both of these effects are important in designing radio frequency CMOS circuits. As shown in Fig. 1, the gate resistance component will significantly affect the input admittance at RF so the model without including RG cannot accurately predict the HF characteristics of the device. It is very crucial because one may use this resistance for impedance matching to achieve maximum power transfer. Also, The thermal noise introduced by the gate resistance increases the noise figure of the transistor. It is an important noise source to be considered when optimizing the noise performance of a RF circuit. Furthermore, The gate resistance also reduces fmax (the frequency at which the maximum available power gain of the device equals to 1), which is an important device parameter in RF circuit design in addition tofT, the frequency at which the current gain of the device equals to 1.

It has been known that two additional physical effects at HF will affect the value of the effective gate resistance obtained at DC and low frequency, one is the distributed transmission line effect on the gate, and another one is the distributed effect or NQS effect in the channel.7,8 Therefore, detailed theoretical analysis with the consideration of these two HF effects is needed to obtain an accurate and physical gate resistance model, which is critical in predicting the HF behavior of the MOSFETs in designing a RF circuit.

0.014

0.012

55" ° ° 1 °

>F 0.008

~ 0.006 c CD -~. 0.004

"5* 0.002

0.000

•0.002

0 2 4 6 8 10 12

Frequency (GHz)

Fig. 1 The model without the gate resistance cannot predict the measured Yu characteristics.

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1010 Y. Cheng

i • 1 • 1 • 1 ' 1 > r-0 2 4 6 8 10

Frequency (GHz)

Fig. 2 The model without the substrate resistances cannot predict the measured Yu characteristics.

Another important component that almost all of the compact models implemented in commercial circuit simulators did not account for is the substrate resistance. Actually, substrate-coupling effects through the drain and source junctions and these substrate resistance components play an important role in the contribution to the output admittance so the inclusion of these substrate components in a RF model is needed. This effective admittance of the substrate network can contribute 50% of the total output admittance.9

As shown in Fig. 2, a MOSFET model without the substrate resistance components cannot predict the frequency dependency of the output admittance of the device so the simulation with such a model will give misleading simulation results of the output admittance when the device operation frequency is in gigaherze range.

1.3. The status of the RF MOSFET modeling

Compared with the MOSFET models for both digital and analog application at low frequency, compact models for HF applications are more difficult to develop due to the additional requirements of bias-dependence and geometry scaling of the parasitic components as well as the requirements of accurate prediction of the distortion and noise behavior. A common modeling approach for RF applications is to build sub-circuits based on the intrinsic MOSFET that has been modeled well for analog applications.,0, " '2The accuracy of such a model depends on how to establish sub-circuits with the correct understanding of the device physics in HF operation, how to model the HF behavior of intrinsic devices and extrinsic parasitics, and how to extract parameters appropriately for the elements of the sub-circuit. A reliable and physics-based parameter extraction methodology based on the appropriate characterization techniques is another important

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portion of the RF modeling to determine the model parameters and generate scaleable

models for circuit optimization. Currently, most RF modeling activities focus on the above subcircuit approach

based on different compact MOSFET models developed for digital and low frequency analog applications, such as EKV,13 MOS9, 6 and BSIM3v3.5 Several MOSFET models for RF applications have been reported.11,12'1415 With added parasitic components at the gate, at the source, at the drain and at the substrate, these models can reasonably well predict theHF AC small signal characteristics of short channel (<0.5nm) devices up to 10GHz.11'15

However the RF MOSFET modeling is still at a preliminary stage compared with the modeling work for dgital and low frequency analog applications. Efforts from both industry and universities are needed to bring RF MOSFET models to a mature level in further improving the RF models in describing the AC characteristics more accurately, and in improving the prediction of noise characteristics, distortion behavior, and NQS behavior.

2. AC Small Signal Modeling

2.1. MOSFET structure and components

As shown in Fig. 3, a four terminal MOSFET can be divided into two portions: intrinsic part and extrinsic part. The extrinsic part consists of all the parasitic components, such as the gate resistance RG, gate/source overlap capacitance Caso, gate/drain overlap capacitance CGDO, gate/bulk overlap capacitance CGBO, source series resistance Rs, drain series resistance RD, source/bulk junction diode DSB, drain/bulk junction diode DDB, and substrate resistances RSB, RDB and RDSB. The intrinsic part is the core of the device without including those parasitics. Even though it would be desirable to design and fabricate MOSFETs without those parasitics, they cannot be avoided in reality. Some of them may be not noticeable in DC and low frequency operation. However, they will influence significantly the device performance at HF.

2.2. Discussion of equivalent circuits of a RF MOSFET

Equivalent circuits have been an effective approach to analyze the electrical behavior of a device by representing the above components. In this section, we discuss the equivalent circuits for both the intrinsic device without the parasitics and the extrinsic device with different parasitic components.

2.2.1 Equivalent circuit for an intrinsic device

For an intrinsic device, AC small signal currents referring to the source of the device can be calculated by the following:

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1012 Y. Cheng

jCCCoGi — jCOCcDl —jCOCaBi

Gm— jCOCoGi GDS+jCOCDDi Gmb~ JCCCDBI

— JCOCBGI —JOCBDI JCOCBBI

vast

VDSi

VBSI

(1)

Where vG5,-, vDSi, and vBSi are the A C voltages at the intrinsic gate, at the intrinsic drain, and

at the intrinsic bulk (all referring to the intrinsic source); J'G„ iDil and iBt are the AC currents

through the intrinsic gate, through the intrinsic drain and through the intrinsic bulk; Gm,

GDS, and Gmb are the transconductance, channel conductance, and bulk transconductance

of the device respectively; Cxyl are intrinsic capacitances between the terminals with the

following definitions:

Gv = dVy

when X & y

Cxy = — ^ when X = y

(2a)

(2b)

RSB P-3™ RDB

Fig. 3 A MOSFET schematic cross-section with the parasitic components.

Eq. (1) can be rewritten as the following

id = JCOCcCiVCSi - jOOCGDiVDSi- j(l)CGB,VBSi (3a)

im = GmVOSi + GDSVDSi + GmbVBSi — jCOCodVaSi + jCOCDDiVDSi — J0)CDBiVBSi

IBi = -jCOCBGVGSi- JQ}CBD!VDSi+ JQ)CBB!VBSi

(3b)

(3c)

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In Eq. (1), we assume that the components between the gate and other terminals can be considered as pure capacitive ones with infinite resistance so the gate current in Eq. (3a) does not contain any conductive current component. Similarly, the components between the bulk and other terminals can be also considered as pure capacitive ones with infinite resistance so the bulk current in Eq. (3c) does not contain any conductive current component. Those assumptions can usually hold for an intrinsic MOSFET because of the very low leakage currents through the gate to other terminals and through the bulk to other terminals in a MOSFET with current advanced technology.

To derive an equivalent circuit from the above equations, we rearrange the above equations in the following forms:

ia = j(oCasiVasi + jaCGDivoDi + J(£CGB<VGB\ (4a)

IDl = {Gm— JG)Cm)VGSi + JWCGDIVDGI + (Gmb — JCOCmb)vSSi + J0>CaDiVDBi + (Gds + J0)CsDi)VDSi

(4b)

Ui = j(X)CmgbVGBi + j(0 CBSiVBSi + j(OCGBiVBGi + J0i)CBDiVBDi (4c)

where C„, Cmb and Cmgb are the differences of the transcapacitances between the drain and the gate, between the drain and the bulk, and between the gate and the bulk, and given by

Cm = CoGi— CGDi (5a)

Cmb = CDBi— CBDi (5b)

Cmgb = CGBi — CBGI ( 5 C )

CSDI and Cfls,are intrinsic trancapacitances between the source and the drain, and between the bulk and the source and have the following relationships with other capacitances

CsDi= CDDI— CBDI— CGDJ (6a)

Cssi = CBBI—CBGI— CBDI (6b)

According to the equations given in Eq. (4), an equivalent circuit (EC) referring to the source can be derived as shown in Fig. 4.

Different from the low frequency AC small signal EC, several current components contributed by the transcapacitances cannot be ignored at HF and they are included in the EC in Fig. 4.

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1014 Y. Cheng

Gi

CGB :r: _ CGS

CBS T O

(Gn-jwCm)vCS/

-e— (GDS+j WCSDi)vDSi

-© (Gmb-JHCmb )vBSi

• e — jwCmgbvflSi

O Bi

-,- CGD

Di -0

-T- CBD

Fig. 4 /4n equivalent circuit for an intrinsic MOSFET.

2.2.2. Equivalent circuit for the device with extrinsic capacitances

As shown in Fig. 3, parasitic capacitances such as the overlaps of gate-to-source/drain/bulk and the junction capacitances from the source/bulk and drain/bulk diodes are not negligible in a MOSFET and must be included in the EC to describe the device behavior at HF. With the inclusion of those extrinsic capacitances, the EC for a MOSFET can be given in Fig. 5. The EC in Fig. 5 can be further simplified to that in Fig. 6 by merging the intrinsic and extrinsic capacitances together, that is,

CGS= CGSI+CGSO

CGD = CGDI+ CGDO

CGB= CGBI+CGBO

CBS — CBSI + CJBS

CBD = CBDI + CJBD

(7a)

(7b)

(7c)

(7d)

(7e)

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CGBo CGBi

I

(Gm-jnGn)vGS

-e-_ _ _ _ COD.

T T O

(CPS+jWCSDj)VDSi

-e-— (Qnb-j^CmbJvMi

-e— I jHCmgbl'flS;

Bi

Fig. 5 Equivalent circuit of an intrinsic MOSFET plus extrinsic capacitances.

„ Gi

CGB ~_

CBS

CGS

T O

(Gm-j wCm)vOSi

-© (G>S+jwCSDi)vDS

- e — (Gmb-jwCmb)v»-n

- e — jwCmgbvBSi

6 Bi

COD

Di - O

ZZ CBD

Fig. 6 Another simplified representation of equivalent circuit in Fig. 5.

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1016 Y. Cheng

2.2.3. Equivalent circuit for the device with parasitic resistances

In a MOSFET model for DC and low frequency applications, the parasitic resistances at the gate and substrate can be ignored with little influence on the simulation accuracy. Usually, the parasitic resistances at the source and drain can be treated as "virtual" components by incorporating them in the /-Kequation to account for the influence of the voltage drops at those resistances.5, 6 At HF, however, these parasitic resistances will influence the device performance significantly and they all should be modeled and included in the equivalent circuit for the device.

The gate resistance is in principle a bias-independent component at DC and low frequency, but may contain the contribution of an additional component with bias dependence at HF.8 The parasitic resistances at the source and drain consists of several parts as we will discuss later and can be also treated as a bias-independent component even though they do have some bias dependence depending on the device structure and process conditions. The resistances in the substrate can be modeled by different EC networks, such as 5-resistor network, 4resistor network,'2 3-resistor network,11,16 2-resistor network,13 and 1-resistor network,17 as shown in Fig. 7. The 4 and 5 resistor networks are more accurate and can be valid up to higher frequency, but the analysis and parameter extraction of the components are very complex. The 1- and 2-resistor networks introduce fewer components and are easier for the analysis and parameter extraction. However, they may be less accurate when the operating frequency goes to higher frequency.18 The 3-resistor network is a compromise among these substrate networks. It can ensure the accuracy up to 10GHz while maintaining a simple analysis and parameter extraction. However, it should be pointed out that the intrinsic bulk has been shifted to the end of RDSB, as shown in Fig. 7 (c), instead of located somewhere along the resistor RDSB. It has been concluded that this approximation does not influence much the simulation accuracy.11,14

With further consideration of parasitic resistances at the drain, at the gate, at the source, and at the substrate, a complete lumped equivalent circuit for a MOSFET at HF can be given in Fig. 8.

(Intrinsic source) (Intrinsic source)

Si, Su o Di

r -^VvV-L-^VVV—i-^Wv—L-WV-| RSB RDSB1 L RDSB2 RDB

S RDSB3

Fig. 7 (a) Five-resistor substrate network.

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(Intrinsic source)

a. (Intrinsic Drain)

Di I I rÂAAr-J-^VVV-£W\Ar--^\AA^-i

RSB RDSBI RDSB2 RDB

Fig. 7 (b) Four-resistor substrate network.12

(Intrinsic source) Si

(Intrinsic drain) Di 1 1

• O B C ° B .

—I V\A. 1—ww-i r^WV RSB Bi RUSH RDB

Fig. 7 (c) Three resistor substrate network."

(Intrinsic source)

1 (Intrinsic drain)

p Di

CSB

RSB i

CDB

RDB

B Fig. 7 (d) Two-resistor substrate network."

131

1018 Y. Cheng

(Intrinsic source) (Intrinsic drain)

>SB Q)B

RSI :UB

B

Fig. 7 (e) One resistor substrate network.1

r~ (Gm-j>*Cm)K»

- e — (QK+j»CsDi)vas/

- e — (Gmb-j»Cmb) vs#

-e-

RDSB

^ / W O

Fig. 8 An equivalent circuit with both intrinsic and extrinsic components.

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2.2.4. Implementation of a subcircuit RF model in circuit simulators

The equivalent circuit shown in Fig. 8 can be used to understand and analyze the HF behavior of a MOSFET. In order to implement this equivalent circuit in a Spice simulator, a subcircuit approach has to be used. In the subcircuit, the characteristics of the intrinsic device is described by a MOS transistor compact model implemented in the circuit simulator, and all the extrinsic components have to be located outside the intrinsic device, so that the MOS transistor symbol in the subcircuit only represents the intrinsic part of the device \ For example, (1) the source and drain series resistors have been added outside the MOS intrinsic device to make them visible in AC simulation (in most compact models, since the internal series resistances are only "virtual" resistances embedded in the I-Vmodel to account for the dc voltage drop across the source and drain resistances in calculating the drain current, they do not add any poles and are therefore invisible for AC simulation); (2) The gate resistance should be added to the subcircuit model (usually RG is not part of the MOS compact model, but plays a fundamental role in RF circuits as we discussed in Section 1); (3) The substrate resistors should be added to account for the signal coupling through the substrate; (4) Two external diodes should be added in order to account for the influence of the substrate resistance at HF (the source-to-bulk and drain-to-bulk diodes are part of the compact model but their anodes are connected to the same substrate node, which will short the AC signal at HF12 so the diodes internal to the compact model should be turned off). With the above considerations, a subcircuit that represents a RF MOSFET in a circuit simulator can be given in Fig. 9. Note that the intrinsic substrate node should be connected at some point along the resistor RDSB, but simulations have shown that connecting the intrinsic substrate to the source or the drain side has little influence on the simulated AC parameters. In some RF models,9-" the intrinsic substrate has been connected to the source side of in order to save one node and one component for the subcircuit model. Two external overlap capacitances, CGSP and CGDP as shown in Fig. 9, with bias dependence can be added but this is not always required, depending on the compact model used. For example, BSIM3v3 accounts for bias dependent overlap capacitances that, if extracted correctly, have shown a sufficient accuracy. However, by adding these external capacitances, the inaccuracies of the intrinsic capacitance model appearing for short-channel devices can be corrected. In the next section, we will discuss the modeling of these intrinsic and extrinsic components shown in Fig. 8.

2.3. Modeling of the intrinsic MOSFET

Compared with the MOSFET modeling for digital and low frequency analog applications, the HF modeling of MOSFETs is more challenging. All of the requirements for a MOSFET model in low frequency application, such as continuity, accuracy and scaleability of the

It may include the overlap capacitances at the source, at the drain and at the bulk, depending on the intrinsic compact MOSFET model used in the implementation.

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1020 Y. Cheng

DC and capacitance models should be maintained in a RF model." In addition, there are further important requirements to the RF models: (1) The model should accurately predict bias dependence of small signal parameters at HF operation; (2) The model should correctly describe the nonlinear behavior of the devices in order to permit accurate simulation of inter-modulation distortion and high-speed large-signal operation; (3) The model should correctly and accurately predict HF noise which is important for the design of, e.g., low noise amplifiers (LNA); (4) The model should include the NQS effect so it can describe the device behavior at very high frequency range in which NQS effect cannot be ignored for a model to behave correctly and will degrade the device performance significantly; (5) The components in the developed equivalent circuit model should be physics-based and geometrically scaleable so that the model can be used in predictive and statistical modeling for RF applications.

J: Rs

-AA/V JV

• Ro Core/Intrinsic MOSFET

CGSPJ_ • _iL. • .I^J_CGDP

CSB

l—AA/V

' Substrate Network

/W\r RSB RDSB

AAAr-i RDB

B B

fig. 9 A subcircuil that can be implemented in a circuit simulator.

To achieve the above, the model for the intrinsic device should be derived with the inclusions of most (if not all) important physical effects in a modern MOSFET, such as normal and reverse short-channel and narrow width effects, channel length modulation, drain induced barrier lowering (DIBL), velocity saturation, mobility degradation due to vertical electric field, impact ionization, band-to-band tunneling, polysilicon depletion, velocity overshoot, self-heating, channel quantization." Also, the continuities of small signal parameters such as transconductance Gm, channel conductance G&, and the intrinsic trancapacitances must be modeled properly. Many MOSFET models, including MOS9,6 EKV,20 and BSIM3v35 have been developed for digital, analog and mixed signal

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applications. Recently, they all are extended for use in RF applications. We do not present any new models in this work. Instead, in the following, we give a brief discussion on the concept of deriving a compact model of the intrinsic device for RF applications.

A compact model includes many mathematical equations for different physical mechanisms. The most important and essential parts are DC and capacitance models. It has been found that the model accuracy in fittings of HF small signal parameters and large signal distortion of a RF MOSFET is basically determined by the DC and capacitance models.21

2.3.1, DC model

In general, a DC MOSFET model is derived based on the following

Jn = qiimE + qDn V« (8)

JP = q^pE-qDpVp (9)

where J„ and Jp are the current density for electrons and holes respectively; q is the electron charge; n, and /j, are the mobilities for electrons and holes, respectively;« is the electron concentration in the channel; p is the hole concentration in the channel; £ is the electric field; D„ and Dp are the diffusion coefficients for electrons and holes, respectively. D„ and .Dp link tojn and y, with the following equations:

Dn = V,Hn (10)

Dp = viflP (11)

where v, is the thermal voltage. The first terms in Eqs. (8) and (9) describe the drift current components due to

the electric filed E. The second terms describe the diffusion current component due to the carrier concentration gradient. In the strong inversion region, the total current is dominated by the drift current. In the subthreshold region, the diffusion current component dominates. However, in the transition region (moderate inversion region) from subthreshold to strong inversion, both drift and diffusion currents are important, and need to be included in the model.

As shown in (8) and (9), the electric field E, carrier density, and mobility are the basic factors determining the current characteristics. The electric field E can be obtained by solving the Poisson equation

V > = — £ - (12)

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1022 Y. Cheng

where 0is the electrostatic potential; p i s the charge density including electron, holes, and other charges in the interesting region of the device. However, to get analytical solutions for I-V models, simplified approaches are needed to consider the influence of the electric field in compact modeling."

Besides the proper consideration of the electric field, the channel charge and mobility need to be modeled carefully to describe the current characteristics accurately and physically, based on which, different physical effects can be added in the I-V model.

In modeling the channel charge, physical effects such as short channel effect, narrow width effect, non-uniform doping effect, and quantization effect etc. should be accounted for in order to describe the charge characteristics accurately in today's devices. There are two types of charge models, one can be called threshold-voltage (Vlh)-based models, another can be called surface-potential (y*)-based models, yf-based charge models are based on the analysis of the surface potential that will appear in the I-V model to describe charge characteristics with the influence of many physical effects.22 F,A-based charge models are derived also by solving the surface potential with the consideration of those physical effects, but finally V,h is used instead of 1/4 in the charge (and hence I-V) model to account for the influence of some process parameters such as oxide thickness and doping and device parameters such as channel length and width.5'6,20 In both models, the continuities of the charge and its derivatives should be modeled carefully for the I-V model to have good continuity and to predict correct distortion behavior of the devices.

A F,A-based charge model used in BSIM3v3 is given in Eq. (13) as an example. As shown in Fig. 10, the model fits the measured data of the channel charge and ensures the continuity of the channel charge from strong inversion to the subthreshold regions.23 Fig. 11 shows the continuity of the ^ ^ ( a n d hence the charge model as given in Eq. (13) and its first and second derivatives.19

Qchs o = Cox Vpieff (13a)

2nv/ln

VgsKff =

VGS-V,H, l+exp(— )

2nvi l„CoX\^.

^ qe,iN

(13b)

1 + 2nCox I—-—exp( —) îNd, 2nvi

Here Cox is the unit area oxide capacitance; n is the subthreshold swing factor; Nch is the doping concentration in the channel; Voff\s a fitting parameter; " Vas is the gate voltage; V,h is the threshold voltage; vt is the thermal voltage; q is the electron charge; £,, is the dielectric permittivity of the semiconductor; and $ i s the surface potential when Vgs=Vlh,

and is given by

0 s = 2 v , l n ( - ^ - ) (1 3 c)

where Nch is the doping concentration in the channel;«, is the intrinsic carrier density.

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lO itt

1 0 - " •

.2 o o GJ

io-13 ;

10-

10-'

N =ax ia i e

OS OO OS 1.0 1-5 2X1 2.5 3 0 3 5

VGS(V)

Fig. 10. The charge model covers the weak, moderate, and strong inversion regions of MOSFETs.23

The second derivative of VgsUff vs. VGS

The first derivative of Vgsiaff vs. VGS

Vgstsff .

ft******** *****

•1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 yos(V)

Fig. 11. The continuities of the charge model and its derivatives are needed in different operation regimes."

Mobility is another key parameter in MOSFET modeling. It will influence the accuracy and distortion behavior of the model significantly.19,24 The relationship between the carrier mobility and the electric field in MOSFETs has been well studied.25,26 Three

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1024 Y. Cheng

scattering mechanisms have been proposed to describe the dependence of mobility on the electric field.27 Each mechanism may be dominant under specific conditions of doping concentration, temperature and biases as shown in Fig. 12.

Effective Field Eeff

Fig. 12 Mobility behavior influenced by different scattering mechanisms, depending on the bias and

temperature conditions.27

In strong inversion, mobility depends on the gate oxide thickness, doping concentration, threshold voltage, gate and substrate biases. In weak inversion, it is usually modeled as a constant. Thus, continuity of the mobility model is also required to ensure the continuity of the /-K model. In BSIM3v3, a mobility expression based on the Vêff given in Eq. (13) is used,

fJ, (14)

1+(U.+UCVBSX ) + Ub{ ) J ox I ox

where ^& Um Ub and Uc are fitting parameters extracted from measured data; V,h is the threshold voltage; Tox is the gate oxide thickness."

With Vg5leff\n Eq. (13), the mobility model given in Eq. (14) is continuous from strong inversion to weak inversion. It has been known that the I-Vmodel based on Eq. (14) can predict the distortion behavior of the devices.21 Recently, other detailed analysis of the influence of the mobility model on the distortion behavior of the 7-Kmodel has also been reported.24 In Fig. 13, is shown the comparison of characteristics of Gm and its derivatives versus gate bias between the model and measured data for a device of 5fim

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channel length, with the consideration of the distortion behavior of the mobility model.24 It has been realized that an accurate and physical description of a mobility model in compact MOSFET RF models for circuit simulation is essential for distortion analysis. It is also suggested that different models for electron and hole mobilities should be developed because of the difference in quantum-mechanical behavior of electrons and holes in the inversion layer in today's MOSFETs.24

%. " 6* * l«

•90 r

-ISO " " • " • ^ « • » » • . - < « » . i

- H O »!»««»

S S n i ^ i ^ ^ • . • i -1 *

m -120

-130 *** ,:-***•' •rnxs*******

,rf-r ; -i-%>/-- t » ' - - V / - - - f - - - } - - - - --:•

lOB 2.50 3.00 3.30 *M 4.50 5.00 5.50 6.00

.if

VcsCV)

Fig. 13 Measured (symbols) and modeled (lines) behavior of Gm and its first and second derivatives as a function of VGS for an n-channel MOSFET with a width of lOum and length of 5\im at fis=0V.24

Based on the charge and mobility models, complete I-V equations can be developed with further inclusions of many important physical effects such as short channel and narrow width effects, velocity saturation and overshoot, poly-depletion effect, quantization effect, and so on. In order to meet the requirements for both AC small signal and larger signal applications, the continuity and distortion behavior of the I-V model should be ensured in deriving the equations when including these physical effects.

2.3.2. Capacitance model

In real circuit operation, the device operates under time-varying terminal voltages. Depending on the magnitude of the time-varying signals, the dynamic operation can be classified as large signal operation and small signal operation. Both types of dynamic operation are influenced by the capacitive effects of the device. Thus, a capacitance model is another essential part of a compact MOSFET model for circuit simulation.

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1026 Y. Cheng

Many MOSFET intrinsic capacitance models have been developed. Basically, they can be categorized into two groups. (1) Meyer and Meyer-like capacitance models and (2) charge based capacitance models.28,29 The advantages and shortcomings of the two groups of model have been well discussed and both of them have been implemented in circuit simulators. The Meyer and Meyer-like models are simpler than charge-based models so they are efficient and faster in computations. But they assume that the capacitances in the intrinsic MOSFET are reciprocal, which is not the case in real device,"and earlier models based on this assumption cannot ensure the charge conservation.19'30 Charge-based models ensure the charge conservation and consider the non-reciprocal property of the capacitances in a MOSEFT. These features are required to describe the capacitive effects in a MOSFET, especially for RF applications where the influence of trans-capacitances are critical and should be considered in the model. But usually the charge-based capacitance models require complex equations to describe all of the 16 capacitances in a MOSFET with four terminal, as given in the following,

Q=^SL i*j,ij=G,D,S,B (15) d/,j

Cj = - ^ L i=j (16)

The development of an intrinsic capacitance model of modern MOSFETs is another challenging issue in RF modeling. To meet the needs in RF applications, besides ensuring charge conservation and non-reciprocity, an intrinsic MOSFET capacitance model should at least have the following features such as (1) guaranteeing model continuity and smoothness in all the bias regions, (2) providing model accuracy for devices with different geometry and different bias conditions, and (3) ensuring model symmetry at the bias of VDs=(N.

Some comparisons between the MOSFET capacitance models and the measured data have been reported.31 However, a complete verification of the bias and geometry dependencies of those capacitance models has not been seen. It has been found that some engineering approaches have to be used to improve the accuracy of the capacitance model if the intrinsic capacitance model cannot describe the device behavior accurately.32

Recently, the model continuity has been improved greatly. Many discontinuity issues in earlier capacitance models have been fixed.33 However, most capacitance models still cannot ensure the model symmetry when VDs=0. In Fig. 14 and 15, the asymmetries of the capacitance model in BSIM3v3 are shown for CGs=CGD, Q>0 and C^, and for CBD and CBS.

i9 It has been known that a MOSFET should be symmetric for some capacitances at VDs=0, i.e. CDD=Css and CBD=CBS. The asymmetric issue in the capacitance model is apparently non-physical and may cause convergence and accuracy problem in the simulation. This issue may become more critical in the model for RF applications because the devices are often biased in the region of KDS=0V in some applications such as switching. Efforts have been made based on the source-referenced approach, the bulk-referenced approach and surface potential oriented approaches to improve the symmetry property of the models.34 The development of advanced capacitance models with good

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continuity, symmetry, accuracy and scalebility is still a challenge for the model developers.

V D S (V)

Fig. 14 Simulated Css and CDD as a function of VDS- Css *€DD when VDS-0. "

^ 8

O

£ 'a o B o

0.2 -

0.1 -

0.0 -

-0.1 "

-0.2-

-0.3-

-0.4-

-0.5-

• \ T \ 1 . . . . y f

1 t/SD

1

O s s

W/L=10/0.5

V B S = O V

0.0 1.0 1.5 2.0

VDS(V)

2.5

Fig. 15 Simulated Css and CDD as a function of VDS. CBS ^BD when VDS~0.'9

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1028 Y. Cheng

2.4. Modeling of the extrinsic MOSFET

For an AC small signal model at RF, the modeling of parasitics is very important. The models for these parasitic components should be physics-based and linked to process and geometry information to ensure the scalability and prediction capabilities of the model. Also, simple sub-circuits are preferred to reduce the simulation time and to make parameter extraction easier.

Besides a development of a physical and accurate intrinsic model discussed above, the following issues should be considered in developing a MOSFET model for deep submicron RF applications:

1) The gate resistance should be modeled and included in the simulation. 2) The extrinsic source and drain resistances should be modeled as real external

resistors, instead of only a correction to the drain current with a virtual component.

3) Substrate coupling in a MOSFET, that is, the contribution of substrate resistance, needs to be modeled physically and accurately using approriate substrate network for the model to be used in RF applications.

4) A bias dependent overlap capacitance model, which accurately describes the parasitic capacitive contributions between the gate and drain/source, needs to be included.

2.4.1. Modeling of gate resistance

At DC and low frequency, the gate resistance consists mainly of the poly-silicon sheet resistance. The typical sheet resistance for a polysilicon gate ranges between 20-40 £2/square, and can be reduced by a factor of 10 with a silicide process, and even more with a metal stack process. At HF, however, two additional physical effects appear, which will affect the value of the effective gate resistance. One is the distributed transmission line effect on the gate, and another one is the distributed effect or NQS effect in the channel.8,35

The distributed transmission line effect on the gate at HF has been studied.7 It will become more severe as the gate width becomes wider at higher operation frequency. So multi-finger devices are used in the circuit design with narrow gate width for each finger to reduce the influence of this effect. A simple expression of gate resistance, R0, based on that in DC or low frequency has been used to calculate the value of gate resistance with the influence of the distributed gate effect (DGE) at HF. However, a factor of a is introduced, which is 1/3 or 1/12 depending on the layout structures of the gate connection to account for the distributed RC effects at RF, as given in the following,

Rc.^^XZL^+Ot) (17) N/Lf a

where RGsh is the gate sheet resistance, ffyis the channel width per finger, Lf is the channel length, and Aîs the number of fingers, Wex, is the extension of the poly-silicon gate over the active region.

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Complex numerical models for the gate delay have been proposed. However, the simple gate resistance model with the a factor for the distributed effect has been found accurate up to VfTfov a MOSFET without significant NQS effects."

The NQS effect or the distributed RC effect in the channel is another effect that should be accounted for in modeling the HF behavior of a MOSFET. For the devices with NQS effects, additional bias and geometry dependences of the gate resistance are needed to account for the NQS effect.8,35 It has been proposed that an additional resistive component in the gate should be added to represent the channel distributed RC effect.8

As discussed above, when a MOSFET operates at high frequencies, the contribution to the effective gate resistance is not only from the physical gate electrode resistance but also from the distributed channel resistance, which can be "seen" by the signal applied to the gate, as shown in Fig. 16. Thus, the effective gate resistance RG consists of two parts:

Ra =Ra. poly +Ra, mis (18)

where Ra.poiy is the distributed gate electrode resistance from the poly-silicon gate material and is given by Eq. (17), RG.^ is the NQS distributed channel resistance seen from the gate and is a function of both biases and geometry.8,35

Fig. 16 Equivalent gate resistance consists of the contributions from the distributed gate poly resistance

and distributed channel resistance.S3S

The HF characteristics of the gate resistance have been studied.35 In Fig. 17, it is shown that RG decreases first as Lf increases while showing a weak bias dependence in this region, then starts to increase with £/as Lf continue to increase above 0.4um while showing a strong bias dependence. The Lf dependence of Ra varies for different VGS. At lower VGS, the Lf dependence of Ra is stronger. Also, RG for the devices with longer Lf

increases significantly and has stronger VGs dependence. Fig. 18 shows the Wf

dependence of RG. It demonstrates that Ra increases as W -decreases when Wf<6\\m, and the device with the same Wf has higher RG at lower VGS, which becomes more obvious when Wf narrows. Figs. 19 and 20 give RG for devices with various geometries at several VDS, from which we observe similar Lf and Wf dependencies of RG as what we found in

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1030 Y. Cheng

Figs. 17 and 18. However, the VDS dependence of RG becomes very weak when VDS is larger than IV.

o CD O c ra jOl 'tn o a.

50

30

20

CO

C3

VGS=0 .8V .

1.0 1.2 1.6

,w Fig. 17 Curves of Ra versus Lfat different VGS. The dotted lines illustrate approximately the dependence

ofRG,poiy portion on 1/Lf, and the dependence ofRGnqs portion on Lf respectively.35

E c O

0)

o

VQjfO.SV V =1.0V V5.1.BV

L=0.18(im Nf=10

frequency=2GHz

vDS=iov V„c=0V

4

w , W

Fig. 18 Curves of Rc versus Wtat different VGS. The dotted lines illustrate approximately the dependence

ofR0,pofy on Wf, and the dependence ofRGnq, on 1/Wp respectively. 3i

The U-shape Independence of RG in Fig. 17 can be explained with the consideration of the DGE and the NQS effect, in RF MOSFETs. It has been well known that the resistance of a poly-silicon resistor, simulating the ploy-silicon gate in a MOSFET, is 3 or 12 times smaller (depending on the layout) at HF due to the DGE than that at DC but still scales with W/Lf. It has also been known that the NQS effect occurs in

144


a MOSFET operated at HF in which the carriers in the channel cannot respond to the signal immediately. Thus, there is a finite channel transit time for the distributed effect of the carrier transportation in the channel due to the varying gate signal. In that case, the signal applied to he gate suffers an additional equivalent gate resistance, which is proportional to L/Wj, from the distributed channel resistance, which adds to the contribution from the poly-gate resistance. In another word, Rc consists of two parts: the RG.poiy contributed by the poly-gate resistance and the RGnils due to NQS effect. As NQS effect becomes more significant, the contribution of RGm,s dominants. This is the case in devices with longer Lf. Thus, we can understand the irregular geometrical dependence of Ra in Fig. 17 when L;is longer than 0.4um. It has been shown that the channel transit time for the NQS effect is roughly inversely proportional to (Vcs-V,i,), where V,h is the threshold voltage of the device, and proportional to Lf

2.34 Thus, RG,„V (and hence RG) is higher in a device with longer Lf and at lower VGS. As shown in Fig. 17, the NQS effect has begun to influence RG values in devices with relatively short Zyat RF. However, when Lfis short enough, the contribution of RGlMp is smaller and RGxP0iy is dominant. In that case, RG

becomes larger as Lf tends to be shorter.

Similarly, we can understand the ^dependence of RG in Fig. 18. As discussed above, the RG portion from the distributed poly-silicon gate, RGpoty, is proportional to WJLfi

however, the RG portion from the distributed channel, RGm,s, is proportional to LjlWf. As Wf

becomes narrower, RGmp becomes higher so it may dominate the total RG when ^ reduces to some value, say 6um in Fig. 18. As Wf becomes wider, RGpofy becomes higher so it may dominate the total RG after Wf is larger than some specific value. Thus, as Wf changes, there exists a minimum RG at some point of Wfi as demonstrated in Fig. 18.

The stronger VGS dependence of RG in the narrow Wf region of Fig. 18 can be understood because RG.„^S with strong bias dependence is dominant in the narrower device while RG,poiy without bias dependence plays a bigger rule in the longer ^region.

The VDS dependence of RG shown in Figs. 19 and 20 can be explained also. It is known that the distributed effect at the gate is independent of VDS and the distributed effect in the channel is stronger in the saturation region than in the linear region. Thus, according to the above analysis, we should have lower RG,nqs (and hence RG) at VDs=0.5V, at which the device operates in the triode (or linear) region, than VDS =1V, at which the device operates in the saturation region, for the device with the same H^-andL/. When VDS

is higher than IV, the device remains in saturation and the channel conductance (and hence the NQS effect) does not change much as VDS increases, so.Rcis insensitive to VDS

(>1V) in Figs. 19 and 20. Efficient and accurate modeling of the NQS effect in MOSFETs is very

challenging. A RG model with the consideration of NQS effect has been reported.8

However, the following simple expression can be used to obtain the Ra,nqs approximately in the strong inversion regime,

RG.«,= P- (19) Gm

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1032 Y. Cheng

where Gm is the transconductance of the device, P is a fitting parameter with a typical value around 0.2.

E .c O CD o c 3 22 CO

<D

a: <o

* - » CO

O

40

30

20

10

Wf=6um Nf=10 VDg=1.5V

-i 1 1 1 1 1 1 1 r 1 1 1 1 1 1-0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6

L d r a * n ( ^ )

Fig.19 Curves ofRG versus Lfat different VDS-3!

40

15

* — — 1 .

r-Sl O CD CJ c CO

sis

a> OH

2 CO O

35-

30-

25-

20-

VDS=1.5V

V =1.0V

V =0.5V DS

4 6

Wd r a w n (um)

Ldrawn=0.18um Nf=10

frequency=2GHz

10

Fig. 20 Curves o/Ra versus W;at different V^.'

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2.4.2. Modeling of source and drain resistances

The total source and drain series resistances in a MOSFET used in IC designs have several components such as the via resistance, the salicide resistance, the salicide-to-salicide contact resistance, and the sheet resistance in the LDD region, as shown in Fig. 21. However, the contact and LDD sheet resistances usually dominate the total resistance. The typical value of the sheet resistance is around lkii/square in the LDD region for a typical 0.25um CMOS technology and much smaller in more advanced technologies.

Rvia

Rsalicide

Fig. 21 An illustration of the components of the source/drain series resistance.

It has been known that the source/drain resistances are bias dependent. In some compact models such as BSIM3v3,5 these bias dependencies are included. However, since these parasitic resistances in BSIM3v3 are treated only as virtual components in the I-V expressions to account for the DC voltage drop across these resistances, they are invisible to the signal in the ac simulation. Therefore, external components for these series resistances need to be added outside an intrinsic model to accurately describe the HF noise characteristics and the input AC impedance of the device." Typically, the source/drain resistances RD and Rs without including any bias dependence can be described by:

RD = RDO +

R, = R,o +

rdv

NfW,

NfW/

(20a)

(20b)

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1034 Y. Cheng

where r^ and rm are the parasitic drain and source resistances with unit width, RD0 and Rso account for the part of the series resistances without the width dependence. Eq. (20) can work reasonably well in today's MOSFETs for RF applications, because the LDD region in these devices with advanced technologies (0.18um and less) has a very high doping concentration. Thus, the bias dependence of RD and Rs becomes weaker compared with devices with longer channel lengths and lighter LDD doping concentrations in the older technology generation.

2.4.3. Modeling of substrate resistance

The influence of the substrate resistance is usually ignored in compact models for digital and analog circuit simulation at low frequency. However, at high frequencies, the signal at the drain couples to the source and bulk terminals through the source/drain junction capacitance and the substrate resistance. The substrate resistance influences mainly the output characteristics, and can contribute as much as 20% or more of the total output admittance.9,11 Recently, several studies on the modeling of substrate components were reported. Different substrate networks have been proposed to account for the influence of substrate resistance at RF.11"17

It has been known that the substrate components become distributed at HF. Although it is always desirable to have a detailed distributed RC network to account for the contribution of the substrate components, it is too complex to be implemented in a compact model. Some simulation tools using 3 dimensional or quasi-3-dimensional numerical approaches to simulate the effects of the substrate resistance are available; however, a proper integration of such a tool into the design system remains an issue. Also, the accuracy of the simulation results is dependent on the accuracy of the process information provided by process simulation, which needs to be calibrated carefully and is time-consuming to obtain the desired accuracy. Thus, a good compromise is still to use a lumped RC network, if it is accurate in the required operation frequency range, to simulate the contribution of the substrate components.

A simple equivalent circuit for the substrate network shown in Fig. 7 (c) has been used to analyze the HF substrate-coupling-effect and the characteristics of substrate resistance at HF.37 Even though a simpler substrate network has been reported,17 it is found that the 3-resistor substrate network can ensure better model accuracy in a higher frequency range.18

Generally, assuming that the device is symmetric between source and drain and that it has no difference between the outer and inner source/drain regions in a multi-finger device, we have

RDSB=rjmk. (2i) N/Wf

where rA4 is the sheet resistance in the substrate between the source and drain. According to the layout, RSB andi?Bfl should be functions of the channel width of

the device. The following equations have been proved by the measurements for the

148


devices with substrate ties, in parallel 0 the gate, outside the source/drain regions

(isolated by shallow trench between the substrate ties and the active region),

RDB»— (22a) Wf

RSB»— (22b) Wf

where rdbw and rsbw are the substrate resistances per unit-channel-width. Some bias dependence of the substrate resistances had been expected, based on

the fact that the depletion regions below the gate and surrounding the source and drain diffusions may vary at different gate and drain bias conditions." However, it has been found that the bias dependence of the substrate resistances is actually very weak for the devices with substrate ties isolated by shallow trench from the active region, and the above simple substrate resistance network is accurate up to 10GHz.18,37

2.4.4. Modeling of parasitic capacitances

As shown in Fig. 22, the parasitic capacitances in a MOSFET can be divided into the following components. (1) The outer fringing capacitance between the polysilicon gate and the source/drain, CF0; (2) the inner fringing capacitance between the polysilicon gate and the source/drain, CFI; (3) the overlap capacitances between the gate and the heavily doped S/D regions (and the bulk region), CGSO & CGDO (CCBOX which are relatively insensitive to terminal voltages; (4) the overlap capacitances between the gate and lightly doped S/D region, CGSOL & CGDOL, which change with biases; (5) the source/drain junction capacitances, CJD & CJS; and (6) the substrate capacitance, CSUB- Most of them have been included in models for digital/analog applications." However, additional parasitic capacitance components may have to be added to the existing models (either intrinsic or extrinsic capacitance models) if they cannot meet the accuracy requirements at RF.

In Figs. 23 and 24, the capacitances CGDP and CGSF obtained from the total capacitances extracted from the measured s-parameters and the intrinsic capacitances simulated with the model are shown. The definitions of C0DP and CGSP are given in the following

CGDP = CGDtotal_ extracted— CGDimrinsic _ simulated (23)

CGSP = LtGStotal _ extracted ~ L^GS intrinsic _ simulated f 2 4 1

where CGDtomi extracted is the total CGD capacitance extracted from the measured data; ^GDintrinsic simulated *S the intrinsic CCD simulated by the model; CGs,0iai_exiracted is the total CGS

capacitance extracted from the measured data; Casnirmsicjimuiated is the intrinsic CGS

simulated by the model.

1 4 9

1036 Y. Cheng

P-sub

B

Fig. 22 Illustration of different capacitance components in a MOSFET.

Depending on the accuracy of the intrinsic capacitance model and the device geometry, the values of CGDP and CGSP may be larger or smaller than those values shown in Figs. 23 and 24. According to the definition of CGDP and CGSP, we can consider these capacitances as overlap capacitances if the intrinsic capacitance model is accurate enough. However, in some cases, CGDP and CGSP should not be considered as overlap capacitances since they may contain the correction to the intrinsic capacitances if the intrinsic capacitances are not properly modeled. It is clear that C0DP and CGSP have strong bias dependences that cannot be fitted by a constant overlap capacitance model. To improve the overall RF model accuracy, an engineering approach, adding additional capacitance components with bias dependence for CGDP and CGSP in the subcircuit, can be used if the capacitance model in a RF model cannot provide good accuracy over different bias regions.

The substrate capacitance is another extrinsic capacitance that should be considered in a subcircuit model for ultra HF applications. In the above substrate RC network, we did not include the contribution of the substrate capacitance. It does not influence the model accuracy to fit the measured data up to 10GHz. However, the substrate capacitance component may be necessary in a subcircuit model when the device operates at frequencies much higher than 10GHz.

150


3.0xi(rM.

2.8X10-14.

2.6X10"14-

2.4x10"14-

2.2X10"1*-

Nf lO

W=6Mm

m D=0.1fym y ^ V V„=1.5V

• V [ B =iov

• V =0.5V

CS

VGS<V>

Fig. 25 An example to show the bias dependence of extracted equivalent extrinsic capacitance between

the gate and the source from measured HF data at different drain biases.32

Fig. 24 An example to show the bias dependence of extracted equivalent extrinsic capacitance between

the gate and the drain from measured HF data at different drain biases.32

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1038 Y. Cheng

2.5. Parameter extraction for IC design

2.5.1. RF measurement and de-embedding techniques

For a model to describe the device characteristics accurately, all important model parameters should be extracted from the measured data. To extract the RF model parameters, on-chip HF measurements are performed by using specifically designed test structures. Also, a de-embedding methodology has to be developed to remove the influence of the parasitics in the test structure from the measured raw data in order to obtain the data for the characteristics of the device-under-test (DUT).

Figure 25 illustrates the setup of a HF measurement system for on-wafer RF measurements. A controller is used to send the commands to instruments (vector network analyzer (VNA) and /-Ftester etc.) and the probe station to perform the measurements for a specific DUT, and to gather the measured data for post-processing. To ensure the accuracy of the measurement, a system calibration has to be performed before conducting any measurements on DUT. Typically, the system calibration for on-wafer measurements is done by using a so-called impedance standard substrate (ISS) that can provide high-accuracy and low-loss standards for two-port calibration procedures such as SOLT (short-open-load-through) and TRL (through-reflect-line). The SOLT calibration has been widely used because it is supported by virtually every vector network analyzer. However, TRL calibration is the most fundamental of the advanced calibrations and requires the least amount of information about the standards. Only VNA with advanced calibration capability will support the TRL calibrations. ISS calibration can ensure reasonable accuracy if the substrate and interconnect losses of the DUT are comparable to those of the ISS. Recently, however, it has been discussed that additional de-embedding of substrate parasitics in RF CMOS devices may be needed because of the high substrate losses compared with other devices such as GaAs MESFETs.

VNA/TV Tester Probe Station (DUT)

V. J \ /

Fig. 25 Equipment requirement of a HF measurement system.

Besides the system calibration discussed above, de-embedding methodology for raw data measured from the DUT has also to be developed based on specific test structures designed according to de-embedding techniques. Figures 26 (a), (b) and (c) show the test structures for the so-called two-step de-embedding procedure. Figure 26 (a) illustrates the test structure with the DUT. The pads for port 1 and port2 are signal pads connecting the gate and the drain terminal of the DUT and the top and bottom ground

152


pads connect to both source and substrate of the DUT, as illustrated further in Fig. 27. So this test structure is used for the s-parameter measurement of a two-port system. Test structures for multi-port systems (more than two ports) can be designed and measured also. But the measurement system with specific design consideration of the probe tips and calibration techniques should be used. Also, the de-embedding technique of the raw data is more complex than that measured from a two port system.

Figure 27 (b) is the so-called "open" structure for a two-port measurement. It uses the same test structure as in Fig. 26 (a) but the DUT has been removed so all the pads are open without any connections between them. Figure 26 (c) shows the so-called "short" structure that is an opposite of the "open" structure and all of the pads are shorted to each other.

f_ Ground pad ] 6 Ground pad i Ground pad

rr I foe 1 3=3 C=C*>«2| [ponp3= =c£3

Ground pad Ground pad

(a) (b) (c)

Fig. 26 Illustrations of the test structures for a two-step calibration of s-parameter measurements; (a)

test structure with DUT; (b) open test structure; (c) short test structure.

[Port 1 of NWA) r

r Ground pod to

substrate/source

(Port2ofNWA]

-* Ground pad to ^ substrateteource

Fig. 27 Illustration ofon-wafer HF measurement for a two port system.

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1040 Y. Cheng

Different de-embedding techniques have been developed based on different calibration test structures.38,39'40 Here, the de-embedding procedure based on the above open and short calibration test structures is dis cussed as an example. This two step de-embedding technique has been widely used in HF measurements for different technologies.38

Typically, a DUT with parasitics from the test structures can be represented by the equivalent circuit in Fig. 28, where YpJ, Yp2 and Yp3 represent the influence of the parallel parasitics and Zsl, Zs2 and Zs3 describe the influence of the series parasitics.

These parallel elements Yph Yp2 and Yp3 can be obtained from the measured data of the open structure, that is,

Yn = —712, open = —Yl\, open (25a)

Yn = Yn ,open + Y\2 , open (25b)

Yn = Yn, open + Yn, open (25c)

The series elements Zsl, Zs2 and Zs} can be obtained from the measured data of both open and short structures, that is,

= (Yshor, - Yopen)-1 (26)

The measured data corresponding to the transistor can be obtained according to the following equation

Ytrtmsistor =[(YDUT — Yopen) — (Yshorl — Yopen) ] (27)

Thus, according to the above, the procedures of the two-step de-embedding technique can be given as follows,

(1) Measure the s-parameters (SDUT, Sope„, and Sshon) for DUT, open and short test structures and convert them to Y parameters (YDUT, Yope„, and Ysnon);

(2) Perform the first step de-embedding by removing the parallel parasitics from both YDUTand Ysi^ according to the following equations,

YDUTI = YDUT- Yopen (28)

Yshorl 1 = Yshorl — Yopen (29)

(3) Perform the second de-embedding by removing the series parasitics Zshoni, converting from Yshorll, from ZDUTI, converting from YDUT1 according to the following equation

Zsl + Zs3 Zsl

Zsi Zs2 + Zsl

154


Zlraraisior — Z>DUT\— Lshort\ (30)

S/B S/B

Fig. 28 Equivalent circuit used for two-step de-embedding of measured HF data of MOSFETs.

Figures 29 and 30 show the data of the measured Y,, and Y22 before and after 1 step and 2 step de-embedding. Significant difference between the data before and after 1 step de-embedding has been observed. Thus, the data de-embedding with the open calibration structure is absolutely necessary to extract accurate parameters of a RF model. A minor difference between the data after the 1-step and the 2-step de-embedding indicate that the calibration with the short structure may be ignored for the MOSFETs at a frequency range up to 10 GHz. However, for the device to work at much higher frequency range, the importance of the calibration with the short structure should be considered. Also, the short calibration may have to be used to obtain the measured data for other devices such as inductors because the devices themselves are very sensitive to the influence of the series parasitics.

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Fig. 29 (a). Illustration of the necessity of the de-embedding of the real part of the measured Yn data.

155

1042 Y. Cheng

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a

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before and after de-embedding.

156


2.5.2. RF model parameter extraction

Depending on the equivalent circuit used in the model, methodologies of HF parameter extraction have been developed [9, 41]. In Section 2.2, we have discussed the equivalent circuit of a MOSFET for RF applications. Usually the Vparameter analysis of the equivalent circuit is adopted to obtain the necessary equations to extract the values of some resistive and capacitive components. It has been known that the poles due to the terminal resistances (that usually are small because of the large finger numbers) are at a much higher frequency than typical transit frequencies, so that they basically can be neglected when calculating the Yparameters and the related quantities. The substrate resistances h the small-signal circuit of Fig. 8 is also neglected when analyzing the y-parameters (Yn, Y,2, and Y2, except the Y22) to obtain expressions that are suitable for use in parameter extraction.

The parameters related to the DC characteristics are extracted with the data from the DC measurements. The methodologies for the DC model parameter extraction have been well developed l9'42 and they are not discussed here. Next we will focus on the discussion of the extraction of the AC parameters for the components shown in Fig. 8.

The equivalent circuit given in Fig. 8 contains too many components, especially current sources, which make the y-parameter analysis very complex and difficult if not impossible, to obtain any useful analytical expressions for the parameter extraction. In order to extract the AC parameters, the influence from the intrinsic components has to be minimized as discussed in [9]. By considering the transistor biased in the strong inversion mode with VDs=0V, the intrinsic behavior of the transistor becomes symmetric in terms of drain and source. Therefore, the effects of the transconductances and the transcapacitances become very small and can be neglected, that is, G„=0, Gmb=Q, Cm«0, C„4=0, CS(f=Q, and the small-signal equivalent circuit in Fig. 8 can be simplified to that shown in Fig. 31, where RDs=VGDS.

By applying a gate bias high enough to operate the device in strong inversion regime, the intrinsic gate-to-bulk capacitance COB is small enough and can be neglected. The equivalent circuit for the Y,, parameter analysis is obtained, as shown in Fig. 32, by shorting the output port and neglecting CQB m Fig. 31. Since the transistor is operating in the linear region with KOJ=0, Cos is approximately equal to COD. The structure and the equivalent effects of the circuit are fully symmetric, which makes the effect of RDS very small so that it can then be neglected. Further, the following assumptions have been adopted in the y-parameter analysis of the equivalent circuit in Fig. 32,

(a) RQ, R S and RD are dominated by the contributions from the resistance of poly-silicon and diffusion layers, and are treated as parameters independent of bias condition and frequency. (b) the equivalent impedance from the intrinsic source/drain nodes to the external source/drain nodes are dominated by the terminal resistances Rs and RD, that is, „ _„ 1 and „ „ 1 .

Rs « ; • RD « : r |y'<wC«s| \JO£BC\

(c) the frequency range considered in this analysis is up to 10GHz, within which the following simplifications hold, {aCosRsf « 1 , (OCCGDRD)2 « 1 ,

157

1044 Y. Cheng

<D2CGSCBD(RD+ Rs)Ra « 1, and ! < < , _ i0}CccRG, where CQO is the total

X + jaCaoRa

gate capacitance Caa = CGS + CGD + CGB •

Fig. 31. An equivalent circuit used for extracting the HF model parameters.

Based on the above, the following approximate equations for Y-parameters can be obtained,

7ii = OJ(CGG2RG + CGS1RS + CGD1RD) +JG£GG

Yn = —COCGGCGDRG—j O£GD

Y2l ~ Gm — (02CGGCGDRa —JG](CGD+GmR.GCGG)

(31a)

(31b)

(31c)

Direct extraction of the AC parameters can be performed from the measured data

according to the above equations,

CGC =

CCD =

Im{r.i}

0)

Im{yu}

(32)

(33) a

158


CGS = CGD

CGB — CCG — Cos — Can

Re {712} Ra =

RD =

Im{rii}Im{ri2}

Re|721}-Re{yi2}

Rs =

1m{YnY

MM_ i b_C2lJ t | ixi{Yn}2

CGG2

Coo

"o7

(34)

(35)

(36)

(37)

(38)

Depending on the measured data, which can be influenced by the design of the test structure, the calibration of the measurement system, the experience of the measurement person, and the accuracy of the de-embedding procedures, the values of RD

and Rs extracted from the Sparameter measurements may or may not equal the ones extracted from DC measurements. To ensure the DC characteristics predicted by the model parameters extracted from DC measurements not to be disturbed by the possible different RD and Rs extracted from the measured s-parameters, it is recommended that the values of RD and Rs extracted from DC measurements are used in extracting the AC parameters. In that case, the RG parameter can be extracted with the following equation,

RG = Re{Yu} - C3(CGJRD + CG!?RS)\

Im{rn}" (39)

To extract the parameters for the substrate network, additional analysis for the Y22 parameter (KGS=Foi=0) is needed. Figure 32 (a) gives the equivalent circuit (EC) for the device at the given bias conditions. To simplify the analysis, the influence of the RD is subtra cted first from the Z22 corresponding to the two -port network given by Fig. 31,

Z2J = Z22— RD (40)

By performing a tedious but straightforward y parameter analysis for the EC shown in Fig. 32 (a), we finally obtain the following equations:

Re{Ysub} = Retyn} - RG(COCGD)2 — — RDS

(41a)

Im{Ysub) = Im{yi2} - JCOCGD (41b)

159

1046 Y. Cheng

where y22 is the Y22 without the influence of RD, Ysub is the output admittance of the substrate network in Fig. 32 (b), co=27f and f is the operation frequency. In the above analysis, the contributions of transconductances Gm and Gmb are ignored since no obvious current flows in the channel at the given bias conditions. Also, the influence of Rs on total admittance is not taken into account in the analysis; this is reasonable because of the dominant contribution of CGS- Furthermore, the assumptions of CO2(CGS+CGB)2RG2 « 1 and (O£GD)2RG2 « i a r e used, which are generally valid in the frequency range up to 10GHz.

The parameters of CGD and RG can be obtained as discussed earlier. Thus, the Ysub data de-embedded from the measured Y22 data according to the above equations represents the contribution of the substrate network.

To extract the SCs, such as the substrate resistance and junction capacitances, we further derive the following equation by doing a Y parameter analysis of the substrate network in Fig. 32 (b)

IU . RDB(RSB+ROSB) ( ( O C M ) 2 +J(OCDB = ^(COCDB)2 + JOCDB (42) RDB + RSB + RDSB

where, ( < B Q » ) 2 ^ < < l t (aCssf RDBRSB2 _ y a n d ia}CsB)2 RSB2 « 1 . These RDB+ RSB + RDSB RDB + RSB+ RDSB

assumptions are valid in the frequency range up to 10GHz.37

Therefore, we have

G » = l m { y " t } (43) CO

Rsub = -MM- (44) Im{( Ysub}2

The extracted CDB includes the contribution of both the intrinsic capacitance CBDi

and the drain junction capacitance CJDB. The CBm can be separated from the extracted CDB

with the measured data at different VDS because CjDB is a function of drain bias and CBDi is approximately independent of drain bias in the saturation regime. But, typically the capacitance CDB is dominated by CJ'DB- The value of capacitance CJDB at zero bias can be extracted from Eq. (43) with the measured data at KDS=0V. The parameters to describe the bias dependence of capacitance CjDB can be extracted according to Eq. (43) with the measured data at different VDS.

Figure 33 shows the extracted resistances as a function of frequency with the transistor at the given bias condition. It is shown that those components are frequency-independent. The extracted capacitances versus frequency are shown in Fig. 34. For the given device in the figure, all of the capacitive components are also frequency-independent. The extracted substrate resistance versus frequency is shown in Fig. 35.

160


C° D

A/W-r RSB D 1

R DSB RDB

Fig. 32 (a). Equivalent circuit used for Y-parameter analysis to extract the HF model parameters-

Si Di

I 1 1 ^ _ l _ CSB - p CDB

- i — V W - M A / H — V W - i

Ysub

RSB Bi RDSB RDB

B B

Fig. 32 (b). A simplified equivalent circuit of the substrate network.17

>l Ysub

- r CP"

Rsub

— B

Fig. 32 (c). One resistor EC for the substrate network [37].

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Fig. 35. Extracted values of substrate resistance at several different bias conditions.37

2.6. Simulations and comparisons with measurements

According to the methodologies discussed above, a subcircuit model based on different core models can be developed. In this section, as an example, we present some results of the RF MOSFET model based on BSIM3v3.10'43 The model has been examined with devices of different geometries at different bias conditions from several technologies. Here we shown the results by using devices fabricated with a 0.25|im RF CMOS technology.

Multi-finger devices with lengths Lf from 0.36|lm to 1.36fXm and width per finger (Wj) from 2.5|lm to 12|im are characterized with a HF measurement system consisting of a HP8510 network analyzer and a HP41421-Vtester. S-parameters are measured and are then converted to Y-parameters to facilitate the parameter extraction. The measured raw data are de-embedded with the two-step (open and short) procedure discussed in Section 2.5.1.38 The model parameters for the intrinsic devices as well as for the series source/drain resistances are extracted from the measured DC data. Other parameters for the extrinsic components such Ra, RDB, RSB etc. and some parameters for the capacitance model are extracted from the measured HF and AC data.

The simulations with the subcircuit model show satisfactory agreement with experiments. As an example, Figure 34 shows a comparison of the Y-parameter characteristics between measurements and the model for devices with different geometries at VG=VD=W. Y-parameters in liner scale plots instead of Smith-chart plots are presented to clearly show the fitting of the model against measurements. The good match between the model and data proves that the simple subcircuit model can be accurate up to 10GHz. Figure 37 gives a comparison offj-ID characteristics between the model and measurements for several devices. Together with the plots in Fig. 36, it demonstrates that the subcircuit

163

1050 Y. Cheng

model can predict the HF characteristics of the devices with different geometries at different bias conditions.

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different devices.4>

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Fig. 37. Measured and simulated characteristics offT versus IDSfor several devices.41

2.7. NQS modeling issues

In the above, the model does not include the so-called NQS effect. However, as we know, NQS effect should be included for a RF model to accurately describe the HF characteristics of devices if the devices themselves exhibit this effect at the operating frequency. Most MOSFET models available in circuit simulators use the quasi-static (QS) approximation. In a QS model, the channel charge is assumed to be a unique function of the instantaneous biases, i.e. the charge responds to a change in voltages with infinite speed. Thus, the finite charging time of the carriers in the inversion layer is ignored. In reality, the carriers in the channel do not respond to the signal immediately, and hence, the channel charge is not a unique function of the instantaneous terminal voltages (quasi-static) but a function of the history of the voltages (non-quasi-static). This problem may become pronounced in RF applications, where the input signals may have rise or fall times comparable to, or even smaller than, the channel transit time. For long channel devices, the channel transit time is roughly inversely proportional to (VGS-K>,) and proportional to L2. Because the carriers in these devices cannot follow the changes of the applied signal, the QS models may give inaccurate or anomalous simulation results that cannot be used to guide circuit design.

166


2.7.1. The experimental observation of the NQS effect in RF MOSFET

Figure 38 shows the characteristics of RGshHF (_ RaN/Lr ^ extracted for devices with Wf

different Lf. Rosh.cat in the figure is the measured DC gate sheet resistance but divided by 3 to consider the distributed effect at HF,7' 8 and is a constant value independent of the device geometry. However, the measurements show that the RGSI,.HF not only is larger than the /?Gj/,C0/(even for the device withL/of 0.35um) but also increases as Lf increases. For the device with a Lf of 1.35um, the frequency dependency of Ra,hMF^ obvious, which is in contradiction to what we have seen in low and intermediate frequency for the components

Caa in a MOSFET. Figure 39 shows the characteristics of CCG,„„,, (= • .) vs. frequency for

W/LjNf devices with different channel lengths. As observed, the extracted Caa.umi shows some weak frequency dependency in the device with Lf of 0.35|im but can still be considered approximately as a constant over the frequency range. This is consistent with the results in low and intermediate frequencies. However, for the devices with longer Lf, the value of Cecum! is smaller compared with the device with shorter Lf at the same operation frequency; Furthermore, CGa.unu is not a constant any more with frequency and decreases as the frequency increases, which is significant in the devices with the longest channels.

Figure 40 shows that the normalized Gm (_ ReO^') ) degrades seriously in devices with Re(K2.(/o))

longer L{ as the frequency increases, where fa is a fixed frequency. The frequency dependency of Gm in the device with Lf of 0.35|im is weak; however, it becomes very strong in the device withL/of US^m 4 4

*1.35jim

L=0.8S |im

" • 00 o 0

o o 00 0 o 0 0 o o 0 t 0 o o o 0 o 0 0 0 0 o o 0 0 o , o o 0 o o o o o 0 o

1 8.0x109 2.0x109 1.0x1<>™

Frequency (Hz)

Fig. 38. Gate sheet resistance /Jc..*.w vs. frequency for devices with different channel lengths. Higher value of RG,I,MF is obtained at HF compared with Rc,h.c<,i

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1054 Y. Cheng

As mentioned earlier, the NQS effect results in a signal delay or even a malfunction of the circuits in some case when a MOSFET operates at HF.45 Typically we can see this NQS effect in a device with an L of 10|jni at about 1MHz.46 However, it is expected that the critical channel length (Lc) for NQS effect to happen will decrease as the signal frequency increases.

When the device cannot respond to the signal immediately, the distributed effect of the channel resistance should be accounted for. This distributed effect in the channel or NQS effect will cause an increase in the effective gate resistance.8 So it can be understood that in Fig. 38 because of the existence of the NQS effect the extracted HF gate-sheet-resistance, RGshMF is higher than RCsh.cah a theoretically estimated value for gate sheet resistance where only the distributed effects on the gate is considered. Because the influence of the NQS effect can be ignored at low frequency but increases significantly as frequency increases, the extracted effective gate sheet resistance, RGSI,.HF, exhibits strong frequency dependency. Similarly, the frequency dependency of RGshMFm a 0.35nm device is not obvious because of the weak NQS effect in this device, but becomes stronger as/,/ increases. Thus larger RGSH.HF'S and stronger frequency dependency of RGSI,.HFare found in devices with longer L/s.

0 . 0 0 4 5 -

0 .0040-

0 .0035-

0 .0030-

0 .0025-

0 . 0 0 2 0 -

1 • 1 • 1 ' T - •*• 1 '

Lf=0.35(im _

oooo0ooooooooooooooooooooooooooooooo0oooooooooooo

^ ^ ^ ^ ^ ^ ^ L . 0 . 8 5 ^ .

^ ^ ^ w -Vcs=1.8V Wf=15nm 11^1.35 jitn. ^ = 1 . 9 / Nf=10

1— ' i • i | 1 1 1 r - - i | i " —

0.0 2.0x10' 4.0x10 6.0x10 8.0x10 1.0x10 1.2x10

Frequency (Hz)

Fig. 39. Effective unit-area gale capacitance CGG.MII versus frequency for devices with different channel

lengths. The value of CQGU„U is reduced for the device -with longer Lf and also ^GG.unu Is not a constant

as the frequency varies in the devices with strong NQS effect.

168


It is also known that the NQS effect will equivalently introduce a transcapacitance between the drain and gate.47 The displacement current from this additional capacitance (referred as C„qs) can cancel partially the output current, which is equivalent to an increased delay to the signal. Cms is negative relative to the positive gate-to-source, gate-to-drain, and gate-to-bulk capacitances CGS, CGD, and CGB so the effective COG with NQS (the sum of CGs, CGD, CGB and C„,3) is less than that without NQS (the sum of CGs, CGD, and CGB only). In devices with longer Lfi the NQS effect is stronger so |C„,S| is larger and hence CGG is smaller. Also, as frequency increases, the NQS effect in the device is stronger so |C„,S| increases and CGG decreases. Thus, a frequency dependency of COG

can be seen in Fig. 39 due to the existence of the component C^.

The degradation of Gm at HF has been considered as an important phenomenon that should be modeled well to predict the circuit behavior at HF.48 The reason for the degradation of Gm is considered as the contribution of NQS effect even though it may be partially caused by the increased signal "feed-through" via CDG at HF \

2

.1

o

.9-

8-

7-

6'

.5

4-

3

2-

1

0-| 1 1 1 1 , 1 1 1 1 1 1 r

0.0 20x109 4.0x109 6.0X109 8.0x109 1.0x10™ 1.2x1010 1.4x10™

Frequency (Hz)

v\fi5pm 1 =10

Vg=i.8v

V D S =1 .5V

V =0V

1^=0.35^ Ly=0.6 |im 1 =0.85(1111

1 =1.35)0(11

Fig. 40. Normalized equivalent transconductance versus frequency for devices with different Lf. The

degradation ofGm can be explained with the existence of NQS effect.

Because the existence of Coo provides a signal path, more and more signals feedback through this capacitance as frequency increases so the total output current (and hence the tranconductance) is reduced. However, it can only explain partial Gm degradation.

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1056 Y. Cheng

2.7.2. Modeling of the NQS effect

The modeling of the frequency dependent components caused by the NQS effect is challenging in compact models for circuit simulationb. Due to the existence of the NQS effect, a MOSFET model based on the quasi-static approximation may not accurately describe the HF device behavior.

The NQS effect can be modeled with different approaches for RF applications: (a) RG approach, in which a bias-dependent gate resistance is introduced to account for the distributed effects from the channel resistance as discussed earlier,8 (b) if, approach, in which a resistance R, (as used in modeling a MESFET or HEMT) is introduced to account for the NQS effect,49 (c) transadmittance approach, in which a voltage-control-current-source (VCCS) is connected in parallel to the intrinsic capacitances and transconductances to model the NQS effect,1' and (d) core model approach, in which the NQS effect can be modeled in the core intrinsic model.42 It should be pointed out that all of these approaches would have to deal with complex implementation issues.

Both the Ra and Rt approaches will introduce additional resistance components in the model besides the existing physical gate and channel resistances measured at DC or low frequency, so the noise characteristics of the model using either RG or Rs approach need to be examined. Ideally, the NQS effect should be included in the core intrinsic model if the model can predict both NQS and noise characteristics without a large penalty in the model implementation and simulation efficiency.

2.7.3. Verification of the NQS model in BSIM3v3

It has been known that BSIM3v3 includes an NQS model option that has been verified with measurements for devices at the medium frequency range.42'30'51 Here we examine the model further with HF measurements, to explore whether the NQS model can describe device behavior with the frequency dependent components at HF. In Fig. 41, we show the simulation results by using the models with and without considering the NQS effect. It is clear that the model without the NQS effect cannot predict correctly the device behavior in both Y,j and Y2I. By including the NQS effect, BSIM3v3 can predict the measured data very well in both of the real and imaginary parts of Y2i. However, the model needs to be improved for fitting Yi,. The reason for the model inaccuracy in Y,, is not very clear at this moment. It may be something related to a fact that the model cannot simulate accurately the ImfYjJ of devices with strong the NQS effect. The model always predicts smaller Im{Yu} and cannot be modulated no matter what values are used for NQS model parameters in the model, as if a constant shunt capacitance component exists and this capacitance dominates the contribution to lm{Yn} when the operation frequency increases up to some level 44. Further investigation of the model including the implementation is needed to improve the accuracy of the BSIM NQS model. The inclusion of the NQS effect would be a desirable feature for a RF model even though it remains a

b Because devices with longer Lf have lower fT and strong NQS effect, they usually is not suitable for small signal RF applications. However, devices with longer Lf may be used in circuits such as switch or biasing circuits. It is still desirable that a RF model can simulate devices having obvious NQS effects.

170


question whether the devices in RF circuits for small-signal applications will operate in the frequency region at which the devices show significant NQS effects.

• D C ra

CD

0.005.

0 .000.

0 .005.

0 .010 .

0 .015 .

0 .020 .

1 R"^y)

~«~^Jj v^***

^ ^ ^ ^ ^ y u * ^ . I m M Y ^

Wp10x15Mm ^ Y ^ f t f e ' ^ ^

Symbols: Measured data

Solid lines: Simulation with NQS

Dotted lines: Simulation without NQS

p——i 1 • 1 • 1 p

V O f 1 V

vaf ' v

VBS=0 V

1 • 1 2.0x10s 4.0x10s 6.0x10s 8.0x10s

Frequency(Hz)

1.0x10'°

Fig. 41 (a). Measured and simulated results of Y2I for a MOSFET with 1.35um channel length. Model

without considering the NQS effect cannot describe the HF device behavior. BSIM3v3 NQS model can

predict accurately the Y2, characteristics even though the device has strong NQS effect.44

0.045

0.040

O.035 -

0.030

0.025 .

0.020

0.015

0.010.

0.005

0.000

Symbols: Measured data Solid lines: Simulation with NQS Dotted lines: Simulation without NQS

Wf=10x15u,m

Lf*1.35uni

2.0x10s 4.0x109 6.0x10s 8.0x10s

Frequency (Hz)

Fig. 41 (b). Measured and simulated results of Yi,. The fitting of the Y,, characteristics of the model

needs to be improved."

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1058 Y. Cheng

3 Noise Modeling

3.1. Noise sources in a MOSFET

It is known that both passive and active components in a circuit will generate various types of noise in the operation. A single MOSFET can also be considered as a small circuit with different resistive, capacitive and active components as we have seen in the above section on modeling of the AC behavior of the device. Thus different noise sources exist in a MOS transistor as shown in Fig. 42 with their power spectral densities (PSD). They include (1) terminal resistance thermal noise at the gate, (2) terminal resistance thermal noise at the drain, (3) terminal resistance thermal noise at the source, (4) thermal noise and the flicker noise in the channel, (5) substrate resistance thermal noise, and (6) induced gate noise.

Di RD D

ZTT 1—"—\6-y<»' l o - M l = f — T ^ -©•

Cs» D. Rosa

—|) , VV*-

* J ? * B'Gw Rst "» W ril I *»

Fig. 42. An equivalent circuit to illustrate the noise sources in a MOSFET. iG!, is

!, and iD2 are the noise

contributions by the terminal resistances at the gate, at the source, and at the drain; id1 is the noise contribution in the channel, including the flicker noise portion; j , f l

2 , iSB2, and insJ are the noise

contributions by substrate resistances; and been defined in Fig. 8.

ig is the induced gate noise. All other components have

The flicker noise mainly affects the low-frequency performance of the device and can be ignored at very high frequency. However, the effect of flicker noise cannot be neglected in some RF circuits such as mixers, oscillators or frequency dividers that up-convert the low-frequency noise to higher frequency and deteriorate the phase noise or the signal-to-noise ratio. Channel resistance and all terminal resistances contribute to the thermal noise at HF, but typically channel resistance dominates in the contributions of the thermal noise from the resistances in the device. Induced gate noise is generated by the capacitive coupling of local noise sources within the channel to the gate, and usually it plays a more important role as the operation frequency goes much higher than the frequency at which channel thermal noise dominates.

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3.2. Flicker noise modeling

Among all noise sources, the flicker noise is the dominant source for phase noise in silicon MOSFET circuits, especially in the low-frequency-range. It sets a lower limit on the level of sgnal detection and spectral purity, and is one of the factors limiting the achievable dynamic range of MOS ICs, so it is important for device and circuit designers to minimize this effect in order to improve the circuit performance. As designers begin to explore circuits with low power and low voltage MOSFETs, the effect of low frequency flicker noise becomes more and more crucial to provide enough dynamic range and better circuit performance.

3.2.1. The physical mechanisms of flicker (1/f) noise

Noise at low frequencies in a MOSEFT is dominated by flicker noise. Measurements generally show a spectral density of the input (gate) referred voltage noise, which is roughly inversely proportional to frequency, as shown in Fig. 43. Therefore, flicker noise is also called 1/f noise. Much effort has been made in understanding the physical origin of flicker noise. However, the physical mechanism is still not very clear so far. A lot of discussions and investigations are continuing to find a universal model to exp lain the experimental results reported by different research groups that use devices from different manufactures.

u r 10* FREQUENCY tHi)

Fig. 43 Drain current noise spectral density of an n-channel MOSFET.

Although there are probably several different physical mechanisms resulting in noise in MOSFET's, there are strong indications that traps at the Si-Si02 interface play

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1060 Y. Cheng

the most important role.53'54 Electron trapping and de-trapping can lead to conductance variations. The exact mechanism is still under discussion, however, basically, there are three different theories on the mechanism of flicker noise as follows: 1) Carrier-density fluctuation models (number fluctuations), predicting an input referred

noise density independent of the gate bias voltage and proportional to the square of the oxide thickness;

2) Mobility fluctuation models, predicting an input referred noise voltage increasing with gate bias voltage, and proportional to oxide thickness;

3) Correlated carrier and mobility fluctuation models, a unified model55 with a functional form resembling the number fluctuation model at low bias and the mobility fluctuation model at high bias.

In the carrier density fluctuation model, the noise is explained by the fluctuation of channel free carriers due to the random capture and emission of carriers by interface traps at the Si-Si02 interface. According to this model, the input noise is independent of the gate bias, and the magnitude of the noise spectrum is proportional to the density of the interface traps. A 1/f noise spectrum is predicted if the trap density is uniform in the oxide. Measurements of devices from many different CMOS processes with oxide thickness between 10-80 nm suggest that nMOS transistors behave as predicted by the number fluctuation model.56 However, noise neasurements of newer deep sub-micron transistors present a much less consistent picture. For instance, nMOS transistors also may show bias dependence, while pMOS transistors may have a noise corner frequency comparable to nMOS transistors. Also, the experimental results show a 1// spectrum and n is not always 1 but in the range of 0.7-1.2. Some experimental results even show that n decreases with increasing gate bias in p-channel MOSFETs. Modified charge density fluctuation theories have been proposed to explain these experimental results. The spatial distribution of the active traps in the oxide is assumed to be non-uniform to explain the technology and the gate bias dependence of n.

The mobility fluctuation model considers flicker noise to be the result of fluctuations in carrier mobility based on Hooge's empirical relation for the spectral density of the flicker noise in a homogeneous device. It has been proposed that the fluctuations of the bulk mobility in MOSFETs are introduced by changes in the phonon population. The mobility fluctuation models predict a gate bias dependent noise. However, they cannot always account for the magnitude of the noise.

The unified theory for the origin of the 1/f noise suggests that the capture and emission of carriers by the interface traps cause fluctuation in both the carrier number and the mobility. All unified noise models assume implicitly that the mobility, limited by Coulomb scattering at trapped interface charges, does not depend on the inversion carrier density. However, recent experimental results indicate that the mobility, limited by Coulomb scattering, is proportional to the square root of the inversion carrier density.57,58

Recently, some arguments even claim that the correlated mobility fluctuations can be neglected compared to the noise contribution from carrier number fluctuations, if the correct dependence of the Coulomb scattering limited mobility on inversion carrier density is taken into account. As a result, the unified noise models cannot predict the experimentally observed noise as a function of gate bias in p-type MOSFETs unless

174


nonphysical fitting parameters are used.57 Nevertheless, even though this unified theory cannot explain all the details of the experimental data, it seems to be the most attractive model available today in circuit simulators.

3.2.2. Flicker noise models

It is for historic reasons that different flicker noise models have been developed based on the three different approaches discussed above. They are implemented in different simulators such as HSPICE, SPECTRE, ELDO, PSPICE etc. Almost all of the commercial simulators provide different options for users to select different noise models in noise simulation together with a specific compact model, such as MOS 9, EKV and BSIM3v3, for simulations such DC, AC small signal or transient analysis. For example, HSPICE includes three different models for the drain current flicker noise that are distinguished with different model levels (0-3).

ForNLEV=0:

Sid=^L (45) CoxLeff f

where Su is the drain current noise power spectral density, IDS is the drain current, Cox is the unit-area gate oxide capacitance, Lîs the effective channel length,/is the frequency, KF andAF are fitting parameters.

ForNLEV=l:

& , - * " » * (46) CoxLeff Weff f

where W -is the effective channel width.

ForNLEV=2and3:

5* = ^ L (47) CoxLeffWefff*

where Gm is the transconductance of the device, AF is a fitting parameter. In fact, some compact models have their own flicker noise models. For example,

BSIM3v3 introduces two flicker noise models.5 One is the SPICE2 flicker noise model, 62

while another is the unified flicker noise model. The latter is a newer model developed recently and has been considered a more accurate model than the SPICE2 flicker noise model.55 The reason why the SPICE2 flicker noise model was included in BSIM3v3 is to provide the convenience for some BSIM3v3 users who are familiar with the SPICE2 flicker

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1062 Y. Cheng

noise model before the unified BSIM3 noise model was developed and want to continue to use it in the noise simulation."

The SPICE2 flicker noise model is

S, = -^L- (48) CoxLeff f

where EF is a fitting parameter. The unified flicker noise model in BSIM3v3 is more complex. Basically, it includes

a portion equivalent to the SPICE2 flicker noise model given by Eq. (48), but contains another portion to give a more accurate description of the flicker noise characteristics in the saturation region."

Currently, it is a fact that many different noise models are included in circuit simulators. However, it has to be pointed out the these models in commercial simulators are not fully compatible with each other. For example, the geometry dependence between Eq. (45) and Eq. (47) are different, and the bias dependence between them is also different. Furthermore, those flicker noise models contain different oxide thickness dependencies. Modeling engineers and circuit designers need to be aware of this when performing noise simulation. A lot of work has been done to verify the accuracy of the flicker noise models over various bias conditions, but further work is still needed to develop a better flicker noise model that can explain most (if not all) of the experiments. So a careful selection of the flicker noise model is required to make sure that the model will predict reasonable noise performance according to the circuit applications.

3.2.3. Future work in flicker noise modeling

(i) Flicker noise modeling with the consideration of new physical mechanisms in MOSFETs with ultra thin oxides

The above physical mechanisms of flicker noise are the ones we have frequently encountered in literature. However, as the technology enters more advanced stages, new noise mechanisms may appear and play an important role. For example, it has been reported that the influence of a new mechanism to flicker noise performance should be accounted for in ultra thin oxide MOS transistors (e.g., 1.5 nm or less 59) due to direct tunneling currents which will alter the characteristics of the 1/f noise depending on the length of the channel and the thickness of the gate oxide, as shown in Fig. 44 and Fig. 45.

In Figs. 44 and 45, the gate length and the oxide thickness dependence of gate referred voltage noise are shown at 1kHz operation. Figure 44 shows the gate oxide thickness dependence of the gate referred voltage noise in devices with 0.15|im and 0.2um channel lengths. For the devices with gate lengths less than 0.2um, the flicker noise in a device with 1.5nm gate oxide thickness is lower than that in devices with thicker gate oxides. It means that the noise characteristics of devices have been improved with

176


-120 i 1 r

2.0 3.0 Tox (nm)

5.0 7.0

Fig. 44. Gate oxide thickness dependence of flicker noise in n-channel MOSFETs with 0.J5JM and 0.2

\Xm gate channel lengths.59

I -130-

-140

-150

-160

¥—IT"

" M

-

1 i I I ( I 1 I I

v*?\ ys. M-MOSFET* ^ [ °\Z» e t k H z

. Vd-1.SV x. -. < •

• " B kf»tfrA$m

... JU_l„JL. i i i t i i i i i

i i i i ~

*•

" " % •

z*>

j i n 0.02 0.05 0.1 02

LgO/m) 93 1J)

Fig. 45. Gate length dependence of flicker noise in n-channel MOSFETs with various gate oxide thicknesses."

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1064 Y. Cheng

decreasing gate oxide thickness for the devices with such short channel lengths, although the gate leakage current becomes larger in the former. A possible mechanis m for the lowering of flicker noise in the devices with thinner oxides is the appearance of band-to-band tunneling. However, as also shown in Fig. 45, for devices with channel length longer than 0.2|im, the flicker noise in the device with 1.5nm gate oxide is higher than that in the device with thicker oxide (2.2nm). As a understanding of this result, it has been believed that the higher flicker noise in such devices with longer (than 0.2um) channel length and thinner (1.5nm) gate oxide was caused by the much larger gate leakage current as the devices with longer channel lengths have larger gate area. Further theoretical and experimental investigations on this issue are needed to fully understand the contribution of the band-to-band tunneling and gate leakage to the flicker noise characteristic in today's devices. A compact flicker noise model with the consideration of band-to-band tunneling and gate leakage has not been reported so far.

(ii) Modeling and simulation of flicker noise under switched bias conditions

It has been reported that devices under switched bias conditions show lower flicker noise than those measured at DC bias conditions.60 Figure 46 shows a typical measurement result. The noise spectrum between 10 Hz and 100 kHz is shown for constant biasing (no switching) together with noise spectra resulting from a 10 kHz switched bias signal with 50% duty cycle. For 50% duty cycle, a low frequency noise power that is

1000 Frequency [Hz]

10000 100000

Fig. 46. Noise reduction as a function of the "off" voltage for an NMOS, V0So„ = 2.5 V, V,h=l = 10 kHz. duty cycle = 50%6'

178


reduced by 6 dB compared to the constant-bias situation is expected. Further noise reduction is observed when the gate-source voltage in the 'off state is decreased, indicating an increasing noise reduction closer to accumulation. Figure 47 shows the results at various switching frequencies. All noise spectra appear to "merge" at low frequencies, with about 7 dB of intrinsic noise reduction (apart from the 6 dB related to 50% duty cycle). Even at MHz frequencies, where the settling of the output voltages becomes incomplete, this noise reduction is found.

As switched biasing has been proposed as a technique for reducing the flicker noise in MOSFET's with reduced power consumption to benefit HF circuits,61 it becomes essential for RF MOSFET models to give a reasonable prediction of flicker noise performance of the device under such conditions. In order to do that, the flicker noise model contained in the RF model must be continuous and accurate over a wide bias range from strong inversion to accumulation and from linear to saturation regimes. Further work is needed to validate the flicker noise models with measured noise data in devices under switch biasing conditions and develop more advanced noise models for RF applications.

- * u -I , 1 , ,

10 100 1000 10000 100000 Frequency [Hz]

Fig. 47. Noise reduction while switching at different frequencies for an NMOSFET, VGSo„ = 2 .5 V, Vcs,0ff

= 0V, duty cycle = 50%. Also shown is the noise floor under the same conditions.61

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1066 Y. Cheng

3.3. Thermal noise modeling

3.3.1. Existing thermal noise models

At HF, although all the noise sources contribute to the total noise, the dominant contribution comes from the channel thermal noise. The channel thermal noise characteristics in MOSFETs operating in the strong inversion region have been studied for over two decades. The origin of this thermal noise has been found to be related to the random thermal motion of carriers in the channel of the device. Various models have been developed and some of them have been implemented in circuit simulators.

A simple thermal noise model has been implemented in circuit simulators since SPICE2 was developed,62

SidJKsTGm ( 4 9 )

3 where k is the Boltzman constant and T is the absolute temperature in K; Gm is the transconductance of the device.

Other Similar models have also been proposed as given in the following:19,42,62

SIJ=SKSTGOS ( 5 0 )

3

„ _ SKaT(Gm + Gos) (ri\

„ _ %Kl>T(Gm+GDS+Gmb) (52)

3

where GDS and Gmh are the channel conductance and bulk transconductance. Most compact models developed for circuit simulation have their own thermal

noise models. For example, BSIM3v3 includes the following equation to calculate the thermal noise of the device as a user option besides the one given by Eq. (52),

Sid=4K*r&LQm (53) Lqf

where j % i s the effective carrier mobility, I cîs the channel length of the device, Qim is the total inversion charge in the channel.

It has been reported that Eq. (50) gives a non-physical prediction of thermal noise at FDÔV.63 Eqs. (51) and (52) are proposed to fix this problem even though their accuracy and physical basis need to be verified. Studies to validate the accuracy of the above noise models have been reported recently.64 Some discussion will be given later.

Another thermal noise model that is not implemented in all commercial circuit simulators but widely used for noise analysis by circuit designers is

Sb*< =4KsTGiKh C54\ = 4KBTyGm

180


where G„ch is the channel thermal noise conductance and y is a bias dependent factor, which for long-channel devices is equal to unity in the linear region and to 2/3 in saturation."

The y factor has been used as a figure of merit to compare the thermal noise performance of different devices. It shows how much noise is generated by the device at the input for a given transconductance. It has been found that the y factor is not a constant for devices with different channel lengths and the y factor for short channel device can be larger than that for long channel device in the saturation regime due to both velocity saturation and hot electrons.65,66 Some models have been proposed to account for the velocity saturation effect 67 and hot carrier effects,68 but they have not been implemented in any compact model yet. Recently a simple thermal noise model is proposed to account for both velocity saturation and hot carriers and can be easily implemented.69

That noise model was originally developed for a transistor biased in saturation and in strong inversion,, but an extended expression has been proposed to cover the regions from weak to strong inversion by rewriting the noise parameter as "

y = y ( 1 + l 2 = 2 ) (55) ' G Leff'

where vml is the saturation velocity, % is a relaxation time (of the order of ps) used as a fitting parameter and G is the normalized GJID ratio, % is the y factor for the long channel device.

This simple model assumes that the carrier velocity is saturated and that the lateral field is equal to the critical field all along the channel from source to drain. Although these assumptions are questionable, the resulting model can fit the measured data over bias and geometry.6'

3.3.2. HF noise parameters"

In noise model derivation and circuit simulation, the noise power spectral density is used as a measure for the noise output in the device. Circuit designers also prefer to use the noise power spectral density, the parameters related to the noisy two-port equivalent circuit. However, in measurements, the HF noise is usually characterized by several other parameters: the minimum noise factor (or minimum noise figure), the input referred noise resistance and the optimum source admittance for which the minimum noise figure is obtained. Therefore, it is necessary to discuss these parameters to understand their physical meanings and their relationship in describing the HF noise characteristics of the device.

The noise factor is a figure of merit for the performance of a device or a circuit with respect to noise. The standard definition of the noise factor of a two-port network is the ratio of the available output noise power per unit bandwidth to the portion of that

More discussion on this topic can be found in the Chapter by Chen and Deen.

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1068 Y. Cheng

noise caused by the actual source connected to the input terminals of the device. It can be given by the following equivalent equation,

F=*1HL (56) Sol No

where 5, and S0 are input and output signal; N, and N0 are input and output noise power. The noise factor can be expressed in decibels form, which is termed as the noise

figure, that is,

Afr = 101ogF (57)

The noise figure of a two-port network is given by

NF = NF miiiH \ys - yop\ (58)

where r„ is the equivalent normalized noise resistance of the two port network, ys=gs+jbs is the normalized source admittance, and y0pi=gopi+jbopt represents the normalized source admittance which results in the minimum (or optimum) noise figure NFmi„.

The ys and yop, can be expressed in terms of the reflection coefficients 77 and ropti

the ratio of the incident to the reflected wave along a transmission line

(59)

and

y,=

y»pt

. l - C i + n

1 — I opt

i+rv

i, Eq. (58) becomes the following form

(60)

NF = NF^+ 4 > l p ' r ^ (61)

O-lrfHi + rvi2

In the HF noise measurements, the source reflection coefficient is varied until a minimum noise figure is reached. The value of NFml„, which occurs when r,= ropl, is read from the noise figure meter, and the source reflection coefficient that produces NFmi„ is determined by a network analyzer. The noise resistance r„ is measured by reading the noise figure when /7=0-

NFmi„ is a function of the biases (operating current) and frequency. Each NFmi„ is associated with one value of Top,. Figure 48 shows a typical measured characteristic of

182


NFmi„ versus frequency for a RF MOSFET. Figure 49 gives a typical measured plot ofNFmi„ versus bias current. According to the measured noise characteristics, MOSFET can provide a low noise figure that is attractive to the RF applications. Also, a careful selection of the bias conditions is import for the device to achieve a lowest noise performance as shown in Fig. 49. Since RF MOSEFT with a very short channel length includes many different physical effects and contains non-negligible parasitics, it is not very easy to optimize the noise performance of the devices in a circuit with hand calculation by using analytical equations. So it is desirable that an RF model with accurate noise prediction is developed for use in circuit simulation. Whether a RF model can predict accurately the characteristics of noise figure versus bias currents for devices with different sizes is another challenge to device model developers.

4!>.

tO-

SO-

2.5-

2.0-

1.5-

LO

OS-

0.0-

'

•

V D S = 1 V

V BB = 0 V

•

-T—'

•

•

1

•

• •

•

Finger numbers*1G Width per fingers6^m Length=0.18jim

-3 4 5

Frequency (GHz)

Fig. 48 An example of measured NFmi„ versus frequency for a MOSFET.

4.0-

35-

ID

S' S 25-

J Z Z0-

1.5-

1.0-

1 i | .

Finger numbers=10

Width per finger=€lirn

Length~0.18um

-1 • 1 •

•

. •

• •

•

V B S = 0 V

Frequency =3GHz

10 20

los(mA)

Fig. 49 An example of measured NF min versus IDS for a MOSFET.

As mentioned above, circuit designers prefer to use the parameters re lated to a two-port network to describe the noise performance of a device and a circuit. Universal

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1070 Y. Cheng

noise models have been developed for any two-port network. A noisy two-port network shown in Fig. 50 (a) can be represented by a noise-free two-port network with two noise current sources, one at the input port (i,) and the other at the output port (i2) as shown in Fig. 50 (b). Figure 50 (b) can also be transformed to a noise-free two-port network in Fig. 50 (c) with a noise current source, Sm=4KBTGin, and a noise voltage source, S™ = 4KBTRW at the input port, where the v„ and i„ are correlated to each other and the correlation relationship is described by a correlation admittance Yc = Gc + JBc The noise source /'„ can be further separated to a noise source /„„ that is uncorrelated to v„ and a noise source /„cthat is fully correlated to v„

in = irm + Inc (62)

and inc = YcVn (63)

The above relationship can be expressed in terms of noise power spectral density as follows:

+ S,nc (64)

Sinc=\Y(S™ (65)

According to the two-port network given in Fig. 50, we further have the following relationships,

v» = h (66) Y21

in =h + Y\\Vn (67)

Si 2

&2 (69) S» = - ^ 7 = 4KaTR,

N2

Sm=4KBTGm (70)

184


(a)

(b)

+ -InQ Noise-free two port

Ii

(c)

Fig. 50. Noisy two-port and its ABCD-parameter representation.

Based on the above relationships, the four noise parameters discussed earlier can be calculated,

Xtrt — IYv<

G, [G7

* - V A " &2

(71)

(72)

Bopi ——Be

NF mi. = 1 + 2Rn(Gc + G,p<)

(73)

(74)

Similarly, noise parameters related to the two-port network can be calculated once we have the four noise parameters, R„, G^,, Bop, and NFmim

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1072 Y. Cheng

Jvva — i\n

Be = —Bopl

Gn = (Gop,2+Bc2)R»

(75)

(76)

(77)

AfFmin- 1

2R, (78)

To this point, we have established a conversion relationship between the four noise parameters obtained from the measurements and the noise parameters related to the two port network for circuit analysis. Detailed analysis can be further performed for the noise performance of the device and a circuit based on the above derivations.

According to the noisy two-port network theory, a useful equation for the power spectral density of i2 can be obtained as follows,71

Sn = S,\Yi\z =4KBTR\YI( (79)

where KB is the Boltzmann's constant, T is the absolute temperature, Y2i is the transadmittance from port 1 to port 2 of the noise-free two-port and R„ is the equivalent noise resistance, which is a resistance cascaded at the input port that will produce the same amount of noise power spectral density as i2 does at the output port.

3.3.3. Analytical calculation of the noise parameters

Figure 42 illustrates all noise sources in a MOSFET. However, it is too complex to be used to calculate the contribution of each noise source analytically. A simplified EC shown in Fig. 51 can be obtained by neglecting some components in Fig. 42."

r»—i—wv-

Ki o

• &

a

ig20 *Cc.

Gm Vast GmbVBSl

©J ©1 Q"f

h D -4 0

RSVB

Fig. 51 Simplified small-signal schematic for noise calculation."

186


In Fig. 51, the capacitances CBS and CBD have been neglected, and the influence of the different substrate resistance components is taken care of by Rmb. Based on the equivalent circuit, the following noise parameters are obtained:"

(80)

(81)

(82)

(83)

^=l+Cfe + C&«i+(Gm/?G0)V (84)

9 = 27f— (85) Gm

where A t is a parameter proportional to y factor discussed earlier, parameters y and % account for the induced gate noise and its correlation to the drain noise; eg is the ratio of the noise power spectral density of the gate resistance to the input referred channel noise, and Ciu,, is the ratio of the output referred substrate resistance noise power spectral density to the output referred channel noise,

Rvn

Gin

Gc =

R- =

Gm

= AsalGmO Iff

Ra{Gm0)2\f/

t?

_G»6x,

Ok : GmRa (86)

Asat

Kjmb Rsub soi\ Osub = (87)

CfmAsat

Parameters \y and % are given in the following,

, Gsat _ lOsat /oo\

\ff = 1 + Osub + + 2Cg J (88) Asat I Asat

i I &sat soi\\

X = \ + a,ub-cgA— (89) | Asat

where qa, is a bias and geometry dependent factor," cg is a fitting parameter that is 0.395 for a long channel device.

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1074 Y. Cheng

Both y/and ^reduce to l+a,ubwhen the induced gate noise is ignored (cj„=0). The induced gate noise contributes mainly to Gin through the factor i#the gate resistance Ra contributes to Rv„, and the channel noise and substrate nois e contribute to both G,„ and Rv„. Substrate noise may typically contribute to 20% of Rv„ whereas R0 typically contributes to about 5%. It is therefore important to account for the substrate resistance when doing noise calculation and noise optimization.

2.5

2

E . 1 .5 or

as

<y$-0 rimJMfcn«ittihflD «Wb(<UU>.o)

CI.1JW} <1.1,1fl) (1.1,1.1)

11 0L2 THM

0,3 Tfl.

0/4

G.16

0L5

Fig. 52. Comparison between measured and simulated noise parameters (NFml„ R„, Gop„ BopJ.'

The noise parameters of an n-channel device have been measured and carefully de-embedded using the methodology presented in.72'73-74 They are presented in Fig. 52 and compared to the results obtained from simulation using the complete subcircuit of Fig. 42 with the additional induced gate noise source added to the sub-circuit (but not accounting for the correlation between induced gate noise and drain thermal noise)." The results obtained from Eqs. (80)-(85) including the correlation between induced gate noise and channel drain noise are also shown in the figures. The meaning of the symbols (si, s2, s3, s4) shown in the Fig. 52 are defined as follows:" si enables the gate resistance noise, s2 enables the substrate resistance noise, s3 enables the induced gate noise without correlation (cg=0) and s4 enables the induced gate noise correlation (cg=0.395), respectively in the simulations. Figure 52 shows that the gate and substrate resistances strongly affect the minimum noise figure NFmin, the optimum noise conductance Gopl and the input referred noise resistance Rm. The induced gate noise slightly affects NFmin and

188


Gop„ but has no effect on Rv„. From these results, it can be concluded that induced gate noise is not the only contributor to the minimum noise figure, and the gate resistance and, more importantly, the substrate resistance also contribute significantly.

Note that the analytical expressions for the noise parameters give reasonable results below fj/5 and the discrepancies appearing at HF between the analytical and the measured results mainly come from a wrong frequency behavior due to the very simple equivalent circuit used for the derivations of Eqs. (80X85).

3.3.4. Simulation and discussions

With the extracted parameters from the measured data for a 0.25um RF CMOS technology, the noise characteristics of the subcircuit model discussed above are verified.78 The four noise parameters calculated with the simulated noise characteristics are given in Fig. 53 against the measured data for a 0.36um device at different bias conditions. While the RF model with extracted parameters fits accurately the measured s-parameters data, it can also predict well the HF noise characteristics of the device as shown in Fig. 53 by the curves at VGS** IV and VDs= IV. The discrepancy in the R„ characteristics between the model and the measured data at f/GlS=2V needs further investigation. However obvious disagreement in the simulated and measured imaginary part ofy,2, has been found at that bias condition so the discrepancy in the R„ characteristics may be caused by the inaccuracy of the capacitance model in that operation regime.

1 =10 Mxf™ W=1CHm ^tefW L=0.36um

1 2 3 4 5

Frequency (GHz)

Fig. 53 (a). Comparisons of measured data for mnimum noise figure, NFm/„, with simulations at different bias conditions. The Nf is the finger number of each device. The channel width per finger is lOum and the channel length is 0.36um.

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1076 Y. Cheng

£ to

C B-

Symbols: Measured data Solid line: Model

-< 1 • r

Frequency (GHz)

Fig. 53 (b). Comparisons of measured data for the magnitude of the optimized source reflection coefficient IZP„ with simulations at different bias conditions.

< H J -

35-

30-

25-

"S" "5) 20-C

< « •-^ 15 -

, * ^ 1 0 -

5-

0-

IMf=10

W=10nm

L=0.36)OT

1 •

•

•"ii

— r

' •

Vos=w

V B S ^

— 1 •

Vffi=2.0V

V O / J

^ \ V -5s(*Ss^

* ^ *Jr\ ys m 1 1 y ^ V^LOV

•

Symbols: Measured data Solid line: Model

1 • T 1 — •! -

1 2 3 4 5

Frequency (GHz)

Fig. 53 (c). Comparisons of measured data for the phase of the optimized source reflection coefficient, rop„ with simulations at different bias conditions.

190


Mor

mal

ized

) 14-

12-

10-

8-

6-

4-

2 -

0-

\ ^ ^

— 1 — n - 1 . — 1 —

Vbf

Symbols: Measured data

Seed ire: Model

N f 1 0

W=10um

L=0.36u,m

-0V _ _ _ _ _ ^

8 1 £ °~*B 0 n, • • • • • • ^ " y

VQS=1.0V

r • ' — i • i—•— i ' 2 3 4

Frequency (GHz)

Fig. 53 (d). Comparisons of measured data for the noise resistance normalized to 50ii r„ with simulations at different bias conditions.

N X

%,

bs(mA)

Fig. 54. Power spectral densities of channel thermal noise versus bias current of a 0.36 um n-channel MOSFET. They are extracted from the measured data and calculated from different channel thermal noise models.

191

1078 Y. Cheng

The noise characteristics of several nois e models including the subcircuit RF model above are also verified with the extracted channel thermal-noise with the methodology discussed in [79]. Figure 54 shows the curves of the channel thermal noise versus bias current, from the measured data, and simulations of the subcircuit model given in Fig. 21 with BSIM3v3 noise model (Noimod=4) and several other noise models given by Eqs. (79)-(81). It shows that the calculated channel thermal noise based on Eqs. (79)-(81) cannot predict the channel thermal noise extracted from measured data. The subcircuit RF model with the BSIM3v3 noise model (Noimod=4) has much better accuracy at several different bias conditions.

3.3.5. Induced gate noise issue

The concept of the induced gate noise has been used for three decades. But many researchers are still studying how to model it correctly. At high frequencies, it is believed that the local channel voltage fluctuations due to thermal noise couple to the gate through the oxide capacitance and cause an induced gate noise current to flow. ' This noise current can be modeled by a noisy current source connected in parallel to the intrinsic gate-to-source capacitance CG5, as shown in Fig. 55." Since the physical origin of the induced gate noise is the same as for the channel thermal noise at the drain, the two noise sources are partially correlated with a correlation factor cg.

Cos

Fig. 55. Illustration of induced gate noise and the equivalent circuit model.

192


The power spectral density of the induced gate noise PSD is given by,64-65-66

Sing = 4KBTGng (90)

and

_ asa(27Zf Cos)2 (9J )

Gm

Device noise simulations performed for a finger length have shown that the correlation factor remains mainly imaginary (real part about 10 times smaller than the imaginary part) and that its value is slightly smaller than the long-channel value 0.395 (it typically ranges from 0.35 to 0.3 for for-short-channel devices).75

Currently, the induced gate noise and its correlation to the thermal noise at the drain are not yet implemented completely in compact models. One reason is the difficulty of modeling the induced-gate noise and implementing it in circuit simulators. Another reason is that it is not very critical at frequencies much smaller than the fT of the device, since at that frequency range two more important contributors to the total noise are the substrate and the gate resistances, instead of the induced gate noise, besides the channel thermal noise. A methodology to extract the induced gate noise has also been developed.78,79 however, further detailed investigations are needed to understand the induced gate noise issue and model it correctly. The subcircuit RF model discussed in this paper does not include the contribution of the induced gate noise.

4. Summary

Both AC and noise modeling of MOSFETs for RF applications have been discussed. The modeling of both intrinsic and parasitic components in MOSFETs is crucial to describe the HF behavior of MOS devices operated at GHz frequencies. The analyzing of equivalent circuits with intrinsic and extrinsic components indicates the importance of the some resistive components (such as gate, source, drain and substrate resistance) and some capacitive components (such as C0D, CGS, CaB, CBS, CBD as well as the transcapacitance Cm, Cm6and Cmgb). An RF model with accounting for the contributions of both the polysilicon gate resistance and distributed channel resistance may be adequate to predict accurately the HF characteristics of MOSFETs. Also, a physical and accurate model, without introducing many difficulties for simulation and parameter extraction, for the substrate components is critical in a RF model. Based on the y-parameter analysis, procedures of HF model parameter extraction are discussed with detailed description of the HF measurements and data de-embedding. As a example, a BSIM3v3 based RF MOSFET is presented with the considerations of the above resistive and capacitive components, where BSIM3v3 is the core of the subcircuit model to describe the characteristics of the intrinsic and some parasitic components including the transcapacitances. The model has been verified by HF measurements. Good model accuracy at different bias conditions has been found for devices with different channel

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1080 Y. Cheng

lengths, widths and fingers. The developed RF MOSFET model can be a basis of a predictive and statistical modeling approach for RF applications.

The modeling approaches of NQS effects have been discussed. A RF model including NQS effect is desirable without introducing penalty in complex implementation and simulation time. The discussed RF model can predict well the y2i characteristics of devices with significant NQS effect but it needs to be improved in fitting the yn

characteristics. Noise modeling is also discussed by analyzing the theoretical and experimental

results in both the flicker noise and thermal noise modeling. Modeling efforts to incorporate new physical effects are needed to predict better the flicker noise characteristics in today's MOSFETs. A detailed analysis of the HF noise parameters has been conducted to establish the relationship between the noise parameters preferred by circuit designers and obtained by HF noise measurement. Analytical calculation of the noise parameters has also been discussed to understand the noise characteristics with/without some parasitic components such as gate and substrate resistances as well as the influence of the induced gate noise. The predictivity of HF noise characteristics of the RF model has been examined with the measured data. It shows that the model can predict the HF noise characteristics while the model with extracted parameters can simulate accurately the HF AC parameters. The results of several other noise models are also shown with the comparisons of the measured data. The subcircuit RF model gives better prediction of HF channel noise characteristics. The concept of the induced gate noise is briefly introduced without further theoretical analysis and experimental investigation. It is still an issue to model the induced gate noise, the correlation with channel thermal noise and its influence to the circuits at RF.

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71. G. Gonzalez, "Microwave Transistor Amplifiers- Analysis and Design," second edition, Prentice-

Hall, 1997.

72. K. Aufinger and J. Bock, "A straightforward noise de-embedding method and its application to high

speed silicon bipolar transistors," procedding of ESSDERC'96, pp. 957-960, 1996.

73. M. J. Deen and C. H. Chen, "The impact of noise parameter de-embedding on the high-frequency

noise modeling of MOSFETs," Proceedings of the 1999 International Conference on Microelectronic

Test Structures, pp. 34-39, 1999.

74. M. Pospieszalski, "On the measurement of noise parameters of mictowave two port," IEEE Trans.

On Microwave Theory Tech., vol. MTT-34, no. 4, pp. 456-458, 1986.

75. H. E. Halladay and A. Van der Ziel, "On the High Frequency Excess Noise and Equivalent Circuit

Representation of the MOSFET with n-type Channel," Solid-State Electronics, vol. 12, pp. 161-176,

1969

76. D. P. Triantis, A. N. Birbas and S. E. Plevridis, "Induced Gate Noise in MOSFETs Revisited: The

Submicron Case," Solid-State Electronics, vol. 41, No. 12, pp. 1937-1942, 1997.

77. D. K. Shaeffer and T. H. Lee, "A 1.5-V, 1.5-GHz CMOS Low-Noise Amplifier," IEEE Journal of

Solid-State Circuits, vol. 32, No. 5, pp. 745-759, May 1997.

78. C .H. Chen, M. J. Deen,, M. Matloubian, and Y. Cheng, "Extraction of the channel thermal noise

in MOSFETs,", Proceedings of the 2000 International Conference on Microelectronic Test Structures

pp. 42 -47, 2000.

79. C .H. Chen, M. J. Deen, Y. Cheng and M. Matloubian, "Extraction of the Induced Gate Noise,

Channel Noise and their Correlation in Sub-Micron MOSFETs from RF Noise Measurements", To be

published in IEEE Transactions On Electron Devices, Vol. 48, 2001.

198


RF CMOS NOISE CHARACTERIZATION AND MODELING

CHIH-HUNG CHEN and M. JAMAL DEEN Department of Electrical and Computer Engineering

McMaster University, Hamilton, Ontario, Canada L8S 4K1 Email: [email protected], [email protected]

This paper presents a through description of radio frequency (RF) noise characterization and modeling of CMOS transistors. It begins with the definition of the four noise parameters of a two-port network - minimum noise figure (NFmjn), equivalent noise resistance (Rn), optimized source impedance (Ropt) and optimized source reactance (Xopl). These four parameters are used in device characterization and it is shown how they can be calculated by using the noise two-port network theory and a circuit simulator. Then two de-embedding procedures are discussed in detail for noise and scattering parameter de-embedding to get rid of the parasitic effects from the probe pads and interconnections in the device-under-test (DUT). Ideally there is no frequency and geometry limitation for the method based on a cascade configuration. Methods to directly extract the channel noise, induced gate noise and their correlation from the RF and noise measurements are developed and the extracted noise sources as a function of frequency and bias condition for different channel lengths are presented. Some design consideration for the design of low noise circuits - how to select the device size, choice of DC bias conditions and design device layout, are presented. Finally, some published noise models for the channel noise, induced gate noise and their correlation are discussed.

1. Introduction

Many high-speed or radio-frequency (RF) integrated circuits (ICs) are likely to be implemented in CMOS technology since very high unity-gain frequencies (/T) of deep sub-micron MOSFETs of more than 100 GHz have already been achieved. ' However, when working at high frequencies with deep sub-micron devices, the noise generated within the device itself will play an increasingly important role in the overall noise performance of analog circuits.3"5 Due to the long turn around time and the high cost of actual fabrication of an analog circuit, noise simulation of an analog circuit becomes a realistic alternative to determine whether the overall noise performance of a circuit would be good enough to allow the circuit to function properly.

In order to perform accurate noise simulation, an appropriate physics-based noise model that can predict accurately the noise performance of transistors is required. This model should be valid over a wide range of operating conditions of frequencies, currents and device geometries and it is urgently needed for the design and simulation of RF CMOS integrated circuits (ICs).

Before going into the details of the noise characterization of MOSFETs, a general noise theory to calculate the four noise parameters of a noise two-port network - minimum

199

mailto:[email protected]

mailto:[email protected]

1086 C.-H. Chen & M. J. Deen

noise figure (NFmin), equivalent noise resistance (/?„), optimized source impedance (Ropt)

and optimized source reactance (Xopt) is presented in section 2. It is then followed by the direct calculation technique in section 3. This technique is used to calculate these four noise parameters based on any equivalent noise circuit model. In addition, circuit simulators are often used by circuit designers and they might want to verify the noise model based on the compact model built in the circuit simulator. Therefore, another calculation method for the noise parameter calculation based on compact models is also presented.

Parasitics in the test chip is another important issue in the RF noise modeling.8"11 With the continuous downscaling of the device dimensions, the impact of the surrounding parasitics on a transistor's characteristics has gained importance in the RF noise measurements. In Refs. 12 and 13, a noise de-embedding method based on a parallel-series configuration was presented. This method assumes that the capacitive effect of metal interconnections between the probe pads and the transistor can be lumped into the probe pads and the inductive and resistive effects are modeled in series with the transistor at the frequencies of interest. However, this might not be true for designs with long (or wide) interconnections, or at operating frequencies of several tens of GHz. Therefore, the DUT (Device Under Test) has to be modeled as probe pads, interconnections and the transistor connected in a cascade configuration. The method presented in Ref. 14 is based on a cascade configuration, but it requires specific equivalent circuit models for both probe pads and the metal interconnections. This means that the de-embedding results rely on the accuracy of the equivalent circuit models and the element values used in the calculation. In addition, this procedure is not easy to automate since the parasitic elements in the equivalent circuit model are both technology and design dependent. In section 4, two de-embedding methods based on the parallel-series and cascade configurations are presented in detail.

Verification of the noise model has always been challenging in the RF noise modeling

of MOSFETs. Presently, models of the channel noise that are physics-based are confirmed

by the measured minimum noise figure (NFmin) of devices through the help of a device

simulator or the device's small-signal model.15,16 However, the accuracy of the small-sig

nal model, the values of model parameters used in simulation and the noise model itself

will all affect the simulated noise parameters. These factors make the confirmation of

noise models more difficult, even when accurate noise parameters were measured. In addi

tion, when transistors operate in the GHz range, the random potential fluctuations in the

channel resulting in the channel noise will be coupled to the gate terminal through the gate

oxide capacitance and cause the induced gate noise, which is usually correlated with the

channel noise. Because of the difficulties in the extraction of the induced gate noise and its

correlation term with the channel noise, several noise models17'18 and simulation results1

have been presented, but they could not be verified directly with the noise parameters

obtained from RF noise measurements for deep sub-micron MOSFETs. Therefore, to have

200

RF CMOS Noise Characterization and Modeling 1087

the proper topology of a equivalent noise circuit suitable for RF modeling, to obtain the

element values of the equivalent noise circuit directly from the measured scattering

parameters (or y-parameters), and to get the channel noise, induced gate noise and their

correlation directly from RF noise measurements are crucial for the high-frequency noise

modeling of deep sub-micron MOSFETs.

In this paper, a systematic procedure to extract the induced gate noise (ij), channel

noise (id) and their cross-correlation {i id*) directly from the S-parameter and RF noise

parameter measurements is presented in section 5. With the help of the direct calculation

technique described in section 2, the extracted noise currents are fed back to the equivalent

noise model to calculate the noise parameters - minimum noise figure (NFmin), equivalent

noise resistance (Rn) and optimized source reflection coefficient (Topt) - and to compare

the calculations to the measured data for the verification of the extracted noise sources.

After that, the extracted noise currents of the deep sub-micron MOSFETs fabricated in a

0.18 urn CMOS process as a function of frequency, bias condition and channel length are

presented and discussed. Based on the measured a.c. and noise parameters, some consider

ations for the design of low-noise circuits are discussed in section 6.

Finally, some noise models published in the literature for the channel noise, induced

gate noise and their correlation are included and discussed.

2. Noise Parameters

The noise figure, defined as the signal-to-noise ratio at the input port divided by signal-to-noise ratio at the output port, is widely used as a measure of noise performance of a noisy two-port network. It is usually expressed in decibels (dB). The noise figure (NF) is generally affected by two factors - the source (input) impedance at the input port of a network and the noise sources in the two-port network itself. In general, the noise figure of a two-port network with any arbitrary source impedance can be calculated from

W = NFmin + 7? • KG, - Gopt)2 + (Bs - Bopf\ (1)

s

or

N F = N F . + ^ ^ l 2 . r = *S+JXS-ZQ ( 2 )

where Gs is the source conductance, Bs is the source susceptance, Gopl is the optimized source conductance, Bopt is the optimized source susceptance and Z0 is the system impedance. From (1) and (2), it is shown that the four noise parameters - the minimum noise figure (NFmin), the optimum source (input) impedance (Zopt) for the NFmin, and the

201


equivalent noise resistance (/?„) which characterizes how the noise figure increases if the source impedance deviates from the optimum value - will reflect how noisy a two-port network itself will be.

A noisy two-port may be represented by a noise-free two-port and two current noise sources as shown in fig. 1(a), and these two noise sources are usually correlated with each other.

H-

"i <.(j ;

Noise-Free

Two-Port

A : ( Jh V2

-o o f~\

•o Noise-Free

Two-Port

(a) (b)

Fig. 1. Different representations of a noisy two-port network.

Based on the y-parameters of the two-port and the noise source information (i\, i2 and their correlation term T^*), we may evaluate the noise parameters of the two-port by transforming the noisy two-port to a noise-free two-port with a noise current and a noise voltage sources at the input side of the two-port (as shown in fig. 1(b)). Here, i and u and

the correlation factor called Ycor are defined as

l ' = im

+ uYcor (3)

and

'"«* = Yr„M . (4)

where iun is the part of noise current in i that is uncorrelated to u and uYcor is the part that is fully correlated to u. In addition, the values of i, u and Ycor can be calculated from

1 . u = -y~i2, (5)

M l . 721

(6)

' l ' 2 * Ycor ~ M 1 _ I 2 1 ^ = ^ ' - Gcor+JBcor> (7)

202


and the noise power of i and u can be calculated from

u = = 4kTAfRu (8)

'21

and

\i\2 = liZ + l i / [21

v * Mi

2Re\ili2*-f-\ = 4kTAfGi l21

From (7) to (9), we can calculate the four noise parameters using

J? Ru>

opt

B

k "' _ _ D

opt cor

and

NF„ = l + 2Rn(Gcor+Gopt)

(9)

(10)

(ID

(12)

(13)

Another approach to calculate the noise parameters which is suitable for computer-

aided analysis is to use the generalized admittance matrix of a noisy two-port net

work.20'21 According to the noise circuit shown in fig. 1, we can write the admittance

nodal equations at port 1 and port 2 as

(14) /21 *22_

+ B

P h

.'2

= h

where [B] - [1 0] and [D] = [0 1], and define the noise correlation matrix [C] as

[C] = M ' l * ' l z 2

l2ll l2l2

(15)

Using the y-parameters, [B], [C], and [D] matrices defined in (14) and (15), Ru, Gt and

Ycor can be calculated from the following expressions21

R.. = 1

" 4kTA -/• -^x[D]*x[Clx[D]T

[ 2 l

(16)

203


G ' 4/fcTA, f< [B]--^x[D] r21

x [ C ] x W - T ^ x f D ] r21

(17)

and

cor c o r ' cor 4kTAfRnYn* [D]*x[C]x IB] x[D] (18)

where the asterisk (*) denotes the complex conjugate and T denotes the transpose of the matrix. Once Ru, G, and Ycor calculated from (16) to (18), the noise parameters can be calculated using (10) to (13).

3. Noise Parameter Calculation of MOSFETs

The noise model of MOSFETs, in general, are made up of active two-ports, passive components, and some noise current (voltage) sources. The accuracy of noise modeling relies on the topology of small-signal model combined with the appropriate values for model elements which can accurately predict the electrical performance of devices, and the knowledge of the physical noise sources. Assuming that an appropriate small-signal model is available, all the element values of the capacitors, resistors, etc. and the location of noise sources in the small-signal model are obtained, then there are two methods that can be used to calculate the noise parameters - minimum noise figure (NFmin), equivalent noise resistance (Rn) and optimized source reflection coefficient (Topt) of a noisy two-port:

(i) direct matrix analysis based on the equivalent noise circuit of the two-port13'

and

(ii) circuit simulator analysis based on compact models in the circuit simulators (e.g.

Spectre, HSPICE,... etc.).

3.1. Direct matrix analysis

The advantage of the direct matrix analysis13'20 is that it easily allows designers to charac

terize the noise sources in the equivalent noise circuit model if there is any correlation

existing between the noise sources. This analysis can serve as a tool to develop a proper

noise model and to verify its implementation in a compact model of a circuit simulator. In

this section, the theoretical background for the noise parameter calculation of MOSFETs

will be introduced. This method can be used in any sophisticated equivalent noise circuit

with any correlated noise sources.

204


Direct calculation of noise parameters uses a matrix operation based on the noisy two-port network theory mentioned in section 2. Figure 2 shows one of the RF noise models of an intrinsic MOSFET that is suitable for high-frequency circuit applications.13 In order to perform the matrix calculation of the noisy two-port shown in fig. 2, we transform our noisy circuit model into its equivalent graph for network analysis. Figure 3 shows the network graph of the equivalent noise circuit model shown in fig. 2.

S/B

Fig. 2. Equivalent noise circuit model of an intrinsic MOSFET suitable for RF applications.

T H T Y ^ Y , 1 • ^ 1 "

>G

V i \

•

Y2 v4

i K ^ Y * gmV Y 5 t TA ii

[ v 1 ' 'Y° r 1

AL. ^ v 5 ^

' Y8 i D

^ v '

' (jx V7 (ground)

Fig. 3. The network graph of the equivalent noise circuit model shown in fig. 2.

Based on the network graph shown in fig. 3, we write the node equations corresponding to each node (sub-set) in a matrix form as follows,

205


Y, 0

0 Y3

-Yx 0

0 ~Y3

0 0

0 0

- ^ 1 0 0

0 -Y3 0

Yl + Y2+Y,+ Y6 -Y2 - r 4

Sm~Y2 Y2+Y,+ Y5+Yz -gm-Y5

-Sm~yA -Y5 gm+Y4+Y5+Yl

o - r 8 o

[Y]6x6

+

0 0 1 0 0 0

0 0 0 0 1 0

- 1 0 - 1 0 0 0

0 - 1 0 0 - 1 0

1 1 0 1 0 0

0 0 0 0 0 1

; '.

l8

ls lD

]DB_

h 0

0

0

0

0

0

0

^ 8

0

Yi+h

[A]6x6 [ i j

y,

V4

[V]

(19)

where Yj = 1/Rc Y2 = sCGD, Y3 = 1/RD, Y4 = sCGS, Y5 = 1/RDS, Y6 = sCGB, Y7 = *CBS

+ 1/Rs, Yg = SCDB> Y9 = 1/RDB' S = J® a n d u) is the angular frequency. Once the matrix

equations are formulated, die network is reduced by eliminating four nodes - node 6, 5, 4,

and 3, one by one, leaving only the input and output nodes - node 1 and node 2. For exam

ple, we eliminate the node 6 first, then each element of Y and A not in row 6 will be trans

formed according to the following formulas,

Yu = y . y 6 / X y , 6

^66 ( 1 < * < 6 ) ( 1 < 7 < 6 ) (20)

A _±S£L< ( i < ; < 6 ) ( 1 * 7 * 6 ) . (21)

Row 6 and column 6 are deleted from the Y matrix in the first step, however, for the A

matrix, only the 6th row of A is deleted and 6 columns remain. This procedure is repeated

until only the input and output nodes remain, at which point, the Y matrix is 2x2, and the

A matrix is 2x6 with complex elements. Now, we define the B and D matrix by

= [A]. (22)

The correlation matrix C of our equivalent noise circuit model is

206


c =

W W w w

0 0

0 0

0 0

0 0

0

0

^G^G

0

0

0

0

0

0

lsls

0

0

0

0

0

0

iDlD

0 ir

0

0

0

0

0

i *

(23)

By using (16) to (18), and (10) to (13), we can directly calculate the four noise parameters

ofaMOSFET.

3.2. Circuit simulator analysis

As mentioned above, the noise figure (NF) of a noisy two-port can be represented by its minimum noise figure (NFmin), equivalent noise resistance (Rn), and optimized source impedance Zopt = Ropl + j»Xopt given previously in (1). If we rearrange (1), then it can be written as

NF = A + v "J

Bs (24)

where Gs is the source conductance and Bs is the source susceptance (i.e. Gs = Re(l/Zs)

and Bs = Im(l/Zs)) and the four noise parameters can represented by

K = B,

and

NF.

UBC-D2

ôpt -

Bopt =

r „ ; „ = A +

IB

D 2 5 '

UBC-D1

(25)

(26)

(27)

(28)

If we provide values for four sets of linearly independent source impedances (Zs) and calculate the corresponding noise figure (NF), we obtain four linear equations and can solve for the four variables A, B, C, and D in (24). The four noise parameters can then be calculated from (25) to (28).

207


The next question is how to calculate the noise figure of a noisy two-port using a circuit simulator? By definition, the noise figure is the signal-to-noise ratio at the input port divided by the signal-to-noise ratio at the output port, i.e.

noise power referred to the input port

5. t

NF = AkTR, {G„-4kTR •

v a s N

DUT' VGn

G S. a in

4kTR„ (29)

Ga-4kTRs + NDUT

where Ga is the power gain of the device and NDUT is the noise power at the output port generated by the device itself. In (29), the numerator of the second expression at the right hand side can be obtained from the square of INOISE which is the total output noise power referred to the input port and usually can be calculated by a circuit simulator. Therefore, NF can be obtained by the square of INOISE divided by 4kTRs.

4. De-embedding of Noise Parameters and Required Dummy Structures

De-embedding techniques are based on the noise power matrix first introduced by Haus

and Adler23 and later renamed the noise correlation matrix by Hillbrand and Russer. In

Ref. 22, various representations and transformations have been tabulated to demonstrate

that the correlation matrix was ideally suitable for the computer-aided analysis of noise in

linear two-port circuits. In general, the device-under-test (DUT) can be modeled by a

physical equivalent circuit which is either in a parallel-series configuration (shown in fig.

4) or in a cascade configuration (shown in fig. 5).

Port 1

r _

o—L

- 1

YPAD

ZINT1

v „ . ' 5 U B

Transistor

ZINT3

ZINT2 r "1

YPAD

- J — o

D

Port 2

L J L _l Probe pads Probe pads

Fig. 4. Equivalent circuit diagram representing the structure of a DUT which includes probe pads, metal

interconnections and a transistor connected in a parallel-series configuration.

208


G

Port 1

s

Probe pads

[APAD]

Interconnections (Metal lines)

[AINT]

Transistor

[ATRANS]

Interconnections (Metal lines)

[AINT]

Probe pads

[APAD]

D

Port 2

S

LYPAD 1 J LYPAD 1 J

[AIN] [AOUT]

Fig. 5. Equivalent circuit diagram representing the structure of a DUT which includes probe pads, metal interconnections and a transistor connected in a cascade configuration.

In fig. 4, YPAD is the admittance between signal pads and ground, YS(JR is the admittance between the input port and the output port and ZjNT's are the impedances of the interconnections between the pads and the transistor.

In this section, the commonly used de-embedding procedure based on the parallel-series configuration is first introduced. This is then followed by the de-embedding procedure and dummy structures based on the cascade configuration.

4.1. Parallel-series configuration

The RF probe-pad parasitics are de-embedded from the measured noise parameters with

the help of "OPEN" and "SHORT" dummy structures. Figure 6 shows the layouts of a

DUT and dummy structures used in the method based on the parallel-series configuration.

Transistor

warn, G DUT OPEN SHORT

Fig. 6. A device-under-test (DUT) and its corresponding "OPEN" and "SHORT" dummy structures for the DUT modeled in the parallel-series configuration.

209


The "OPEN" dummy structure consists of the signal pads and interconnections without the transistor. The "SHORT" dummy structure consists of the signal pads and interconnections except with shorted interconnections at the location of the transistor. Based on the DUT and dummy structures shown in fig. 6, the procedure for the noise parameter de-embedding12'13 is now described. All details are given for completeness.

1. Measure the scattering parameters [SDUT], [SOPEN ] and [SSHORT] of a DUT, "OPEN"

and "SHORT" dummy pads, and then convert each of them to the Y parameters EN] and [YSH0RT] using the,

(l-Sn)(l + S22) + SnS21

[YDUT], [Y0PEN] and [YSH0RT] using the conversion formula

[11 =

-2S 12

-25. 21 ( l + 5 n ) ( l - 5 2 2 ) + S12521

Z0-[(l + Sn)(l+S22)-SnS2l]

DUT

(30)

2. Measure the noise parameters, N F ^ " " r , YoptDUT and Rn

DUT of the DUT.

3. Calculate the correlation matrix [CADUT] of the DUT from the measured noise

parameters using

[C?" 7 ] = 2kT NF* UT

min

DUT MlPUT 1

' * o o t > •K opt

•R PUT, J)UT

Y°. opt *ricf

(31)

where k is Boltzmann's constant, T0 is the standard temperature (290°K), and the

asterisk denotes the complex conjugate.

4. Convert the [CADUT] matrix to its [CY

DUT] correlation matrix using

[C?O T] = [iJ3UTUCDA

UT}liJ'UT]' (32)

where [TDUT] is given by

[T° UT, r l l

r21 UT

(33)

and the f in [TDUT]^ denotes the Hermitian conjugate.

5. Calculate the correlation matrix [Cy'

ÔPEN

OPEN ] of the "OPEN" dummy structure with

[Cy ] = 2kTS{([Y°PEN]) (34)

210


where <R() stands for the real part of the elements in the matrix and T is the absolute temperature at which the measurement was made.

6. Subtract parallel parasitics from the [YDUT] and [YSH0RT] according to

[Yf07] = [yDUT]-[YPPEN] Bnd

.ySHORT, _ ^HORT,_,,X)PEN,

7. De-embed [CYDUT] from the parallel parasitics using

(35)

(36)

(37)

8. Convert the [Y?m] and [YjSH0RT] to [ZIDUT] and [ZiSH0RT] with the conversion

formula

[Z] = ^11 ^22 — ^12^21

22 ~Yn

- i21 11

(38)

9. Convert [CYjDUT] to tCZIDUT] with

[c°^ = vrncT^n • (39)

10. Calculate the correlation matrix [CZISHORT] of the "SHORT" test structure after de-

embedding the parallel parasitics with

[CSZ"°RT] = 2km([ZS,H0RT]). (40)

11. Subtract series parasitics from the [Zj0177] to get the Z parameters [ZTRANS] of the

intrinsic transistor using

[ZTHANS] = [z0OTj _ tfBOKT^ ( 4 1 )

12. De-embed [CZi ] from the series parasitics to get the correlation matrix [Cz] of an intrinsic transistor using

[Cz] = [C^r]-[C^r] (42)

13. Convert the £zTRANS] of the intrinsic transistor to its chain matrix [ATRANS] with the conversion formula

[A] J_ *21

'11 Z 1 1 Z 2 2 - Z 1 2 Z 2 1

-22

(43)

211


14. Transform [Cz] to [CA] with

[CA] = [TA][CZ][TAV (44)

where [TA] is given by

[TA] = 1 _ 4 TRANS 1 An

0 -A™ANS (45)

15. Calculate the noise parameters, NFmin, Yopt and Rn of an intrinsic transistor from the noise correlation matrix in chain representation [CA] using the expressions

NFmin = 1 + ik*(Cl2A> + J^ÎZA " (3(C1 2 A))2) , (46) kr

4CUAC22A~^(-C\2A>} + ' S ( C - 1 2 A ) 1 opt ~ r ^ '

C11A

and

C HA R„ = — ^ (48) n 2kT K '

where 3( ) stands for the imaginary part of the elements in the matrix and i is the

imaginary unit.

4.2. Cascade configuration

In the cascade configuration, the DUT is modeled by the networks of probe pads, inter

connections and a transistor connected in a cascade configuration.24'25 Figure 7 shows the

layouts of a DUT and dummy structures used in the de-embedding procedure based on a

cascade configuration.

In these dummy structures, the "OPEN" dummy structure consists of signal pads with

out the metal interconnections and the transistor, the "THRU1" dummy structure consists

of the signal pads and the section of the interconnection at the input port of the transistor

in the DUT and the "THRU2" dummy structure consists of the signal pads and the section

of the interconnection at the output port of the transistor. The electrical chain matrices of

the interconnections at the input and output ports of the DUT can be directly obtained

from the scattering parameter measurements of these two additional "THRU" dummy

structures.

212


G

Transi.

S

G

W >tor

WA

1 I

////A

G

S

G

G ^ I I L . fZ Metal Lines

G ^ G G ^ G

G i

zzz

mmm. G G ^ G G % G

DUT OPEN THRUl THRU2

Fig. 7. A device-under-test (DUT) and its corresponding "OPEN", "THRUl" and "THRU2" dummy structures

for the DUT modeled in the cascade configuration.

Based on the DUT and dummy structures shown in fig. 7, the procedure for noise parame

ter de-embedding,24'25 in detail, is as follows.

1. Measure the scattering parameters [SDUT], [S0 P E N] , [STHRU1] and [STHRU2] of the

DUT, "OPEN", "THRUl" and "THRU2" dummy pads.

2. Measure the noise parameters - NFminDUT , Yop t

DUT and RnDUT of the DUT and

calculate the correlation matrix [CADUT] using (31).

3. Convert [SOPEN] to its Y parameters [YOPEN], using (30). Then calculate YPAD using

YPAD = y?xPEN+ y?2PEN(or Y°2

PEN+ Y°fEN)

and the ABCD parameters of the input/output pads [A ] from

[A PADn

PAD

(49)

(50)

4. Calculate the ABCD parameters [ATHRUl] and [ATHRU2] from [STHRU1] and rgTHRU2] u s m g t n e conversion formula

[A] 2S. 21

(1 + Sn)(l-S22) + SUS21 [(1 + S n ) ( l + S22)-Sl2S2l] • Z0

L ( 1 - S U ) ( 1 - S 2 2 ) - S 1 2 S 2 1 ] / Z 0 ( l - 5 n ) ( l + 522) + 512S21

.(51)

5. Calculate the ABCD parameters [AIN] and [A0UT] which include the parasitic effects of probe pads and interconnections connected in cascade at the input and output ports from

r.W, r .THRUl-.r .PAD,-l [A ] = [A ][A ] (52)

213


and

r .OUT. r .PAD1-lr ATHRU2-. [A ] = [A ] [A ] (53)

where the superscript " - 1 " denotes the inverse of the matrix.

6. Convert [SDUT] to its ABCD parameters [ADUT] using (51) and calculate the ABCD parameters [A ] of the intrinsic device from

r . TRANS-. , AIN-.-lr .DUT-.r .OUT.-l [A ] = [A ] [A ][A ] (54)

7. Convert the ABCD parameters [Am] and [A0UT] to their Z parameters [ZIN] and [Z0UT] with the conversion formula

[Z] = -C

A AD-BC

1 D (55)

8. Calculate the correlation matrix [Cz ] and [Cz°UT] which include parasitic effects

from the probe pads and interconnections connected in cascade at the input and output

ports from

[df] = 2kTR{[z!N]) (56)

and

[c°7UT] = 2km{[z°UT]) (57)

where 9l() stands for the real part of the elements in the matrix.

9. Convert the [CZIN] and [Cz

OUT] matrixes to their correlation chain matrixes [CAIN]

OUTn and [CAUU1] with the conversion formula

[c'AN] = [ r w ] [c^] [ r / A r ] +

and

[C°UT] = [TOUT][COUT][TOUT]t

where the transformation matrix [T ] and [T0UT] are

(58)

(59)

[T1N] = 1 -A(r

0 - A ^ (60)

and

214


rjOUT-i _ 1 -AOUT 1 An

0 -A0UT

U A2l

(61)

10. Calculate the correlation matrix [CA] of the intrinsic transistor using

[CA] = [A'^-HlC^-lCâA1^)-1 -[ATRANS][COUT][ATRANS}t ^ ( 6 2 )

11. Calculate the noise parameters - NFmin, Yopt and Rn of the intrinsic transistor from the

noise correlation matrix [CA] based on (46) to (48).

In step 7, the reason to transform the ABCD parameters [AIN] and [AOUT] to their Z

parameters for calculating die correlation Z matrixes instead of to their Y parameters to

calculate the correlation Y matrix is to avoid the singularity error for the designs without

the interconnections during the transformation.

4.3. Measurement results

In order to verify the de-embedding procedure based on the cascade configuration and to compare it with the traditional de-embedding procedure, three different DUTs -PAD50x40M, INT160L and INT160R and their corresponding dummy structures -"OPEN", "SHORT", "THRU1" and "THRU2" are designed for the verification of the algoritiim and their layouts are shown in fig. 8. All test structures are designed as ground-signal-ground (GSG) configurations and fabricated in a standard 0.35 um CMOS technology through Canadian Microelectronics Corporation (CMC), Kingston, Ontario.

In these structures, the dimension of the signal pads are 50 |im x 40 p.m (PAD50x40M) and the channel length and width of the transistor is 0.35 \ua and 12 x 10 jam (twelve 10 |im wide fingers connected in parallel), respectively. The dimensions of the metal interconnections at the input port (Ij) and output port (I2) are approximately zero for PAD50x40M. For INT160L, lx is 160 |Lim x 1 im and I2 is ~ 0 jam2 (the drain of the transistor is connected right next to the output pads). On the other hand, for INT160R, \x is - 0 pim2 and I2 is 160 \im x 1 \xm (the gate of the transistor is connected right next to the input port).

For the de-embedded noise parameters, figs. 9 to 12 show the measured (squares) and de-embedded minimum noise figure (NFmin), equivalent noise resistance (/?„), optimized source impedance (ROPT)

anc* optimized source inductance (LOPT) versus frequency characteristics of an INT160L biased at VDS = 1.0 V and VGS = 1.2 V (IDS = 7.8 mA) based on the cascade (solid circles) and the parallel-series (lines) configurations. The scattering and noise parameters are measured by using the ATN NP5B S-Parameter and Noise Parameter Measurement System (0.3 - 6 GHz) and both de-embedded procedures are applied.

215


PAD50x40M INT160L INT160R

T 1

T 1 • • T

1 OPEN50x40M OPEN160L OPEN160R

SHORT160L SHORT160R THRU160L/R

Transistor Interconnections

Fig. 8. Layouts of the test DUTs (PAD50x40M, INT160L and INT160R) and their corresponding dummy structures used in the de-embedding method based on the parallel-series configuration (OPEN50x40M, OPEN160L, OPEN160R, SHORT160L and SHORT 160R) and the proposed method based on the cascade configuration (OPEN50x40M and THRU160L/R) for the verification of the proposed de-embedding method.

216


l V^ l . ZV

fe1

INT160L Measured Data

\ -

Cascade Configuration

Parallel-Series Configuration

2 3 4 5 6

Frequency (GHz)

Fig. 9. Measured (squares) and de-embedded minimum noise figure (/Vfmm) versus frequency characteristics of

an INT160L with an n-type MOSFET (L = 0.35 urn and W = 12 x 10 urn) biased at VDS = 1.0 V and VGS = 1.2

V (IDS = 7.8 mA) based on the cascade (solid circles) and parallel-series configurations (lines).24

a

90 r

80

70

60

INT160L

a • ° Measured Data

Parallel-Series Configuration \

D a

V =1.2V Cascade Configuration GS

3 4 5

Frequency (GHz)

Fig. 10. Measured (squares) and de-embedded equivalent noise resistance (Rn) versus frequency characteristics

of an 1NT160L with an n-type MOSFET (L = 0.35 urn and W = 12 x 10 um) biased at VDS = 1.0 V and VGS =

1.2 V (IDS = 7.8 mA) based on the cascade (solid circles) and parallel-series configurations (lines).24

217


400

300

G 200

100

INT160L

VD S

= 1 - 0 V

V =1 2V Measured Data GS

D ^ Parallel-Series Configuration

. Cascade Configuration

2 3 4 5 6

Frequency (GHz)

Fig. 11. Measured (squares) and de-embedded optimized source impedance (Ropr) versus frequency characteristics of an INT160L with an n-type MOSFET (L = 0.35 um and W = 12 x 10 urn) biased at VDS = 10 V and VGS = 1.2 V (IDS = 7.8 mA) based on the cascade (solid circles) and parallel-series configurations (lines).24

30

20

10

0

Parallel-Series Configuration

INT160L

vM=i-ov

V c s = 1 - 2 V

. Measured Data n

•Cascade Configuration

3 4 5

Frequency (GHz)

Fig. 12. Measured (squares) and de-embedded optimized source inductance (L0pr) versus frequency characteristics of an INT160L with an n-type MOSFET (L = 0.35 um and W = 12 x 10 \im) biased at VDS = 1.0 V and VGS = 1.2 V (IDs = 7.8 mA) based on the cascade (solid circles) and parallel-series configurations (lines).24

218


It is shown that the de-embedding procedure based on the parallel-series configuration

will give higher RQPT ar"d L0PT, although the de-embedded NFmin and Rn based on cas

cade and parallel-series configurations are approximately the same. The reason for the

higher ROPT a nd ÔPT obtained based on the parallel-series configuration is because it

gives smaller Zr0pr- than that obtained from the cascade configuration. For the test struc

ture PAD50X40M, only the OPEN dummy structure - OPEN50x40M which has no inter

connection sections is used in the de-embedding, and both methods give the same ROPT

and LQPT. Therefore it is suspected that the smaller Z r 0 p r obtained from the parallel-

series configuration is caused by lumping the capacitive effects into the bond pads, and it

overestimates the admittance of the probe pads.

For the effect of the metal interconnections at different locations of a DUT, figs. 13 to 16 show the measured (dashed lines with symbols) and de-embedded (symbols) noise parameters versus frequency characteristics of PAD50x40M (circles), INT160L (triangles) and INT160R (squares) biased at VDS = 1.0 V and VGS = 1.2 V (IDS = 7.8 mA) based on the cascade configuration. From figs. 13 and 14, it is shown that the metal interconnection (Ij) at the input port of a transistor has more impact on NFmin and Rn than that (I2) at the output port because the resistive effect of the interconnection is amplified by the transistor to the output port. In addition, from measured and de-embedded Rn of PAD50x40M, the effect of probe pads does not affect the measured Rn of the transistor. Finally, from figs. 13 to 16, the de-embedding procedure based on the cascade configuration gives approximately the same results for three different test structures.

m -a

I"'

0

—A—: Measured A : De-embedded

INT160L..

INT160R/A Jg^*

a-A

S*

^PAD50x40M

s

V =1.0V DS

V =1.2V GS

2 3 4 5

Frequency (GHz)

Fig. 13. Measured (dashed lines with solid symbols) and de-embedded (symbols) minimum noise figure (NFmin)

versus frequency characteristics of PAD50x40M (circles), INT160L (triangles) and INT160R (squares) with an

n-type MOSFET (L = 0.35 urn and W = 12 x 10 urn) biased at VDS = 1.0 V and VGS = 1.2 V (IDS = 7.8 mA)

based on the cascade configuration.24

219


a

90

80

70

60

-A—: Measured A : De-embedded

vM=i.ov

V G S = L 2 V

A _ A - A ^

EST160L / ^ A A A ^~-A A

ESIT160R

PAD50x40M a

3 4 5

Frequency (GHz)

Fig. 14. Measured (dashed lines with solid symbols) and de-embedded (symbols) equivalent noise resistance (Rn) versus frequency characteristics of PAD50x40M (circles), INT160L (triangles) and INT160R (squares) with an n-type MOSFET (L = 0.35 um and W = 12 x 10 am) biased at VDS = 1.0 V and VGS = 1.2 V (IDS = 7.8 mA) based on the cascade configuration.

1.0

0.9

0.8 h

^ 0 . 7 :

0.6 :

0.5

A CU A-

vM=i-ov

VG s = 1 " 2 V

A : LNT160L

D : INT160R

g O: PAD50x40M

A~Sg

A : Measured A : De-embedded

3 4 5

Frequency (GHz)

Fig. 15. Measured (dashed lines with solid symbols) and de-embedded (symbols) magnitude of optimized source reflection coefficient (r0pr) versus frequency characteristics of PAD50x40M (circles), INT160L (triangles) and INT160R (squares) with an n-type MOSFET (L = 0.35 um and W = 12 x 10 um) biased at VDS = 1.0 V and VGS

= 1.2 V (IDS = 7.8 mA) based on the cascade configuration.24

220


60

40

s ^ 20

A : INT160L

• : INT160R

O:PAD50x40M -

v„=i.ov

V G S = L 2 V

^ ^

^Jl A JS- A Q

A A O

6 D

i t i

A A Q

A Q 0 —A—: Measured

A : De-embedded I . I . I

2 3 4 5 6

Frequency (GHz)

Fig. 16. Measured (dashed lines with solid symbols) and de-embedded (symbols) angles of optimized source reflection coefficient (r0pr) versus frequency characteristics of PAD50x40M (circles), INT160L (triangles) and INT160R (squares) with an n-type MOSFET (L = 0.35 um and W = 12 x 10 ujn) biased at VDS = 1.0 V and VGS

= 1.2 V (IDS = 7.8 mA) based on the cascade configuration.24

5. Extraction of Noise Sources in Deep Sub-micron MOSFETs

As mentioned in the introduction, the topology of the equivalent noise circuit model is important in the RF noise modeling of MOSFETs. Figure 17 shows the noise model of an intrinsic MOSFET that is suitable for RF applications. In fig. 17, gm is the transconduc-tance, T is the time constant,26 /?, is the channel resistance, RDS is the output resistance, CSB and CDB are source-to-bulk and drain-to-bulk junction capacitances respectively, and CGS, CGD, and CGB are gate-to-source, gate-to-drain, and gate-to-bulk capacitances, respectively. For the noise sources, i\ is the channel noise, i2 is the induced gate noise occurring at very high frequencies, i2

s and i2D are the noise current sources caused by the

source (Rs) and drain (RD) resistances, i2G is the noise current source caused by the poly-

silicon gate resistance (RG) which is important in the RF and noise modeling,16'27 and i2DB

is the noise current source caused by the substrate resistance (Rpg).

In this section, two extraction methods to obtain the channel noise of deep sub-micron MOSFETs based on the simplified equivalent circuit model at DC (section 5.1) and the full model valid at the frequencies of interest (section 5.2) will be presented. For the induced gate noise and its correlation with the channel noise, since they are frequency dependent, they have to be extracted at each measured frequency point based on the full equivalent noise circuit model.

221


internal part

G RG

1

% CGB -r-

V

S/B

Fig. 17. A complete equivalent noise circuit model suitable for RF noise simulation with ym = gmx(,l-ju>x).

5.1. Extraction of the channel noise

As mentioned in section 2, the noisy two-port may be represented by a noise-free two-port

and two noise current sources, one at the input port (ij) and the other at the output port (i2).

From (8) and (10), the power spectral density of i2 can be obtained from

^L = 4*rv |V 2 '21 (63)

where k is the Boltzmann's constant, 7" is the absolute temperature, Y2i is m e transadmit-tance from port 1 to port 2 of the noise-free two-port and Rn is the equivalent noise resistance which is a resistance cascaded at the input port that will produce the same amount of noise power spectral density as i2 does at the output port.

At low frequencies, if we convert the noise current sources associated with the para

sitic resistances to noise voltage sources and assume that all the capacitors in the equiva

lent noise circuits of BSIM328-29 (shown in fig. 18), MOS 930 '31 (shown in fig. 19) and

EKV32'33 (shown in fig. 19) models are open-circuited (i.e. all the admittances of the

capacitors are approximately zero), the equivalent noise circuit can be simplified to that

shown in fig. 21. Here, the thermal noise sources associated with the resistances as well as

the channel noise current have been included in the figure. Also, note that at low frequen

cies, the induced gate noise and its correlation with the channel noise tend to zero and

have therefore been omitted from the figure.

222


Fig. 18. BSIM3v3 RF noise model and its simplified noise equivalent circuit (parts with thicker lines) at DC or

low frequencies.28,29,34"37

G Rg G\

,'*>

9-rf=F iS-

CQD

/k\ / i s ' ' PU # € s/ dvy

* - * At !

£>'! fy D

W fV-jnn^

A

^fron * at

B T<V

r1"! ;Rb

^ " ^ f V a l 'd W8ds Q dd W

-'jun.d

- 0 *

Fig. 19. Philips MOS 9 noise model and its simplified noise equivalent circuit (parts with thicker lines) at DC or

low frequencies.30,31,34"37

223


R„

^ = (Vfe)-V(S())

D

Vo

O B

Fig. 20. EKV noise model and its simplified noise equivalent circuit (parts with thicker lines) at DC or low frequencies.

G ^ R G

o—0^W^

S/B

Fig. 21. Simplified equivalent noise model at DC or lower frequency. 34-37

In fig. 21, vj and v2D are the noise voltage sources caused by the source (Rg) and drain

(Rrj) resistances, v^ is the noise voltage source caused by the polysilicon gate resistance

(RG)-3 4"3 7

224


From the definition, the current noise power spectral density (Amp2/Hz) of the total

noise currents (i^) at the output port can be obtained from

lGout 2 - +

lSou\ lDout 2

- + ldout

A/ A/ A/

= 4 « V N 2

A/ A/ (64)

where

Y = 8mRDS

2 1 8mRSRDS + RD + Rs + R

(65) DS

Here, i^0H(, i\out, i2Dout and $o u ( are the noise currents contributed at the output port by

VQ, vj , vf, and the channel noise (;J) respectively, and they are given by

^2 i J2 f

^SM. = 4*77?,-. • A/

8mR m'xDS

A/ 5

JmRSRDS + RD + RS + RDSt

l+SmRDS '

8mRSRDS + RD + RS + RDS,

(66)

(67)

and

Dout

A/ = 4*77? r

1

° ySmRSRDS + RD + RS + RDS-

ldout

A/ = M.

R DS

8mRSRDS + RD + RS + RDS,

(68)

(69)

The induced gate noise (;2) and its correlation with the channel noise are negligible at low frequencies and are therefore neglected in (64). In addition, because CDB causes an open circuit at low frequencies, then there is no noise current contributed by i2

DB at the output port. Substituting (65) - (69) to (64), the power spectral density of the channel noise in MOSFETs can be calculated from Refs. 34 - 37,

id\2 = 4*7-. (Rnn-Rn-Rs)8

28mRs RD + RS

SJ°m ft DS R2

KDS

(70)

where Rno is the equivalent noise resistance extrapolated at low frequencies from the mea

sured Rn versus frequency characteristics.

225


5.1.1. Experimental results

A 0.36 jam n-channel MOSFET which consists ten 12 nm wide transistors connected in parallel and fabricated in a 0.25 nm CMOS technology is used as the device-under-test (DUT). The device is biased at VDS = 1.0 V and VGS = 0.9 V (IDS = 3.09 mA and the unity current gain frequency/T = 16.3 GHz). Based on the measured s-parameters and the parameter extraction method described in Ref. 38 to obtain the element values in the small-signal model, the extracted values of the model elements in fig. 17 are gm = 16.5 mS,RG = 9.2 Q,R s = RD= 1 Q, /?, = 9.91 Q,RDS = 2.56kQ, RDB = 11.5 Q, CGB = 0F, CGS

= 133 fF, CGD = 36.8 fF, CSB = 120 fF and CDB = 125 fF. In addition, by extrapolating the Rn versus frequency characteristics at low frequencies, Rno is 80 Q. for this bias condition. Based on these element values and (70), the power spectral density of the channel noise {i2

d) in this device is 3.13x10"22 Amp2/Hz at this bias condition.35 For the sensitivity of the extracted channel noise to the Rno, since Rno is usually much larger than RG and Rs, therefore, if there is ±10% inaccuracy in the extrapolated value of Rno, there will be about ±10% error in the extracted channel noise.

In order to confirm the extracted i | , figs. 22 and 23 show the measured and simulated NFmin and the normalized equivalent noise resistance rn (Rn normalized to 50 Q) versus frequency characteristics by using the calculation method described in section 3.11 3 '2 0 and the measured y-parameters without including the induced gate noise (i* in fig. 17) and its correlation with the channel noise (i i/ in fig. 17).

0 5 10 15 20 Frequency (GHz)

Fig. 22. Measured and simulated minimum noise figure (NFmin) versus frequency characteristics of a 0.36 ^m n-channel MOSFET.36

L = 0.36|im

W=12xl0uni extracted,/

226


as,

2.0

1.6

a 1.2 •8 N

I 0.8

0.4

0.0

, . Rno = rnox5QQ = 80Q extracted if

/

V D S = 1.0V

VG S = 0.9V L = 0.36um

ID S = 3.09mA W = 12xl0um

5 10 15

Frequency (GHz)

20

Fig. 23. Measured and simulated normalized equivalent noise resistance rn (/•„ = Rn I 50£2) versus frequency

characteristics of a 0.36 urn n-channel MOSFET.36

In these two figures (figs. 22 and 23), the solid lines are the simulated results based on

the extracted id from (70) and the dashed lines are based on the equation id = 8kTgm/3

which was suggested for long channel transistors but underestimates NFmin and rn for sub-

micron transistors. These results show that the calculated channel noise based on the sim

ple expression id = 8kTgm/3 cannot be used to predict the channel noise of sub-micron

MOSFETs biased in the saturation region, 9 which is typically where analog circuits are

biased.

Figures 24 and 25 show the measured and simulated Ropt and Lopt (X t divided by 27t/, where / is the operating frequency) versus frequency characteristics. In general, the extracted id from (70) can give very good agreement between the simulations and measurements for all the four noise parameters of MOSFETs without any parameter fitting of the measured noise parameters. This good agreement is also obtained without adjusting or changing any of the small-signal or large-signal equivalent circuit model parameters. Results at other biases, IDs = 0.3 mA (VGS = 0.64 V and/T = 5 GHz) and IDs = 1-0 mA (VGS = 0.74 V and/T = 10 GHz) were just as good those presented here.

227


200

150 "

V00

50

\ "

: k >l-

extracted id

8kT8m/3

• •

L =

W =

Vr*

vGs

IDS

0.36nm

12xl0jim

= 1.0V

= 0.9V

= 3.09mA

5 10 15 Frequency (GHz)

20

Fig. 24. Measured and simulated optimize source resistance (/?„„,) versus frequency characteristics of a 0.36 um n-channel MOSFET.36

4U

30

20

10

•

1 extracted

• Y

A id

2=8kTgJr*

i/

MLft.

L = 0.36nm

W = 12xl0nm

VDS=1.0V

VGS = 0.9V

IDS = 3.09mA

5 10 15 Frequency (GHz)

20

Fig. 25. Measured and simulated optimized source inductance (Lopt) versus frequency characteristics of a 0.36 Hm n-channel MOSFET.36

228


5.2. Extraction of the induced gate noise and the correlation noise

Because the induced gate noise (i •?) and its correlation with the channel noise (i if)

shown in fig. 17 are frequency dependent, they have to be extracted at each measured fre

quency. This section describes a general and systemic procedure for any equivalent noise

circuit to extract the power spectral densities of T1 and i if .40,41

For any given equivalent noise circuit (e.g. the one shown in fig. 17), we define the

internal part which consists of CGS, CGD, Rt, gm, RDS, j | and i2d, as a two-port network

with port 3-3' as the port 1 and port 4-4' as the port 2. On the other hand, the external part

which includes all the components outside of the dashed box in fig. 17, such as RQ, CGB,

Rs, RSB, i?oB' CDB a n ^ RD' is characterized as a four port network with port 1-1' as the

port 1, port 2-2' as the port 2, port 3-3' as the port 3, and port 4-4' as the port 4. Note that

ports 1-1' and 2-2' do not share a common reference terminal with the ports 3-3' and 4-4'.

Using the DUT and the dummy structures described in section 4.2, the induced gate noise,

channel noise and their correlation in MOSFETs can be extracted by using the following

15-step procedure. '41

1. Measure the scattering parameters SDVT, SOPEN, STHRU1 and STHRV2 of the DUT, OPEN, THRU1 and THRU2 dummy structures, respectively.

2. Measure the noise parameters, NFminDUT, YoptDUTand R„DUT°ftne DUT.

3. Perform a parameter de-embedding to get the intrinsic scattering (Fdev) and noise

parameters (NFmindev, Yoptdev and Rn,dev).24'25

4. Perform a parameter extraction based on Ydev and other measured data to get all the

element values (e.g. gm, CGS, CGD,... etc.) in the RF noise model.26

5. Calculate the chain correlation matrix Cêv of the transistor based on the intrinsic

noise parameters by

CAdev = 2kT0

n min,dev „ (y \=l n,dev T n,dev^ opt,dev'

NFmin,dev~l n . , „ , „ ,2

2 — R Y R \Y \

n,dev opt,dev n,dev\ opt,dev\

(71)

where k is Boltzmann's constant, T0 is the standard reference temperature (290°K) and the asterisk denotes the complex conjugate.

6. Calculate the four-port admittance matrix Yextr of the extrinsic part in the RF transistor

model by excluding Cgs, C„^ 8m' ^DS an(^ î which define the intrinsic part, and partition Yextr as

r

extr ~ Y Y • ee ei

Y Y (72)

229


where the submatrixes - Yee, Yei, Y^ and Yu are 2x2 matrixes.

7. Calculate the two-port admittance matrix Yintr of the intrinsic part in the RF transistor model.

8. Calculate the matrix D as follows

D = -Yei(Yii+Yintr) -1 (73)

9. Convert the noise correlation matrix C^jev to its admittance form CYljev by using

CYdev ~ TYCAdevTY (74)

where the t in TY denotes Hermitian conjugation (transpose and complex conjugate) and the transformation matrix TY is given by

TY = -Y 1

IU,dev *

-Y2X4ev °

(75)

10. Calculate the admittance noise correlation matrix Cyextr of the extrinsic part by'

CYextr = kT(Yextr+Yextr^

43

(76)

or

CYextr = 2km(Yextr) (77)

where Tis the device temperature, 9l() denotes for the real part of the matrix elements.

Partition CYextr as

Yextr

C C •

C C-(78)

where the submatrixes - Cee, Cei, C^ and C,-,- are 2x2 matrixes.

11. Calculate the admittance correlation matrix CYintr of the intrinsic part in the RF

transistor model from

Cv. , = D(CVJ -C )Z)t-C- flt-DC -C Yintr v• Ydev ee> i le i i ei u

(79)

where D,- - D~ .

12. Convert Yintr to its chain representation Aintr using the conversion formula

A = — wtr Y. -1

21, intr

' 22,intr 1

V V — V Y Y 111, intr122, intr ' 12, intr121, intr lU,intr

(80)

230


13. Convert Cy^tr to its chain matrix form CAinlr by using

CAintr ~ TACYintrTA[

where TA is given by

TA = 0 A

1 A

12, intr

22, intr

(81)

(82)

14. Calculate the noise parameters, NFmin, Yopt and Rn of the intrinsic part in the RF

transistor model from the noise correlation matrix CAintr by using the following

expressions.

NFmin = 1 + £r(*{CnA.ntr) + Jc1 1 A^rC2 2 A > J .„r r-(3(C1 2 A > I .„,r))- | (83)

^ 11 A,intr<-:22A,intr~ ( " ^ 1 2 A , i i i f r ) ) + - / ' " ^ 1 2 A , i n f r ) y =

opt , and

HA.infr

/?n 2*r

(84)

(85)

where 3 ( ) stands for the imaginary part of elements and j is the imaginary unit.

15. Calculate the power spectral density of the channel noise i j , induced gate noise i2 and

their correlation i if from

^ = UT0Rn\Y2Unt\\ (86)

HA2

A/ = 4*r o J ! B { |y o p J2- |y 1 1 > I . j2 + 2ca [ (y n i i | i r r _y c < > r )y l l i . | | f r *] } , (87)

and

A/ - 4kT0(Yn intr-Ycor)RnY2Xiintr*

where Fcor is given by

NFmi„ - 1 y _ min y

cor 2R °P1'

(88)

(89)

231


5.2.1. Experimental results

The DUTs are n-type MOSFETs with channel width W = 10 x 6 \im (10 fingers) and lengths L = 0.97 \xm, 0.64 \ixa, 0.42 Jim, 0.27 |am and 0.18 um, respectively, fabricated by Conexant Systems Inc., Newport Beach, CA. Figures 26 and 27 show the measured unity gain frequency (fT) and the minimum noise figure (NFmin) versus gate voltage VGS characteristics for different channel lengths.

3

V^CVolt)

Fig. 26. Unity gain frequency (fT) versus VGS characteristics obtained from the measured |h21| at 0 dB for the n-type MOSFETs with channel width W = 10 x 6 nm (10 fingers of width 6 urn) and lengths L = 0.97 um, 0.64 (im, 0.42 lira, 0.27 um and 0.18 um, respectively, biased at VDS = 1.0 V.

oq 4

I 1 3

2

1

0

/ = 2 GHz

W = 10x6 um

L=0.97um L=0.64um L=0.42um L=0.27um L=0.18um

VGS(Volt)

Fig. 27. Measured intrinsic minimum noise figure (NFmin) versus VGS characteristics for the n-type MOSFETs with channel width W = 10 x 6 (im (10 fingers of width 6 |im) and lengths L = 0.97 urn, 0.64 um, 0.42 |im, 0.27 Um and 0.18 um, respectively, biased at VDS = 1.0 V.

232


Measured data were obtained by using an ATN NP5B Noise and S-Parameter Measurement Systems (0.3 ~ 6 GHz). All the parasitic effects from probe pads and interconnections were de-embedded from the measured s-parameters using the procedure described in section 4.2.24'25 The VGS biases for the peak/T and the lowest NFmin are reduced when the channel length reduces and this trend makes MOSFETs very possible for low power, low noise RF circuit designs. The measured peak/T of the 0.18 \xm devices is about 50 GHz at the specified VDS = 1.0 V. Figures 28 and 29 show the measured IDs versus VGS

and VDS characteristics to demonstrate the DC performance of the devices.

I

L = 0.18|xm

L = 0.27(im

L = 0.42nm

L = 0.64um

L = 0.97nm

Fig. 28. Drain current (IDs) versus gate voltage VGS characteristics for the n-type MOSFETs with channel width W = 10 x 6 nm (10 fingers of width 6 nm) and lengths L = 0.97 \im, 0.64 urn, 0.42 nm, 0.27 urn and 0.18 nm, respectively, biased at a drain voltage VDs = 1.0 V.

50

U c Q

: W=10x6um

L=0.18um

Fig. 29. Drain current (IDS) versus drain voltage VDs characteristics for the n-type MOSFETs with channel width W = 10 x 6 jim (10 fingers of width 6 nm) and length L = 0.18 (im biased at the gate voltages VGS = 0.8 V, 1.0 V, 1.2 V, 1.4 V, 1.6 V, 1.8 V and 2.0 V, respectively.

233


In the extraction procedure, the element values used in the RF noise model are crucial

to obtain the noise sources. In this work, they are directly obtained from DC c44-48 measurements^"*8 and the intrinsic y-parameters. , z / Figures 30 to 33 show the mea

sured (symbols) and simulated (lines) y-parameters of an n-type MOSFET with channel

width W = 10 x 6 Jim (10 fingers) and length L = 0.18 Jim biased at V D S = 1.0 V and V G S

= 1.2 V based on gm = 28.4 mS, RG = 5.75 £2, RD = Rs = 1.75 Q, RDS = 486 Q, Rt = 90.6 Q,

RDB = 134 Q, CGS = 68.5 fF, CGD = 30.6 fF, CGB = 0.0 fF, CDB = 76.9 fF, CSB = 496 fF,

and x = 4 . 5 2 x l 0 - 1 2 s based on the equivalent circuit shown in fig. 17.

as

1

3.5xl0"3

3.0xl0"3

2.5xl0"3

2.0xl03

1.5xl03

l.OxlO"3

5-OxlO"4

0.0

:-^L^ -.msmsssWl0*^

':

;

•JJê*******

rtfP?

[ r itrf I f I f f ,L=0.18um

W=10x6um

V = 1 . 0 V DS

V =1.2V GS

^ ^ ^

0 1

Frequency (GHz) Fig. 30. Measured (symbols) and simulated (lines) real parts of y^ and yî v e r s u s frequency characteristics for the n-type MOSFET with the channel width W = 10 x 6 um (10 fingers of width 6 um) and length L = 0.18 um biased at VDS = 1.0 V and VGS = 1.2 V.

L=0.18um

W=10x6um

vM=i.ov

V a s = 1 - 2 V

4.0x10"

£ . 3.0x10"

2.0x10'

~ l.OxlO'3

0.0 0 1 2 3 4 5 6

Frequency (GHz) Fig. 31. Measured (symbols) and simulated (lines) imaginary parts of y\\ and y22 versus frequency characteristics for the n-type MOSFET with the channel width W= 10x6 um (10 fingers of width 6 um) and length L = 0.18 um biased at VDS = 1.0 V and VGS = 1.2 V.

234


a;

ft!

3.0x10"'

2.0x10"

1.0x10"'

0.0

Re(yn)

L=0.18nm

W=10x6nm

V G S = 1 - 2 V

Re(yl2)

0 1 2 3 4 5 6

Frequency (GHz)

Fig. 32. Measured (symbols) and simulated (lines) real parts of yn and >2i versus frequency characteristics for the n-type MOSFET with the channel width W = 10 x 6 um (10 fingers of width 6 um) and length L = 0.18 um biased at VDS = 1.0 V and VGS = 1.2 V.

0.01-

-1.0x10 •

-2.0xl0:

jf -3.0x10"

1 -4.0xl0":

>> -5.0xl0":

-6.0xl0":

-7.0xl0":

1 2 3 4 5 6

Frequency (GHz)

Fig. 33. Measured (symbols) and simulated (lines) imaginary parts of y^ and y^\ versus frequency characteristics for the n-type MOSFET with the channel width W = 10 x 6 um (10 fingers of width 6 um) and length L = 0.18 um biased at VDS = 1.0 V and VGS = 1.2 V.

Figures 34 to 37 show the extracted gm, RDS, CGS and CGD versus gate bias VGS

respectively, for devices with different channel lengths. These extracted parameters give similar fitting accuracies as the y-parameters versus frequency characteristics shown in figs. 30 to 33 at all the gate biases shown in figs. 34 to 37.

235


30 r

%

1 o u

W=10x6nm

L=0.18um

• I^0.27nm

L=0.42nm

L=0.64um

• L=0.97um

2.0

Fig. 34. Transconductance (gm) versus VGS characteristics extracted from the measured Re(y2i) at the low frequency region for the n-type MOSFETs with channel width W = 10 x 6 (im (10 fingers of width 6 um) and lengths L = 0.97 um, 0.64 urn, 0.42 urn, 0.27 nm and 0.18 urn, respectively, biased at VDS = 1.0 V.

L=0.97um L=0.64u.m L=0.42um L=0.27um L=0.18nm

Fig. 35. Output resistance (#DS) versus VGS characteristics extracted from the measured Re(y2i) at the low frequency region for the n-type MOSFETs with channel width W = 10 x 6 um (10 fingers of width 6 um) and lengths L = 0.97 um, 0.64 urn, 0.42 um, 0.27 um and 0.18 um, respectively, biased at VDS = 1.0 V.

236


fe

400

300

200

100

0

I V^l.OV

• - • - • - -•-•-•-i W=10x6nm

• L=0.97um

. _ , - • - • - • - • - •—-•—•—•- - • L=0.64um

^ ^ - A - A - A - A - A — A — A — A _ A L=0.42nm

^ • ^ - » • • • • — • — • — • L=0.27nm

T - T • ^ • - • • • — • — • — T — T L=0.18um

0.5 2.0 1.0 1.5 V^CVolt)

Fig. 36. Gate-to-source capacitance (CGS) versus VGS characteristics extracted from the measured lm(yn) at the low frequency region for the n-type MOSFETs with channel width W = 10 x 6 urn (10 fingers of width 6 um) and lengths L = 0.97 urn, 0.64 um, 0.42 um, 0.27 um and 0.18 urn, respectively, biased at the drain voltage VDS

= 1.0 V.

£

160

120

80

40

W=10x6um

V =1.0V DS

m*$$^

L=0.97um

• L=0.64um

. L=0.42um

< ^ I ^ - - * L=0.27um

"^ T —•L=0.18un i

0.5 1.0 1.5

Vra(Volt)

2.0

Fig. 37. Gate-to-drain capacitance (CGD) versus VGS characteristics extracted from the measured Im(yn) at the low frequency region for the n-type MOSFETs with channel width W = 10 x 6 um (10 fingers of width 6 um) and lengths L = 0.97 um, 0.64 um, 0.42 um, 0.27 um and 0.18 um, respectively, biased at the drain voltage VDS

= 1.0V.

The gate resistance (RG) used in the simulation for different channel lengths is obtained from

* G = 3 • « • L

(90)

237


where RQSH = 5.17 Q and n is the number of fingers. In fig. 34, the VG$ bias for the peak gm decreases as the channel length is reduced, and this results in the shift of the peak / T

shown in fig. 26. Although the peak gm increases when the channel length is reduced, the output resistance (Rps) m fil- 35 decreases at the same time, and this results in the amplification factor (Ay(Hy= gm x RDS) remaining about the same at the VGS where the peak gm

occurs.

Based on the element values extracted from the measured y-parameters and noise parameters, figs. 38 and 39 show the extracted channel noise and induced gate noise versus frequency characteristics for n-type MOSFETs with different channel lengths biased at VDS = 1.0 V and VGS = 1.2 V. It is shown that the channel noise, in general, is frequency independent and increases when the channel length decreases because of the higher drain current at the same VDS and VGS bias. The solid lines in fig. 38 are the extracted channel noise based on the method described in section 5.1 which provides an alternative way to verify the channel noise extracted by the proposed method. The small increase in the channel noise at low frequencies for deep sub-micron devices might be caused by the inaccuracy of the measurement system at low frequencies. In fig. 39, the induced gate noise is proportional t o / 2 (solid lines in the figures) where/is the operating frequency. In addition, when channel length decreases, the induced gate noise also decreases because of the decrease of gate-to-source capacitance Q J J , as shown in fig. 36. Therefore, the strength of the induced gate noise is mainly determined by the gate-to-source capacitance instead of the voltage or current fluctuation in the channel.

1E-21

&.

1E-22

V =1.0V V =1.2V DS GS

• • • -w-* L=0.18um

* • • • • • • » » • • I^0-27um A A A A A A A A A A A L=o.42um

— • • • • • • • • • • L=0.64um

• • • • • • • , • • • I^0.97um

W=10x6um

0 1 2 3 4 5 6

Frequency (GHz)

Fig. 38. Extracted channel noise (ij) versus frequency characteristics for the n-type MOSFETs with channel width W = 10 x 6 urn (10 fingers of width 6 |im) and lengths L = 0.97 um, 0.64 um, 0.42 um, 0.27 um and 0.18 um, respectively, biased at VDS = 1.0 V and VGS = 1.2 V. The solid lines are the extracted channel noise based on the method in section 5.1.

238


1x10

1x10

L=0.97um L=0.64um

L=0.42uin

> L=0.27um

L=0.18um

h~« lxl0_24

1x10

Frequency (GHz)

Fig. 39. Extracted induced gate noise (i-?) versus frequency characteristics for the n-type MOSFETs with channel width W = 10 x 6 urn (10 fingers of width 6 um) and lengths L = 0.97 um, 0.64 um, 0.42 um, 0.27 um and 0.18 um, respectively, biased at VDS = 1.0 V and VGS = 1.2 V.

Figure 40 shows the extracted noise correlation between the channel noise and induced

gate noise versus frequency characteristics for n-type MOSFETs with different channel

lengths biased at V D s = 1.0 V and V G S = 1.2 V. It shows that the noise correlation between

the channel noise and the induced gate noise is proportional / In addition, when channel

length decreases, the noise correlation also decreases because of the decrease in the gate-

to-source capacitance CGS.

8x10 r

6x10"" •

4x10"" -

2x10"

L=0.97um

L=0.64um

L=0.42nm

L=0.27um

L^.18um

2 3 4 5 6 7

Frequency (GHz)

Fig. 40. The noise correlation between i* and i\ ( ' „ ' / ) versus frequency characteristics for the n-type MOSFETs with channel width W = 10 x 6 um (10 fingers of width 6 um) and lengths L = 0.97 um, 0.64 um, 0.42 um, 0.27 um and 0.18 um, respectively, biased at VDS = 1.0 V and VGS = 1.2 V.

239


Another useful parameter that is sometimes used to describe the relationship between the channel noise, induced gate noise and their correlation is the cross-correlation coefficient c, which is defined as,

y / (91)

W Figure 41 shows the extracted cross-correlation coefficient c versus frequency characteristics for the devices with different channel lengths. In general, c is frequency independent and decreases when the channel length is reduced. This implies that the channel noise and the induced gate noise are less correlated for the shorter channel length devices. These results show an opposite trend to the simulated results presented in Refs. 49 and 50

0.6

§

8 u S

o o

s

r V^l.OV

0.4-

0.2

0.0

*-*-r A A A A

W=10x6nm

-* b=0.97um

• L=0.64um

-* -* -

• T

• T

L=0.42um

L=0.27|xm

b=0.18um

1 2 3 4 5 6 7

Frequency (GHz)

Fig. 41. The cross-correlation coefficient c versus frequency characteristics for the n-type MOSFETs with channel width W = 10 x 6 urn (10 fingers of width 6 um) and lengths L = 0.97 fim, 0.64 \xm, 0.42 um, 0.27 um and 0.18 um, respectively, biased at VDs = 1.0 V and VGS = 1.2 V.

For the VGS bias dependence of the extracted noise sources, figs. 42 and 43 show the

extracted i | and fl versus VGS characteristics for the n-type MOSFETs with channel

width W = 10 x 6 um and lengths L = 0.97 ^.m, 0.64 \im, 0.42 |am, 0.27 um and 0.18 um

respectively, biased at VDs = 1.0 V. The channel noise is caused by the voltage or current

fluctuation in the gradual channel region which is from the intrinsic source terminal to the

pinch-off point, and from the saturation region which is from the pinch-off point to the

intrinsic drain terminal. For long channel devices, the channel noise mainly comes from

the gradual channel region. However, for short channel devices, the noise from both

regions has to be taken into account. It is shown that the channel noise has a strong VGS

dependence and it increases, but then tends to saturate when VGS increases. On the other

240


hand, the induced gate noise has a weak VQS dependence because it is mainly determined

by the gate-to-source capacitance CGS instead of the voltage or current fluctuation within

the channel of the transistor.

P-

1.5xl0'2

1.0x10"'

5.0x10"'

O.OL

W=10x6|am

V =1.0V DS

• • A' • A I

T L=0.18um T

u • L=0.27um

A A L=0.42um

• • L=0.64um

• • L=0.97|xm

li A .

0.5 1.0 1.5 2.0

V^CVolt)

Fig. 42. Channel noise (i? ) versus VGS characteristics for the n-type MOSFETs with channel width W = 10 x 6

\im (10 fingers of width 6 fim) and lengths L = 0.97 um, 0.64 um, 0.42 um, 0.27 um and 0.18 urn, respectively,

biased at V D S = 1.0 V.

1x10"

!§ lxlO"2

10"

' • • • , ' • •

I I I | L=0.97um L=0.64|im

A A , • • • • A A A A L=0.42Lim

• • • L=0.27Mm

T T T T T T T y

V^l.OV

W=10x6nm

• • L=0.18um

0.5 1.0 1.5 2.0

V^CVolt)

Fig. 43. Induced gate noise (ij;) versus VGS characteristics for the n-type MOSFETs with channel width W = 10

x 6 um (10 fingers of width 6 um) and lengths L = 0.97 um, 0.64 |im, 0.42 um, 0.27 um and 0.18 um,

respectively, biased at VDS = 1.0 V.

Figures 44 and 45 show the extracted correlation noise i Jd* and the cross-correlation coefficient c versus VGS characteristics for the n-type MOSFETs with channel width W =

241


10 x 6 Lim and lengths L = 0.97 Jim, 0.64 Lim, 0.42 iim, 0.27 Lim and 0.18 Lim respectively, biased at VDs = 1.0 V. For the correlation noise, it increases, then tends to saturate when VGS increases. This follows the VGS dependence of the channel noise. However, the correlation noise decreases when the channel length is reduced and this follows the channel length dependence of the induced gate noise. On the other hand, the cross-correlation coefficient tends to decrease when VGS increases. It is because of the faster increase in the channel noise compared to the correlation noise, and it follows the trend predicted in Ref. 17.

3x10

2x10 F

2 lxHT C3

0

W=10x6um

vK=i.ov

: •

. • • : * *

, • • • • • • • JTTTTTTT

L=0.97um

L=0.64um

L=0.42um

• • L=0.27um T . • , T .l>0.18nm

0.5 1.0 2.0

V „

1.5

c s ^ Fig. 44. The correlation between fl and A ('J/ ) versus VGS characteristics for the n-type MOSFETs with channel width W = 10 x 6 um (10 fingers of width 6 um) and lengths L = 0.97 um, 0.64 um, 0.42 um, 0.27 um and 0.18 um, respectively, biased at VDS = 1.0 V.

a 'o

8 u a o

! u

I CO a

0.6

0.5

0.4

0.3

0.2

0.1

0.0

vDS=i.ov

A

* * * • • • • • • • • T T T T ,

W=10x6um

1 L=0.97um

1 L=0.64um ' L=0.42um

• L=0.27um L=0.18um

0.5 1.0 2.0

V

1.5

Fig. 45. The cross-correlation coefficient c versus VGS characteristics for the n-type MOSFETs with channel

width W = 10 x 6 um (10 fingers of width 6 um) and lengths L = 0.97 um, 0.64 um, 0.42 um, 0.27 um and 0.18

um, respectively, biased at VDS = 1.0 V.

242


For the VD S dependence, figures. 46 and 47 show the extracted channel noise versus VGS

characteristics at different VDs biases for the devices with 0.97 |im and 0.18 jam channel

length, respectively. For the long-channel devices, because the channel noise is mainly

contributed from the gradual channel region, it is not sensitive to different VDs biases.

However, for the short-channel devices, the saturation region contributes considerable

noise power to the overall channel noise. Therefore, the channel noise will increase when

the VDs bias is increased because of more noise current contributed from the saturation

region than the decrease of the noise current contributed from the gradual channel region.

3.0x10

1.0x10

5.0x10

VGS(Volt) Fig. 46. Channel noise (/^ ) versus VGS characteristics for the n-type MOSFET with channel width W = 10 x 6 um (10 fingers of width 6 um) and length L = 0.97 um biased at VDS = 1.0 V, 1.2 V, 1.5 V, 1.8 V and 2.0 V, respectively.

1.8xl0'21 r

1.2xl0"21 h

L=0.18um

W=10x6um

6.0x10"

0.0

VGS (Volt) Fig. 47. Channel noise ( i j ) versus VGS characteristics for the n-type MOSFET with channel width W = 10x6 M.m (10 fingers of width 6 um) and length L = 0.18 um biased at VDS = 1.0 V, 1.2 V, 1.5 V, 1.8 V and 2.0 V, respectively.

243


In order to verify the accuracy of the extracted noise sources, and compare the simulation results against the measured data and those based on van der Ziel's model which is suggested for long channel devices, figs. 48 to 51 show the measured (symbol) and simulated (lines) noise parameters versus frequency characteristics. The simulations are performed using the direct calculation technique described in section 3.1 • for the n-type MOSFET with the channel width W = 10 x 6 Jim and length L = 0.97 Lim biased at VDS = 1.0 V and VGS = 1.2 V. In these figures, the solid lines are the simulated results based on the extracted noise sources (solid lines in figs. 38 to 40) and the dashed lines are the simulated results based on van der Ziel's model in which the power spectral density of the noise sources are given by

'J = ySatn4kTSdo (92)

2_2 - co C0 i2

g = 5

satn4kT-r- and

°do

(93)

V 7 = *satn4kTJ<»Co (94)

where 8do = 12.5 m S , y s a t n = 2 / 3 , 5 s a t n = 16/135, esatn = 1/9, C0 - 3C G S / 2 and co = 2itf.

m 4 •a

I Van der Ziel's model

L=0.97nm

W=10x6um

2 3 4 5

Frequency (GHz)

Fig. 48. Measured (symbols) and simulated (lines) minimum noise figure (NFmin) versus frequency characteristics for the n-type MOSFET with the channel width W = 10 x 6 u,m (10 fingers of width 6 nm) and length L = 0.97 u.m biased at VDS = 1.0 V and VGS = 1.2 V. The solid line is calculated with all the extracted noise sources included (solid lines in figs. 38 to 40) and the dashed line is calculated using the Van der Ziel's model.

244


120

100

80

60

h O oo

extracted noise sources

Van der Ziel's model

VDS=1.0V L=0.97nm

Vn(=1.2V W=10x6um

O c r

2 3 4 5

Frequency (GHz)

Fig. 49. Measured (symbols) and simulated (lines) equivalent noise resistance (R„) versus frequency characteristics for the n-type MOSFET with the channel width W = 10x6 urn (10 fingers of width 6 um) and length L = 0.97 um biased at VDS = 1.0 V and VGS = 1.2 V. The solid line is calculated with all the extracted noise sources included (solid lines in figs. 38 to 40) and the dashed line is calculated using the Van der Ziel's model.

l . U

0.9

0.8

- £ 0.7 o _c-_

0.6

0.5

1 cP^s

ON;

: V =1.0V DS

' VGS=1.2V

' . — i — i . i i

L=0.97um

W=10x6um

<-.. Van der Ziel 's model

^c/ A^C:-..

extracted (5^--noise sources

i — i — i — i — i — i i •

" 0 1 2 3 4 5 6

Frequency (GHz)

Fig. 50. Measured (symbols) and simulated (lines) magnitude of the optimized source reflection coefficient (|r0Fp|) versus frequency characteristics for the n-type MOSFET with the channel width W = 10 x 6 um (10 fingers of width 6 u,m) and length L = 0.97 um biased at VDS = 1.0 V and VGS = 1.2 V. The solid line is calculated with all the extracted noise sources included (solid lines in figs. 38 to 40) and the dashed line is calculated using the Van der Ziel's model.

245


100

80

60

C o 40

N 20

" 0 1 2 3 4 5 6

Frequency (GHz)

Fig. 51. Measured (symbols) and simulated (lines) phase of the optimized source reflection coefficient (/.

r O F r ) versus frequency characteristics for the n-type MOSFET with the channel width W = 10 x 6 (im (10

fingers of width 6 p.m) and length L = 0.97 urn biased at VDS = 1.0 V and VGS = 1.2 V. The solid line is

calculated with all the extracted noise sources included (solid lines in figs. 38 to 40) and the dashed line is

calculated using the Van der Ziel's model.

It is shown that the extracted noise sources, in general, give a good prediction of the noise

parameters. However, van der Ziel's model predicts lower NFmin and Rn, and this might be

caused by not including the channel noise and induced gate noise contributed from the

velocity saturation region,18'52 because of the assumption Ec - °°, where Ec is the critical

field.

Figures 52 and 53 show the measured (symbol) and simulated (lines) minimum noise

figure (NFmin) and equivalent noise resistance (Rn) versus frequency characteristics based

on the extracted noise sources and the equations id = 8&Tgm/3 and id = ikTg^J'i for the n-

type MOSFET with the channel width W = 10 x 6 |im and length L = 0.97 |im biased at

VDs = 1.0 V and VGS = 1.2 V. For long-channel devices, the extracted channel noise can

have good minimum noise figure and equivalent noise resistance prediction. The equa

tions ij = 8kTgJ3 and i | = 8kTgdo/3 suggested for the channel noise calculation of long-

channel devices give good minimum noise figure prediction, but they predict lower equiv

alent noise resistance Rn.

1 Van der Ziel's

extracted noise sources

; V j&

J2i

I . I .

V P S

Vos 1

model

=1.0V

=1.2V '

L=

W '

=0.97nm

=10x6um i

246


4-

8

ft\

'•; = 8kTg/3

Extracted i

Measured Data

r2 = 8kTg/3 d °m

L=0.97nm V^l.OV

W=10x6mn V ^ l ^ V _i i , i_

0 1 2 3 4 5 6 Frequency (GHz)

Fig. 52. Measured (symbols) and simulated (lines) minimum noise figure (NFmin) versus frequency

characteristics for the n-type MOSFET with the channel width W = 1 0 x 6 | x m ( 1 0 fingers of width 6 um) and

length L = 0.97 |im biased at VDS = 1.0 V and VGS = 1.2 V. The solid line is calculated with all the extracted

noise sources included (solid lines in figs. 38 to 40) and the dashed lines are calculated using the equations i2d =

8CTgm/3 and i | = UTgdo/3.

O

2.5

20

1.5

1.0

NfeasuredData V*=h0W " ^ V ^ l ^ V W=10x6nm

»da = 8 H3BL/3

1 2 3 4 5 6 Frequency (GHz)

Fig. 53. Measured (symbols) and simulated (lines) equivalent noise resistance (Rn) versus frequency

characteristics for the n-type MOSFET with the channel width W = 1 0 x 6 (im (10 fingers of width 6 u,m) and

length L = 0.97 (im biased at VDS = 1.0 V and VGS = 1.2 V. The solid line is calculated with all the extracted

noise sources included (solid lines in figs. 38 to 40) and the dashed lines are calculated using the equations A -

8*Tgm/3 and i | = MTSdo/X

247


6. Design Consideration for Low Noise Circuits

Before going into the noise models in detail, the most general questions being asked by the circuit designers are how to properly choose the device size, select the bias conditions (VGS and VDs), and design the device geometries to achieve the best noise performance for their RF circuits. In this section, the noise behavior of MOSFETs will be explained qualitatively based on the extracted noise sources and noise parameters, and this leads to the proper selection of the device size and the determination of the bias conditions.

6.1. Selection of bias conditions

In general, the minimum noise figure NFmin decreases when VQS increases at the low VGS

region, and it increases at the high VGg region, as shown in fig. 27. This can be understood by comparing the transconductance gm (shown in fig. 34) and the channel noise id (shown in fig. 42) versus VGS characteristics. Basically, NFmin is mainly determined by these two factors - gm and id. In the low VGS region, the increasing rate of gm is greater than that of id and therefore it causes the drop of NFmin. However, in the high VQS region, since gm

decreases but id keeps increasing, this causes NFmin to increase. There are two observations that can be made from this explanation. First, as shown in fig. 27, the VGS value for the lowest NFmin becomes lower when the channel length is reduced, and this is because of the faster increase of gm for the short channel devices. Second, from fig. 27 and fig. 34, it is shown that the lowest NFmin actually happens before the peak gm instead of at the peak gm. This is because the derivative of gm with respect to VGS is zero at the peak gm.

0.012 r

0.009 -

oo

60

0.006

NMOSFETs

L=0.97um

W=10x6um

V„C=2.0V

M-a.J VDS=1.5V

8m ' V D s = 1 - 0 V

0.5 — i —

1.0

GS

1.5

(Volt)

2.0

Fig. 54. Transconductance (gm) versus VGS characteristics extracted from the measured Re(y2{) at me low

frequency region for the n-type MOSFETs with channel width W = 10 x 6 um (10 fingers of width 6 um) and

lengths L = 0.97 urn biased at VDS = 1.0 V 1.5 V and 2.0 V, respectively.

248


As for the VDS dependence, figures 54 to 56 show the measured transconductance gm,

NFmin and equivalent noise resistance Rn versus VGS characteristics at VDS = 1.0 V, 1.5 V

and 2.0V, respectively. It is shown that, at higher VD$ bias, because of the increase of gm

at the high VGS region and this causes NFmin and Rn drop at the high VGS region. There

fore, higher VDS bias will make the noise performance of the transistor to be less sensitive

to the VGS variation, but then the power consumption will be higher.

4.5 r

4.0

3.5

3 3.0 (-

r g

fe 2.5

2.0

1.5

NMOSFETs

L=0.97um

W=10x6nm

9VM=1.0V

VDS=2.0V

0.5 — i — 1.0 1.5 2.0

VGS(Volt)

Fig. 55. Minimum noise figure (Wml„) versus VGS characteristics for the n-type MOSFETs with channel width

W = 10 x 6 nm (10 fingers of width 6 um) and lengths L = 0.97 um biased at VDS = 1.0 V 1.5 V and 2.0 V,

respectively.

240

200

g 160 C

120

80

L=0.97um

W=10x6nm

NMOSFETs VDS=2.0V

0.5 1.0 1.5 2.0

VGS(Volt)

Fig. 56. Equivalent noise resistance (/?„) versus VGS characteristics for the n-type MOSFETs with channel width

W = 10 x 6 um (10 fingers of width 6 jtm) and lengths L = 0.97 um biased at VDS = 1.0 V 1.5 V and 2.0 V,

respectively.

249


6.2. Consideration of device geometry - multi-finger gate design

In general, the effective gate resistance RG of a single finger device with the input signal

from one side of the transistor as shown in fig. 57(a) can be modeled as53

1 W R = -xfl . x —

G 3 8sh L

(95)

where 1/3 is used to model the distributed effects of the gate resistance, Rgsh is the sheet

resistance, W and L are the channel width and length, respectively.

W

P ^ ^ Gate

mm Signal traveling direction

L

T M L RG = 3XRgshXI

Distributed effects

W

(a)

n transistors , „, , _ 1 W/n 1

(width = W/n) KG-3XHgshX L Xn

connected in parallel

(b)

R ,-W gsh

3n2L

J^ • each signal travels half of the distance W

1 D W/2 1 1 W R = -xR ,x——x- = -—-xR ,x —

G 3 gsh L 2 3 - 4 gsh L V - two resistors connected in parallel

(c)

Fig. 57. Effective gate resistance (RG) of (a) a single finger design with the input signal from one side of the transistor, (b) a multi-finger design with the input signal from one side of the transistor and (c) a single finger design with the input signal from both sides of the transistor.

In order to improve the noise performance by reducing the gate resistance RQ two

approaches were investigated. One involves metal-reinforced gates ' and the other

250


employs the multi-finger design technique. The first approach reduces the RQSH S 0 a s t 0

reduce RQ. This approach can achieve the goals of reducing the overall noise level, but it

requires a change to the fabrication process. The multi-finger gate design shown in fig.

57(b) in which some narrower devices are connected in parallel to reduce RG based on the

existing technology can improve the overall noise performance as well. In general, as

shown in fig. 57(b), because the signal path is reduced by a factor of \ln and there are n

narrower transistor connected in parallel, where n is the number of fingers, the effective

gate resistance RG will then be reduced by a factor of n .

Figure 58 shows the measured NFmin (symbols) of a 60 um transistor and a multi-fin

ger gate design in which there are six 10 um wide transistors connected in parallel. The

calculated NFmin (dashed lines) for the 1 x 60 um transistor is based on RG = 175 Q. and

the RG value for the calculation of NFmin for the 6 x 10 um transistor is 175 Q/36. It is

shown that the multi-finger gate design will decrease the overall noise performance by

decreasing the gate resistance RG Also, good agreement between the measured and calcu

lated NFmin of multi-finger gate design is obtained.

PQ T3

55

6.0

5.0

4.0

3.0

2.0

A L=0.8um

: i V D S = 3 V

\ W=lx60f im'

\ o " °"-?....G....Q..

W=6xl0um"

f=4GHz

o

A .A-

-Or- 'O '"

'•>

-o

IDS ( nA) Fig. 58. The measured (symbols) and calculated (dashed lines) NFmin of a single 60 u,m transistor (triangle) and

a multi-finger gate design (circle) with six 10 um wide transistors connected in parallel. The calculated data for

multi-finger gate design is obtained by changing RG to Rclr? (n = 6 in this calculation) and the rest of model

parameters are the same as those used in the noise calculation for the single 60 um transistor.57

Another way to reduce the gate resistance is to apply the input signal from both ends of

a transistor, as shown in fig. 57(c). In this case, since the signal path for the signal to travel

is reduced by a half and there are two half-width transistors connected in parallel, there

fore the effective gate resistance can be reduced by another factor of 4 in this configura

tion.

251


7. Noise Source Modeling

The noise discussed in this paper is the electrical noise which is caused by the small voltage (or current) fluctuation generated within the devices themselves. The most important sources of noise in semiconductor devices are thermal noise, shot noise (present in diodes and bipolar transistors), generation-recombination noise, and flicker noise. Working in the microwave region, generation-recombination noise and flicker noise are usually negligible at high frequencies unless they are up-converted in circuits such as oscillators or mixers. Therefore, only the thermal noise or shot noise are considered in high frequency noise modeling.

7.1. Thermal noise in the conducting channel

There have been several channel noise models for MOSFETs that are described in the literature.58"62 In this section, several noise models will be presented. Some of these models have already been reviewed in Ref. 13.

• HSPICE Model

The HSPICE MOSFET noise model59 has a parameter NLEV that is used to select differ

ent equations for the calculation of flicker noise and channel thermal noise. If the model

parameter NLEV is less than 3, then the power spectral density of the channel thermal

noise is given by

- 8kT-gm

i\ = —f^ (%) where gm is the transconductance and kT is the Boltzmann's thermal energy. The above

formula is used in both saturation and linear regions, and it can lead to wrong results in the

linear region. For example, at VDs = 0 V, it predicts that ^ is zero because gm becomes

zero, whereas the power spectral density should be 4kTgdo, where gdo is the drain

transconductance gd at Vd = 0 V. In the analog circuits, such as transconductance-C

filters63 and MOSFET-C continuous-time filters,64 the transistors are operating in the lin

ear region and (96) would fail to accurately describe the thermal noise.

If the model parameter NLEV is set to 3, HSPICE uses a different equation which is

given by

il = * f • P • (VG5tint- VT0) • l-^f- • GDSNIO (97)

where

252


{

w V = T£t-»,effCoX> (98)

Leff

"DS, int j • Linear region VDsat ~ hsat ' (RS + RD)

a =

0 Saturation region ,QQ,

and the model parameter GDSNOI is the channel thermal noise coefficient whose default

value is one. This formula is derived assuming that the carrier mobility is constant and

therefore the velocity saturation effect is not considered. ' This model works reason

ably well for long channel devices, but is not adequate for short channel devices.

• BSIM3v3 Model

BSEvI3v3 model2 8 is the HSPICE Level 49 MOS Model released by UC Berkeley on October 30, 1995 and proposed as a standard MOSFET model for industry use. There are two models for channel thermal noise which can be selected by the model parameter NOI

MOD. If the value of NOIMOD is one, which is the default value, then the power spectral density of the channel thermal noise is modeled as

- MT-{gm + gds) i2

d = f — . (100)

This model solved the problem at VDS = 0 artificially, but it underestimates the noise power in the linear region. For example, at VDS = 0, the power spectral density should be 4kTgdo, but it only predicts two third of it. If the model parameter NOIMOD is set to two, the power spectral density is given by

- 4kTu i2 = —J^.{_Q.nv) ( 1 0 1 ) ,;2 = ££f f . ,

,2 £ eff

where

QinV = " V M - 4 1 -KV^Z**/*^ ( 1 ° 2 )

and y ^ - i s the effective surface mobility. The derivation for this thermal noise expression is based on the noise model in Ref. 61. Again, without taking the velocity saturation effect into consideration, this model is not suitable for the noise modeling of modern transistors.

253


• Fox's model

Fox presented some comments on the circuit model for MOSFET thermal noise based

on Van der Ziel's earlier expressions. According to his simulation results, he suggested

that the power spectral density of the channel thermal noise should be expressed as

7d = a4kTgd0 (103)

where gdo is the channel conductance with zero drain-to-source voltage and

a { l _ v + ( v

2 / 3 ) l - v / 2 d • dsat

2 V. >v, 3

(104)

with v = Vd/Vdsat. This model works reasonably well for long channel devices but it is not

adequate for short channel devices, especially in saturation region, which is the usual

region of operation for MOSFETs in analog integrated circuits. Because of the channel-

length modulation and carrier heating effects, a will increase beyond 2/3 for deep-sub-

micron devices.

* Wang et al. model

t o

Wang et al. derived the equations for the channel thermal noise in both the linear and saturation regions for long and short channel devices. In this model, the derivation started from the expression

Tj = 4kTip£QN (105) Leff

and then included the velocity saturation effect in the calculation of QN. However, the der

ivation of (105) is based on the assumption that the effective mobility |êff is independent

of lateral electric field.61 If we include the velocity saturation effect at the very beginning

when the channel thermal noise, is derived, then we should end up with (117) given later.

On the other hand, without taking the hot-carrier effect into account, this model cannot

accurately predict the noise performance of short channel devices.

• Triantis et al. model

Triantis et al.66 presented a thermal noise model which included the velocity saturation

effect, and hot-electron effect. In this model, the transistor channel is divided into two

regions - a gradual channel region and a velocity saturation region, and two channel mod-

254


els were derived for these regions. However, according to the velocity-field relationship in

Ref. 67, the carrier velocity is not saturated until the electric field reaches the critical field

Ec = 4 V/jim at room temperature. For 0.5 urn devices, this corresponds a VDsat = 2.0 V.

For most analog circuit applications, the devices are biased such that the VDsat is around

1.2 V to 1.5 V (e.g. VGS = 2.0 V). Therefore, before the carrier velocity saturates, channel

pinch-off occurs. If we increase VDS further to push the tip of the channel at the drain side

towards to the source end, then the effective channel length is shorter at higher VDs

biases, the carrier velocity saturates, and the conducting channel of a transistor should be

divided into a gradual channel region and a velocity saturation region. This is shown sche

matically in the fig. 5 of Ref. 66 where the noise originating from region II (saturation

region) is visible only at very high VDS. However, for deep sub-micron devices, the maxi

mum drain-to-source voltage VDS is scaled down to prevent punch through in the devices,

and therefore the maximum carrier velocity is not reached for most analog circuit applica

tions.

• Van zer Ziel's Model

The general expression for the drain current of a MOSFET operated in strong inversion is

given by

W = ^ / / - 2 / W ' v W (106)

where x is the position along the channel, Weg is the effective channel width, Qrfx) is the inversion layer charge per unit area, and v(x) is the carrier drift velocity in the channel as shown in fig. 59.

Fig. 59. Schematic diagram of a n-type MOSFET operated in saturation region.

255


For the models presented above, two important physical effects were not considered - the velocity saturation effect and the hot-electron effect, and these effects are especially prominent in modern deep sub-micron transistors. For short channel devices, the carrier drift

68 velocity in the channel will saturate at the high lateral electric field, and it can be

expressed as

V(JC) = { V-•seff E(x)

1 + E(x) £ W K EC

E(x) > Ec (107)

where \lsejf is the effective surface mobility, E(x) = dV(x)/dx is the lateral electric field, vsat

is the saturation velocity, and Ec is the critical field at which carrier velocity saturation occurs. The critical field and the effective surface mobility are given by

EC-2v„

Xseff (108)

V Vn

Seff l + *(VGS,int-VT0) (109)

where |J,0 is the low-field mobility, 8 is the mobility degradation coefficient due to vertical

channel field, VTQ is the threshold voltage at the source end of the channel with zero

source-substrate bias, and VGSint is the voltage drop between the gate and source of a

intrinsic device (i.e. VGS int = V G S - IryRs). as shown in fig. 60 .

DS.int

Fig. 60. N-channel MOSFET with drain (RD) and source (Rs) series resistances. The terminal voltages (V0 VD, and Vs) and the voltages applied to the intrinsic transistor (VD int and Vs int) are indicated.13

256


The saturation velocity, vsat, of the carriers in the channel is approximately 107 cm/s at a

temperature of 300°K. Substituting (107) into (106) for E{x) < Ec and rearranging the

equation, we can get the drain current 1D is

f In(xh dV

where V is the voltage along the channel. Multiplying by dx, integrating over the effective

channel length Leff, keeping in mind that the drain current ID(x) is independent on position

x (i.e. ID(x) is the same at every position x), and finally solving for ID gives

*o = zM "''"W "v Q'(v)-Ez)dv (111) 11 vS,int c

where VDint is the channel potential at the drain end of the intrinsic device (i.e. VDint = VD

- ID'RD m linear region and VDint = VD - lD,sat'^D - ^D.saf where VDsat is the saturation

voltage and I[)tSat is the drain current at VD = VDsat, in the saturation region), and V s int is

the channel voltage at the source end of intrinsic devices (i.e. Vs int = V$ + IQ-RS). The val

ues of Leff, VDsat and Q/(V) depend on models used and are of different complexity, pro

ducing different accuracies.

From (111), we find that if there is a small time varying voltage fluctuation Av(t) caused by the thermal noise in a unit length segment of the channel, then the current fluctuation Ai(t) caused by Av(t) is given by

Ai(t) = l~-[^seff Weff QlM-f) • Av(0 (112)

as long as the variation of Av(t) is slow enough so that quasi-static behavior is maintained.

Because of the negligibly small Av(t), Q/(V) is practically constant and independent of

Av(t). The mean square value of Aj'(t) will then be

(AO2 = -T--UeffWeffQI(V)-^] -(Av)2. (113) L eff V &

From (110), it can be shown that the resistance Afl of a small element of the channel of

length Ax centered around a point x = xj is

AR = ^ — — (114) ( ID(X\ A [VseffWeffQMx)-2^)

since AV = IDAR. Using the concepts from statistical physics, the power spectral density of the noise voltage generated across a resistor of value ? is equal to AkTR for frequencies

257


at which hfAT « 1, and assuming that the small element of the channel acts as a resistor

of resistance AR, we will find a small voltage Av(t) across it with a mean square value of

~2 UcT(xx)-Ax (Av)2 = £ - i — — - • A/ (115)

where Te(xj) is the effective electron temperature at xj. If the channel does not show hot

electron effects, which is valid only for long channel devices, Te would be the same as T

which is the lattice temperature of the device. Substituting (115) into (113),we obtain

(Ai)2 = —f-^-k.frWefrQl(V)-f).Af-Ax. (116) L eff

V CC^

This gives the contribution of the element at xj to the drain current noise. The contribu

tions of all similar elements in the channel are assumed uncorrelated, and one can thus

find the mean square value of their combined effect by adding the individual mean square

values. In this limit, letting Ax become a differential, integrating over the effective channel

length, and changing the variable dx to dV based on (110), we obtain that the power spec

tral density of the thermal noise in a channel ij is given by

LeffID VS,int V ^

Equation (117) includes both velocity saturation effects and hot electron effects, and it is a

general expression for the thermal noise in a channel. In general, the electron temperature

Te increases with increasing field strength. The exact dependence is not known, but to sim

plify the calculations, it is assumed that51

with 0 < n < 2. Solving for E/Ec from (106), (107), and (110) and using E(x) = dV(x)/dx,

yields

! , * ( * ) _ êff-KffQliV) ( n 9 )

Ec ^//tvcw-^

so that

258


AkT f VD, int

efflD "V, ^seffWeffQ,W (120)

S, int

êffWeffQ^-f dV.

Equation (120) is valid for the bias conditions at which the lateral electrical field at any

position in the conducting channel is smaller than Ec (i.e. the channel pinches off before

carriers reach the saturation velocity).

• Model of Knoblinger et al.

Knoblinger's model69 takes the velocity saturation and hot-carrier effect into account in a different way compared to van der Ziel's model. In his model, the channel has been divided into two regions - gradual channel region (I) and a velocity saturation (II) as shown in fig. 61, and then the noise power spectral densities from both regions are computed.

Fig. 61. The gradual channel region (I) and the velocity saturation region (II) defined in a transistor channel.69

Starting from the contribution of a small element of the channel dx to the noise spectral density39 which is given by

- 4kTeWn(x)Qinv(x) dij =

d L2 dx (121)

259


and the electron temperature Te which is70

2

Te = T0 + 5To^f-, (122)

where T0 is the lattice temperature, E(x) is the electrical field at- the position x along the

channel, Ecrit is the critical electrical field and 8 is a fitting parameter, the overall noise

noise spectral density is the sum of those in these two regions. In the derivation of the ana

lytic model, the mobility is n(x) = v{x)IE(x), the drain current is ID = Wejfv(x)Qinv(x) and

the electrical field in region II is given by

E(x) = Ecritcosh(ax) (123)

and

a = X \ \ - ^ - (124)

where xj is the junction depth at the source and drain regions, Cox is the gate-oxide capacitance and X is a fitting parameter for the channel length modulation. It is found that the channel noise is mainly determined by the sum of the noise power from the gradual channel region without the hot-electron effect and the noise power from the velocity saturation region with the hot-electron effect. The channel noise can be obtained from

- 4kT ld ~

AkTo( r, x ZD sinh(aAL)^ . . . . .

1T{U^- + 8E-—a J (125)

where AL is the length of the velocity saturation region in fig. 61 which is given by

AF ! 1 (aiVDS-VDSsat) + ED\ n o , , AL = « H — £ - — J (126)

and

_ , . fa<.VDS-VDS,*,V , , , , ,

7.2. Induced gate noise

At high frequencies, the MOSFET must be considered as an RC distributed network, with

the capacitive coupling to the gate representing the distributed capacitance and the chan

nel itself representing the distributed resistance. This means that the high-frequency gate

admittance Ygs of the device contains a conductive component. To obtain the capacitive

260


and conductive components, we start from the wave equation of the distributed line repre

senting a MOSFET with a low conductivity substrate given by71

J-[A/D(x)] = jwWefJC0XAv(x) (128)

where Av(x) is the AC voltage fluctuation along the channel caused by the small variation

in gate voltage VGS. Geurst has solved this equation and expanded Ygs in terms of j(0 to

get

gs 8mo 4 - i - 2 4 * 3 ( ' 1 + l 5 ^ + 4 5 0 ( O ) + 4455° ' ° ) ) + -

where

_ ^seffCoxWeff(v v .

M = ( d u i v e / / - v )' (131)

Ky«//-KGS, m? "ru.*

CO = 2n/ and / is the operating frequency. If we take the first order approximation of (129),

and model Ygs by a capacitance Cgs in series with a resistance /?,-, we may write at satura

tion

Ygs = 8mo • \\j^+ii^2! = — r — • ( 1 3 2 )

— ^ - + /?. J gs

For frequency at which a2R2C2 « 1, we may solve for Cgs and Rt to get

4 "2 P • — < V >

2 (o 2 m o 45 1 Cgs = ^mo^ = 2CoxWefJLeff' Ri = J^— = Jg^ ' ( B 3 )

From (133), we find that the maximum value of Cgs at saturation is 2/3 of the total oxide

capacitance and /?, will decrease with increasing VGSint since gmo is increasing with bias

(c.f. (130)).

The resistance /?, may have noise associated with it. To evaluate the noise of /?, at

higher frequencies, one must know fl and the cross-correlation i j d * , if they exist. Let's

take a section Ax0 at x0 in the channel. It has thermal noise Av^ and produces a fluctuating

voltage Av(x) along the channel. By capacitive coupling to the gate, this produces a gate

261


noise current. The total gate noise current Aig flowing out of the gate is found by integrating along the channel, and it is

eff Mg = j<nWeffox • J Av(x)dx (134)

In addition, there is a drain noise current Ai^ due to Avxo flowing out of the drain, and this drain noise current has been discussed in section 7.1. Because the gate noise current and drain noise current resulting from the same noise source Avxo, then Aig and Aid are correlated. By expressing i2 and i id* in terms of Avxo and integrating over the channel length, one can obtain i2 and i Jd* for MOSFETs at saturation as

ig = 4kT-O)

2 c 2 w2 "VDJnt ^Kff f

VS. in.

^seffWeffQ,W (135)

iWHV<2i<iO- ; 'CJ

(v„t-vfdv,

rDLeff ' V, I.

D, int

êffWeffQ^r S, int

(136)

»seffWeffQ,(V)- (vas-v)dv,

where

as DS, int ' 9 p j I tcLeff

1 \ 2

+ l^DSJnt _ 2{VGS'^~VT)VDS,int-lVDS,intr + VDSJnf

^GS.int Vj 2 DS.int ECLeff-

(137)

and

*DS, int ~ *D, int Ks, int • (138)

7.3. Thermal noise from the parasitic resistances

For sub-micron MOSFETs, there are three major parasitic resistances present - source and

drain resistances (Rs and RD respectively) which play a more important role in degrading

the current drive capability of devices46"48 and gate resistance which has a strong impact

on the maximum oscillation frequency (fmax), time response, and AC performance of wide

262


devices working at high frequencies.53 These resistances, of course, will contribute ther

mal noise and their power spectral densities are

o 4Jfcr i 2 -' p — R

(139)

where R could be Rs, RD, and RQ. The resistance values of Rs, RD, and RG depend on mod

els used and will give different results.

7.4. Comparison of some different noise models

Finally, several noise models for channel thermal noise were compared. Figure 62 shows

the calculated data for different channel thermal models. It is shown that the HSPICE level

3 (NLEV < 3) and BSIM3 (NLEV < 3) models tends to saturate in the high current region

and underestimate the channel thermal noise.

20

16

5 jS 12 -e u

-C H TJ B C at

J3

u

Wang et al.'s model

HSPICE level 3 model (NLEV < 3)

Ziel's model (n=0.5)

level 3 model (NLEV = 3)

model (NLEV < 3)

0 3 6 9

IDS (mA)

Fig. 62. Calculated power spectral density of channel thermal noise for different models.57

As for HSPICE level 3 (NLEV = 3) model, it is based on (8.5.16) in Ref. 61 which does not take into account the velocity saturation effect. Therefore, it gives lower noise prediction for intrinsic transistors. In addition, it is observed that Wang et al.'s model58

overestimates the channel thermal noise in the high current region compared to the other modes. This is because the model in Ref. 58 included the velocity saturation effect based on the noise expression (see (8) in Ref. 58) which is (8.5.16) in Ref. 61. If we include the velocity saturation effect at the very beginning when the noise expression is derived, then the channel noise expression we will end up with is (117), which is the Van der Ziel's

263


noise expressions in Ref. 51, and it gives reasonable noise prediction. Figure 63 shows the measured and calculated NFmin vs. 1DS for different noise models. It is shown that the HSPICE level 3 model (NLEV < 3) gives a wrong trend for NFmin vs. IDS characteristics and is unsuitable for low noise RF circuit designs.

CQ

6.0

5.0

a 1

£ 4.0

3.0

L = 0.8um VDS = 3.0V

J W =lx 60um /=4 GHz

> " T " A A ±J.-*-""

Wang et al.'s model

V Van der Ziel's model S (n=0.5)

HSPICE level 3 model

(NLEV = 3)

HSPICE level 3 model

^ (NLEV < 3)

IDS ( m A )

Fig. 63. Measured (symbol) and calculated (dashed lines) NFmin vs. IDS for different noise models.57

8. Conclusions

High-frequency noise characteristics of modern MOSFETs are becoming increasingly

important in high-frequency circuit design. Noise parameters (minimum noise figure,

equivalent noise resistance, and optimized source impedance) are the noise indicators of a

noisy two-port network. Based on a sophisticated small-signal model which can predict

accurately the high-frequency performance of devices, it is usually very difficult to obtain

analytical expressions for the noise parameters based on the fundamental definition of

noise parameters. In this paper, a technique to directly calculate the noise parameters

based on matrix operations was used to determine the noise parameters of intrinsic transis

tors. In addition, the method of using a circuit simulator based on a compact model to cal

culate the noise parameters is also presented.

High-frequency test structures and de-embedding techniques used for both s-parame-

ters and noise parameters are two critical requirements in noise measurements and model

ing. In this paper, the design of dummy pads and DUTs are described. Appropriate de-

embedding techniques have also been explained in detail. In general, the parallel parasitics

of probe-pads can be easily de-embedded by the subtraction of the measured y-parameters

of an "OPEN" test structure from the measured y-parameters of the DUT. However, the

264


distributed capacitive parasitics caused by the interconnections between probe-pads and

the intrinsic transistors will be difficult to de-embed from the intrinsic transistor because

very wide transistors are usually designed for the investigation of high-frequency charac

teristics, especially for MOSFETs. Therefore, the "SHORT" dummy pads and the corre

sponding de-embedding technique used for BJTs are not suitable for de-embedding the

series parasitics in DUT of MOSFETs. In this paper, the de-embedding method of using

one "OPEN" and two "THRU" dummy structures based on a cascade configuration has

been presented in detail, and this method can solve the dilemma caused by the intercon

nections.

A general direct extraction procedure of the induced gate noise, channel noise and their correlation in MOSFETs from the on-wafer scattering and noise measurements has been presented in detail and verified with measurements. In general, the channel noise %

is frequency independent and increases when the channel length decreases for all bias conditions at a fixed V Q S . However, fl and iJd* are proportional t o / and/, respectively, which agrees with the theoretical prediction, and they both decrease when the channel length decreases because of the decrease of CQ$. In the case of the cross-correlation coefficient c, it is frequency independent and decreases when the channel length decreases. It was found that i2

d and i id* have a strong VGS bias dependence and they increase then tend to saturate when VQS increases, but i1 has a weak VGg dependence. In addition, both ^ and i'l have weak VDS dependences for devices in which channel length modulation by the drain bias is weak. Also, van der Ziel's model predicts lower NFmin and Rn than the measurements. The extracted channel noise, induced gate noise and their correlation can be used as a direct target for the verification of the physics-based noise models of deep sub-micron MOSFETs.

Finally, the origin of different noise sources and various noise models for the thermal

noise in the conducting channel have been introduced. Hot-carrier effects and velocity sat

uration effects are two very important effects which have to be taken into account for the

noise modeling of sub-micron transistors. On the other hand, from the equation of channel

thermal noise, an accurate high-frequency noise modeling for intrinsic transistors relies on

an accurate DC modeling as well. Therefore, without an accurate DC model, it is not pos

sible to accurately to predict the noise performance.

Acknowledgements

We thank M. Matloubian, Y. Cheng and J. Zheng of Conexant Systems Inc., CA for their assistance in the RF noise measurements and K. Aufinger of SIEMENS AG, Germany for some technical discussions. We are also grateful to Canadian Microelectronics Corporation (CMC), Kingston, ON, Canada and Conexant Systems Inc., Newport Beach, CA for arranging the fabrication of the test structures, and to Conexant, NSERC and Micronet for

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financial support of this work. We are also grateful to several of our current and previous colleagues for their interest and support, and for their comments and useful suggestions on our work over the past several years.

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271



SOI CMOS TRANSISTORS FOR RF AND MICROWAVE APPLICATIONS

D. FLANDRE \ J.-P. RASKIN", D. VANHOENACKER-JANVIER11

'MicroelectronicsLaboratory, "MicrowaveLaboratory Bdtiment Maxwell, 3 place du Levant, B1348 Louvain-la-Neuve, Belgium.

The new communication markets are vey demanding: high frequency, high degree of integration, low power consumption. Silicon-on-Insulator offers many advantages and this paper illustrates the potentialities of this technology for RF and microwave applications. After an overview of the SOI material, the properties of the SOI MOSFETs are analyzed and compared to bulk Si MOSFETs. The models of transmission lines and inductors on SOI are compared and further used in the on-wafer characterization of the transistors. Various models for the transistors are presented and their limitations are given. A new model is described, valid from DC to the microwave region. This model agrees very well with the measurements for various transistor dimensions. Finally, various RF and microwave circuits are presented. This paper does not fully describe all the properties and applications of SOI but the numerous references offered to the reader help him to gather more informations.

1. Introduction

The improvement of the quality, the multiplication and the democratization of portable electronics and mobile communication services need an optimization of technologies and circuit design. A very high degree of integration, a lower power consumption and the use of a lower supply voltage are the goals set for new developments in high speed electronics and wireless transceivers. The integrability and power consumption reduction of the digital part will further improve with the continued downscaling of technologies. It is also the digital part that benefits most from a reduction of the power supply voltage. The bottleneck for further advancement is the analog front-end.

The analog front-end forms the interface between the antenna and the digital signal processor. For the analog front-end, integrability and power consumption reduction are closely related to the physical limitations of the transceiver topology and to the used technology. Present-day transceivers often consist of a three or four chip-set solution combined with several external components. The required number of external components is linked with the physical limitations of the analog front-end topology. A further reduction of the number of external components is essential to obtain a lower cost, power consumption and weight, but it will require a fundamental change in die design of analog front-end architectures. An even further step in the evolution of wireless transceiver design is the realization of the complete transceiver (analog and digital processing) on one chip. Apart from the problem of interference of digital switching noise on the analog signal processing, which is a problem for the realization of any mixed analog-digital design, there is also a problem of incompatible technologies. The analog front-end requires a high performance technology, like GaAs or silicon bipolar, with devices that can easily achieve operating frequencies of more than 2 GHz. For the digital signal processor a small device feature size is essential. It implements complex algorithms and

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1160 D. Flandre, J.-P. Raskin & D. Vanhoenacker-Janvier

this requires the implementation of a huge number of transistors. Therefore, it appears that only the best sub micron CMOS technologies allow for a feasible and cost-effective integration of the mobile communication systems. Silicon offers many advantages as a microwave material and as a system substrate:

• silicon is a mature technology • it has an excellent planarity for all chip bumping and bonding technologies • it is a good thermal conductor • multi interconnect metal layers are easily achieved • an ample set of analog and digital devices can be realized • devices that cannot be realized on wafer can be realized on other materials and

then flip chip attached • the price of float zone silicon wafer has gone down considerably.

Eight- and twelve-inch bulk silicon wafers are available. There exists also eight-inch Silicon-on-Insulator (SOI) wafers (SIMOX: Separation by Implanted Oxygen, Smart-Cut or BESOI: Bonding and Etching-back SOI) of various resistivity, from 20 Q.cm to 10 k£2.cm.

The present article demonstrates the great interests of SOI CMOS technology for improving low power low voltage high-speed analog electronics. SOI has been under development for more than three decades. Interest in thin-film SOI for high performance applications dates back from the late 70's, when several commercial companies undertook research efforts in this area. SOI remained an exotic technology, confined in niche applications for some time, until recently, when the quest for low-voltage performance driven by the boom in portable electronics and mobile communications brought it under the spotlight. Many recent realizations of logic circuits, memories, and RF circuits1,2, have confirmed both the advantages and the viability of thin-film SOI circuits, even in the case of very large systems.

Section 2 presents the evolution of material, devices and circuits in SOI CMOS technology. The electrical behavior and properties of SOI MOSFET's are shown and compared to bulk Silicon MOS transistors in Section 3. The integration of high-Q passive elements on SOI substrates is studied in Section 4. Models have been developed for integrated transmission lines and spiral inductors; and crosstalk is also addressed in that section. These models and CAD tools are helpful to investigate new solutions for increasing the integration of high quality passive elements on silicon substrates. To support the development of thin-film SOI circuits, adequate device modeling must be made available concurrently with the maturation of fabrication processes. Section 5 of the present article focuses on modeling and high frequency equivalent circuit extraction techniques for submicron SOI CMOS transistors. The characterization procedure and the analytical models developed have been used to monitor and analyze the performance, in order to guide the process engineers in their effort to produce high-performance low-voltage low-power SOI CMOS transistors. Section 6 shows measured microwave characteritics such as cut-off frequencies and high frequency noise parameters for various SOI MOS transistors versus bias conditions, channel length and transistor width. Some examples of successful microwave circuit designs in SOI CMOS technology are presented in Section 7. These first circuits indicate clearly the potential of SOI CMOS for low-power high-speed electronics.

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SOI CMOS Transistors for RF and Microwave Applications 1161

2. Overview of SOI Material, Devices and Circuits

2.1. Introduction

SOI standing for Silicon-on-Insulator, the basic difference between conventional bulk silicon and new SOI technologies indeed lies in the starting material (Fig. 1):

• in bulk Si, the active devices are built at the surface of a wafer of monocrystalline silicon, which is several hundreds of microns thick.

• in SOI, the top Si active layer is separated from the underlying mechanical substrate by a thick insulating layer, which leads to a number of advantageous device and circuit properties when compared to bulk Si.

Easy CMOS processing, excellent device scalability, better device and circuit performance and potentially lower cost are among the reasons why SOI technology is considered as a serious contender for the fabrication of future integrated circuits1.

Bulk CMOS

SOI CMOS

Fig. 1. Cross-sections of bulk and SOI CMOS inverters pointing out major advantages of SOI over bulk: (a) Reduced parasitic capacitance, (b) increased radiation hardness against single events, (c) reduced junction leakage at high temperatures, (d) easier inter-device isolation without latch-up structures and subsequent increase of integration density, (e) inherent shallow junction structure without Al spiking effects.

In the present section, a review of the evolution of the material, devices and circuit applications over the last fifteen years will demonstrate that SOI has now reached maturity. SOI technology has indeed evolved from a mere laboratory curiosity in the early '80s to a technology in which large circuits such as 16 Mbit DRAMs3'4 or a 550 MHz 1.8 V Power PC microprocessor5 have been realized. IBM and other major semiconductor IC suppliers have announced the progressive industrialization of their SOI processes since the end of 19986.

We will then briefly review a particular application field for which SOI has already proved very promising: i.e. low-power, high-performance digital circuits, emphasizing the SOI capabilities and possible shortcomings.

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2.2. SOI material

Early SOI research was devoted to finding replacement material for the costly and poor-quality Silicon-on-Sapphire or SOS substrates, primarily used in military and aerospace applications since the 70s for their excellent radiation-hardness. Thick monocrystalline silicon films (> 0.5 urn) on silicon dioxide layers were first obtained by deposition of polysilicon followed by its zone-melting recrystallization (ZMR) using graphite heaters, laser or electron beams1. So-called ZMR materials, as well as others such as ELO (Epitaxial Lateral Overgrowth) or FIPOS, have progressively been abandoned in favor of SIMOX, BESOI and more recently Smart-Cut techniques, because of defect, reproducibility or manufacturability problems.

SIMOX (Separation by IMplantation of OXygen) has been one of the most widely used SOI materials until now (Fig.2.A). It is produced by an implantation of a high dose of oxygen ions (typically 1.8 1018 cm'2) into a silicon wafer, followed by an annealing at very high temperature (1300-1400°C) to finally form a very well-defined buried silicon dioxide layer beneath a single-crystal silicon overlayer1. Large SIMOX wafers (up to 8") with low defect densities have been commercially available for several years. Most early applications still aimed at the improvement of the SEU resistance by exploiting the reduction of the charge collection depth in SOI devices to the film thickness. SOI 64 kb SRAMs have shown improvements of SEU and total-dose resistances by a factor of 100 over bulk CMOS equivalents7. SOI CMOS 29101 16-bit microprocessors and divide-by-16 frequency dividers have been mentioned to survive 0.1 and 0.5 Grad (Si02) respectively8. Furthermore, a simultaneous increase of speed performance by 30 to 40 % was observed as a result of the well-known reduction of the junction parasitic capacitances in SOI circuits9. Applying the same property to the collector of bipolar transistors once allowed the achievement of a record 32 GHz transition frequency10. 1 Mb SRAM have also long been studied and realized11. Other applications for thick-film SOI have exploited the perfect dielectric isolation provided between adjacent devices when field or trench isolators extend down to the buried oxide. Latch-up suppression and substrate noise reduction then make possible the easy realization of smart-power circuits combining on the same chip low-voltage CMOS with high-voltage DMOS, bipolar or JFET devices12. Similarly SOI CMOS mixed-mode circuits have also been realized, such as a sigma-delta A/D converter with a S/N ratio improved by 8 dB over the bulk CMOS equivalent13.

Bonding and Etch-back SOI or BESOI material appeared next1. The technique consists in the bonding of two thermally oxidized standard Si wafers, followed by the thinning of one side by mechanical, chemical or plasma etching (Fig. 2.B). In principle BESOI can provide defect-free Si overlayer and then compete with SIMOX for thick-film SOI applications. However a quality of the SIMOX material, which BESOI is still missing, is the relatively well-controlled thickness of the top Si film (down to ± 1 nm) that is required for the fabrication of very thin-film SOI devices (thickness < 100 nm). BESOI will therefore remain devoted to very thick film applications, e.g. smart power.

Smart-Cut material was developed more recently out of an original combination of ion implantation and bonding techniques14 (Fig. 2.C). In order to solve the control problem of thin film thickness in BESOI, a starting wafer A is implanted with hydrogen ions at a low depth below a previously grown oxide. In a second step it is bonded to oxidized wafer B. After activation, the assembly can be accurately split at the level of the hydrogen implant since hydrogen ions have the property to weaken the Si atoms bonds. Smart-Cut features many advantages with regards to SIMOX and BESOI:

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• film thickness control depends on the accuracy of a conventional well-mastered ion implantation.

• throughput is considerably increased and cost reduced since on one hand, high-dose implantations and long high-temperature annealing are avoided while on the other hand, wafer A can be reused and wafer B can be of lesser quality.

After just a few years of development, 8-inch Smart-Cut wafers already achieve the same quality and cost as SIMOX material does after twenty years. The future also looks very bright since the technique can be easily extended to 300-mm wafers and the film thickness could ultimately be controlled at the atomic level. Smart-Cut material is commercialized in large volumes by SOITEC in Grenoble, which opened a dedicated facility with almost 1 million wafers per year production capability.

The latest commercially available SOI substrates appear as alternatives to the Smart-Cut concept, substituting the hydrogen ion implant used for defining the precise cleavage layer by other ion species or implanting techniques or by porous silicon in the case the Canon ELTRAN process15.

2.3. SOI CMOS processes and devices

Thick-film Partially-Depleted (PD) SOS or SOI MOSFET's (Fig. 3.A) are long-known to feature degraded electrical characteristics due to floating substrate ("body") effects1 (FBE, Floating Body Effect). Their origin lies in the existence of a quasi-neutral region which is sandwiched between the isolation oxides and the front/back interface and source/drain space charge regions and hence left unconnected or floating. Under normal static operating conditions, the potential of this quasi-neutral region will be defined by the currents of forward-biased source and reverse-biased drain junctions and will therefore remain close to the source voltage, so that the device behaves similarly to a conventional bulk MOSFET with a local well. However, for drain voltages large enough to generate significant impact ionization in the pinch-off region, a phenomenon known as the kink effect occurs (Fig. 4). Impact ionization indeed creates excess electron-hole pairs. In an nMOSFET, the electrons flow to the drain along with the channel current, whereas the holes flow towards the lowest potential node. In a bulk Si device, the excess holes are then evacuated by the substrate or well contact, whereas in a PD SOI MOSFET, they have to be recombined at the source junction, thus forward biasing it. The quasi-neutral region potential increases, leading to a reduction of the threshold voltage which, in turn, yields an increase of the drain current and hence of the impact ionization hole current until this positive feedback mechanism is limited when the source junction forward bias achieves 0.6-0.7 V. FBEs in PD SOI MOSFET's are not restricted to a static degradation of the output conductance in saturation which is detrimental for analog applications, they also lead to a number of dynamic phenomena which may alter the functionality or timing of digital circuits16'5. For a larger review of PD device performance, FBE phenomena and related circuit design tricks please refer to Refs. 17, 18.

FBE in PD SOI MOSFET's may be suppressed by providing a lateral body contact in order to tie the quasi-neutral region to a fixed potential (Fig. 5), at the expense of die area and speed performance. For low-voltage applications, the lateral body tie may however be exploited to implement DTMOS (for Dynamic Threshold) transistors, in which the body

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potential is being controlled by the gate. It increases under turn on conditions thereby yielding lower threshold and increased drive current17

I Oxygen ion implantation i

I I 4 4 I

Silicon substrate

anneal ini &^

Silicon overlaver

Buried oxide layer \ sv^

Silicon substrate

Si wafer (fiiture SOI layer)

D * Y;/W;;;AUM;;;;;/7777.

I I I I | Polishing/etching

4 4 4 4 4 _,Si02

Si-handle wafer

H+ implant

\//S////J/»J;/;//A

Wafer A

Wafer A

'/SJWSSSWS//J

Wafer B

Wafer

bonding

Wafer A

splitting

Wafer A £

V/////'//////77777? Wafer B

Wafer A to be used next as. Wafer B

'/;///j//////s/j/r>

SOI Wafer

Polishing

Fig. 2. Fabrication process for SIMOX (A), BESOI (B) and Smart-Cut (C) SOI wafers.

A: Partially depleted

C: Accumulation mode

KflaETTraas Lb .iu)'ffvn"rri"'

N j P

B: Fully depleted

D: Volume inversion

n+ poly gate

*—1 Source/ i^J drain

Depletion

HH Inversion

Hill Accumul.

^ Neutral

Fig. 3. Types of SOI MOSFET's (for sake of conciseness, only the Si film and active gate material and oxide are represented, not the buried oxide and underlying Si substrate).

278


vs

VGf

t»y/yc-';yy"-^'•••'•'";-]

- W - * B • * •

v D

v G b

Kink effect

Drain voltage

Fig. 4. Typical PD SOI MOSFET structure and ID-VD curves for various gate biases.

Substrate j contact

c ©

=•3

3

p+

\ \

Source

N?_. . • -• . ,

§» ' • Drain

i >•?

P+

Gati

a s ©

-Cl a 03

'normal" lateral contact H-gate contact

Fig. 5. Typical body tie layouts.

On the contrary, MOS transistors realized on SOI films thin enough to allow the depletion region to extend across the whole film (Fig. 3.B) feature dramatically reduced FBEs due to the reduction of the source barrier. Furthermore they exhibit superior device characteristics with respect to bulk MOSFET's: sharper subthreshold slope close to an ideal 60 mV/decade value at room temperature, improved drive capability due to smaller body effect and mobility degradation with gate voltage19. These properties result from the front-to-back gate coupling through the Fully-Depleted film capacitance as will be detailed in Section 3. The main drawback of Fully-Depleted or FD devices is-the sensitivity of the threshold voltage to the film thickness and buried oxide parameters, the latter ruling out the use of thin-film FD SOI devices for total-dose radiation-hardness applications. Threshold voltage dependence on the film thickness can however be minimized holding the film total dose constant rather than the doping concentration . Threshold voltage standard deviations similar to bulk devices have indeed been achieved for FD SOI MOSFET's.

The use of thin-film SOI substrates, in which, by definition, the lateral isolation field oxide extends down to the buried oxide providing complete dielectric isolation of neighbor devices, considerably eases the fabrication of deep-submicron MOS devices

279


either FD or PD. When compared to conventional bulk process, threshold voltage roll-off is indeed minimized, reliable ultra-shallow junctions are easily processed, wells and latch-up are suppressed and complicated lateral isolation process can be avoided. In addition, although defect densities may be higher in SIMOX films than in bulk substrates, SOI process yield may actually be higher than that of bulk since SOI devices and circuits are much more tolerant to defects1.

Unique buried-channel MOS devices, such as p-channel transistors featuring P+

source and drain and P" uniformly doped channel regions, can be built on thin-film SOI substrates9 (Fig. 3.C). No current flows as the device is turned off because of the full depletion of holes in the channel region. When the device is turned on, an accumulation current flowing in a surface channel adds to the buried current that flows in the undepleted part of the film. As a result, so-called accumulation-mode or AM devices (Fig. 3c) show low leakage currents, almost ideal subthreshold slopes, as well as excellent drive capability due to the combination of several conduction mechanisms and the use of low doping levels which favors higher mobility. P-type AM devices are of particular interest because -0.7 to -0.4 V threshold voltages are easily achieved using hT-polysilicon gate material, thereby avoiding the problem of boron penetration into the gate oxide when

using P+-doped polysilicon. Various processes using p-channel AM transistors have been proposed21, as well as processes with both n- and p-AM devices22. However, originally, AM devices were not candidates for deep-submicron ULSI integration due to short-channel effects and punchthrough characteristics not as well controlled as in enhancement-mode FD transistors. Nevertheless the feasibility of 0.2 urn AM MOSFET's has been demonstrated23.

Double-gate (DG) thin-film MOSFET's may be regarded as the ultimate FD devices24'25 (Fig. 3.D). Also called volume-inversion devices due to the extension of the inversion layer across the whole Si film, these transistors feature very high drive currents, ideal subthreshold characteristics and totally suppressed body effect. The threshold roll-off is moreover much reduced. However, although several fabrication processes for DG devices have been proposed26'27 and some circuits have shown very promising performances, in particular for total-dose radiation-hardness ' ' ' , the fabrication unfortunately remains non-standard which presently jeopardizes the use of DG devices for ULSI applications. Nevertheless the 1999 SLA roadmap and numerous publications clearly point out the need for DG devices to simply and efficiently control the short-channel effects below 70 nm of channel lengths32'33

2.4. High-speed low-power digital circuits

SOI CMOS is already considered as a very attractive technology for the realization of low-voltage low-power (LVLP) digital ULSI circuits and has a number of well-known advantages over conventional bulk Si CMOS34'1.

The power and speed performance of simple logic gates are usually characterized by means of the following relationships:

Power = fC{vddf

Delay ~ cvdd CD

K{VM-VJ

280


where / is the frequency, C the total capacitance of the logic gate, VM the supply voltage, Vth the threshold voltage and K a constant which is inversely proportional to me body factor. These relationships clearly show that simultaneous reduction of power and delay can only be achieved by reducing the capacitance, which is a long-known advantage of SOI.

It has been recognized for a long time that the SOI dielectric isolation provides much reduced parasitic capacitances with respect to bulk CMOS. In the latter case, the source/drain loads indeed correspond to junction capacitances, which depend on substrate or well doping and bias voltage (Fig. 6). The technological trend towards reduced dimensions and supply voltages inherently leads to an increase of die source/drain junction capacitances per unit area. In thin-film SOI, die source/drain capacitances are mainly defined by the buried oxide mickness and hence are tremendously reduced when compared to bulk, both regarding the bottom area (Cj„, Cjp) and sidewall components (Cjswn. CjSWp) (Fig. 6). In recent deep submicron CMOS processes, the SOI source/drain junction capacitance reduction even achieves factors on the order of 10 when compared to bulk. The parasitic capacitances of polysilicon and metal interconnection layers are also reduced in SOI due to the presence of die thick buried oxide, but to a lesser extend depending on the technological stack height.

cjswn - ' - - • "" ~jswp CVitau bulk /SOI -1.3

Fig. 6. Comparison of bulk and SOI junction capacitances for a typical 1 \xm CMOS process (Q and Qsw denote the bottom area and sidewall peripheral junction components at zero bias).

Overall, the typical speed increase and power decrease related to SOI reduced parasitic capacitances amount to about 30 to 40 % versus comparable bulk CMOS circuits.

From Eq. (1), another obvious way to preserve the speed performance while reducing the supply voltage is to decrease the threshold voltage. In bulk implementations this can only done at the expense of an increase in the leakage current and hence in static power dissipation. Fully-depleted SOI transistors offer the opportunity to limit that degradation owing to their almost ideal subthreshold slope, as well as to further increase die drive current owing to their smaller body factor. These characteristics all add up to significantly increase the power times delay capability, in particular for reduced supply voltages, as discussed below.

281

1168 D. Flandre, J.-P. Raskin & D. Vanhoenacker- Janvier

2.5. Perspectives

Years of worldwide research and development in universities and industrial research centers were necessary to demonstrate the benefits and manufacturability of SOI. The industrialization phase towards mainstream production started in August 1998 with the announcement of IBM's plans to ramp-up its SOI technology towards, firstly, the fabrication of commercial high-speed microprocessors6. IBM chose to rely on its own-fabricated SIMOX material and on a PD SOI CMOS process which at this time, proved to be more straightforward and reliable to scale to sub-0.2 um channel lengths, than FD devices requiring very thin SOI films in order to control the short-channel effects . Inherent PD floating-substrate effects are controlled at the design level by proper simulation and timing of critical digital paths36.

Nevertheless the FD process has been proved to be the best option for 0.25 um and above SOI CMOS and its controllability is improving at a rapid pace. Scalability towards sub-0.13 um dimensions has been demonstrated on 30 nm-thin SOI films37.

The cost issue has long been said to delay the use of SOI for commercial applications. SIMOX or Smart-Cut substrates are still about 3 times more expensive than identical size and comparable quality bulk Si wafers. Nevertheless a past Sematech study demonstrated that if the higher starting cost could be reduced by a factor of 2, the revenues to be made from mass production of 64 Mb SRAM could be substantially higher using a SOI instead of a bulk CMOS process. The reasons are: fewer processing steps, better fabrication yield, smaller chip size and enhanced performance38. More recently, IBM claimed that, even considering the present cost of their SIMOX substrates, the total "SOI wafer + CMOS process" fabrication is only 10 % more expensive than the corresponding bulk Si CMOS process.

The SOI material cost decrease could be driven by the development of a high-volume application such as DRAMs. SOI implementation of DRAMs was not considered at first because the SOI film thickness drastically limited the depth of the buried storage capacitor thereby increasing the required cell area. However with the advent of stacked memory capacitors built atop the cell transistors, DRAMs on SOI have been tested and showed considerable improvements over bulk counterparts in cell area and access time39. Nevertheless, there currently remains a critical problem to be overcome regarding SOI use for high-volume applications, namely wafer availability, which in year 2000 does not exceed 2 million pieces per year.

The challenges for low-power low-voltage analog and microwave SOI CMOS circuits, however, have not been as widely investigated. Preliminary theoretical results nevertheless showed that analog circuits, in particular operational amplifiers, benefit from the lower body effect and load capacitances in FD SOI CMOS40-41'42'43. On the other hand, preliminary experimental results also showed that submicron FD SOI MOSFET's may achieve transition frequencies in excess of 20 GHz for supply voltages on the order of 3 V . Combined with the ability to realize low-loss matching or interconnection lines on high-resistivity SOI substrates45 and the drastic reduction of substrate crosstalk figures46, these properties may lead to the future development of single-chip mixed digital/analog/microwave solutions.

A recent development of SOI applications is related to the field of integrated sensors. High-precision thin membranes can indeed be easily processed on SOI substrates owing to the good control of the film and buried oxide thickness. High-performance pressure sensors as well as accelerometers for use in airbag electronic systems have already been produced.

282


3. Properties of Fully-Depleted SOI MOSFET's

3.1. Introduction

With SOI emerging as a key technology for the realization of future low-voltage low-power (LVLP) CMOS circuits, the impact of the improved characteristic* of SOI MOSFET's on speed and power consumption has already received a lot of attention in digital circuitry1. The challenges for analog SOI CMOS circuits, however, have not been as widely investigated. The reduction of parasitic capacitances and the feasibility of diffusion resistors and capacitors free of junction effects have however long been recognized as advantages for the realization of analog circuits on SOI substrates48. Nevertheless, few SOI analog circuits have been reported, presumably because the occurrence of the kink effect in thick-film partially-depleted (PD) SOI MOSFET's severely degrades the output conductance characteristics in saturation1 and thereby the performance of analog circuits. Solutions to the kink effect such as the use of body contacts49 or twin-gate devices50 have been implemented in operational amplifiers but the results showed little improvement of the performances over bulk CMOS counterparts, exception for the ability to withstand elevated temperatures in excess of 300°C51.

The kink effect is known to be greatly reduced in thin-film fully-depleted (FD) SOI MOSFET's. Moreover FD devices provide much smaller subthreshold swing and substrate factor than bulk or PD SOI MOS transistors1. This might offer interesting opportunities for LVLP analog circuits.

The present section will present the major properties of FD SOI MOSFET's, of interest for the analog circuit design and operational amplifiers (opamps) in particular, i.e. the I-V characteristics of MOS transistors in saturation and principally, the ratio of transconductance over drain current, the output conductance and the intrinsic gate capacitances. Noise, linearity and dynamic range performance will be briefly treated as well. In addition, an engineering model, efficient for opamp design, will be validated.

3.2. I-V characteristics and body effect - impact on digital circuits

The main interesting feature of FD SOI MOSFET's is the low value of the body-effect coefficient, which influences both the current drive of the device and its subthreshold swing. The body-effect coefficient, denoted n, is an image of the ideality of the coupling between the gate voltage and the surface potential. It is well known that FD SOI devices offer near-ideal coupling, which yields a value of n close to unity, contrary to bulk Si MOSFET's. This can be intuitively explained by relating the body effect to the capacitive division between channel, gate and substrate potentials (Fig. 7).

283


Bulk Si MOSFET

i

mmmsmm;3®is!s& S//////J//JWM'f'( Vs^r i C

T CH

'B

Fully-depleted SOI MOSFET

Fig. 7: Comparison of bulk and SOI MOSFET space charge regions and body effect models.

In a bulk transistor, n is then given by

n = l + -£ „ •

(2)

where COT is the gate oxide capacitance per unit area, esi is the permittivity of silicon and ^dmax *s m e m a x i m u i n depletion width in strong inversion. In a bulk CMOS process with channel lengths around 1 um (i.e. corresponding to a gate oxide thickness of about 30 nm), n is equal to 1.4-1.6 typically. In a 0.25 um processes, the scaling down of the gate oxide to about 5 nm is partly counterbalanced by the Xdmax reduction due to doping level increase which yields typical n values of 1.2 - 1.3.

In a SOI FD MOS transistor, on the other hand, the body effect is given by

« = 1 + -Cjcsi/( +Coxb

(3)

where Coxb and tsj are the buried oxide capacitance and the silicon film thickness, respectively. Typical n values reduce to 1.05 - 1.1 for a 1 um processes with oxide thickness tm, silicon thickness tsj and buried oxide mickness tmb equal to 30, 80 and 400 nm respectively and even reduce to 1.01 - 1.02 for a 0.25 um processes with tgx, r and r equal to 5,40 and 400 nm respectively.

The influence of the body-effect coefficient on the current drive of the device can be best understood by using a simple device model. The saturation drain current of a MOSFET is given by the following expression:

oxb

tDsa,=^Cox^-(Vg5-Vlhf (4)

H being the effective mobility, V the gate-to-source bias, Vth the threshold voltage and W and L the width and length of the device respectively. From the above equations, it follows that the saturation drain current may be 30-40% higher in a FD SOI device than in a bulk device with similar parameters, depending on body effect.

284


A more accurate model for submicron devices would include velocity saturation and series resistance effects52. These tend to somewhat degrade the superior current drive capability of FD SOI MOSFET's as short channel lengths are considered. It has been shown however that non-optimally designed FD SOI transistors still present a 25% current drive improvement over comparable bulk devices for gate lengths down to 0.2 um which could be restored to even better values with optimization of the device structure .

In addition, the subthreshold swing (inverse subthreshold slope) of a MOSFET is also affected by the body effect. Indeed, the subthreshold swing is given by the following expression1:

S(mV/dec.)=n—In(l0) (5) 1

if the influence of the interface traps is neglected. The low value of n in FD SOI devices yields an improvement of the subthreshold slope over bulk devices. Almost ideal subthreshold swings of 60 mV/dec at room temperature corresponding to the predicted n values have been experimentally demonstrated for optimally designed FD SOI MOSFET's with channel lengths down to 0.2 um54. As a result, a lower threshold voltage can be used in SOI devices without jeopardizing the OFF leakage current (Fig. 8a), and ON drive current much higher than in bulk devices can be obtained, in particular for reduced supply voltage (Fig. 8b).

Gate Voltage (V) Supply voltage (V)

(a) (b)

Fig. 8. (a) Subthreshold slope of bulk and fully depleted SOI MOSFET's, (b) Ratio of fully depleted SOI to bulk saturation drain currents.

Fig. 9 validates these concepts comparing the Id-Vd curves of short-channel nMOSFET's, from SPICE model results of three available 0.25 um CMOS processes: bulk, PD SOI with body tied to source or not, FD SOI. The impact of the improved FD SOI CMOS characteristics on speed and power consumption has already received a lot of attention in digital circuitry. ASIC's and gate arrays have been realized showing speed improvement factors over bulk counterparts by up to 1.7, with a 3 V power supply ' . Circuits built on a 0.5 um FD SOI CMOS IM gate array showed twice the speed or half the power consumption of similar bulk CMOS circuits when operated at 2 V supply voltage.

285


1.40E-03

1.20E-03

1.00E-03

^ 8.00E-04

< Q — 6.00E-04

4.00E-04 •

2.00E-04 -

O.OOE+00 •

/ ^ ^ M - - ~ " ~ """

/

'

BULK

PD-SOI with body contact

PD-SOI with floating body

FD-SOI

0.2 0.4 1.2 1.4 1.6 0.6 0.8 1

VD(V)

Fig. 9. Comparison of bulk, PD and FD SOI n-MOSFET drain currents for W = 10 um, L = 0.25 |jm, Vgs = 1 V and VbS = 0 V. In the PD-SOI case with body contact, the latter is tied to the source.

It can be shown that around 40 % of the improvement results from the capacitance reduction and the other 60 % from the drive current increase. A threefold enhancement of the power times speed figure of merit has been demonstrated for 1 V supply voltage, in particular in the case of a 512K SRAM57. A 0.25 um 625 MHz 1.5 V fully-depleted SOI CMOS 64-b microprocessor recently demonstrated an increase of speed by 30 % and a decrease of power by a factor of 3.3 when compared to the bulk equivalent58.

Regarding very high-frequency circuits, 0.25 um FD SOI CMOS circuits had already been processed in 1987 with frequency dividers achieving a record 2 GHz input frequency59. Further improvements lead to 6.2 GHz frequency dividers comparable in speed to bulk Si bipolar or GaAs implementations but with considerably smaller power dissipation60. Frequency dividers operating at 1 GHz with a 1 V supply voltage have been realized in a 0.12 (am SOI CMOS process, consuming only 50 uW61.

3.3. CAD models

Several analytical modeling alternatives exist for the electrical simulation of FD SOI CMOS circuits. The best-known SOI SPICE model62 was originally developed for 5 V-digital applications. It has been proved efficient for the reliable simulation of LVLP digital circuits down to a 1 V-supply voltage63. However, as it is a strong inversion-based model, it is inadequate for reliable analog design. It indeed suffers from the troubles common to this family of models such as improper modeling of moderate inversion current, discontinuous transition from triode to saturation, discontinuities of the current and charge derivatives (i.e. the small-signal conductance and capacitance parameters) between the different regions of operation, unphysical overshoot of the transconductance/drain current ratio in moderate inversion64, etc. On the contrary, efficient analog design, and especially for LVLP applications, requires a model valid from weak to strong inversion and non-saturation to saturation conditions with smooth continuous transitions. The EKV model initially developed for bulk MOSFET's provides such properties65. It has been proved that it can successfully be extended to FD SOI MOSFET's56,43. A dedicated FD CMOS model which features infinite continuity of both

286


current and charge expressions as well as their derivatives (i.e. conductance and capacitance) has also been proposed, initially for channel lengths down to 1 urn , then extended down to 0.16 um effective channel lengths68 as well as towards RF simulation up to more than 20 GHz69. The latter will be further used in the next sections on microwave devices and circuits.

In the next paragraphs of this section, we will mostly exploit the EKV modeling as a simple and efficient empirical engineering model for the design of analog blocks. Occasionally we will also refer to charge-sheet models when the EKV model reaches its limitations. Charge-sheet models such as presented in Ref. 70 for bulk Si MOSFET's and in Ref. 71 for FD SOI MOSFET's also fulfill the conditions of validity and continuity from weak to strong inversion and non-saturation to saturation conditions with smooth continuous transitions. However charge-sheet models rely on the resolution of a set of highly non-linear implicit equations and are not computationally efficient, nor widely available in SPICE.

3.4. Analog properties

In the case of analog circuit design, operational amplifiers (opamps) in particular, we are mostly concerned with the characteristics of MOS transistors in saturation and principally, the ratio of transconductance over drain current, the output conductance, the intrinsic gate capacitances and the noise performance. We will then focus our discussion on these parameters and their modeling in the EKV formulation. The extension of the EKV model to fully-depleted SOI MOSFET's will be presented and supported by measurements on both bulk Si and SOI MOSFET's.

Two special cases of MOSFET operation of interest in analog applications, i.e. as a linear resistor in continuous-time filters and as a CMOS switch in switched-capacitor structures, will be briefly treated as well regarding their linearity and dynamic range performance.

3.4.1. Ratio of transconductance to drain current

The transconductance-to-drain current ratio directly affects the open-loop gain of operational amplifiers as will be discussed in Section 7. As far as analog micropower circuits are concerned, it is known that the maximum performance may be obtained when the value of the transconductance/drain current ratio (gUh) is the largest. This condition appears in the weak inversion regime for MOS transistors72. The value of gjlo can be rewritten as:

gm= dID = l n ( ! 0 ) = q ID IDdVa S nkT

The low body-effect coefficient of SOI devices allows for obtaining near-optimal micropower designs (g„/Io values of 35 V"1 are obtained close to the maximum physical value at room temperature, while g„/lo reaches only values of 25 V"1 in bulk MOSFET's).

In strong inversion, the gjlo becomes (for long-channel devices):

287


nlr, (7)

and remains higher in FD SOI than in bulk MOSFET's with similar technological characteristics.

Experimental SOI and bulk n-MOSFET %JID characteristics are compared in Fig. 10. The good agreement between measured and modeled gjlo characteristics, using the EKV model, is also demonstrated for both bulk and SOI devices. This model proposes an analytical expression for the gJID in saturation, which is continuous from weak (WI) to strong inversion (SI) and simplifies to the well-known expressions presented above in WI and SI, when the corresponding conditions are applied:

I

1-e {-JhJh

D nUT vw7

= 2nnCoxi^/LyT

(8)

where Is a normalization current, n is the mobility, Cox the gate oxide capacitance per unit area, W the width and L the length of the device, and UT the thermal voltage. This expression is valid and mathematically identical for both the bulk and FD SOI MOSFET's but the SOI n body factor is constant from weak to strong inversion according to Eq. (3), whereas in bulk, it is slightly dependent on V Q according to Eq. (2). However as a first approximation, this variation can usually be neglected7 .

1 0 " 1 0 " 10" 10" V(M-COX.W/L) (v2)

Fig. 10. Experimental (symbols) and modeled (lines) transconductance over drain current ratios vs. normalized drain current in saturation: Bulk (x) and SOI (o) measurements, EKV model with n - 1.1 for SOI (—) or 1.5 for bulk case (—).

Rewriting Eq. (8) as

288


ID

J _Ip_ (W/L) C Is 2nnCmU}

I c is also called the inversion coefficient65. Denoting ID/(W/L)=I', the "adimensional" current normalized to the aspect ratio, we may deduce that the gjlo versus / ' characteristic does not depend on the actual device sizes, but only on device type, technology and temperature. Hence, it appears as a universal curve that characterizes all the devices of a given type (either nMOS or pMOS) for a given technology, at constant temperature. As will be shown in Section 7, such a curve proves very efficient for top-down analog design in which device dimensions are unknowns of the problem and very difficult to guess a priori.

This analysis has been extended to deep-submicron SOI CMOS processes and our results demonstrates that optimized sub-0.25 urn-effective length FD MOSFET's still present significantly larger gjlo ratios than PD and bulk devices thanks to their well-known much better subthreshold slope and body effect. However, for the nominal 40 nm film thickness, the longer channel devices show an unexpected degradation of the g„/Io under weak inversion conditions. This has been related to non-fully-depleted conditions due to the low gate voltage applied. Whereas in shorter channel devices, the source/drain-to-body depletion regions start to interact with channel depletion and fully deplete the film even at zero gate voltage.

As will be discussed into full details in Section 7, the combination of this gJlD

improvement with the reduction of the parasitic capacitances can be exploited to boost the performances of SOI CMOS amplifiers over bulk implementations by a factor between 3 to 10, in terms of either the transition (unity-gain) frequency, the circuit area, the dc open-loop gain or the stand-by current.

3.4.2. Early voltage

The EKV model incorporates the non-zero output conductance (i.e. gd =dID/dVD ) of

MOS transistors in saturation by introducing the concept of channel-length modulation7

and multiplying ID by the appropriate factor. We may also define an Early voltage parameter73,74 Vea so that in saturation, gd is equal to ID IVea .

This second formulation will be preferred for the opamp small-signal analyses to be discussed further. Vea indeed appears as a figure of merit for each technology since, to the first order, it does not depend on the drain current amplitude as does the output conductance. Measurements have shown that our FD SOI MOSFET's exhibit mean Vea

values proportional to L as is usual and on the order of 7-10 (V/um) times the length for 2 < L < 20^/w . Such figures are similar to those of comparable bulk devices.

More detailed analyses of Vea have shown strong dependence on biases and technologies75 (Fig. 11), i.e.:

• an increase of Vea from WI to SI corresponding to enhanced vertical gate coupling and lesser lateral drain influence on the drain current,

l-e h/ n (Q\

289


• an increase of Vea in FD SOI when compared to bulk MOS technology which can be intuitively explained by a reduction of the penetration of the drain depletion charge into the channel region when compared to bulk (Fig,

0.5 1.0 1.5 2.0 2.5

VdsW Fig. 11. Early voltage as a function of diain-to-source voltage, with gate bias referred to threshold (GVO - Vc-V„i) varied from weak to strong inversion, for n-MOSFET's from a 2.4 \tm bulk technology ( ) and from a 2 Mm FD SOI process ( ).

BolkSiMOSFET

SOIMOSFET

Kg. 12. Intuitive interpretation of the Early voltage improvement in FD SOI MOSFET's due to a relatively smaller drain charge penetration (dark area), when compared to bulk equivalent.

Table 1 presents Veo extraction for 0.25 |im FD SOI CMOS process and shows that improved full depletion in thinner devices also tends to slightly better Vea, due to reduced

290


short-channel effects. But more importantly, it demonstrates that full depletion maintains a linear relationship between Vea and L, on the order of 10 V/um, from very short to long channel lengths, contrary to recently reported sublinear degraded trends in bulk Si transistors with Halo pocket implants7 .

L

vD=vG 0.4 V 0.6 V 0.8 V 1.0 V

L

vD=vG 0.4 V 0.6 V 0.8 V 1.0 V

0.25 urn fs,=30 nm 1.16V 2.43 V 4.37 V 9.05 V

1 um tsi =30 nm 10.05 V 13.71V 18.37 V 25.63 V

0.25 jim r„=40 nm 0.78...0.86 V 1.81...1.84V 3.44...3.57 V 7.71V

1 Jim tsi = 40 nm 6.79... 10.74 V 12.75...13.21V 15.05...16.10 V 26.97 V

Table 1. Early voltage as a function of length (L) and silicon film thickness (f„), for gate voltage equal to drain voltage and Vgbs= 0 V.

3.4.3. Intrinsic gate capacitance

The intrinsic capacitances are important elements of the small-signal dynamic model of the MOS transistor73. They do not correspond however to actual physical capacitors, but are mathematical elements conveniently describing the variations of the different charges stored within the device as a function of the voltages applied to the different terminals. Considering that a MOS transistor has four terminals and that a charge is referred to each of them, we will face a complex model of sixteen intrinsic capacitances, noted Cy and defined as:

C = x-

with i and j suffixes corresponding to either gate, source, drain or substrate terminal. As they depend on applied bias, the intrinsic capacitances are non-linear components, furthermore non-reciprocal since C„ corresponding to the variation of the charge associated to terminal i with the voltage applied to terminal j does not have to be equal to Cjj which corresponds to the variation of the charge associated to terminal j with the voltage applied to terminal i.

In OTA design, the two most important intrinsic capacitances are Cgg and Css, which respectively correspond to the two basic amplifier configurations, i.e. the common-source where the device is seen from the gate and the common-gate where the device is seen from the source. The complete Cy model may therefore be reduced, for sake of simplicity, to two elements, the gate-source Cgs and gate-bulk Cgb capacitances. Since in saturation the gate-drain Cgd and non-reciprocal drain-gate Cdg capacitances both tend to be identical

3V,

+ 1 if i = j ,Xii~U if i*j

(10)

291


and equal to zero, Cgg indeed reduces to Cgs+Cgb = Csg+Cbg. Following Ref. 77, a worst-case approximation for Css in saturation will be to take it equal to Cgs approximately, although it is generally slightly lower.

The EKV model proposes empirical analytical expressions for Cgb and Cgs, which are valid in and continuous between all regimes of operation65. Figure 13 illustrates this behavior as a function of Vc, showing that in moderate inversion, the intrinsic gate capacitances strongly depart from their well-known strong inversion values, e.g. Cgs equal to two thirds of Cox. The lower values are obviously related to the progressive build-up of the inversion layer from WI to SI and should be taken into account in efficient opamp synthesis in order to reliably locate the associated poles and zeros.

Measurements16, 2-D numerical device simulations16,40 and modeling78 have shown that the intrinsic gate-to-source Cgs and gate-to-drain Cgd capacitance characteristics of FD SOI MOSFET's are similar to those of bulk devices. The source/drain-to-gate coupling through the conducting inversion channel and the gate oxide is indeed similar in both cases.

-0.1

TTTryr

.& & See-* »«w-»-»-w

o 9-^ C u ° - ( .0_PJ?<2°

b 9 of

/

/

c ° / o/ /

o/ o /

•seoe ^-tsoS A o©o-Q-& 8-o_o_o_P_°_ /

d o/

VGf

Fig. 13. Normalized intrinsic gate capacitances CIS (x) and Gg(i (o) as a function of the gate voltage for Vrj = 1.5 V and Vg = 0: measurements (x,o) and FD SOI MOS model (curves) for different gate voltage (a-0.05 V, b-1.05 V, c-2.05 V, d-3.05 V).

However, the gate-to-substrate capacitance Cgb which is non-zero in the subthreshold and saturation regimes is much smaller in FD SOI than in bulk MOSFET's78'79 because the depletion capacitance is here combined in series with the buried oxide capacitance. This leads to a smaller value of the FD SOI MOS Cgg, when compared to bulk.

Our FD SOI MOS model67 extended to compute the charges and intrinsic capacitances clearly reproduces these behaviors with the smooth continuous transitions between operating regions desired for analog design (Fig. 13). We have verified that the EKV expressions also accurately match the characteristics of FD SOI MOSFET's. They can then be used for the reliable analog design of CMOS SOI circuits.

292


3.4.4. Noise

The intrinsic noise generation within a MOSFET is another important phenomenon regarding the design and operation of analog circuits. The classical MOSFET noise model takes two noise sources into consideration at low frequencies, i.e. the thermal and flicker (or 1/f) noises.

1) The thermal noise arises from the resistive nature of the MOSFET channel. Typical SPICE noise models express the thermal noise power spectral density on the drain current by:

SlD=\kTgm (11)

The validity of this model is however limited to strong inversion and saturation conditions.

The EKV model proposes again a formulation, based on the physics of the device, that remains continuously valid diroughout all regimes of operation65. Under saturation conditions of main interest here for amplifier design, the model simplifies to:

S,D=4kTngma (12)

where a is a factor ranging from 2/3 in SI to 1/2 in WI. We propose here a simple formula for directly computing a from the g„/lo ratio:

a= - 5- (13) ( \

^-nUr 3 =

2) The flicker or 1/f noise is related to the phenomena of channel charge fluctuations and is modeled by the addition of a noise source in series with the applied gate bias. A typical expression for the flicker noise power spectral density on the gate voltage relates this statistical behavior to a technological empirical parameter Kf, the total gate capacitance W.L.Cox and the frequency/:

Kf •

Sv = L— (14) Vc WLC0Xf

Kf values extracted for various SOI CMOS processes under normal operation have shown figures similar to typical bulk MOSFET's80, e.g.

Kfn • 8.61024 V2.F, for FD SOI nMOSFET's, KfiP • 5.5 1025 V2.F, for AM SOI pMOSFET's.

293


3) The total input referred noise power spectral density is finally equal to:

Si

am (15)

According to (12), the thermal noise will be smaller in FD SOI than in bulk, for the same gm and frequency specifications, given the reduction of the n body factor. The 1/f noise will be made smaller in FD SOI too, since in Section 7, we will show that the reduced body effect and parasitic and gate capacitances can be exploited to increase the gate area (i.e. W.L in (14)) when compared to bulk for same frequency performance.

However designers should be aware of the fact that floating substrate phenomena may lead to increased low-frequency noise levels in PD as well as in FD SOI MOSFET's, if full depletion is not ensured for any bias or temperature operating conditions81'82. This appears as an additional Lorentzian noise component showing a plateau noise value followed by a 1/f2 slope (Fig. 14). This component may be related to currents flowing in the floating body due to the kink effect or the source/drain junction behavior.

i >

10

u 10

> 10

-11

-12

-13

10

10

-14

-15

*Ut_

40 nm

30 nm <s N

10 10 ^ 10 D

Frequency ( I t )

10 10

Fig. 14. Low-frequency gate-referred noise power density function for 0.25 nm FD SOI n-MOSFET's with VG = 0.5 V, VD = 1 V and tsi = 30 or 40 nm.

3.4.5. Linearity

Transistors biased in non-saturation SI conditions are used as tunable linear resistors in MOSFET-C continuous-time filters83. The major limitation of the technique lies in the generation of harmonic distortion (HD) because the MOS drain current is not a pure linear function of the drain/source voltages due to the body effect, mobility variations, etc. The balanced 2-MOSFET design (Fig. 14) has been introduced to cancel out the even-order HD terms in the case of bulk MOSFET's83. Nevertheless odd-order terms remain due in particular to the 3/2 power terms of Vs and VD present in an accurate drain current expression73. Simple models such as Refs. 1,62 predict complete suppression of odd-order

294


HD in FD SOI MOSFET's, a result that is obviously not achieved in real application. Model selection must then be very cautious in order to predict reliable linearity results. The EPFL model, which reduces in Si to an ID expression limited to the linear and squared Vj and VD terms, is certainly not adequate. We have used, in both SOI and bulk HD analyses, their more physical charge-sheet models71'73. We firstly focused the comparison on the linearity properties related to the body effect, excluding the impact of mobility variation, device mismatching, etc. Due to the complexity of the charge-sheet models, the dominant third-order HD term of the 2-MOSFET structure has to be estimated numerically performing a FFT of the difference of the currents flowing in two identical MOSFET's with identical VG and VD=VS=V0 DC biases but opposite low-frequency sinusoidal signals superposed to the input terminals (Fig. 15).

V 0 + V i n

Vo-Vino^

Fig. 15. Basic 2-transistor fully differential MOSFET-C integrator.

Input Swing (V)

Fig. 16. Linearity performance of the 2-MOSFET tunable resistor computed, for constant mobility, using the bulk charge-sheet model (—) with /„ = 30 nm, ty, = 3.2 1016 cm'3 and V,h - 0.7 V or the SOI charge-sheet model (—) with r„, = 30 nm, tob = 400 nm, ft = 80 nm, N„ = = 2.5 or 3.5 V and Vin is a 1 Hz-sinusoidal signal.

8.10'" cm'3 and Vlh = 0.4 V. In both cases, V0 = 1 V, V.

The 3rd order HD is presented in Fig. 16 as a function of the amplitude of the sinusoidal signal for different control gate voltages. A tenfold reduction of the body effect-related third-order HD is clearly observed when using FD SOI instead of bulk n-MOSFET's, especially at low tuning gate voltage and large input swing. The phenomenon

295


can obviously be related to the lower Vth and the reduced and almost linear body effect of FD SOI MOSFET's. This demonstrates the potential of FD SOI CMOS for applications requiring good linearity at low supply voltage and especially for MOSFET-C continuous-time filters, which have been proved to be the best candidates for implementing LVLP filters with optimal dynamic range84.

i 1 1 1 1 1 1 1 p

* • • • * ' — • • • • ' • • >

0.0 0.5 1.0 1.5 Amplitude (Vpk)

Fig. 17. Second- and third-order harmonic distortions in the drain current of bulk and FD SOI MOSFET's driven as resistors, with DC gate bias set 1 V above threshold voltage and DC source/drain set to 1 V in bulk, 0 V in SOI, as a function of the ac signal amplitude superposed to the source terminal.

Experimental evidence supporting the superiority of FD SOI over bulk MOSFET's regarding linearity properties is presented in Ref. 85 (Fig. 17).

3.4.6. The CMOS analog switch

The CMOS analog switch combining parallel nMOS and pMOS transistors with complementary inverted gate signals is a key block of sampled-data analog circuits (Fig. 18). A well-known problem of this structure is that the switch on-resistance increases when the supply voltage is lowered. It may even peak to very high values for mid-range input signals when VDD is decreased below a value which can be estimated by 2Vlt/(2-n), assuming identical threshold voltage and body effect parameters for n- and p-MOSFET's74. FD SOI CMOS featuring reduced values for" these parameters clearly allows for correct switch operation at much lower voltages than in bulk43 (Fig. 18).

/

Bulk

SOI

n V T vdd,min

1.5 0.7 3.0

1.1 0.7 1.7 1.1 0.4 1.0

J

Fig. 18. CMOS switch schematic and minimum VDD table computed from 2.VaJ(2-n).

« -20

3 -40

c o £ -60

-80

296


We have refined the analysis using the EKV model, with similar bulk and SOI parameter sets as above and minimal switch dimensions (i.e. (W/L)n = 1, (W/L)p = 2.5), in order to compute as a function of VJJ, first the maximum permissible threshold voltage which keeps the on-resistance below 50 k£2 (Fig. 19), then the resulting switch off-current (Fig. 20). A 50 k£i maximum on-resistance is a typical value corresponding to a maximum settling error of 0.01 % for a 500 kHz clock frequency and a 2 pF capacitance. We observe that the required bulk threshold voltages become extremely low for reduced VDD. The corresponding bulk off-current then exceeds the maximum admissible current, which limits to 0.01 % the relative error due to the discharge of the capacitance during the holding phase. Therefore we believe that low threshold bulk CMOS processes do not represent a viable solution for sampled-data analog circuits. Double threshold processes are required with charge-pump circuits to boost the switch gate signal above the supply voltage. On the contrary, FD SOI CMOS technology offers the simplest solution to the problem of the low-voltage CMOS switch, when using a threshold voltage of about 0.33 V compatible with both maximum on-resistance and off-current switch typical specifications for a supply voltage of 1.2 V.

3.5. High-temperature characteristics

Up to now, room temperature operating conditions have only been addressed whereas circuits will generally run at a higher junction temperature due to environmental issues or just self-heating. In particular, rapid burn-in tests for IC lifetime prediction are generally conducted at 125 °C. The present paragraph will compare the temperature dependences of bulk and SOI MOS transistors.

fc 01

8P o >

cQ b t

^ H

1.2

1

0.8

0.6

0.4

0.2

0 1.5 2 2.5 3 Supply voltage VD D(V)

Fig. 19. Maximum admissible symmetrical threshold voltage of n-/p-channel devices for minimal-dimension CMOS switch with maximum on-resistance of 50 k£2, as a function of VDD-

The drift of MOS transistor current-voltage curves with temperature significantly affects the correct operation of Si MOS integrated circuits. Typical static device characteristics (Fig. 21) clearly show that contrary to SOI, bulk Si MOSFET's present, above 200°C, drastically reduced ON-to-OFF current ratios and threshold voltage values which are not compatible with acceptable noise margins in digital circuits or with bias stability in analog circuits.

SOI Bulk

•

• •

x y

^ • •

+ •

• *

t ^

^ ****

* * s

• •

'

297


1.5 2 2.5 3 Supply voltage V D D (V)

Fig. 20. Bulk and SOI CMOS switch off-currents resulting from the threshold voltages of Fig. 19 as a function of the supply voltage. Also represented is the limit corresponding to a relative error of 10"4 due to the discharge of a 2 pF-capacitance during a 1 us-holding phase.

-2 -1 0

Gate Voltage (V)

Fig. 21. Drain current versus gate voltage curves of SOI (solid line) and bulk (dashed) 20/5 p-MOSFET's with Vo=3V.

Fig. 22. Simplified bulk Si MOSFET cross-section depicting depletion region extension (gray) under channel (dark) and total drain junction area contributing to leakage (large dashed line). Note that other source and well-substrate junctions could also contribute to leakage if reverse biased.

298


The increase with temperature of MOSFET OFF leakage currents (/;«,*), defined for OFF gate bias condition typically equal to 0 V, is related to the degradation of important MOS electrical parameters: the threshold voltage (V,/,), the subthreshold slope (5) and the reverse-biased junction saturation current (Ijs). These are linked to the increase with temperature of the intrinsic carrier concentration (n/) and of the thermal voltage (U, = kT/q). In a bulk Si MOSFET (Fig. 22):

• Vth decreases as the Fermi potential (ty) and the depletion width and charge under channel reduce with temperature.

• IjS is proportional to n, and the total bottom and sidewall drain junction area (AjD) below 150°C when generation mechanisms in the junction depletion region dominate, and is proportional to AjD and n,2 above 150° when diffusion mechanisms of excess carriers in the quasi-neutral transition regions become dominant.

The temperature behavior of a thick-film PD SOI MOSFET is very similar to bulk. Since the channel depletion region does not extend across the whole active film thickness, it changes with temperature modifying V,h and leaves a quasi-neutral region in the film contributing to junction leakage by diffusion mechanisms. However when the film is thin enough so that the junctions extend down to the buried oxide, A]D reduces to a single sidewall component proportional to the channel width (W) and film thickness (*„•) thereby drastically limiting Ijs. In a thin-film FD SOI MOSFET, the channel depletion extension being equal to the film thickness, it remains constant with temperature and V,h only depends on <j>f. Furthermore, as quasi-neutral regions are suppressed, only generation mechanisms may contribute to Ijs, which is now proportional to «/ and the depletion region volume, i.e. W.L.tsi where L is the channel length.

These basic physical behaviors are confirmed by measurements of IJs and V,h as a function of temperature, and performed on bulk and FD SOI MOSFET's (Fig. 23). It may be observed that:

• bulk Iis may be up to 1 uA/um of device width at 300°C, and almost three orders of magnitude lower in FD SOI;

• bulk Vth may shift by 2 to 5 mV/°C depending on doping, temperature86, etc., whereas FD SOI V,h only shifts by 0.7 to 1.5 mV/°C as long as the device remains fully depleted.

Indeed, as the maximum depletion width is reduced when temperature increases, there exists a critical point, typically between 200 and 300°C depending on device optimization, above which FD SOI transistors feature a bulk-like dependence of the threshold voltage and leakage current because the film becomes partially depleted87'88'89.

Three more problems of bulk Si CMOS structures1 related to leakage current and threshold voltage variations with temperature should be pointed out:

• previous data did not take into account the significant leakage current of the reverse-biased well-to-substrate junctions which are required to isolate e.g. n-MOS devices realized in the P-doped bulk Si substrate from p-MOS devices located in very large-area N-doped wells contacted to the positive supply voltage.

299

1186 D. Flandre, J.-P. Raskin & D, Vanhoenacker- Janvier

0 100 200 300 (°C) 0 100 200 300

Fig. 23. ljs and V,h evolutions with temperature for bulk (+) and FD SOI (o) MOSFET's (W = 20 Jim).

• the isolation of individual bulk Si MOSFET's also involves a thick field oxide structure which may give way to lateral parasitic transistors. Their threshold voltages are normally set much above the maximum supply voltage by field implantation, but this is usually not guaranteed for very high-temperature operation due to threshold voltage lowering.

• N-P-N-P thyristor-like parasitic structures and related latch-up problems are then unavoidable in bulk Si CMOS circuits. Latch-up may potentially be triggered at lower voltages for temperatures higher than at room temperature, due to the dramatic increase of thermally generated substrate leakage currents.

All these three process-related problems are totally suppressed by buried oxide isolation in SOI CMOS structures'.

The basic electrical behaviors previously described explain the unavoidable physical limitations of bulk and PD SOI CMOS digital circuits operated at high temperature. Measurements on bulk Si CMOS logic gates show leakage currents per elementary gate on the order of 1 uA at 250°C even though their design was fully optimized for high-temperature operation90'91. On the other hand, FD SOI CMOS logic gates demonstrate leakage currents per inverter lower than 10 nA at 300°C without any design optimization.

Similarly the measured standby currents of bulk Si and PD SOI CMOS 64 kb SRAM's92 increase with temperature following a n,2 dependency. The latter is almost two orders of magnitude lower than the former due to drain junction area reduction (Fig. 24). However extrapolating these values for a 1Mb SRAM of interest for future VLSI applications, we end up with a static power dissipation under 5 V operation larger than 1 W at 300°C even with PD SOI technology! This seems to definitely prevent the use of bulk Si and even questions PD SOI CMOS for VLSI integration at elevated temperature, contrary to FD SOI.

Furthermore, the lower temperature dependence of the FD SOI MOSFET characteristics is not only of interest for very high-temperature conditions above 200 °C, but also in the usual range of operation for IC rated up to e.g. 125 °C according to standard burn-in test conditions.

Also note that starting at 125-150°C, the leakage current in PD SOI MOS is already reduced by about one order of magnitude when compared to bulk.

Fig. 25 compares theoretically a conventional bulk CMOS technology with 0.7 V threshold voltage and 90 mV/dec subthreshold swing to a FD SOI CMOS featuring 0.5 V and 60 mV/dec values respectively, chosen for equal leakage at room temperature. At

300


125°C, both the bulk and FD SOI threshold voltages are lowered to approximately 0.4 V, but the better SOI subthreshold swing yields a leakage current figure more than one decade below bulk. Also note that low threshold voltage bulk CMOS results almost unpractical under such conditions.

64Kb 1Mb SRAM 1

10

10 >

0 in

®

10"

10

o PL, >-> c

CO

10" 150 200 250

Temperature (°C) 350

Fig. 24. Bulk Si and PD SOI CMOS 64 Kb SRAM standby current dissipation vs. temperature and extrapolation of standby power dissipation for 1 Mb SRAM under 5 V supply operation.

-4 vT.bult

- 0.5 - 0.3 V

= 0.5 - 0.1 V

V i i b u l k - 0 - 7 - 0 - ^ -

1 ' ' • •

0.5 1.0 Gate Voltage (V)

2.0

Fig. 25. Extrapolation of bulk and FD SOI MOS characteristics at 400 K.

This theoretical extrapolation has recently been demonstrated comparing the experimental leakage currents of 0.25 \im bulk and FD SOI MOSFET's which feature Ioff

values of about 20 pA/fim93 and 2.2 pA/u.m, respectively94. This may be of tremendous importance regarding the stand-by or static power dissipation of portable systems, as well as die possibility to run IDDQ testing methodologies for rapid production validation. Reciprocally, FD SOI CMOS circuits could be tested under more severe burn-in

301


conditions, approximately 50 to 75 °C higher than in bulk for similar leakage currents, leading to reduced testing time and costs by a factor of about X according to the classical Arrhenius law.

3.6. Conclusion

SOI CMOS can now be regarded as a very attractive and mature technology for the realization of low-voltage low-power (LVLP) digital ULSI circuits owing to a number of well-known advantages over conventional bulk Si CMOS:

• dielectric isolation provides reduced parasitic capacitances and leakage currents when compared to junction isolation.

• full-depletion (FD) operation of thin-film SOI MOSFET's may yield quasi-ideal device properties such as sharper subthreshold slope, lower body effect and smaller vertical field mobility degradation. Improved subthreshold slopes in turn allow for the use of lower threshold voltages for identical subthreshold leakage current values. These characteristics all add up to significantly increase the drive capability, in particular for reduced supply voltages.

• thinned films and dielectric isolation result in simplified submicron CMOS processes: threshold voltage roll-off is minimized, reliable ultra-shallow junctions are easily obtained, wells and latch-up are suppressed and complicated lateral isolation process can be avoided.

• the low temperature dependence of FD SOI MOSFET's drastically minimizes the increase of the leakage currents for typical ratings above 70-100 °C, thereby reducing the stand-by power consumption in this range of temperature or enabling rapid IDDQ or burn-in testing above 125 °C.

Regarding analog properties, available models for the important small-signal conductance and capacitance characteristics of fully-depleted SOI MOSFET's have been discussed and validated. These have been exploited to investigate the impact of the improved device characteristics of FD SOI MOSFET's, i.e. smaller subthreshold swing, body factor and parasitic capacitances, on the performances of several basic analog cells. We have found that:

• CMOS analog switches can still be operated at a supply voltage as low as 1.2 V when optimized in FD SOI CMOS.

• FD SOI CMOS has the potential to boost the speed, accuracy, power and area performances of 1- and 2-stage operational amplifiers well over bulk implementations, especially when moderate inversion operation of the active devices is considered, as is common in LVLP circuits.

• the linearity properties of FD SOI MOS resistors could be much better than those of bulk counterparts, which is of high interest for LVLP filter implementations.

By demonstrating the great potential of FD SOI CMOS for high-performance analog and mixed-mode analog-digital low-voltage low-power applications, this study has opened a whole new field of applications for this technology.

In the next sections, the analysis will be extended to microwave performances and finally applied to high-performance circuit design.

302

SOI CMOS TYansistors for RF and Microwave Applications 1189

4. Microwave Characterization of Passive Elements on the SOI Substrate

This section is devoted to the analysis and modeling of passive elements on SOI substrate, starting with a preliminary analysis of the behavior of the SOI substrate at high frequencies. This model is used afterwards for the transmission lines and integrated inductors.

4.1. High frequency behavior of the SOI substrate

The fundamental difference between the Si substrate and the GaAs substrate is the fact that the silicon resistivity is lower then the GaAs one, so that Si cannot be considered as a dielectric for microwave applications. The behavior of the substrate is a function of bias conditions and frequency and will be analyzed for the microstrip structure represented in Fig. 26.

The microstrip transmission line is considered as a quasi-TEM transmission line, the transverse lineic (i.e. per unit length) elements are a capacitor and a conductance accounting for the substrate losses. The behavior of the MIS (Metal-Insulator-Semiconductor) capacitor illustrated in Fig. 27, has been reported in the literature for some years. Some models are based on the behavior of the charges in the structure but most of them are limited to a few MHz, assuming that the majority carriers in the semiconductor are responding to voltage variations without delay95,96'97'98' 10°. The relaxation time of the majority carriers is neglected. On the other hand, some authors had a special interest in the distribution of electromagnetic fields in planar lines on semiconductor substrate. Hasegawa101 defines three fundamental modes in such structures:

• the dielectric quasi TEM mode • the skin-effect mode • the slow-wave mode.

I Metal

Sl(»,

Si suhMiaie

Ground plane (metal) J

Fig. 26. Cross section of a microstrip transmission line on SOI and its equivalent transverse lineic elements.

He develops for each mode a lineic equivalent circuit RLCG. Various authors102'103'1041"5'106107108 have studied the propagation characteristics of the slow wave mode. In order to fully characterize the various types of transmission lines on SOI, a complete study of the "MOS capacitor" is necessary, taking into account the carrier

><3

303


transport mechanism as well as the repartition of the electromagnetic fields in the substrate. The geometry of the "MOS capacitor" is represented in Fig. 27.

Fringing effect Fringing effect

(a) (b)

Fig. 27. (a) Electric field in the cross-section of the microstrip line and (b) equivalent capacitive structure analyzed, with elements of the equivalent circuit, per unit length.

4.1.1. Simulation of the MOS capacitor

The capacitor analyzed can be considered as the lineic capacitor of a section of microstrip line. The boundary conditions are those of an ideal capacitor: perfect electrical conductor (CEP) for the metal and perfect magnetic conductor (CMP) for the vertical limits, neglecting the fringing fields, even if the thickness is of the order of magnitude of the size of width of the upper conductor. The purpose of this calculation is not to obtain the exact value of the capacitor but to properly model the evolution of its value with frequency and polarization.

The 2D-MEDICI simulator109 is used to analyze this structure. It models the 2-dimensional distributions of potential and carrier concentrations in the device, in order to predict its electrical properties for any bias conditions. MEDICI is also capable of performing an ac small-signal analysis calculating the frequency dependent equivalent capacitance and conductance per unit length.

Fig. 28 shows the small signal capacitance of the SOI capacitive structure, for a unitary surface, a Si substrate thickness dsi = 500 um, an oxide thickness dox = 1 urn under various bias conditions and for various frequencies. The substrate is assumed to be highly resistive (p„ = 4000 £2cm). The results obtained are in agreement with the classical theory widely explained in the literature, but the drop out around 1 MHz is not described in the classical theory100.

When a metal-insulator structure is brought into contact with a semiconductor surface (a p-type silicon substrate in this case), an accumulation, depletion or an inversion region is formed just below the semiconductor surface, depending on the surface potential. This surface potential depends on many parameters, including the metal-semi-conductor work function difference, fixed charges, mobile charges, interface charges, hot electron/hole charges, dox and the voltage applied to the metal.

304


Capacitance of SOI capacitive structure [uF/m2] 40i

inversion

N^S.lO^cm"3

-6

deep depletion T^ A A A—A—A

dielectric mode s>*~*—• • • — • " — • • — • — • • • • ' » dielectric mode ? o 0 | 0 o " p o o p

-2 0 2 dc Bias Condition [V]

Fig. 28. Small-signal characteristics of SOI capacitive structure versus applied dc voltage for various frequencies, d0I = 1 (im, ds, = 500 |im and psi = 4000 Q.cm.

The classical theory explains the low frequency curves: • for positive bias conditions, there is an abundance of electrons below the

oxide. For a p-type substrate, this is called an inversion layer. At low frequencies, the minority carriers follow the excitation. This is not the case anymore when the frequency increases (see Fig. 28 in the kHz range). The inversion layer charge cannot keep up with fast variations of the voltage and the required charge changes are provided by covering or uncovering acceptor atoms at the bottom of the depletion region, just as in the case of depletion operation. When the frequency increases above 1 kHz, the inversion layer cannot follow the variations because it is isolated from the outside world. Thermal generation and recombination only can change its electron concentration; those phenomena are very slow.

• for negative bias conditions, there is an abundance of holes below the oxide (accumulation), forming the "bottom plate" of the capacitor. As a consequence, the total capacitance is approximately equal to the oxide capacitance.

The 2D-Medici simulator gives results in agreement with the above-mentioned theory for low frequencies. It however takes into account the distribution of the potential and the carrier concentration, as well as their evolution with frequency, so that the simulation shows a rapid decrease of the equivalent capacitance for positive and negative bias conditions, at frequencies above 1 MHz. A further decrease happens between 1 MHz and 1 GHz. The section below will briefly explain the behavior of the capacitive structure versus the relaxation time of the carriers.

305


4.1.2. Influence of the relaxation time of the minority and majority carriers on the parameters of the MOS capacitor

The relaxation time of the minority carriers expresses the inertia of the inversion layer under the oxide layer. For a p-type substrate, the minority carriers are the electrons. Three sources can supply minority carriers to the inversion layer: an electron diffusion current from the bulk silicon, a volume generated current within the depletion region or a surface generated current directly related to the surface states at the insulator-semiconductor interface. Sah et al"°. have demonstrated that the finite generation-recombination within the space charge region is the dominant factor controlling the frequency response of the inversion layer. The generation and recombination of electron/hole pairs carry out the charging and discharging of the inversion layer through traps in the depletion region. These traps may be crystal lattice dislocations, impurity atoms located interstitially or substitionally in the crystal lattice, or surface defects. Hofstein and Warfield96 define for the strong inversion layer regime, a resistance Rgr associated with this generation-recombination:

Rgr=^h (16)

where \j/s, X& n, and x0 are, respectively, the surface potential, the thickness of the

depletion region, the density of electrons or holes in an intrinsic semiconductor, and the

time carrier density fluctuation to decay to its equilibrium concentration by recombination

through traps. This lifetime is typically the order of 10"6 sec. This equivalent resistance

allows taking into account the frequency response of the inversion layer. The relaxation

time of the minority carriers is given by Tgr = RgrCb, where Cb is the capacitance

associated to the depletion region under the oxide layer. The simplified equivalent circuit

for SOI capacitive structure represented in Fig. 29 is valid in the strong inversion regime.

The limits of the equivalent capacity Cgb are Cgb —> Cox for co«x~gr and

C + C Cgb —» —^ — for co > r~ . In weak or moderate inversion and in depletion regime

CoxCb

C C this model is not valid for co « T~r

]. Cgb tends to — o x c with Cc - C, + Q,. Cox + Cc

Tsividis104 gives a general expression of Cc valid in all regimes.

The depth of the depletion layer depends on the substrate doping, so it is with the capacitor Cb. As a direct consequence, the relaxation time of the minority carriers depends strongly on the substrate resistivity: the minority carriers react up to higher frequencies for higher resistivity silicon substrates.

The inertia of the majority carriers is often neglected in the literature. The 2-D Medici simulator however shows that this hypothesis is not valid anymore for frequencies higher than a few MHz. When frequency increases up to GHz, neither minority neither

306


majority carriers follow the variation of the applied potential. The silicon substrate is then considered as a dielectric with losses. The final model for inversion mode, taking into account the minority and the majority carrier inertia, is represented in Fig. 29; Csi and Rsi

represent the inertia of majority carriers.

T

Oxide layer

Minority carriers inertia

Majority carriers inertia

Fig. 29. Complete model for capacitive structure valid for inversion mode.

Measurements have been performed up to 500 MHz, to check the validity of the model (Fig. 30). The measured capacitor has been made on a SOI wafer with an oxide thickness of 0.4 u\m and a silicon substrate thickness of 500 urn. The capacitive structure has an area of 900x1200 um2.

100 C „ inversion • O Model

Measurements

ilr iimffiiiil ^— 0

Frequency [Hz] (a)

307


< y c „ c „ + c f c

60

8 40H

o at

u

deep depletion

• O Model Measurements

20

0 " l u m p i n g W«ii| unthj iiinlif iiiiiii|Ti«nl| iiniij niiiij mffij 1111" 0 4 6

10 10 li Frequency [Hz]

10 2 4 6 S 10

10 10 10 10 10

(b)

Fig. 30. Measured and simulated equivalent capacitance and conductance of a SOI capacitive structure with substrate resistivity of 200 Qcm (a) and 8 Qcm (b), for DC bias of 2.5 V, d0^= 0.4 um, ^,=500 um and an area of 900x1200 umJ.

Measurements have been performed for two wafers of different resistivity: 8 Qcm and 200 Qcm. The agreement between the model and the measurements is very good.

The final step is then the evaluation of the equivalent permittivity of the silicon substrate. The interfacial relaxation theory of Maxwell-Wagner111 evaluates the equivalent permittivity of a multi-layer structure, each layer being represented by an equivalent C,G (=1/R) circuit.

Complex permittivity 2000

1500-

1000

-800

- 6 0 0

8 1000

500-

- 4 0 0

-200

Frequency [Hz]

Fig. 31. Complex permittivity of SOI substrates versus frequency, for resistivity of 20 and 4000 Qcm.

308


Fig. 31 represents the complex permittivity for the SOI substrate, taking into account the inertia of the majority carriers. Having a model for the equivalent permittivity of the SOI substrate, it is then possible to develop a model for transmission lines.

4.2. Coplanar transmission line

Having described the evolution of the real and imaginary parts of the permittivity with frequency, it is then possible to calculate the parameters of transmission lines on SOI. Two types of transmission lines are generally used: the microstrip line and the coplanar waveguide structure. Due to the fact that all the conductors are on the same plane, the coplanar waveguide is more suitable for measurement. The structure of the coplanar waveguide is shown in Fig. 32. With a central conductor of 50 u.m and gaps of 30 urn, the represented line is designed for a characteristic impedance of 50 £2 at high frequency, considering the substrate as a dielectric.

30 (im 50 |xm 30 fira

X

oxide

silicon substrate

1 urn

500 jim

Fig. 32. Cross-section of CPW transmission lines on SOI substrate.

The coplanar waveguide can generally be considered as a quasi-TEM (Transverse Electro-Magnetic) line112, in spite of the presence of three different dielectric layers: air, silicon dioxide and silicon for the mechanical substrate. The presence of high losses in the dielectric but also in the thin metallic layer, will of course introduce an imaginary part in the propagation coefficient but also in the characteristic impedance of the line.

The existence of three fundamental modes in the metal-insulator-semiconductor structure has been reported some years ago in the literature101'105. These three modes are the dielectric quasi-TEM mode, the skin-effect mode and the slow-wave mode. The propagation of these modes depends both on the semiconductor losses and the frequency range. The behavior of the MIS structure being known, various authors have presented analyses of lines made on MIS. The full wave method for planar lines is often used but requires several tedious numerical iterations and summations in case of thin films ' and/or high loss substrate115'116. For this reason, some authors113114117118 developed asymptotic formulations for the Green function involved in the spectral domain approach. This requires an in-depth study of the asymptotic behavior of the Green's functions for each kind of multilayered structure. Other authors102,119 developed quasi-TEM models based on the extraction of the R, L, C, G elements of the transmission line from measured data, hence limiting the validity of the model.

309


In order to have a model convenient for low resistivity silicon, an explicit variational principle has been used to calculate the propagation coefficient of the coplanar waveguide . This formulation is well suited for planar structures with very thin layers and losses. This method has been validated by measurements. Fig. 33 shows the measured and calculated real part of the characteristic impedance of the line.

0 5 10 15 20 Frequency [GHz]

Kg. 33. Simulated and measured real part of the characteristic impedance as a function of frequency for coplanar waveguide transmission line, on a standard 20 iicm (a) and high-resistivity 200 Qcm (b) substrates.

This figure shows a good agreement between the model and the measurements but also the fact that, for low resistivity substrate, the characteristic impedance strongly varies with frequency in the range 1 to 10 GHz. Fig. 34 shows the modeled and measured real and imaginary parts of the propagation coefficient for the same transmission line, on both substrates.

0 5 10 15 20 Frequency [GHz]

fig 34. Real part of the characteristics impedance (a), transmission coefficient and losses (b) of a coplanar line on low resistivity (20 iicm) and high resistivity SOI substrate (200 Qcm).

310


The losses are very important on the 20 Qcm substrate, so that it is important to use high resistivity substrate. Looking at the imaginary part of the propagation coefficient, its evolution with frequency is linear for 200 Qcm substrate, as predicted for TEM lines, but departs from the linear TEM behavior 20 Qcm substrate. This will give rise to dispersion and distortion.

The variation of the characteristic impedance has to be taken into account because S-parameter measurements are referred to the characteristic impedance of the transmission lines at the ports of measurement. This problem will be handled in the next section.

4.3. On-wafer calibration

In the microwave domain, the passive and active elements are characterized by S-parameters, more suitable than Z or H parameters in that frequency range. The Vector Network Analyzer (VNA) generally used for the measurement is representing the S-parameters in a reference impedance of 50 Q. It is necessary to calibrate the VNA, in order to put the reference planes as close as possible to the element to be measured. The usual calibration method used for planar structure is the Through-Reflect-Line (TRL) method121, using custom standards implemented in-situ, on the test wafer. However, after a TRL calibration, the reference impedance if the measured S-parameters are equal to the characteristic impedance of the transmission line used in the calibration ("Line").

Through Open Short Resistor

Line

Fig. 35. Calibration kit used for TRL on-wafer calibration and characteristic impedance determination.

In the case of coplanar lines on SOI with low resistivity substrate, it has been shown (Fig. 33) that the characteristic impedance of the line varies strongly with frequency in the frequency range of the measurements (40 MHz-40 GHz). Due to the difficulties to predict accurately this characteristic impedance, it seems reasonable to measure it during the calibration procedure. It is then necessary to add one more calibration element.

The calibration kit is represented in Fig. 35; it contains a "Through", an "Open" used for "Reflect" element, and a "Line". The "Short" and the "Load" are used for the determination of the characteristic impedance following a method developed at the Microwave Laboratory123. The probe pads are clearly visible on each of the calibration

311


structures. After the calibration procedure, the reference planes of the two ports are coinciding, just in the middle of the "Through" structure.

The characteristic impedance of the line is extracted using a thin film resistance ("Load") whose impedance lays around 50 Q (Fig. 36). It has been shown by Walker12 , that the intrinsic resistance of a thin film planar resistor can be reasonably considered not to vary with frequency from DC to 40 GHz. The parasitics involved are however frequency dependent and have to be measured.

SiO,

V Thin film resistor

!4=rr- rSgrj.

Si substrate

(a) (b)

Fig. 36. Thin-film planar resistor used for the measurement of the characteristic impedance of the coplanar waveguide, (a) Layout (b) Cross-section.

The model proposed here generalizes the one presented by Walker : a parallel admittance and a series impedance take into account the parasitic effects (Fig. 37).

T* U %

z«

Fig. 37 Equivalent circuit of the thin film resistor.

The parallel and series elements are evaluated by measuring the open and the short of the calibration structure, the environment of those two elements being similar to the one of the thin film resistor. The open gives the parallel admittance Yn and the short gives Y„ and Z<j in parallel. The absolute value of the intrinsic resistance Rj can be deduced at DC from resistance measurements of the three devices and at high frequencies, the value of the resistor, normalized to the characteristic impedance (r,) is extracted from S-parameters. Finally the characteristic impedance is deduced by evaluating /?/r,. This method has been validated by comparison to the method of Marks and Williams , using a series of lines of different lengths and to the numerical prediction of Heinrich . The agreement is very good, within 3% in the whole frequency range. This new method has preferred to the one of Marks and Williams due to the lower number of calibrating elements.

Having the characteristic impedance, it is then important to correct for the difference between the actual impedance and 50 Q. This correction is far from negligible as shown in Fig. 38. The curves in black represent the Su and S22 curves before taking into account

312


the variation of the characteristic impedance and the gray curve show the same parameters after correction for the variation of the characteristic impedance and scaling to a constant 50 Q value, as usually when represented on a Smith Chart.

Fig. 38: Smith Chart representation of Sn and S22 parameters of a SOI transistor, before (black) and after (grey) correction for the variation of the characteristic impedance of the coplanar lines.

4.4. Spiral inductor

Spiral inductors are widely used in MMICs for wireless applications. Inductors with high quality factor are needed for the design of local oscillators and tuned RF amplifiers, but also for the optimization of low noise amplifiers. The classical RF and microwave models available for the integrated inductors are of various types. Full-wave electromagnetic simulators are based on 2D or 3D modeling of the element and use a spectral domain approach127, the method of moments128, the method of lines129 or a finite element method130. The computation time however is reported to increase with the number of turns and the ratio of line width to line spacing, and becomes rapidly too large for on-line design and optimization. MMIC's designers often use lumped element models, due to reduced computer time and facility to introduce it into a commercial simulator. The parameters of the equivalent circuit are evaluated mathematically and validated by measuring a series of inductors of various geometries. However, these models suffer from various limitations: they are not valid above the resonant frequency, they are generally scalable versus some parameters, and they are accurate for the technology, the type of substrate, the range of dimensions of the measured inductors, and the frequency range of the measurements. Models found in the literature have been implemented to check their validity and to compare with the new model developed at the Microwave Laboratory.

4.4.1. Model of Liao

Liao131 developed a semi-empirical formula for the inductance:

313


L= 8.5 JAN5'3 (17)

with ^ — A*o» ' '-•htot

U,tot and Lhlot are the overall length and width of the spiral, respectively; N is the number of turns of the inductance.

4.4.2. Model of Croh

Crols has proposed a formula for inductors integrated on silicon 132.

L = 1.310 -7 Lhlot I Ltotws

V V ws [ LfuotLvu

w. xl/4

w,+s (18)

where ws is the width of the strips, Lto, is the total length of the strips, s is the gap between the strips.

4.4.3. Semi-empirical model

Ronkainen et al.133 have developed a semi-empirical model for inductors on silicon:

Ls=l.5n0N2De-31^-l^+s)lD

with d = max{Lhto„Lvtol)

Ho the permittivity of vacuum (4J I10 7 )

N, ws and s as defined above.

/ \0.1

\W>J

(19)

4.4.4. Model of Yue

The model of Yue134 gives a full equivalent circuit for an inductance with the output grounded. The parameters of the inductance are represented in Fig. 39. There are no limitations given by the author. The value of the inductance is calculated by using the Greenhouse algorithm135.

Fig. 39. Equivalent lumped circuit of an inductor integrated on SOI.

314


1) Model for the ohmic losses

The series resistance Rs of the spiral with underpassing strip takes into account the skin depth of a conductor with finite thickness and the current distribution in a microstrip conductor:

*.=4= (20) ' _wA-e-'s') Wu{\-e-'»'s»)

with Sm - j2pm/oofi , pm is the metal resistivity at DC, Sm is the metal skin depth, t is the

thickness of the metal layer, / is the overall length of spiral, ws is the strip width, tu is the

metal thickness of the underpass layer, lu is the length of the underpass between centre of

spiral and the output access and W is the width of the underpass.

2) Model for the parasitic capacitance

The parasitic crossover capacitance Cs between spiral and the underpass strip is approximated as a parallel-plate capacitance by:

C=nw.WuÊs. (21)

where n is the number of crossovers between spiral and underpass and doxMP is the oxide thickness between spiral and underpass.

3) Model for the substrate effect

The expressions of parasitic elements for an inductor realised on SOI substrate are derived from the relations given by Yue. The parasitic capacitors and resistance of the SOI substrate are expressed by:

C „ = I / w , S £ « (22) 2 d„

Csi=LlWsMjL (23) 2 dsi

Rs.=2£i!^L (24) lws

where / is the overall length of spiral, ws is strip width, do% is the oxide thickness between

spiral and substrate, psi is the silicon substrate resistivity. Finally, the equivalent parallel admittance elements Rp and Cp are obtained

respectively from the real and imaginary parts of the admittance resulting from the series connection of oxide capacitance Cgx with the complex admittance WR + j<QCsj) modelling

the silicon substrate effect.

315


4.4.5. Model of UCL

It can easily be verified that the method of Yue yields spurious resonances in the frequency behaviour of the extracted elements. Those resonances occur at frequencies where the spiral length is a multiple of a quarter wavelength. Around those frequencies, the correspondence between the transmission line infinitesimal elements and the equivalent circuit with one access grounded is not valid anymore.

A transmission line model has been developed by the Microwave Laboratory, UCL135. The main advantages of this model are a direct link with the geometry of the inductance and with the electric and magnetic properties of the substrate. The inductance is modeled as a combination of sections of coupled microstrip lines and for that purpose, it is divided in groups of coupled microstrip lines whose S parameters are calculated with the method used for the evaluation of single line parameters. The Y-matrix of each section of coupled lines is then calculated by straightforward matrix conversion. All the matrices are then connected together to form the inductance (Fig. 40).

The comparison between model and measurements showed that the model overestimates the value of the inductance. This is partly due to the fact that the groups of coupled lines only take into account the lines on the same side of the spiral (positive mutual inductance) and totally neglects the lines being at the opposite side of the spiral (negative mutual inductance). This effect has been added in the final model and the performances are improved.

(a) (b)

Fig. 40. Model for the integrated inductances: (a) sections of coupled lines (b) connection of the admittance matrices of the coupled lines sections.

316


4.4.6. Comparison of the models

The various methods described above have been tested on a set of inductances of various geometries. The results are shown in Table 2. Concerning the value of the inductance, the model of Yue is very accurate and can be used in SOI. This model has however some difficulties in predicting the resonance frequency when the total length of the inductance strip approaches a quarter wavelength. In that case, the lumped nature of the model has limitations and it is necessary to use a transmission line model.

Label

35T 45TS5 45TEH10 45TEH30 55T 45TL

W(um)

10 10 10 10 10 10

S(um)

1 5 1 1 1 1

N turns

3.5 4.5 4.5 4.5 5.5 4.5

E»(um)

50 50 90 70 50 141

Eh(nm)

50 50 10 30 50 141

Liao model

L(nH) 0.89 1.90 1.55 1.58 2.54 2.54

F,(GHz) 70.6 35.9 46.4 45.9 32.4 36.3

Crols model

L(nH) 2.16 6.25 3.88 3.79 5.84 9.27

F,(GHz) 29.1 10.9 18.5 17.9 14.1 9.9

Yue model

UnH) 1.52 2.8 2.3 2.55 4.05 6.74

Fr(GHz) >40 30 31 30.5 20.5 19

Ronk. model L(nH) 1.929 5.502 4.466 3.6 4.954 7.4

UCL final model

UnH) 1.8 3.2 2.56 2.94 4.5 --

Fr(GHz) 36 30 30 27 21 -

Measurements

L(nH) 1.66 2.91 2.53 2.74 4.15 6.82

Fr(GHz) 37.2 28.4 26.9 25.9 19.1 11.9

Table 2: Comparison of the various models on a subset of inductors.

The positive and negative coupling is taken into account in the Yue model, which explains its good accuracy in the evaluation of the inductance value. The new model developed by UCL predicts the resonant frequency with a good accuracy, is able to calculate inductances on substrates composed of various layers, lossy or not, and to take into account the geometrical parameters of the spiral. It is not linked to a particular technology.

5. Deep-Submicron DC to RF SOI MOSFET Macro-Model

5.1. Introduction

Thin-film short-channel SOI MOS technology appears to be a good candidate for low-power microwave circuits because of its excellent performance in terms of gain, speed and cutoff frequency137138'139. Therefore, there is a need for an accurate submicron RF SOI MOSFET model with adequate non quasi-static extensions for designing RF circuits.

Very little work has been done in RF SOI MOSFET modeling. Furthermore, even in bulk MOSFET modeling, the RF extensions presented so far have a very limited accuracy. The present standard bulk MOSFET models for circuit simulation, such as BSIM3v3, are not accurate enough in high-frequency operation140, because they include neither the extrinsic elements, nor the intrinsic non quasi-static effects (which arise because of the channel propagation delay), and because of their poor fitting and scaling of the intrinsic

317


device transconductance and output conductance, which critically affect the gain and the S-parameters. As a result, these standard models can be used only for frequencies up to a few GHz140141, and with the restriction of a small range of channel lengths and bias conditions. In a recent work an effort has been done in order to account for the intrinsic non quasi-static effects by introducing a distributed channel resistance seen from the gate ; however, this approximation requires the use of an additional fitting parameter, the final expression of the resistance has to be evaluated numerically and furthermore, it cannot be used in large-signal analysis. The model presented in Ref. 143 accounts for non-quasi-static (NQS) effects by using a voltage controlled current source in parallel with the intrinsic capacitances and admittances; the additional transadmittances are calculated from first-order expansions. However, again, this model is only valid for small-signal analysis only.

The model we present in this section can be applied for both small and large-signal analysis. In our circuit model, following Tsividis100, we split the transistor into three shorter transistors in series along the channel length (Fig. 41); this technique automatically takes into account the channel delay propagation effects. An accurate quasi-static intrinsic model is used for those shorter transistors144. This DC model is an extension to the deep-submicron range of our previous unified and charge-based fully-depleted SOI MOSFET model. Then, we combine our intrinsic model with a complete model for the extrinsic part of the device, with scalable equations for its components and which includes an additional lumped capacitance, which is necessary in order to properly account for the effect of the distributed gate resistance on the phase of the S-parameters. A similar technique was used in Ref. 145 for bulk MOSFET's with channel lengths longer than 0.35 um. However, in this reference the device parameters were extracted for the sectioned channel length, by global optimization. In this model, all but two of the parameters, the ones which control DIBL (Drain Induced Barrer Lowering) and the charge sharing, are independent of the number of channel sections and can be extracted using the DC model with just one section.

Gate

Fig. 41. SOI MOSFET split into 3 sections along die channel length.

We validated the complete proposed macro-model by comparison with the measured current gains, Maximum Available Gains (MAG's), and the modules and phases of the S-parameters for fully-depleted SOI MOSFET's with effective channel lengths down to 0.16 u.m and for frequencies up to 40 GHz.

318


5.2. Model Description

5.2.1. Extrinsic Part

This new model is based on the equivalent circuit shown in Fig. 42. This equivalent circuit is an enhancement of our previous one146, in order to include all the extrinsic capacitances which represent the coupling effects between gate, drain and source metallization levels (Fig. 43a), excluding the line access parameters (e.g. series inductors), which do not depend on the device size (but circuit design). For simplicity, we consider one finger of width equal to W.

c—r-1 -ww-cei

Intrinsic Bi

MOSFET

Si

—|—Cfe* —i— C VI

X> 3

C/3

"1

Fig. 42. Complete equivalent circuit topology for a SOI MOSFET CAD model.

The exact distributed nature of the gate resistance is accounted for by performing a careful small-signal analysis. The small-signal propagation effects along the gate width (Fig. 43b) can be accurately modeled by inserting an effective resistor, R , in series with

the gate terminal, and an effective capacitor, C e, in parallel with R e. The values of both

elements are proportional to the gate width. Rge and Cge arise from the first and second order terms, respectively, of the Taylor expansion of the admittance expression. The value of 7?^ is found to beRge =^„,,/3139 (where Rlotis the total gate resistance, Rlot =Wppoly,

Ppoiy being trie polysilicon gate resistivity and W the gate width), and the value of c is

determined as Cge ~Cg/5 (where Cg is the total gate capacitance)141. Many models do not

consider the lumped capacitor c „ ; however it critically affects the values of the phase of

the S-parameters. In this model, for the extrinsic part of the device, we consider the geometry

dependence of all elements. The extrinsic source and drain resistances affect the power gain of the device and should be accurately modeled. Assuming that the main contribution comes from the resistance of the diffusion region, the resistance at the source or drain is evaluated as: RXe =Ldiffrdiff IW, where Ldiffis the diffusion length and rdiff is the

diffusion sheet resistivity. rpoiy and rd\g are extracted directly from S-parameters measurements as explained in the next section.

319


There are several components of the extrinsic gate-source and gate-drain capacitances (Fig. 43a). Cgse and Cgde are the overlap gate-source and gate-drain capacitances. Q « corresponds to the proximity parasitic capacitance between the drain and source diffusion regions, partly accounting for the effect of the back gate (assumed floating in our RF equivalent circuit) too.

-.. .~ ^ Gate porysilicon W

(b)

Fig. 43. (a) Cross-section of the SOI MOSFET showing'the extrinsic capacitances and (b) top view of one gate finger indicating the distribution of the gate resistance along the transistor width.

These three capacitance elements, Cgse, Cgde and Cdse can be assumed to be proportional of the finger width. Cgsee, Cgdee and Cdsee are the extrinsic capacitances due to parasitic couplings between metallic interconnection lines outside the transistor active zone between gate-source, gate-drain and drain-source, respectively.

5.2.2. Intrinsic Part

In order to account for the channel propagation delay effects, the channel of the transistor is split into several smaller sections along the channel length where quasi-static conditions can be fulfilled and a quasi-static model can be applied. This approach is also valid for large signal simulation. Regarding delay effects, the accuracy of the model becomes better

320


by increasing the number of these smaller transistors, but the computation time also increases. Furthermore, the DC equations must remain valid for the smallest subsections, which may be hard to achieve for section lengths below 0.05 Jim. A tradeoff between accuracy and computation time is thus necessary. We have found that the splitting of the channel into three sections is a good choice. In each transistor we use the expressions of the quasi-static drain current and charges given by a new submicron fully-depleted SOI MOSFET model we have developed. This model is an extension of our previous model144'146 to the deep-submicron regime, and it has been validated for channel lengths down to 0.16 |im. The model looks very adequate for the RF equivalent circuit, because it has the advantages of being physics-based, scalable, charge conserving and infinitely continuous through all operation regimes, and accurately predicts the values of the intrinsic DC, small and large signal parameters. The drain current and charge equations are written in terms of continuous expressions of the inversion charge densities at the source and drain ends of the channel; therefore, the same parameters can be used in all the equations. The most important short-channel effects are included using continuous equations: velocity saturation, channel length modulation, charge sharing and DIBL. We also account for relevant effects in deep-submicron technologies, neglected in standard models: quantum effect on the effective gate oxide thickness147, short-channel effects in the charges, impact ionization at high lateral fields and adequate scaling. This is of great importance to allow channel splitting into sections of lengths smaller than 0.1 urn. Only two parameters (the ones that model DIBL and charge sharing) have channel-length dependences and therefore, they have different values for a different number of sections. This model has been implemented in the ELDO circuit simulator and tested by simulating some benchmark circuits.

In the quasi-static model, the drain current is written as:

h = W an

Leff x | Hn(<lnf[d-<inf,s)

r , I \ VnfJ VT{<lnf,d-<lnf,s)-- —

wlf.d-qlf.s) 2ac. oxf

acoxfêffvsat

(25)

where Leff is the effective channel length (including its reduction by channel length modulation), coxf is the front gate oxide capacitance, q„p and q„fj are, respectively, the inversion charge densities at the source and drain ends of the channel, UT is the thermal voltage, vsal is the saturation velocity, a is the body effect parameter (which is fairly constant in fully-depleted SOI), jU, is the effective mobility expression (which includes degradation by normal fields).

We use continuous expressions for qnfs and q^j which tend to the desired expressions:

in weak inversion: 1nf,s " -ôxf^j exp Vgfs-V,h

riU7

Inf.d = -1coxfriUT exp VG/S •W DS

T]U7

(26a)

(26b)

in strong inversion: 4nf,s=-coxftyGfS-Vth)

Inf.d ~ -CoxfiyGfS -V,h -aVDSE)

^7a)

(27b)

321


where VGjs is the front-gate-to-source voltage, Vth is the threshold voltage, VDS is the drain-source voltage and rj is the subthreshold ideality factor. We use a smoothening function for the effective drain-source voltage, VDSE . which gives VDS in the linear regime and the saturation voltage in the saturation regime; the latter depends on the saturation velocity.

The expression of the threshold voltage includes the charge sharing and DIBL with their channel lengths dependencies (to the first order):

V -V dvM aD'BL 1/ (78") vth - vth0 7 7 VDS *••">/

where Vlh0 is the long-channel zero-drain bias threshold voltage, dvM accounts for the

charge sharing effect and aD/BL accounts for the DIBL effect.

The total charges are obtained by integrating the charge densities along the channel. Analytical expressions are obtained as functions of qnfiS and qnfj. The intrinsic capacitances are obtained by differentiation of total charges with respect to the applied voltages.

When we split the device into several sections, we apply the above equations of drain current and charge to each section. This means that we define a source and a drain for each section, which correspond to the two ends of the section. In each section end, we consider a channel charge density. Therefore, the expressions of the current and charges in each section have the same form as in a real transistor, but they are written in terms of the channel charge densities corresponding to the source and the drain defined for each section (these are now qnfj and q„fj), which in turn, depend on the front and back gate voltages, and the voltage difference between the drain and the source of the section. It is the simulator, by iteration, which obtains the values of the voltages between the section drains and sources. However, note that the drain of the section next to the source, the source of the section next to the drain, and the source and the drain of the middle section are artificial sources and drains; this implies that the parameters defined for these sections do not follow the scaling rules in the same way as a real transistor. Therefore, parameters dvM and aDIBL will not have the same parameters in these sections as in a real transistor of the same channel length.

By definition, the total gate capacitance cg, used in the calculation of the lumped

element cge, includes both the extrinsic and intrinsic gate capacitance elements.

However, in order to use our equivalent circuit in a circuit simulator it is necessary to derive cg in a closed-form expression. For simplicity we have made cg equal to the total

extrinsic gate capacitance. We have proven that this approximation gives a sufficient improvement of the S-parameters phase values under all practical bias conditions.

5.3. Extraction Procedure

5.3.1. Intrinsic Part

The parameters of the model used for the intrinsic transistors are extracted under DC conditions by combining direct algorithms with global optimization144. In Fig. 44a and b, we show comparisons of the measured and modeled DC characteristics (drain current

322


versus VGS and VDs) for deep-submicron transistors. These transistors come from a 0.25 |im process developed at LETT, Grenoble, France138. The front and back gate oxides are, respectively, toxf = 4.5 nm and toxb = 400 nm. However, because of the quantum effect,

it is necessary to consider in the model an effective oxide thickness, tOXfeff, which is larger than the real one, since the distance between the channel and the interface is not negligible compared to the oxide thickness. This quantum effect has been confirmed by RF measurements of the gate oxide capacitance, from which we have extracted the value of the effective oxide thickness (t0^,eff= 5.8 nm)148. The Si film thickness is tb = 30 nm. The

transistors are composed of 16 fingers of 6.6 urn width (W) each connected in parallel.

14

VGfS = 0.9V

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

Drain Voltage [V]

(a )

c 8 u i— 3

<-> 6

• Lefr=0.16 nm x Leff=0.26|im a Leff=0.41 nm

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 Gate Voltage [V]

(b) Fig. 44. Comparison of measured (symbols) and modeled (a) ld-Vos and (b) /d-Vq/s of a SOI nMOSFET with L,j = 0.16 urn. Solid line: three-section model; dashed line: one section model.

When we split the transistor into three shorter transistors, a few parameters related to the short-channel effect have to be changed in order to obtain the same I-V c :jtics of the single transistor. The standard scaling rules cannot exactly be applied to these

323


shorter transistors, since it is just the transistor closest to the drain, which comprises most of the longitudinal field effects. The transistor closest to the source and the one in the middle have a more "long-channel" behavior despite they may be very short. As a result, we only consider the DIBL effect in this drain-side transistor and neglect it in the other two transistors. The charge-sharing effect does not depend on the longitudinal field. However, the scaling rule of the charge-sharing in the real transistor should not be followed in these shorter transistors and we observed that in each section the reduction of threshold voltage because of charge-sharing is smaller than for the single transistor; the charge sharing is modeled in the three transistors using the same parameter value for all of them. Anyway, because of the physical basis of the model, these two parameters are the only ones that have different values for different numbers of sections. The rest of the parameters are the same in the three shorter transistors as in the single one.

35

30

S 25

<g 2 0 ( P * X ) 0 0 ° 0 O O O o o O o 0 0 0 o o o < * 3 O O O O o O c 0 0 0 o b

u I 1 5 s BO

I io

5

0 I

10

0

-10

a -20 00 a> a - 3 0

?!* -40

-60

0 % > „

o Measurements Model with 3 sections Model with 1 section

10 20 30 40

Frequency [GHz]

(a)

50 60

-70

-80

^ \ \

^v o ^<-^

° X -

-

o Measurements Model with 3 sections Model with 1 section

\ ~ ~ , 0 ° < v \ " - -

"-~"Cf\

-

_

-

-

"

\

0 10 50 60 20 30 40 Frequency [GHz]

(b) Fig. 45. Comparison of measured and modelled (a) magnitude and (b) phase of the intrinsic Yu. SOI nMOSFET with Leff= 0.41 urn.

324


We see in Fig. 45a and b the magnitude and phase of the intrinsic Y2i. The experimental results correspond to a transistor with tb = 30 nm, an effective channel

length of 0.16 um and composed of 16 fingers of 6.6 urn-width each parallel-connected. The applied front gate and drain voltages are VGjs = VDS = 0.9 V. The model with one section shows a wrong behavior at high frequencies, as expected from Ref. 100, whereas the model with three sections agrees reasonably well widi the measurements.

5.3.2. Extrinsic Part

The access transmission lines and the extrinsic elements of the transistors are directly extracted from the measured S-parameters using a new parameter extraction scheme based on the good knowledge of the measured transistors 3-D physical structure and the physical meaning attributed to the various lumped elements of transistors small-signal equivalent circuit (Fig. 42). According to the physical meaning attributed to the elements, the circuit can be split into three parts:

• the intrinsic elements model the core of the transistor, and are thus dependent on the bias conditions and on the size of the active zone.

• the extrinsic elements (index "e") are supposed to be independent of bias, but scale with the active zone.

• the access line parameters (index "a") caused by the metal connections just outside of (adjacent to) the active zone. It is constant under normal biasing conditions, and not dependent on the width of the active zone.

Biasing the transistor under certain conditions we can neglect some elements compared to others and therefore simplify the equivalent circuit presented in Fig. 42. The main steps of the small-signal model extraction are: 1) Using standards implemented on the SOI wafer, a Through-Reflect-Line (TRL) calibration is performed according to the algorithm of Ref. 149 for defining the S-parameters' reference planes close to the input and output of the measured transistors. 2) Knowing the transmission line characteristics (Zc and y) from the measured calibration kit built on SOI substrate; the residual length of transmission line between the previously defined reference planes and the beginning of the transistor active zone is calculated (determination of Zga, Ygat Z<& and Yja). 3) By using a 2-D electrostatic simulator, we estimate the parasitic extrinsic capacitances (Cgsee, Cgdee and C^). These capacitors represent the parasitic coupling effects existing between the gate, drain and source metallization levels. 4) From the calculated capacitance values Cgsee, Cgd(,e and Cjsee and the measured imaginary part of Y-parameters for the transistor biased in deep depletion (VGjs « V,h and VDS = 0 V), the extrinsic capacitances Cgde, Cgse, respectively, the gate-to-drain and gate-to-source overlap capacitances, and Qse, the source-to-drain proximity capacitance, are extracted. Figures 46a and b present the simplified equivalent circuit for MOSFET's under deep depletion and the measured equivalent capacitances noted Cgs, Cgj and Cj, of three SOI nMOS transistors having all 10 gate fingers, a 0.75 um gate channel length, and total active zone widths (W) equal to 60, 120 and 240 um. The plotted capacitances were obtained for each measured transistor by fitting the slope of the Y-parameters imaginary parts versus pulsation ox, in the frequency band from 2 to 20 GHz. The measured capacitance curves are linear in function of W and their intercept at the origin equals to

325


zero. This is in agreement with the equations (29a)-(29c) and also with the definitions used for the extrinsic parameters.

lm(Yu)=a>{cgM+Cgde)

lm(Y22)=m{cgde + Cdse)

Im(K12) = Im(r21)=<o{Cgde + C^ )

(29a)

(29b)

(29c)

1 — i / v W ° D

40

• 30

w

3 20 5 a a. a

W . 0

-ft- Cgd - e - Cgs - * - Cds

\--Jft

y/2'''''

^

20 40 60 80 100 Transistor total width \\aa\

120

Fig. 46. (a) Equivalent circuit of MOSFET's under deep depletion conditions, (b) measured equivalent capacitances of three SOI nMOS transistors having all 10 gate fingers, a 0.75 |im gate channel length, and total active zone widths (W) equal to 60,120 and 240 nm.

5) After removing the parallel extrinsic capacitances (by simple matrix manipulations), we consider the parametric curves defined in a two dimensional plane [x,, x2] by [RefZarf/a))),Re(Zorti(a))], where {i,j} * [k,l], for the transistor biased in saturation (VDS

> ^G/S)- In agreement with the work of Lee et al.'so, the real parts of Z-parameters under saturation bias conditions are expressed by the following analytical expressions:

Re(z (W,y)=Re(zoiy)+-A- for i,j e {1, 2} m2 + B

(30)

where B, the Ay, Ey and Fy are real and frequency independent expressions involving only the intrinsic and shunt extrinsic elements.

All series resistances can be calculated from the asymptotic values obtained from the equation (30) at infinite frequency. In order to evaluate these asymptotic values, the authors of Ref. 154 use an optimizer to fit the expressions on the right-hand side of (30) individually to the evolutions of the measured data over the available frequency band. It is however possible to transform the determination of the asymptotic values into simple linear regression problems taking advantage of the dissymmetry of ZOT (Z^^ * Zmai) in saturation. In fact, this is done by considering the parametric curves defined in a two dimensional plane [xj, x2] by [ReiZÔ))), RefZa^dfco))], where {i,j} * {k,l}. Using equation (30), it is straightforward to establish that these curves must be straight lines, and that their intercept at the origin [0, x2ol and slope dxjdxi are given by:

326


x20=Re{ZaU)-^-Rc(zatJ)

dx2

A;

(31)

(32)

Substituting the values of intercept and slope obtained from a linear regression on the measured data points into (31)-(32), yields a linear equation relating the series resistances. To determine all series resistances, it is necessary to combine three linearly independent equations formed by varying the indices i, j , k, I in (31)-(32). Such a set of equations can only be constructed when Z^n and Zâi are significantly different, which requires to use measurements from the MOSFET in saturation. A sensitivity analysis showed that the following pairs yield the most accurate results: [RefZ^n), RefZaî)], [Re(ZaKl2), Re(Zcnai)\, [Re(Z<a22)> Re(Za7tI2)\. Figure 47a represents the equivalent circuit of a MOSFET under saturation bias conditions and Fig. 47b illustrates the quality of the linear regressions performed on data measured from 500 MHz to 40 GHz.

u ° — A / W - W W — ° D

1 OS

ou

50-

40-

30-1

20-

10-

Reeression jf + Measurements y**

^ 3 % = 0.2

...-•'' Rge+(l-0.2)R.,c="7.7

x20= 17.7

1 • l • l •

(a)

50 100 150 Re(Z2i) ["]

(b)

200

Fig. 47. (a) Equivalent circuit of MOSFET under saturation bias conditions, (b) parametric plot of resistances in the 0.5-40 GHz band for a nMOSFET with W= 240 um and Z*#= 0.5 Jim at VCjs = IV and VDS = 2V.

6) After subtracting the extrinsic resistances from the measured Z-parameters, all of the intrinsic elements {Cgsi, Cg(u, Csla, Rgsi, Rgln, Gmi, G^ and T) for an arbitrary bias condition can be directly extracted by using simple matrix manipulations on the intrinsic Y-parameters151. By definition the intrinsic parameters have to be constant as a function of frequency. The flatness of the extracted intrinsic parameters versus frequency is a good figure of merit of the equivalent circuit used, the assumptions considered and the direct extraction method itself including the on-wafer calibration technique.

The extraction method described above has been successfully used for characterizing n- and p-type MOS transistors with an effective channel length down to 0.16 urn. Table 3 presents the extracted extrinsic elements for a SOI nMOSFET composed of 16 parallel-connected fingers of 6.6 urn width and 0.16 |im effective length.

In order to determine the geometry dependences of the extrinsic parameters, the extraction procedure has been applied to several transistors with various channel widths and lengths. It is of course assumed that these values are independent of the frequency. It should be remarked that although values of the frequency-independent intrinsic

327


parameters are obtained by the extraction procedure described above, we only use in our circuit model the values of the access and extrinsic elements. When performing a small-signal analysis the intrinsic elements will be automatically evaluated from the complete transistor model applied to the shorter transistors in which the reference transistor is split. The parameters of the quasi-static model have already been extracted in DC conditions as explained above.

c 7.13

êdee

7.2 ^dsee

14.5 r 18.6

êde

11.9 Cdse

2.48 Ree

157 Rde

6.7 Rse

4

Table 3: Extracted extrinsic capacitances and resistances for a 16x(6.6/0.25) um2 non-silicided SOI nMOSFET. The capacitances and resistances are given respectively in fF and in CI.

5.4. Discussion

In Fig. 48a and b we compare the measured magnitude and phase of the S-parameters with the ELDO simulations using our RF equivalent circuit with the new submicron SOI MOSFET model for the intrinsic device. The measurements correspond to the same transistor as in Fig. 45, at the same bias conditions.

8

6

2 J " 2 1/3

"S °

V2

i-4

2 - 6

-8

-10

0 5 10 15 20 25 30 35 40 Frequency [GHz]

(a)

--- Measurements — Model with 3 sections - Model with 1 section

328


150

4) <U

& « 100

*—J

CN

S» « « J5

0<

0

-40

\ v

. \

l 5

Measurements

Model wiin J sections ^ Model with 1 section

^ V "v

*>v *N-

\ . *** . ^ ^ V - ""* "**

^ * > ^ ~* _ ^ ^ i i i - ~~ **- ^ ^

""""""""•-^Cl* - - "~ """" "~ —

0 10 35 40 15 20 25 30 Frequency [GHz]

(b) Fig. 48. Comparison of measured and modelled (a) magnitude and (b) phase of S21. SOI nMOSFET with Leg = 0.41 nm.

As we can see, the splitting of the channel length into three sections improves the accuracy of the magnitude, phase and cutoff frequency of the ^-parameters (especially of S/2. where the fitting is quite good until a frequency of 15 GHz, well above the cutoff frequency), because the propagation delays are taken into account, which are not negligible even for channel lengths as short as 0.16 nm. We also show comparison of the modeled and measured H2i (current gain, from which the cutoff frequency, fT, is determined) and MAG in Fig. 49 and 50, respectively, for the same transistors as in Fig. 48, and at the same bias conditions (VG/5=VDJ=0.9 V). The accuracy of the magnitude of H2i is very good (Fig. 49).

1 2 3 5 Frequency [GHz]

Fig. 49. Comparison of measured and modeled magnitude of ft;.

The accuracy of the calculated S parameters, and of the MAG is better than in standard models; however, the error in the determination of the MAG (from which fmax is

329


determined) is higher than for H2i (Fig. 50). This is because the MAG is very sensitive to the value of the gate resistance and the propagation effects along the gate width, so that the approximation of an effective gate impedance (Rge, Cge) is not so accurate to determine the MAG. The accuracy can be improved by splitting the transistors into several portions along the channel width.

Fig. 51a and b show the results of simulation using a small-signal model with a channel width split into seven sections. The small-signal model corresponds to the equivalent circuit shown in Fig. 42, without using the approximation of effective values of Rge and Cge, and with the intrinsic and extrinsic parameters extracted from S-parameters.

s. v .

" 7 0 j \ -. CQ • - . \ i v 2i 1 "'' X v ^ .3 60 r ^ \ "• ca X-^

^ , „ i o 50 r

.O (0

" S ^ > < g 3 0 h 3

E 1 » r n S ,„i

10 r

0 h

Measurements

Model with i section N

" - ^ - v . "*•

• J v ^ *»v >*

> . N.

**_ >-

\V

\ \ \ \ \ v \ >

\ \ N.

0.3 1 2 3 5 Frequency [GHz]

10 20 40

Fig. 50: Comparison of measured and modeled MAG for a SOI nMOSFET with Ltg = 0.16 |4m.

15 20 25 Frequency [GHl]

(a)

15 20 25 Frequency [GHz]

(b) Fig. 51. Comparison of measured (lines) and calculated (symbols), using a distributed small-signal model, (a) magnitude (b) phase of the S parameters. SOI nMOSFET with Us = 0.16 urn.

330


5.5. Conclusion

We have developed a Fully-Depleted SOI MOSFET macro model valid from DC to RF. Because of the physical modeling of the intrinsic and the extrinsic parts, including the distributed nature of the gate and channel R-C lines along the length of the transistor channel, our macro-model has proven to be very accurate for frequencies up to 40 GHz and effective channel lengths down to 0.16 (J.m.

6. Microwave Characterization of the SOI CMOS Transistors

6.1. Silicidation for the reduction of the contact resistance

Thin-Film SOI MOSFET's are fabricated with a CMOS-compatible process on low-resistivity (20 Qcm) SIMOX wafers. The initial 200 nm silicon film is thinned down to about 100 nm by oxidation and oxide strip. After a semi-recessed LOCOS isolation step, a 30 nm gate oxide is grown and boron is implanted to adjust n- and p-channel threshold voltages. A 340 nm thick polysilicon is then deposited, doped (implantation, As, 100 keV, lxlO16 cm"2) and patterned. Arsenic (80 keV, 4xl015 cm2) and boron (20 keV, 5xl015

cm"2) are implanted to form the source/drain regions, followed by an RTA (950°C, 40 sec) activation step. Then, a 150 nm thick Si02 is deposited and etched by RIE to form spacers. After a short-time 2 % HF dip, layers of titanium, titanium/cobalt stack layer or nickel are deposited with thickness of 30 nm, 7 nm/13 nm and 25 nm, respectively using an e-gun system. The conventional 2-step SALICIDE (self-aligned silicide) process is used for titanium152153 and cobalt154 silicidation (Ti: 675°C, 45 s and 900°C, 15 s; Ti/Co bilayer: 675°C, 45 s and 900°C, 30 s). Nickel monosilicide155156157 is formed with a one-step annealing at 550°C for 40 s. Unreacted metals are selectively removed by a H2SO4+H2O2 (2:1) mixture. A nitride/oxide layer is then deposited and contact holes are opened to access the devices. An aluminum metallization is used to complete the process. The gate sheet resistance of the wafers with TiSi2, CoSi2 and NiSi are 6.2 £2/square, 4.4 fl/square and 2.8 £2/square, respectively.

For high frequency applications, it is necessary to reduce the gate, source and drain resistance.

6.2. S-parameter measurement and stability

At high frequencies, it becomes difficult to measure voltage and current and the devices are characterized by their scattering matrix (S-parameters).

V P2.

'su _5 I 2

S12

522_

a\

.a2.

where a* and bj are the incident and reflected waves respectively, defined in units of square roots of watts, at the input and the output of the device.

The S-parameters of the transistors are measured on wafer by using a Vector Network Analyzer. The calibration of this instrument, using commercial coaxial standards (for example K connectors) allows to compensate for the losses and phase shift

331


of cables and connectors. The reference planes of measurement are then set to the output plane of the connectors. For on-wafer characterization however, it is necessary to transfer the reference planes on the wafer itself, close to the device to be measured. Commercial impedance standards are available to transfer the reference planes to the probe tips. Due to the different material characteristics of the calibration structure and the substrate, an additional correction is necessary to access the "exact" device characteristics. Another possibility is to develop an on-wafer calibration kit, as the one mentioned in Section 4.3. Different calibration methods are available121, but the variation of the characteristic impedance of the coplanar waveguide with frequency needs its accurate determination.

Fig. 52. Layout view showing a MOSFET embedded in a probing structure. The vertical dashed lines represent the reference planes.

The reference planes of measurement are then brought close to the device to be measured and are represented by dashed lines in Fig. 52. Having measured the S-parameters, it is then possible to fully characterize the device by its figures of merit but also to extract its equivalent circuit.

Before using a transistor, it is important to check its stability. Representing a transistor as a two-port, with a source and an output load (Fig. 53), one may calculate the input reflection coefficient of the device, loaded with rL as

= 5„ + i - s22rL

(34)

and the output reflection coefficient of the same device with an input load having a reflection coefficient of fs as

Tow - $2: (35)

332


a l

transistor

b2

1

1

Fig. 53. Representation of the transistor as a two-port device.

The device is unconditionally stable if the input and the output reflection coefficients, rin and rm„ are less than unity for all the possible loads TL and F s . The stability can also be expressed by the Rolled: stability factor:

*= -1-S,, - \S 22

2|S12S21

2 - A 2

(36)

where A = S12S21 - 5, ,522

The active device is unconditionally stable if k >1 and potentially unstable when k <1.

6.3. Cut-off frequencies

At low frequency, the transistor is often characterized by its current gain

\Hn\M 07)

This gain can also be expressed as a function of the admittance matrix of the transistor

\H I = ' 1 2" <°{cgs + cgd)

(38)

where Gmi is the transconductance of the transistor and Cgs and Cgd are the gate-source and gate-drain capacitors, extracted from the small signal equivalent circuit (extrinsic and intrinsic). The high frequency performances of the transistors are characterized by three cut-off frequencies:

• /r , the cut-off frequency of the current gain; • /m<u. the cut-off frequency of the unilateral gain or the maximum oscillation

frequency; • /MAG, the cut-off frequency of the maximum available gain.

The cut-off frequencies are the frequency points where the corresponding gain is equal to unity.

The current gain is derived from the S-parameters of the measured devio~ K'

333


»n = -25 ,

(l-SnXl + S22)+512521

(39)

From the small signal equivalent circuit of the transistor, the transition frequency can be approximated by

h = o mi

27t{Cgs+Cgd) (40)

It has to be mentioned that fT does not depend on the resistors. Sze158 defines a very useful relationship between f^^ and/ r:

/max fr

2j27rfTRge [Cgdi + Cgde)+ Gdsi (Rge + Rse + Rgsi) (41)

Approximate expressions (40) and (41) show that while fT can simply be increased by scaling down the device, fmax depends strongly on the parasitics, as well as on Gmi and Gdsi

which are very sensitive to the drain current and thus to Vgs. A way to reduce the parasitic elements, and the resistors in particular is to use

silicidation of the contacts. A titanium silicide process reduces the gate sheet resistance to about 10 Q/sq. in place of 100 Q/sq. for a classical doped polysilicon gate, for a 0.25 |im gate channel length. Figure 54 shows the evolution of/™,* and/ r as a function of the bias conditions (Vds= Vgs) for silicided and non-silicided 12x(6.6/0.35) um2 transistors.

The maximum values of fT and fmax, respectively 26 and 56 GHz, are reached for V,fa=Vg,= lV for the silicided 0.35 um nMOSFET. This result shows that SOI nMOS transistors are suitable for low-voltage, low-power RF applications.

0.4 0.6 0.8 1.0 1.2 1.4 1.6

Polarisation (Vds = Vgs) [V]

Fig. 54.fi- and/TO, as a function of supply voltage (Vd, = Vgs) for silicided (solid lines) and non-silicided (dashed lines) 12x(6.6/0.35) jim2 SOI nMOSFET's.

The curves of fT and /„„„ versus bias conditions shows a plateau above Vjs = Vgs =1.2 V. The saturation carrier velocity can explain this saturation characteristic. In fact, for high values of longitudinal electric field between source and drain electrodes, the velocity

334

http://54.fi-


of the carriers in the thin inversion layer tends to saturate due to important collisions between them. These effects lead to an important degradation of the effective surface mobility of carriers in the channel. It is easy to understand that these effects are mainly observed in devices with small channel lengths. The saturation velocity of carriers in a MOSFET is reached for a longitudinal electric field between the source and drain, called critical electric field, of about 1 Nl\xm for electrons and about 3 V/jim for holes. These values are in accordance with the measured characteristics presented in Fig. 54. We see that the velocity saturation effect is a very important limiting parameter in the design of small devices and thus particularly for microwave applications. Therefore, the study of the velocity saturation effect on the small-signal microwave performances of SOI MOSFET's is absolutely necessary to establish accurate and physical models.

Figure 54 clearly shows the great interest of the silicidation process in order to improve the maximum oscillation frequency by reducing the parasitic extrinsic resistances Rge> R^ and Rse. After silicidation, the parasitic extrinsic gate resistance is approximately reduced by a factor 10 and fmax is triple.

Figure'55 presents the evolution of fT and/mai versus bias conditions for silicided FD and PD 12x(6.6/0.35) urn2 SOI nMOSFET's. The slight improvement of cut-off frequencies obtained with FD SOI nMOSFET's can be related to the improvement of the gate transconductance and the reduction of the output conductance and channel time delay. The frequency band of the network analyzer being limited up to 40 GHz, the cutoff frequencies above that limit are determined by simple linear extrapolation of the corresponding gains in logarithmic graphs. Due to the measurement and extrapolation inaccuracies, an error of around 15 % can be attributed to these extrapolated cut-off frequencies. That inaccuracy can explain the similar values of /„„„ obtained for FD and PD SOI nMOSFET's at higher bias conditions (V^ = Vgs > 0.7 V).

60

50

a 4 0

2. 130 §•

10

'0~2" 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 Polarisation (Vds= Vg!) [V]

Fig.55./r andfimu as a function of supply voltage (Vds = Vgs) for silicided FD (solid lines) and PD (dashed lines) 12x(6.6/0.35) um2 SOI nMOSFET's.

Figure 56 presents the evolution of fT and / „ , versus the channel length of various silicided SOI nMOSFET's having a total gate width (W) of 80 urn and bia; = Vgs

= 0.9 V. The cut-off frequencies increase with the reduction of the channel length. The dependence in 1/L2 offT is in accordance with the simplified expression (41). In fact, Gmi

335


being proportional to W/L and (Cgs+Cgd) to WL,fT is a function of 1/L2. fmm has also a dependence in 1/L2 for large channel lengths but this increase rate decreases for L smaller than 0.5 urn because the increase of Rge with the reduction of the channel length (L) becomes dominant in equation (41).

°0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

Length [um]

Fig. 56. Cut-off frequencies versus channel gate length for 0.35 um FD (solid lines) and PD (dashed lines) SOI nMOSFET's at Vds = Vg! = 0.9 V.

These results are among the best published in the literature on silicided fully depleted SOI nMOSFET's. M. Harada159 has obtained current gain and unilateral gain cut-off frequencies of 19 GHz and 27 GHz respectively, for 12*(5.0/0.25) um2 transistors at 1 V. The performances are directly dependent on the control of the silicidation process for thin silicon films.

Furthermore, the microwave performances of these transistors compare very favorably with bulk silicon devices of similar gate length, operated at much larger power consumption. Texas Instrument160 has published the following results for silicided bulk nMOSFET's (L=0.1 um, Wtot = 256 um): fT = 120 GHz, fmax = 28 GHz. Toshiba has obtained silicided bulk nMOSFET's cut-off frequencies of fT = 35 GHz, / = 45 GHz under 2.5 V for CoSi2 silicided transistors (L=0.25 um, Wtot = 200 um)161, and/mai of 60 GHz and 70 GHz for 0.15 um and 0.1 um respectively162.

It can be concluded that fully-depleted SOI nMOSFET's have similar microwave performances as bulk transistors, with a lower power consumption (Vps lower than IV),

which is very important for low-power, low-voltage consumer applications163. A comparison between various high frequency devices and the perspectives for Si

devices has been presented by J. Gautier et al.'64. As a conclusion, the fully-depleted silicided (TiSi2) 0.25 Um SOI MOSFET transistors are fully suitable for microwave applications, with cut-off frequencies fn^ and/ r of about 50 GHz for V^s = 0.9 V. This low voltage value, when compared to bulk CMOS, is very attractive for low power telecommunication applications. Their fabrication process is fully compatible with usual CMOS process.

336


6.4. Noise parameters measurement

An important parameter for high frequency design is the noise figure, representing the diffusion noise of the device. The noise model used for the nMOS is derived from the Pospieszalski model165, applied to the extrinsic device. Two uncorrelated noise sources are added to the small signal equivalent circuit: an input noise voltage source ein and an output noise current source iOM. These two noise sources can be represented by equivalent noise temperatures Tin and Tou,.

Accurate knowledge of transistor noise parameters (NFmin, Rm \rop,l and arg(rop,)) is required in performing realistic and reliable design of Low Noise Amplifiers (LNA), which are the key elements of high sensitive microwave receivers. These parameters can be calculated given the noise sources. More details about the physical interpretations of the measured high frequency noise parameters, but also general interest material and the limitations of SOI MOSFET technology for the realization of ultra-low-noise circuits can be found in Ref. 166.

Figure 57 represents the cut-off frequencies (fT and f^) and the minimum noise figure (NFmin) for a 0.25 um FD SOI n-MOSFET with a current density of 100 mA/mm. A current gain cut-off frequency fT and an extrapolated maximum oscillation frequency /„<„ of 40 GHz and 70 GHz, respectively, are reached at Vgs = Vds = 1 V for NFmin less than 1 dB.

Figure 58 shows the variation, at 6 GHz, of NFmin and associated gain (G^) as a function of the drain current density (V& = 1 V). For a drain current density close to 75 mA/mm, NFmin is 0.8 dB with G^ of 13 dB. This result is one of the best reported in the literature. It shows that LNA's could be designed with a power consumption of less than 35 mW/mm. Figure 59 presents the evolution, at 6 GHz, of NFmi„ and Gms as a function of the drain voltage for a constant drain current density of 75 mA/mm.

1.8 1.6 1.4

Z 3

1.2 s 1

0.8 0.6

/ • • " \

60 • " ^

Fig. 57. fr.fmax. NF„i„ versus current density at V*=1V for a 12x(6.6/0.25) pm2 FD SOI nMOSFET.

337


- • -Fully ••-Partially

ap)u

4Fm

i

» :

0.6-

'. \

•. •-...

• ... ' • • • '

,**>

,»

3i*"

. . • • ; : - • •

^ssn =c s •

•

-

200 300 Jds (mA/mm)

Fig. 58. Comparison between 12x(6.6/0.25) |im2 FD and PD SOI nMOSFET's: evolution of NF^ and G«„ as a function of the drain current density at 6 GHz and Vd, = 1 V.

1.2-1

ja 0 , 8

2,

E u.

0 -

| -•• Partially

<2rr . ?

— * — i —

-•-Fully |

-r^. ^ ^ » •

-*C---

0,5 1 1,5 Vds (v)

16 ST

15 g (0

14 w

13

12 2,5

Fig. 59. Comparison between FD and PD SOI nMOSFET's: evolution of W™„ and G„„ as a function of the drain bias voltage at 6 GHz; J&= 75 mA/mm; 12x(6.6/0.25) urn2.

-Fully ••-Partially

1

& '

0.84

• ' • « . " • "

iC-^-B- . . - - • * •

. - - • - •

. . • • - •

. - •

. - • • ' ' 1

100 200 300 400 Jds (mA/mm)

500

25

15 £

Fig. 60. Comparison between FD and PD SOI nMOSFET's: evolution of rop, as a function of the drain current density at 2 GHz; VdI= 1 V; 12x(6.6/0.25) urn2.

338


Figure 60 shows the evolution of ropt as a function of the drain current density at 2 GHz and Vi, = 1 V for 12x(6.6/0.25) urn2 FD and PD SOI nMOSFET's.

By considering the very low value of NFmin at 6 GHz and its estimated measurement accuracy (+/- 0.1 dB), the values and evolutions of NFmin for both FD and PD SOI transistors are similar. However, the extracted equivalent noise resistance Rn, which measures the sensitivity of the noise figure to change in the generator impedance, is slightly higher for PD SOI MOS (Fig. 61). In fact, Rn is proportional to (l/gmi), the subscript "i" being for "intrinsic"; and the transconductance gmi is higher for FD MOSFET's than for PD MOSFET's. The lower the value of Rn, the easier it is to obtain minimum noise condition in LNA designs. As compared with a 0.6 urn channel length device, the value of R„ in Fig. 61 is three times lower.

Figure 62 represents the state-of-the-art results for different kinds of MOSFET technologies. Low noise microwave performances of FD SOI MOSFET's appear to be some of the best reported in the literature.

250 -i

200

£

B 100

50-

0 i

l - ^ R , i Fully • * • Rn Partia "iyl

1

0 100 200 300 400 500 600

Jds (mA/mm)

Fig. 61. Comparison between 12x(6.6/0.25) jim1 FD and PD SOI nMOSFET's: evolution of R„ as a function of the drain current density at 6 GHz and Vj,= 1 V.

20 -

i

l-s •

(

• •

• MOSFET >= 0.5 Jim

A MOSFET "bulk" < 0.2 um

• MOS SOI/SOS >= 0Spm

• SOI 0,25 (im. Salicide

) 0,5 1 1.5 Minimum Noise Figure [dB]

2 2 3

Fig. 62. State-of-the-art high frequency NFmi„ and Ga„ for different published results of MOSFET technologies. Black dot corresponds to this work.

339


As a conclusion, the latest generation of SOI MOSFET's presents very good properties for high frequency low-voltage, low-power applications.

7. RF and Microwave Active Circuits

7.1. Operational Transconductance Amplifiers (OTA's)

In this paragraph, we will firstly compare the gain-frequency performances of common-source MOS gain stages implemented in SOI or bulk technologies and discuss the improvements resulting from the superior device characteristics of fully-depleted SOI MOSFET's. Secondly we will extend these building block performances towards the synthesis of typical single-stage OTA architecture, up to 1 GHz transition frequency.

In this chapter, for sake of generality, we will consider and compare bulk and FD SOI MOSFET's with the parameters listed in Table 4. Comparable technologies are considered, only changing the body effect and capacitance parameters whose improvement in SOI has a clear physical origin. However the same mobility and Early voltage are considered in bulk and FD SOI devices although better values have been reported in SOI167168.

name

body effect linearized factor [V/V]

bottom-plate n-diffusion capacitance

per unit area [fF/um^] bottom-plate p-diffusion capacitance

per unit area [fF/um^] sidewall n-diffusion capacitance

per unit of periphery [fF/um^] sidewall p-diffusion capacitance

per unit of periphery [fF/um^]

n-channel mobility [cm^/(V.s)]

p-channel mobility [cwr/(V.s)]

n-channel Early voltage per unit of length [V/um]

p-channel Early voltage per unit of length [V/um] gate oxide thickness [nm]

notation

n

C

C JP

c jswn

c. jswp

»n

»P

V ean

V eap

t ox

bulk

1.5

0.18

0.4

0.4

0.5

600

250

7

7

30

FDSOI

1.1

0.06

0.06

0.05

0.05

600

250

7

7

30

Table 4. List of parameters, notations and default values in typical bulk and FD SOI CMOS technologies.

340


7.1.1. Common-source synthesis.

In the case of the common-source MOS intrinsic gain stage (Fig. 63), the low-frequency open-loop gain A0 and transition unity-gain frequency fT are respectively given by:

V .Sm_y

fr = gn ID 2itCL

(42)

(43)

where gm, ID and Vea correspond to the transconductance, drain bias current and Early voltage of the active MOS device and CL to the total capacitance at the output node. The performances of SOI and bulk implementations are compared considering the parameters of Table 4 and identical CL. Combining expressions (6), (7), (42) and (43), the following conclusions are found (Fig. 64).

T I

V; in

ffilD° rout

•ml If C gd

(a)

1 I

out

C g s + C g b Snv v in §d C L (b)

Fig. 63. MOS common-source intrinsic gain stage (a) and small signal equivalent circuit (b).

1) If a specified bias current ID is considered, both A0 and/ r are enhanced using FD

SOI instead of bulk MOSFET's by a minimum figure of -J^huikMsoi ^ m s t r o n g

inversion (SI) and a maximum of fabuik/'Hsoi) m w e a k inversion (WI); this corresponds

to improvements ranging from 17 to 36 %. 2) To achieve a specified fr a bias current \nbutk/rlsoi)i*me smaller in SOI than in

bulk is needed over the entire range of device operation, which simultaneously provides a higher gain. The same conclusion obviously holds for the DC power dissipation.

3) If we consider a specified DC gain AQ, the SOI/ r is increased by a factor equal to

fabuikMsoi) m SI when compared to bulk. Expression (6) is too simple however to predict the potential improvement in moderate inversion, but from the experimental data

341


or continuous model reported in Fig. 11, we may conclude that for a given gJlD between 18 and 22 for example, fT may be 3 to 10 times higher in SOI than in bulk. SOI devices operating at larger current densities also have the potential to achieve better noise performances.

Similar conclusions are met when designing an SOI single-stage OTA matching a specified fT with a given load capacitance CL. In SI, expressions (7) and (43) indicate that

we may choose device widths at least (77fcu(jt / r / s o /) times smaller in SOI than in bulk for the same speed performances, assuming that all other device parameters as well as ID are identical. In moderate inversion (MI), we need to use either the continuous expressions (8) or the interpolated gm/ID data curve. The procedure yields a (W/L, lD) locus for a given fT-CL specification (Fig. 65). The relative transistor bias and DC gain AQ are found by comparing the respective gJlD curve. Several design approaches can be considered to exploit the improved SOI gm/ID data in m.i. (Fig. 65):

- either, at the same ID and gm/ID, the device widths are 5 to 10 smaller in SOI than in bulk (regardless of noise or matching considerations which obviously are beyond the scope of this first analysis).

- or reciprocally, the SOI 1D and hence the DC power dissipation are reduced by as far as 40 % and gJlD is increased by the same proportion compared to bulk.

Any compromise between these two extremes exists, demonstrating the potential of SOI for smaller chip area, bias current and power dissipation41'42. Since we did not consider so far the inherently smaller SOI parasitic capacitances, further improvements regarding speed and ease of design can still be achieved.

0 5 10 15 20 25 30 35 Transconductance / Cuirent Ratio (1 /V)

Fig. 64. Transition frequency and drain current of the single-stage common-source amplifier (CL = 10 pF) as a

function of gJID, for bulk (solid lines, n = 1.5) and SOI (dashed lines, n = 1.1) MOSFET's with identical size

(W/L = 100), mobility (fi = 600 cm2/(V.s)), CM (1.15 fF/um2) and DC output drain voltage (2.5 V).

342


400

350

300

250

3 200

> 150

100

50

0

1

J u

•

1 \ i N »

i »

~* '

':

• ! V

S-Si

v i i • * i

_ SOI

— Bulk

• - - -

i<r «D ( A )

40

35

30

25

20 S Q

15 ^ DO

10

5

0 -5

Fig. 65. W/L and %JlD ratios of the input devices of the MOS common-source amplifier as a function of the drain current for CL = 10 pF and/r = 1 MHz, calculated for bulk (solid lines) and SOI (dashed lines).

7.1.2. Single-stage CMOS OTA.

a) Architecture analysis.

The single-stage CMOS OTA constitutes a typical architecture for micropower applications (Fig. 66). Featuring a single amplification stage implemented as an input differential pair whose small-signal current imbalances are reproduced and added at the single-ended output node by current mirrors, this OTA may only provide limited DC open-loop gain. The simplicity of the output stage however enables good output dynamic swing and low loading of the input stage, which are properties of importance for low-voltage low-power or high-frequency applications.

VDD

IkGND

Fig. 66. Single-stage CMOS OTA schematic.

Considering a first-order small-signal analysis limited to the dominant pole, the single-stage OTA low-frequency open-loop gain AQ and gain-bandwidth product GBW are respectively given by:

343


A)=~-y e a (44) 'D

GBW = 8m BI° (45) ID 2nCL

where gm and ID correspond to any of the two input devices of the differential pair (Ml-M2), Vea represents the overall Early Voltage of the output devices (M6-M8), B the current mirror ratio and CL the total capacitance at the output node. This is very similar to the basic common-source stage. The single-stage OTA however features a more complex behavior since in addition to the dominant pole related to the output node, it includes a number of poles and zeros related to the current mirrors.

A complete analytical small-signal analysis has been developed in Ref. 169 but is beyond the scope of this report. We will limit our discussion to a two-pole model which incorporates only the first non-dominant pole related to the intermediate node noted " 1" in Fig. 66. This is given by

/pi = 7 ^ (46)

where Cv the total capacitance at node 1, is the sum of all gate and drain capacitance connected to node 1, i.e. with M4 = M6,

C, »(l + B ) C M 4 + W 4 ^ C ^ + 2 ^ 4 + ^ ) c ^ + W 1 X B C J h + 2 ( W 1 + X I , ) C / n w i (47)

with Wj and W4 the widths of transistors noted 1 and 4 in Fig. 66, C 4 the total intrinsic gate capacitance of transistor M4 and X fn) the drain junction extension of a p(n)-type device.

The phase margin performance can be estimated using:

/ 0n=9O°-atan fpi

GBW \

(48)

A systematic synthesis procedure can be based on the "gjlu methodology using equations (44) - (48). Figure 67 depicts a top-down design algorithm for specified frequency performance, i.e. GBW and phase margin. The procedure starts from the choice of initial gm/ID and length values for Ml and M4. Transistor Ml can then be completely sized from the GBW specification, as well as M4 since it drives the same bias current as Ml. The capacitance at node 1 can hence be estimated, and finally the non-dominant pole frequency location and the OTA phase margin. If the phase margin is not sufficient, the initial gm/lD or length choices have to be corrected.

The choice of the gm/ID and L values for Ml and M4 may also be conditioned by other possible specifications such as DC open-loop gain, input and output dynamic swings, noise, etc. These can easily be taken into account provided that the considered opamp performance can be expressed as an analytical function of the results of the

344


previous algorithm, i.e. the small-signal, current and size parameters of the OTA MOSFET's.

gml = B'1 .ooj . C L Id4 = Idl

L4

14'

gm4

1 c i

W4

1 fpl»tm

Fig. 67. Sizing algorithm for the single-stage CMOS OTA based on the simplified two-pole model ( the/ function is given by eq. (47)).

The common-mode input range CMIR is bounded by

V^+V^KCMIRKVoo (49)

where Vjsat is the saturation drain voltage of the tail current source transistor and Vgs0 is the DC gate-to-source bias of the input transistors defined by the device aspect ratio and bias current.

Similarly, the output voltage swing V0UtSW is defined by the range in which the output voltage can swing without significantly altering the small-signal behavior, i.e. driving the transistors of the output branch out of saturation. The output voltage swing will be approximated as bounded by (VSs + Vdsai + Vpo) on the low side and (VDD - Vdsat) on the high side, considering that Vâ, is also the saturation drain voltage of the load current mirror device, VP0 the pinch-off voltage of the input differential pair transistor and VDD

and Vss the positive and negative supply voltages respectively. One of the design objectives in low-voltage applications will be to maintain

sufficiently large CMIR and VoutSW even for reduced supply voltage. Reciprocally, given specifications on CMIR and VoutSW will limit the minimum allowable supply voltage as follows:

{VDD-VSS)>CMIR + Vn

(vDD-~ " " dsat "•" * gsO

Vss)> (50)

In our gJID methodology, the DC operating point of the input transistors can be easily estimated using the EKV formulation in saturation and

345


VPo = %m/T n

(51)

0.8

?0.6

1 fo.4

0.2

/ /

r i

#»*

_ ^

^ VGO

- » • " " ' * '

•

V P O • • - " ' ^ ^

10"6

Drain current [A] HT

Hg. 68. Vgg and VTO of the input devices of the MOS differential pair as a function of the drain current for same specifications as in Fig. 64, calculated for bulk (solid lines) and FD SOI (dashed lines).

The bulk vs. SOI comparison depicted in Fig. 68 emphasizes the clear SOI advantage for larger CMIR deriving from the lower threshold voltage. However at first glance, SOI may exhibit a degraded output swing due to the reduced body effect. This can nevertheless be compensated and even turned to an advantage when exploiting the SOI capability for larger g„/ID ratios and lower drain currents in order to reduce VP0 values, as will be demonstrated later in more complex OTAs.

The input-referred thermal noise power spectral density of the differential pair is given by:

Sy=2 gnkT

(52)

where g is a factor ranging from 2 in weak inversion to 8/3 in strong inversion65. It is then clear that for a constant frCL - and hence gm - specification, Sv will be lowered by the possible use of devices in weaker inversion, i.e. larger g /ID values for Ml.

The input-referred power spectral density added by the p-type current mirror is:

Vmirror = 2 o m,mirror

Sm

gnkT _ gnkT g„ • = 2

8 m, mirror in I 'DO (53)

DO

346


This equation shows that for constant fT and gm, we can lower the added noise by reducing either lm, or (gjl^mirror- The usual guideline is to follow the latter option i.e., for a given ID0, drive the current mirror in stronger inversion. Our analysis shows that the first option is also very valuable since, by increasing the gJlD of Ml, lm may be reduced for a larger magnitude than (gjl^mirror and since maintaining larger {gjlj^mmr will improve the input range and output swing.

b) Low-voltage applications.

To demonstrate the feasibility and the performance of low-voltage FD SOI CMOS OTAs, the design of the typical 1-stage OTA of Fig. 66 using high gJlD ratios for all the transistors was first investigated. The OTA design parameters and experimental characteristics under a 1.2 V-supply voltage and a 3 uA-total current bias are given in Table 5. They are also compared to the characteristics of a bulk CMOS implementation estimated using the same gjlt, procedure, but with the bulk technological parameters, and aiming a t / r and phase margin performance as similar as possible to the SOI case. Due to the increase of the body factor and the parasitic capacitances, this can only be achieved at the expense of an increase of the current bias and a decrease of the DC open-loop gain and output swing, since the g /ID ratios and transistor widths must be reduced. For the same reasons we estimate that the input range is lower in bulk than in SOI by an amount similar to the output swing reduction if the threshold voltages are identical. The bulk output swing will be further reduced by the ^-difference if the bulk process uses a larger threshold voltage for leakage current considerations in analog switches or digital parts.

Concerning thermal noise performance, from (52), it is clear that for a constant fTCL

- and hence gm - specification, Sy will be slightly lower in SOI than in bulk due to the reduction of the n body factor and the possible use of devices in weaker inversion. Regarding the input-referred power spectral density added by the current mirror, equation (53) shows that for constant fT and gm, we can either use the same (g /Ij)mirror in bulk and SOI and obtain lesser added noise in SOI due to the reduction of n and ID0, or achieve similar noise performance in bulk and SOI using higher (g^/I^mrmr in SOI which will improve the input range and output swing. In this case, the possible increase of (gjl^mirwr in SOI can be larger than a factor of 2 when compared to bulk.

The second implementation presented here is that of the cascoded OTA of Fig. 69 synthesized following our gjlo methodology. The complete analysis and design flow plan are detailed in Ref. 170. The highest possible gJlD values were used for the active transistors, i.e. input differential pair {gjlo =28) and output cascode {gjln =30) devices, in order to optimize the performance for minimal supply current consumption. These upper values are limited by stability considerations because as we increase gJlD for a fixed current, the transistor sizes and capacitances are increased and the phase margin hence decreased. The bias current and mirror transistors are operated in stronger inversion (ftA>=8).

This OTA experimentally achieved a 103 dB-DC open-loop gain and a 271 kHz-transition frequency over a 12.3 pF-load capacitance with a 60c-phase margin and a total bias current of only 2 uA under a 3 V-supply voltage, in accordance with the targeted and simulated specifications.

347


(W/L) 1.2

(W/L) 3.4

(W/L) 5.6

(W/L) 7.8

(gn/lD) 1-2

(gJh) 3-6 (gnflu) 7-8 /DD (MA) /r(kHz) Avo (dB)

phase margin (degrees) output swing (V)

SOI 30/3

33/3 66/3

30/3

25.8

22.3

22.7

3 350 44 85.6 0.9

BULK 27/3

23/3 46/3

17/3 18

14.5

14

4.32 350 41 85.4 0.75

Table 5. Experimental SOI and simulated bulk design parameters and performance of the 1-stage CMOS OTA of Fig. 66 (CL = 10 pF, B - 2). The bulk simulations used the same technology parameters as the SOI simulations in good agreement with the measurements, except for the body effect and junction capacitances, as given by the values of Table 4.

Fig. 69. Cascoded CMOS OTA architecture.

The output swing was almost equal to 2 V. Using our gJID procedure again with the bulk parameters, we simulated that to achieve a similar fT performance with same CL and phase margin, the bulk implementation could only have used gjlo ratios of 19 and 17 for the input differential pair and output cascode devices respectively, and would then have dissipated 45 % more supply current for a DC open-loop gain reduced by 8 dB. Furthermore, the simulation showed that for higher transition frequencies, the FD SOI benefits over bulk increase up to a reduction of the supply current by a factor larger than 3.5 and an improvement of the gain by more than 20 dB, for/r equal to 10 MHz (Fig. 70). Even though the active device gJID values have to be reduced towards strong inversion

348


(13 and 3.5 V"1 in SOI and bulk respectively at 10 MHz). In these estimates, the gJID

ratios of both SOI and bulk current mirrors were taken constant and equal to 5 V . Concerning the output swing and noise performance, the results of the above

analysis, as a function of fT were used to compute the total input-referred thermal noise power spectral density in bulk and SOI from equations (52) - (53). The bulk to SOI noise ratio ranges from 1.54 at 100 kHz to 3.11 at 10 MHz. To achieve the same thermal noise performance, lower gn/Ip values could be used in bulk for the current mirrors according to (53): the higher the transition frequency, the higher the bulk to SOI bias current ratio, the lower the bulk mirror gJID for the same noise and the larger the output swing reduction in bulk when compared to SOI. In our case this output swing reduction in bulk may attain several volts, even for low/ r resulting in unpractical designs.

c) High-frequency applications

We demonstrate here the potential of SOI CMOS technology on high-resistivity substrate towards the implementation of operational amplifier classical architectures with transition frequency above 1 GHz, without the need for extra compensation technique (e.g. feed forward) to boost the frequency performances. Such wideband amplifiers may be required for analog signal processing at intermediate RF frequencies in communication systems.

25

2 0 ~ 3 n

15 % <

io 5

} 5

100K 1M 10M Transition frequency (Hz)

Fig. 70. Comparison of simulated total current dissipation and DC open-loop gain performance of the bulk and SOI cascoded CMOS OTA's of Fig. 69 (with fl-mirror ratio equal to 2) as a function of the transition frequency. The computations were based on the EKV model using the set of parameters of Table 4.

In these applications the opamps are capacitively loaded, locked in closed loop and have to be stable in unity-gain feedback. Consequently, behavioral models of opamp performances and device parameters valid in a large frequency range are required to extend usual OTA design based on the phase margin criterion to the GHz range.

Two opamp architectures have been considered. In both cases, behavioral analytical expressions of the gain-bandwidth product (GBW) and phase margin performance are derived from the device transconductances and capacitances as discussed in previous sections. For frequencies above about 100 MHz, the transconductances and source/drain-to-substrate capacitances become frequency dependent and influence the opamp transition

349


frequency and internal poles and zeros. High frequency opamp design then requires the correct modeling of both the transconductance and substrate capacitances as presented above.

Several opamp implementations have been realized with 1 \im gate length SOI MOSFET's. The opamp voltage gains (Av), total transconductances G and output impedance ZgM were extracted from on-wafer scattering parameter measurements. The transition frequency (fT) and the phase margin <j)M for the one-stage and folded-cascode opamps are respectively 1.1 GHz (load capacitance C L= 2pF) - 30° and 700MHz (CL = 6pF) - 38° without silicidation process and for 50 urn gate finger length. Simulated and measured G and Av of opamps are compared in Fig. 71 and 72 to validate our models. The predicted phase margin enhancements with the silicidation process and for 25 um gate finger length are up to 73° for the one-stage opamp and 66° for the folded-cascode.

30

C/3

S,20

s BO 10 cd

s 0

^

S

4' 'v ! > •

M i fc

i

•

•

•

~t' . •

10 10 Frequency (Hz)

180

o 03

10 10

Fig. 71. One-stage OTA simulated (-) and measured (o) total transconductance as a function of frequency.

40

30

a 20

O 10

0

-10

: - - . .

,

•

k "

"

i id.-... x v

1 - i_; 10° 1 0 ' 10° HT

Frequency (Hz)

10 10

Fig. 72 Measured voltage gain of the one-stage with G=2pF (- -) and 6pF (-) and the folded-cascode opamps

withCi=6pF(-).

The quite low DC voltage gains Av are due to the device short channel length and the

strong inversion operation. Nevertheless for second order sigma-delta converters with low

350


over sampling rate or using reduced gain sensitivity technique e.g., these gain values are sufficient. They may also be sufficient for other high-frequency switched-capacitor filtering applications.

7.1.3. Conclusion

Our OTA synthesis methodology has further been exploited to investigate the impact of the improved device characteristics of FD SOI MOSFET's, i.e. smaller subthreshold swing, body factor and parasitic capacitances, on the performances of several basic OTA architectures. We have found that FD SOI CMOS has the potential to boost the speed, accuracy, power and area performances of 1- and 2-stage operational amplifiers well over bulk implementations, especially when moderate inversion operation of the active devices is considered, as is common in LVLP circuits. By demonstrating the great potential of FD SOI CMOS for high-performance analog and mixed-mode analog-digital low-voltage low-power applications, our study has opened a whole new field of applications for this technology.

Furthermore, our synthesis procedure has been successfully extended, in other works, to a number of other CMOS OTA architectures (two-stage Miller OTA43, folded-cascode 2-stage OTA, regulated-cascode 3-stage OTA171, multipath hybrid nested Miller 4-stage OTA, etc.), considering a variety of small- and large-signal specifications (gain, transition frequency, phase margin, settling time, noise, slew rate, distortion, PSRR, CMRR, etc.), and operating conditions (high-temperature169; high-frequency80; capacitive and resistive loads ) as well as applications (instrumentation opamp173; MOSFET-C continuous-time filter172; SC L-A modulator174175, RF carrier detector176, current-mode structures177, capacitive pressure transducers178, radiation-hardness179180). The validity of the synthesis procedure has been successfully demonstrated by the experimental realizations of several of those circuits.

7.2 Microwave oscillators

Two basic oscillator families are used in the microwave frequency domain: series and feedback oscillators181. They are represented in Fig. 73.

Due to high substrate losses and source biasing difficulties, parallel feedback structures were chosen: the first one with active feedback and the second one with passive feedback (inductance). The active feedback structure is represented in Fig. 74. It can be viewed as 2 inverters face to face, with a tank inductor in parallel. The oscillation criteria imposes that the impedance of the inductance ZL should meet the following conditions

Re(ZL+Zo„,)<0

Im(Z£+Zo u , )+0

At 5.8 GHz, for a MOSFET with dimensions 12x(6.6/0.25) in weak inversion, the impedance seen at the inverter inputs is Zou,= -70.6 - J96.3 [Q]. This value is deduced from measurements and simulations on existing devices using models developed at the laboratory. So the needed inductance should have the following characteristics: L ~2.5nH

351


and QL > 4. These performances can be easily achieved on SOI with a spiral inductor136. The circuit schematic is shown in Fig. 74 and, with more details, in Fig. 75.

Z 2 ir

VI

Y2

Z3

I Y3

Fig. 73. Microwave oscillators structures (a) series feedback, (b) parallel feedback.

w • * * 0 W < O

Fig. 74. Active feedback oscillator structure.

The circuits were fabricated on a standard SOI substrate with a resistivity of about 20 Qcm. The transistors are SOI MOSFET's with a channel length of 0.25 urn for the active feedback oscillator and 0.35 um for the inductive feedback oscillator. Capacitors were fabricated using MIM structures, which give the best quality factor for the values needed. Inductors have been realized with square spiral structures using two metal layers.

bt i id id id NWOS:ir<S.*f0.25)

PMOS:12*(6J/fc2S)

Q.

our DULOCK

—o II 1

?^% Fig. 75. Active feedback oscillator circuit.

352


With such a structure, an inductor with a value of 4 nH and a quality factor of 8 can be achieved up to 10 GHz.

7.2.1. Circuit measurements and discussion

Circuits are measured on-wafer with coplanar probes having a pitch of 150 pm and a DC probe allowing on-wafer circuit biasing. The oscillator output is connected to a spectrum analyzer having an input impedance of 50 Q. A part of the measurements are presented in Fig. 76 (output power) and Fig. 77 (output power and fosc vs. Bias voltage). The active feedback oscillator shows a maximum output power of-19 dBm with a bias voltage of 1.4 V and a total current of 3.44 mA. (and 1.36 mA for 1.2 V) for a total power consumption of 4.8 mW. So a drain-source current of about 900 uA drives each transistor. These results can be compared with those in Refs. 183,184,185. It has however to be kept in mind that the transistors (mainly pMOS) were not optimized at the time the layout was produced due to a fabrication problem in the previous process. The pMOS transistors operate in saturation, so it should be possible to reduce the bias voltage probably to near 1 V by optimizing their behavior. A recent paper presents RF front-end circuits on 0.2 |i.m SOI, operating at 0.5 V. This very low voltage is obtained by using undoped-channel MOSFET's186.

7.2.2. Conclusions

Classical microwave oscillator structures have been successfully adapted to the design of integrated oscillators on SOI substrate. The results obtained demonstrate the possibility to reduce effectively the number of devices used and the bias voltage to near 1 V, which follows the current trend in circuit design for wireless communications. Further results could be obtained by optimizing the MOSFET performances, such as the pMOS behavior in weak inversion as well as the gate resistance, which is critical for the device transition frequency. This could lead to an increase of the oscillation frequency or a decrease of the bias voltage.

8. Conclusion

The results presented in this paper show the opportunity offered by the SOI CMOS technology for high frequency applications. This technology can be regarded as very attractive and mature for the realization of low-power-low voltage digital as well as RF and microwave analog circuits. The co-integration of both analog and digital circuits on the same wafer, due to low crosstalk, makes a step further in the direction of the "single chip receiver".

353


-15r

-20 j -

-25

- 3 0 -

1 - 3 5 -co •o " 1 - 4 0

3

o

-45

inductive feedback

5.3

active feedback

W^ 'Jw#W4*4*rt^ 5.4 5.5 5.6 5.7

Frequency [GHz] 5.8 5.9

Fig. 76. Spectral behavior for passive and active parallel feedback oscillators.

if25

m

-

c--""

—e— P out

o I OSC

,^>

/ / /

/ /

i

\ âr"** avtiput power

oscillation frequency \

5.8

5.78

5.76

5.74

5.72 Jg

P

566

5.64

5.62

Fig. 77. Output RF power and oscillation frequency versus bias voltage for the active feedback oscillator using a spiral inductor of 4 nH.

The latest generation of SOI MOSFET's presents very good properties for high frequency operations: cut off frequencies as high as 70 GHz have been measured for silicided 0.25 Jim gate length transistors. Submicron technology brings SOI far into the microwave range. Oscillators and amplifier applications have been realized in the range of 5 to 10 GHz.

Furthermore, accurate models become available for passive elements as well as for the transistors, for low and for high frequencies. This opens the way to a wider use of CMOS SOI, provided a higher number of SOI wafers becomes available.

354


Acknowledgement

The research performed at UCL on the subject covered by this paper has been partially funded by various contracts, national as well as international, such as two "Action de Recherche Concertee" from Communaute Franchise de Belgique, various contracts of the Walloon Region and of the EEC. The researchers involved in that work have been funded by these contracts or UCL as well as trough FRIA grants, FNRS grants and EEC post-doctoral grants. The authors would also like to thank the whole technical team of the microelectronics and the microwave laboratory.

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Intl. High Temperature Conf, Charlotte NC, pp. 11.21-26, June 1994. 169. J.-P. Eggermont, et al., "Design of SOI CMOS operational amplifiers for applications up to

300°C", IEEE Journal of Solid-State Circuits, vol.31, pp. 179-186,1996. 170. F. Silveira, D. Flandre, P.G.A. Jespers, "A gm/ID based methodology for the design of CMOS

analog circuits and its application to the synthesis of a Silicon-on-Insulator micropower OTA", IEEE Journal of Solid-State Circuits, vol. 31, pp. 1314-1319,1996.

171. D. Flandre et al., "Improved synthesis of regulated-cascode gain-boosting CMOS stage using symbolic analysis and gm/ID methodology", IEEE Journal of Solid-State Circuits, Special Issue on 22nd ESSCIRC conference, vol. 32, pp. 1006-1012,1997.

172. V. Dessard, B. Gentinne, D. Flandre, "Potential and design of MOSFET-C continuous-time filters in SOI technology", ESSCIRC96, Neuchatel, Suisse, pp 416-419, September 1996.

173. L. Demeus, A. Viviani, D. Flandre, "High-temperature analog instrumentation system in thin-film fully-depleted SOI CMOS technology", 4th Intl. High Temperature Conf, Albuquerque, USA, pp. 51-54, June 1998.

174. Viviani, D. Flandre, P. Jespers, "A SOI-CMOS micro-power first-order Sigma-Delta modulator", Proc. IEEE International SOI Conference, Fort Myers, Florida, pp. 110-111, octobre 1996.

175. A. Viviani, D. Flandre, P. Jespers, "A high-temperature sigma-delta modulator in thin-film fully-depleted SOI technology", IEE Electronics Letters., vol. 35, n° 9, pp. 749-751,1999.

176. D. Marin, et al., "Aplicacion de la metodologia gm/Id: Diseno de un detector de portadora para RF en tecnologia SOI", X I Congreso de Diseno de Circuitos Integrados , novembre 1996.

177. J. Sabadell, et al., "Current-mode SOI technology based Tow-Thomas filter", MIXDES'97, Poznan, Poland, pp. 359-364, June 1997.

178. T. Loukil, et al., "SOI MOSFETs capacitive pressure transducers for high-temperature applications", HITEN'97, Manchester, England, pp. 231-235, September 1997.

179. A. Vandooren, et al., "Performance of gamma-irradiated Gate-All-Around SOI MOS OTA amplifiers", Proc. IEEE International SOI Conference, Tenya Lodge, CA, pp. 62-63, October 1997.

180. A. Vandooren, J.-P. Colinge, D. Flandre, "Gate-All-Around OTAs for Rad-hard and high-temperature analog applications", IEEE Trans, on Nuclear Science, vol. 46, pp. 1242-1249, 1999.

181. L. Larson, RF and Microwave Circuit Design for Wireless Communications, Artech House, Boston, 1996.

182. K. Kurokawa, "Some basic characteristics of broadband negative resistance oscillator circuits", BellSyst. Techn. Jl, vol. 48, pp. 1937-1955, July 1969.

183. P. Kinget, R. Frye, "A 2.4 GHz CMOS VCO with MCM-inductor", ERSSCC98, pp 364-367, September 1998.

184. J.-O. Plouchart et al., "Fully-Monolithic 3V SiGe Differential Voltage-Controlled Oscillators for 5GHz and 17GHz Wireless Applications", ERSSCC98, pp 332-335, September 1998.

185. J. Craninckx, M. Steyaert, "A 1.8-GHz Low-Phase-Noise CMOS VCO Using Optimized Hollow Spiral Inductors", IEEE Jl. Solid-State Circuits, vol. 32, n°5, pp 736-744,1997.

186. M. Harada et al., "2 GHz RF front-end circuits in CMOS/SIMOX operating at an extremely low voltage of 0.5V", IEEEJI. Solid-State Circuits, vol. 35, n°12, pp. 2000-2004, 2000.

362


RF CMOS RELIABILITY

SASAN NASEH and M. JAMAL DEEN Department of Electrical and Computer Engineering

McMaster University, Hamilton, Ontario, Canada L8S 4K1 E-mail: jamal@mcmaster. ca

In this chapter the effects of hot carrier on the reliability of NMOS transistors are investigated. First, it is explained why the hot carrier issue can be important in RF CMOS circuits. Important mechanisms of hot carrier generation are reviewed and some of the techniques used in the measurement of hot carrier damages are explained. Next, results of measurement of DC hot carrier stress on the NMOS transistors are presented. The main focus here is the RF performance of the NMOS devices and circuits made of them, but DC parameters of the device such as its I-V characteristics and threshold voltage are presented, as they directly affect the RF performance. Finally, using the measurements of hot carrier effects on single NMOS transistors, the effects of hot carriers on three parameters of a low noise amplifier, matching, power gain and stability, are predicted using circuit simulation.

1. Introduction

In recent years, the tremendous progress in personal and wireless communication has

pushed the development of RF circuits. At the same time, the trend is toward increased

integration to make the electronic equipment more compact and to reduce the cost. There

fore, reducing the dimensions of single devices, e. g., transistors, and placing increasingly

more functional blocks on a single chip have been the natural option. Today CMOS is the

major technology used for most of the digital and many analog integrated circuits (IC's).

In communication circuits, while all digital signal processing steps and many low fre

quency analog functions are already placed in one chip, the next step is to integrate the RF

stage onto the same chip. The general guidelines for reducing the device size have been

investigated and reported. According to these guidelines, by reducing the channel length

L, channel width W, oxide thickness tox and power supply Vdd by a scaling factor of K, and

increasing the doping concentration in the channel Nsub by the same factor, it is possible to

have the same density of current per unit of channel width in moderate and strong inver

sion as that of the unsealed device, and have the same strength of electric field inside the

device. This reduction in the MOS transistor's channel length has increased its unity-gain

frequency thus making MOS transistors very attractive to use in radio frequency inte

grated circuits (RFICs) to complement its use already in base-band circuits. ' '

However, the reduction of the dimensions of the MOS devices brings new problems

associated with the short channel length.6 In the actual scaling, the power supply is not

reduced to the same proportion as the geometrical dimensions of the device1. One reason

for this is that by keeping the voltage value higher, it is possible to obtain higher operation

363

1250 5. Naseh & M. J. Deen

speed. Another reason for keeping the power supply high is that it is not desirable to reduce the threshold voltage to very low levels, in which case the leakage current in the subthreshold region would become very high. Therefore, the power supply is kept high enough above the threshold voltage. As a result of keeping the power supply at relatively high values in comparison to what it should be according to the scaling rules, strong electric fields are created inside the device which in turn will lead to generation of hot carriers. This issue becomes more important as the devices dimensions become smaller.

Even at power supply voltages low enough so that qVdd is less than both threshold energy for impact ionization and Si-Si02 barrier height, device degradation due to hot carriers has been reported. '

Therefore, it is necessary to investigate the problems caused by hot carriers on the way to develop CMOS RF devices and integrated circuits. In the next sections the basic operation of MOSFET and some of the major mechanisms of hot-carrier generation are reviewed.

In the next section the physical damages to the structure of a MOS transistor caused by hot carriers are described and the important mechanisms of hot carrier generation are explained based on MOS transistor operation. In section 3 the important experimental techniques uses for investigating the effect of hot carriers in MOS transistors and MOS capacitors are reviewed. In section 4 the results of hot carrier measurements on DC and RF performance of single NMOS transistors are presented. Finally, in section 5 the effects of hot carriers on some of the parameters of a low noise amplifier made of NMOSFET are explained.

2. Hot Carriers Origin and Their Effects on the Device

Hot carrier generation and the effects on the characteristics of MOS transistors have been known for long time.9'10'11 Hot carriers are a result of the high electric fields present inside the MOSFETs which naturally appear when high biasing voltages are applied to a short-channel length device. Therefore, the mechanisms of hot carrier generation are explained based on the operating conditions of MOS transistors.

By applying a potential difference Vg between the gate and substrate terminals greater than the threshold voltage of the MOS transistor (Vth), a layer of charge called the inversion layer or channel comprised of minority carriers of the substrate appears underneath the gate oxide. At this condition, if a potential difference Vds is applied across the drain and source of the transistor, a current will flow through the channel similar to a resistor. As long as the value of Vds is small, the charge distribution in the inversion layer is almost uniform along the channel. For this operating condition, the electric field in the direction of the drain toward the source, or the lateral electric field, is almost uniform and is

364

RF CMOS Reliability 1251

Efa^V^L in which L is the length of the channel. This operating condition, is called lin

ear or triode region of operation and is shown in Figure 1 (a).

As Vds increases, the resulting potential at the silicon surface near drain decreases. As a result of this, the carrier density in the inversion layer near the drain decreases. As V^ increases further, it reaches to a value of V^.^,, at which the inversion layer near drain disappears and a depletion region will form next to the drain.

By increasing V& even further, this depletion region extends toward the source region. This depleted region is called the pinch off-region. At this condition, the voltage V^ is distributed non-uniformly across the channel with most of the excess voltage Vds'^ds-sat dropping across the pinch-off region. This operating condition is called the saturation region of operation and it is shown in Figure 1 (b).

jrx (a): linear mode

3-^ source

X

- V ^ - V f c

p substrate

X (b): saturation mode

1 - V^V. -V j ,

C 3 ^ avalanche plasma drain

X p substrate

Fig. 1. Hot carrier generation. All voltages are referred to the source and Vs = 0.

The current flowing through the channel can be calculated, and to a first order 12: approximation it is:

W\i„Cnrr 2 ,

1L L x « (1)

in the linear mode, and:

WKCnx 2 ld 2L (yg Vth) (2)

365

1252 S. Naseh & M. J. Deen

in the saturation mode of operation. In these relations, W is the channel width, nn is the electron mobility in the inversion layer and Cox is the capacitance per unit area between gate and substrate.

In the two operating conditions shown in Figures 1 (a) and (b) which are the two main situations encountered in analog circuits, electrons can gain high energies in the electric field. It is possible that carriers with high energy, also called hot-carriers, may have a high enough energy so that they overcome the potential barrier between the silicon and the silicon dioxide and penetrate into the gate oxide. Some of them may get stuck inside the gate oxide at defect sites or traps, denoted by Nox. They may also generate new defects in the oxide after breaking the atomic bonds.13'14 Hot carriers can also break the atomic bonds at the interface of the silicon substrate and the gate oxide and generate new traps which are called interface traps, denoted by Nit. The difference between these two types of traps is that interface traps can be in charge exchange with channel whereas the oxide traps cannot be in direct charge exchange with charges in the channel.

The two types of change appearing in the device structure as a result of hot carriers are considered as damage to the gate oxide and affect the device's electrical parameters. The atomic structures of some of the well-known damages that can appear in the bulk of the oxide are shown in Figure 2.14 Silicon dangling bond shown in Figure 2 (a) in the form of [(SiO)3=Si-j which is thought to be an electron trap. The dangling, or non-bridging oxygen bond (SiO)3=Si-0- shown in Figure 2 (b) is a hole trap. The oxygen vacancy V0 or the double silicon dangling bonds [(SiO)3=Si- •SisCSiO^] shown in Figure 2 (c), can be a hole trap at the oxygen vacancy site.

In the literature14'15, the defect shown in Figure 2 (a) is referred to as E' center by some researchers while others use the E' center to describe oxygen vacancy shown in Figure 2 (c).

I 1 . i I Si Si Si Si

0 0 0 0

Si O Si» O Si O Si — S i o Si--Si O—Si

O \ > O \ ) 1 I j J Si Si Si

T a) Silicon dangling bond b) Oxygen dangling bond c) Oxygen vacancy V 0

Fig. 2. Atomic structures of defects in the bulk of silicon dioxide.

At the silicon-silicon dioxide interface, a family of traps generally known as Pj, centers

exist which are silicon dangling bonds where silicon is bonded to three other silicon

366


atoms, Si3=Si-, and the other three silicon atoms are in the substrate. This interface traps

is shown in Figure 3.

oxide

/ 1 x. substrate —Si P S i -

Si

I Fig. 3. Atomic structures of defects at silicon-silicon dioxide interface.

In the following section, some of the different mechanisms by which hot carriers can damage the device are explained in more detail.

2.1. Channel hot-electrons (CHE)

As mentioned before, one of the damages caused by hot carriers is trapped charges in the gate oxide. These charges are carriers in the channel, which on their way from source to drain gain high enough energy so that they can overcome gate oxide potential barrier 4>6

and penetrate into the gate oxide. The event of a carrier gaining energy and entering the gate oxide is a statistical phenomenon. A model called lucky-electron model, has been developed.17 This model takes into account several probability factors in order to calculate the gate current Ig which is representative of hot carriers entering the gate oxide.'7

According to this model, as carriers are accelerated by the lateral electric field in the channel, their move is hindered by scattering caused by the lattice. Some types of scattering called optical phonon and impact ionization scattering cause the carriers to loose their energy and are called inelastic scattering. The probability of a carrier traveling a distance d without experiencing any energy robbing scattering is exp(-dfk) in which X is called the scattering effective mean free path. Some other types of scattering called acoustical phonon scattering, do not cause the carriers to loose their energy significantly. The acoustical phonon scattering, also called elastic scattering, only causes redirection of carriers. Similar to inelastic scattering, a parameter Xr is defined as the redirecting scattering mean free path, and the probability of a carrier redirection over the differential distance dx is dx/ Xr In the redirection process carriers can isotropicly be redirected to all directions and part of them will be directed toward the silicon-silicon dioxide interface. Again, for carriers directed toward the interface, there is a probability involved that some of them reach the interface without any energy robbing scattering.

Finally, the probability for carriers which have entered the gate oxide to reach the gate terminal is P(E0X) in which Eox is the electric field inside the oxide. Since the events involved for a carrier to reach the gate terminal are independent from each other, the over-

367


all probability for one carrier reaching the gate terminal is the product of probabilities of

each single event. The final result of this analysis can be expressed as:

/ „ = / J/** 1 d] * *b

p(Eox>rdx

0 r

(3)

in which P^b is the probability of a carrier gaining energy higher than <t>b and retaining its

momentum when it reaches the interface and is a function of electric field in the channel, L 11

is the channel length, Id is the drain current and / is the gate current. Figure 4 shows a

graphical exhibition of channel hot electron mechanism.

JTX

v „

^

VH

p substrate drain

Fig. 4. Channel hot electron generation. The dashed line shows the border between depletion region and neutral bulk.

3>

-9

io r

-10 10

10

a io

10

10 J L J L 0 2 4 6 8 10 12

V c > V

Fig. 5. Measured gate current versus gate voltage (from reference 18).

368


Experimental verification of this model has been reported and shows good agreement with measurement.17 The gate current /„ can be an indicator for the amount of charge trapped inside the gate oxide. A sample measurement of/„ versus gate voltage V„ for constant Vds is shown in Figure 5.

The shape of the Ig versus Vds can be qualitatively explained as follows. At low values of V the transistor is in deep saturation which means there is a pinch-off region formed near drain where a high lateral electric field is present. But at low values of Vg, the electric field in the oxide near drain is in a direction which inhibits collection of carriers. As Vg

increases, the vertical electric field in the gate oxide near drain becomes favorable for collection of carriers, but at the same time transistor moves toward the linear region from the pinch-off region, and therefore the lateral electric field in the pinch-off region gradually disappears. Since variation of lateral and vertical electric fields are opposite to each other there is a point where Ig has a maximum. The value of Vg at which this maximum happens is V^Vfr

As mentioned in the introduction, however, there have been observations of hot carrier effects even when power supply is low enough so that qVdd is less than both threshold energy for impact ionization and Si-Si02 barrier height.7'8 This is not possible according to the simple lucky electron model explained above. Therefore a new model was introduced which assumes that electrons are in quasithermal equilibrium with the electric field and therefore energy distribution of electrons follows the Fermi-Dirac statistics.19 This energy distribution can be approximated by Maxwell-Boltzmann distribution as in the case of hot carriers we are mostly interested in the high energy region of the distribution. According to these energy distributions, there is a certain probability that the electron may gain any energy. Therefore it is possible that electrons have energies above the impact ionization threshold energy or Si-SiC>2 barrier height. The improvement provided by quasithermal equilibrium approach has been incorporated into the lucky electron model.20

2.2. Drain avalanche hot-carriers (DAHC)

Another effect that can be caused by energetic carriers in the channel is that carriers on their way toward drain collide with the lattice atoms and generate new electron and hole pairs. These electron and hole pairs can also gain high energy in the electric field and produce new electron-hole pairs, similar to avalanche process in a reversed biased p-n junction. This process is shown in Figure 1 b in the avalanche plasma. During the same process, the energetic carriers can impinge on the atomic bonds at the interface of the substrate and gate oxide or inside the oxide, and break them, thus creating dangling bonds. As a result, new electronic states Nit are created at the interface and these Nit can affect the electrical performance of the device.18

369

1256 S. Naseh. & M. J. Deen

In a NMOS transistor, the extra electrons which are generated by the avalanche process are absorbed by drain, and the generated holes are absorbed by substrate terminal which form the substrate current component Isub. Typical measurement results of Isub versus Vg at various Vjs a NMOS transistor are shown in Figure 6.

0.30 0.40 0.50 0.60 0.70

vgoo

Fig. 6. Measured substrate current versus gate voltage.

As is shown in Figure 6, the variation ofIsub versus V„ for a constant V^s has a maximum. The explanation is as follows. It is known that generation of electron-hole pairs in an avalanche process is proportional to both strength of electric field and the number of primary carriers initially flowing in the channel, that is, carriers which originally flow in the channel and generate new electron-hole pairs by colliding with the lattice atoms. For low values of Vg above threshold, the transistor is in deep saturation and a pinch-off region is formed near the drain which results in a strong lateral electric field in that region. Also, at low values of V the drain current Id is low. As V increases Ij increases but transistor comes out of saturation region gradually. In other words, the variations of the number of primary carriers and the strength of the electric field in the channel with respect to Vg are opposite to each other. This causes that a maximum value for Isub appears at some particular value of Vg It has been observed that this maximum usually happens at about Vg=VJ2. It is reported that the biasing condition which causes maximum Isub is where maximum damage is generated in NMOSFETs.18

370


2.3. Substrate hot electrons (SHE)

Unlike the cases of CHE and DAHC, which were caused by lateral electric field in channel, SHE are caused by the vertical electric field between gate and substrate. The electrons which are thermally generated in the region below the gate, drift toward the silicon-silicon dioxide interface and gain kinetic energy in the electric field below the gate.

^ ^

p substrate

^ _ ^ ^ i _ ^ _ _ _ ^ _ ^ ! _ ? ^ _ _ -* vd

drain

Fig. 7. Substrate hot electron generation.

This is shown in Figure 7. Some of these electrons penetrate into oxide and cause a uniform distribution of trapped charge in the oxide. SHE is not a major problem in short channel devices as most of the electrons are absorbed into source and drain region and a smaller fraction them reaches the device surface, compared to the long channel devices.

2.4. Fowler-Nordheim tunneling (F-N)

A mechanism by which electrons can be injected into the gate oxide is tunneling. If a strong electric field is applied between metal plate (gate in a MOSFET), and bulk or substrate of a MOS structure so that direction of electric field is in favor of attracting electrons from bulk toward the gate, electrons may tunnel from the conduction band of the silicon to the conduction band of the silicon dioxide. This mechanism of tunneling is called Fowler-Nordheim tunneling (F-N). The comparison of F-N tunneling and direct tunneling is shown in Figure 8.

The current density between gate and substrate is shown both experimentally21 and theoretically to be in the following form:

-B/E

J = AKs (4)

in which constants A and B depend on the electron's effective mass and the potential barrier height at silicon-silicon dioxide interface, and Eox is the electric field in the gate oxide.

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This current is shown to cause degradation of the gate oxide and eventually its breakdown.22

Fowler-Nordheim tunneling direct tunneling

Metal Si02 Si Metal

Fig. 8. Comparison of Fowler-Nordheim tunneling and direct tunneling.

Si02

In MOS transistors, as the gate oxide becomes thinner, F-N tunneling can be important. Unlike CHE and DAHC mechanisms which were caused by the lateral electric field in the channel, F-N tunneling is caused by the vertical electric field between the gate and the channel. Therefore, if a large voltage is applied to the gate, this mechanism of current can be important especially near the source which the highest electric field between gate and substrate exists.

2.5. Hot carrier degradation ofMOSFETs

Different opinions has been suggested about the mechanism of device degradation as result of hot carriers. In some researches, only trapped charges are considered as the source of device degradation.10'11'23'24'25 In some others, interface trap generation is considered as the reason for device degradation.13'18'26'27'28,29'30'31'32'33'34 There are as well reports where both kinds of damages are considered to be involved in device degrada-tion.35'36'37

Although the idea that only electron injection being responsible for NMOSFET degradation has been reported,27'28 in most of the researches, it has been proposed that hot holes as well as hot electrons are involved in the process of interface states generation at the silicon-silicon dioxide interface.13'29'30'38 It is observed that the maximum interface state generation in NMOSFETs coincides with the maximum Isub condition, and in PMOSFETs the maximum interface traps generation happens at the condition V^Vj which coincides with maximum hot hole injection into the gate oxide.29 This observation confirms that hot holes are important in interface state generation.

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2.6. Lightly doped drain MOSFETs

In order to reduce the hot-carrier effect in the MOS transistors, the doping profile of the drain and source are modified in a way that electric field in the pinch off region is reduced. By introducing a narrow, lightly doped n-type region between the channel and the n+ drain and n+ source diffusion regions the so called Lightly Doped Drain (LDD) MOSFET is created. In this structure the high electric field in the drain pinch off region is reduced by spreading it into the n- region, similar to spreading of electric field in a lightly doped p-n junction. Therefore, it is possible to have shorter channel length with the same Vds voltage, or use higher power supply voltages, without having too high electric field in the pinch off region. This structure is shown in Figure 9.

t gate

n+

LDD regions

p substrate

Fig. 9. LDD MOSFET structure.

As a result of reduction of electric field, the impact ionization is reduced in LDD MOSFETs compared to the conventional MOS transistor structure. For the same reason, avalanche breakdown also happens at higher Vds voltages. The LDD structure also provides an improvement in the punchthrough voltage of the device, and alleviates the fall off in the threshold voltage due to short channel effects. On the other hand, the introduction of the lightly doped region adds to the ohmic resistance in series with drain and source, but this effect is not seriously affecting the device performance.39

3. Experimental Tools for Hot Carrier Damage Detection

For the purpose of studying effects of hot carriers on MOS transistors, experimental tools are required to investigate the damage caused by hot carriers. One of the important experimental technique used in the study of the hot carrier damage in MOS transistors is the charge pumping measurement. Charge pumping is a powerful technique applied to a MOS transistor which is used for determining the interface traps distribution in the energy band gap and also their spatial profile in the channel.

Two other types of measurements, C-V measurement and floating-gate measurement, will also be discussed briefly. C-V measurement, a technique for investigation of the sili-

373


con-silicon dioxide interface quality in MOS capacitor, can also be used to study the effect of hot-carriers on the MOSFETs by measuring the device parasitic capacitors Cgd and Cgs. Floating-gate measurement is a technique by which the gate current is measured and it is possible to distinguish whether it is caused by hole injection or electron injection.

3.1. Charge pumping method

Charge pumping technique as a mean to study the interface traps at the interface of the silicon substrate and gate oxide of a MOSFET was reported for the first time by the authors of.40 The experimental setup and circuit connection for charge pumping experiment is shown in Figure 10.

V

p substrate

XT ^reverse DC AMMETER

ISL. ^

pulse generator

JL /\ / \

£J

Fig. 10. Charge pumping measurement setup.

In this experiment, the drain and the source of the MOS transistor are connected together and a reverse voltage is applied between drain/source and substrate terminals. A pulse generator applies voltage pulses between the gate and the substrate in a way that it switches the surface underneath the gate between inversion and accumulation. During inversion, a layer of charge made of substrate minority carriers appear underneath the gate. These charges mainly originate from the source and drain diffusion regions. Some of these carriers fill the fast electronic states at the interface of the substrate and the gate oxide. When the gate voltage changes so that surface underneath the gate returns into the accumulation state, the free minority carriers which form the inversion layer return to the source and drain diffusion regions. The charges trapped in the interface states recombine with the substrate majority charges. Also, a small fraction of the free carriers in the inversion layer may recombine with the majority charges of the substrate too. These two com-

374


ponents are called interface trap component and geometric component, respectively, and together, they form a current which flows from substrate to the drain and the source. Therefore, this current, which is called charge pumping current, can be written as:40

hp=MGWit-aC0X(Vgh-Vth)) (5)

in which: / =charge pumping current, / = frequency of the applied gate pulse, AG = gate area, q = electron charge Nit = fast interface states density, a = fraction of free carriers under gate which recombine with substrate majority carriers, Cox = gate oxide capacitance per unit area, Vgh = gate voltage during the inversion and, Vth - threshold voltage.

Usually the waveform of the pulse applied to the gate is chosen in a way that the free carriers have enough time to return to the source and drain, and therefore geometric component of the charge pumping current is small compared to the interface trap component. Therefore, / can be a measure of the density of the fast interface traps under the gate. This forms the basis of the charge pumping technique for studying the interface traps in MOS transistors. In interpreting the result of charge pumping experiment, it is important to consider the kinetics of the charging and discharging of the interface traps.41 Therefore, in the following section, the capture and emission processes are briefly explained.

Interface traps can be acceptor type or donor type. Acceptor traps are the traps which are either in neutral state or negatively charged, and donor traps are traps which can be either in neutral state or positively charged. A trap can charge or discharge through both emission and capture processes at the same time. For example, a neutral acceptor trap can capture an electron or emit a hole, i. e., receive an electron from the valence band and it becomes negatively charged. A negatively charged acceptor state can emit an electron or capture a hole, i. e., send an electron to the valence band, and it becomes neutral. The probability per unit time that an interface state can emit (e„ ) or capture (c ) a charge using the Shockley-Read-Hall model is:42'43

Cn = anvthns' (6>

*n = anvthnl> ( ? )

cp = apV,hPs ( 8 )

and:

% = apvthPi (9)

375


in which o~n and ap are the capture cross section of electrons and holes, respectively; v , is the thermal velocity of the carriers; given by:

vth = (3kT/m*)W2 (10)

in which m* is the effective mass of carrier, and ns andps are the density of electrons and holes at the surface; and:

-{E'-E-)/kT (11)

. ( * , - * • > / « • ( i 2 )

in which nt is the intrinsic density of electrons, E{ is the intrinsic Fermi energy and E, is the energy of the trap in the band gap. ny is the electron concentration in the conduction band and p] is the hole concentration in the valence band that would exist, if the trap energy E, coincided with the Fermi energy EF, and the Boltzmann approximation of the Fermi function is used. If an is much larger than crp, then the trap has a much higher tendency to capture electrons than to capture holes. These sort of traps are considered as electron traps. If on is much smaller than op, then the trap is considered as a hole trap, and if 0n and dp are comparable to each other, then the trap is called generation-recombination center.

Using the expressions (6) to (9), it can be shown that if the surface conditions are suddenly changed so that interface states change their charge state, the transition from neutral to negatively charged states occurs exponentially with the time constant:

and the time constant for the transition from the negative state to neutral state will be:

t = l / (c„ + en). (14)

in which traps are considered as acceptor type. In the charge pumping experiment, if Ton

and T0jr defined as the length of time gate that voltage is kept at V h and Vgi, respectively, are sufficiently long, then the interface traps will reach to an equilibrium with the free carriers in the channel. Also, if rise time Tr and fall time Tf of the pulse applied to the gate are short enough, the interface traps will not have time to emit any charge. In this case, the charging and discharging of traps are done by capture of electrons in inversion and capture of holes in accumulation, respectively.

However, if the rise time of the gate voltage is not short, then the interface traps may emit holes during the rise time. The traps which charge this way will not be able to capture electrons as the inversion layer forms in the channel, and therefore they do not contribute to the charge pumping current. In order to simplify the analysis, it may be assumed that free carriers in the channel are in equilibrium with the gate voltage, that is, free electrons

376


and holes in the channel are only a function of gate voltage and independent of time. But the interface states are not in equilibrium with the free carriers in the channel and their charge exchange process has the time constants explained before. As the gate voltage varies, when it is slightly above the flat band voltage, it can be assumed that the hole emission process is dominating, and as gate voltages increasingly becomes closer to the threshold voltage, then electron capture becomes dominant. It can be assumed that the interface traps below a certain level Eemh which have a short time constant are negatively charged by emitting holes, and therefore, they do not contribute in the charge pumping. Therefore Eemh sets a lower limit for the energy levels which can be covered in the charge pumping process.

During the fall time, as the gate voltage becomes less than the threshold voltage the inversion channel gradually disappears. The interface traps which emit electron before the channel has disappeared will not contribute to the charge pumping current as these charges are collected by the drain and the source terminals. But the interface traps which emit their electrons after the channel has disappeared will contribute to the charge pumping because the emitted electrons recombine with the majority carriers (holes) in the substrate. Similar to the rise time, an energy level can be assumed above which the electron emission time constant is so short that they emit electrons before the inversion layer disappears, and therefore, they do not contribute in the charge pumping current. This sets an upper limit for the energy level which contribute to the charge pumping current.

A similar analysis can be performed for the case of donor traps at interface.

The charge emission and capture by interface traps which was explained need to be considered in order to be able to consistently explain the observations in charge pumping measurements. The basic experimental setup which now is used for charge pumping measurement has stayed the same. But different schemes for applying the gate voltage have been suggested by different groups in order to improve the measurement. 4

In one class of charge pumping experiments known as variable amplitude mode, the base level voltage applied to the gate, Vgi, is kept constant and the high value of the voltage pulse, Vgh, is increased gradually. In the case of NMOSFET, Vgj value is chosen below flat-band voltage Vpg so that channel is in accumulation. By gradually increasing the amplitude of the pulse, so that Vgh becomes greater than the flat-band voltage, the transistor moves into depletion and as Vgh increases to values above threshold voltage, the channel goes into inversion. A typical charge pumping current versus Vgh is shown in Figure 11. The regions 1, 2 and 3 specified on the plot correspond to values of Vgh<VFB, vFB<vgh<vth anc i vth<vgh' respectively. In region 1, at both low and high level of gate voltage channel is in accumulation therefore none of the interface states can capture any electron and the charge pumping current is zero. In region 2, as Vgh increases, those regions of the channel close to the drain and the source moves into the saturation region before the rest of the channel and therefore these parts contribute to charge pumping

377


"gh

Fig. 11. Charge pumping current in variable amplitude mode.

current. As Vgf, increases further, a larger part of the channel moves into inversion and charge pumping current increases. At region 3, Icp becomes almost flat. The slight increase in Icp by Vû is due to small increase in surface potential with the V„^ increase.

In another class of charge pumping measurement the amplitude of the pulse applied to the gate is kept constant and its base level Vgi is swept from values below flat-band voltage to above threshold voltage. Icp versus Vgl in this mode of charge pumping is shown in Figure 12.

cp A

Fig. 12. Charge pumping current in variable base level mode.

378


In this method of charge pumping, in regions 1 and 5, for the whole period of the pulse, the transistor is in accumulation or in inversion, respectively, and interface traps do not exchange any charge with the substrate. Regions 2 and 3 are similar to the regions 2 and 3 of the variable amplitude mode. In region 4, it can be considered that device is switched between strong inversion and weak accumulation modes. As Vgt increases further, the accumulation state becomes weaker and weaker and turns into inversion. Therefore, a lesser number of interface trap can exchange charge with the substrate majority carriers (holes).

The spatial distribution of traps can also be studied with charge pumping measurement. By varying the reverse voltage between the source/drain and the substrate, the effective length of the channel changes, which causes a change in the Icp. This change can be used to study the profile of the traps in the channel. In a modified version of this technique, the reverse biases between the drain-substrate and source-substrate are independent from each other.45'4 In this way, it is possible to study the profile of interface traps at drain side and source side separately.

A more detailed review of the charge pumping technique can be found in reference 42. Other papers that combine charge pumping with other experimental techniques to provide valuable information on the location and quantification of defects in stressed MOSFETs are references 47, 48,49, 50 and 51.

3.2. C-V measurementfor studying the quality of the oxide interface

As mentioned at the beginning of this section, measurement of the MOS capacitance versus the DC voltage across it, V„, can be used to study the quality of the silicon-silicon dioxide interface. Assuming a p-type substrate, as the DC voltage is slowly increased from values below the flat band voltages, VFB, toward values above the threshold voltage, MOS capacitor changes from accumulation toward depletion and eventually moves into inversion. The small signal capacitance of the MOS is defined as:

C = 4 (15)

where QT is the amount of total charge on the gate of the MOS capacitor. When the device is in accumulation, a layer of majority carriers, holes, accumulates under the gate at the silicon-silicon dioxide interface. At this condition, there is little band bending in the substrate and there is no electric field in the substrate. The capacitance value is equal to the oxide capacitance Cox. As Vg increases above VFB, a depletion region develops in the substrate underneath the gate. The capacitance at this condition is comprised of the series combination of the oxide capacitance and depletion region capacitance denoted by Cs, therefore the total capacitance is less than Cox. As V„ is increased toward the threshold

379


voltage, Vth, depletion layer reaches to its maximum depth, which for values of V^V,/, stays almost unchanged. At the same time an inversion layer develops underneath the gate. For this condition of Vg>Vth, the value of the capacitance again becomes the same as oxide capacitance Cox.

In the above explanation, it was assumed that no interface traps were present. If they are present, then they will charge and discharge as the surface potential changes due to the change in Vg. Therefore, they act as a capacitor Cit parallel to the depletion layer capacitor

So far, the variation of gate voltage V„ was considered to be slow enough so that the charge in the inversion layer was able to follow its variation. The charges in the inversion layer are supplied by the diffusion of the minority carriers, electrons, in the substrate and the thermal generation of electron and hole pairs in the substrate.12 These two process have a limited rate, and if the variation of Vg is fast, then the inversion layer may not be able to follow V„. In this condition, the depletion layer charge changes in response to the variation of the gate voltage. If the variation of the Vg is fast enough, then the interface traps will not respond to Vg either, and the total capacitance will be the series of the oxide capacitance and depletion layer capacitance.

Therefore, by measuring the low frequency capacitance C^-and high frequency capacitance Qy, it is possible to obtain the capacitance due to interface traps Cit:

52

cit = (i/clf-i/coxrl-(i/chf-\/cox)-

1 (16)

Cit is a function of surface potential \|/s, and therefore gate voltage. The relation between Cit and the interface trap density Nit is:

ctM = ^ « « P , ) (1?)

in which \|/s=<ps-(pB and <pB=(EF-Ej)/q is the difference between extrinsic Fermi level and intrinsic Fermi level. Therefore, the meaning of <ps in the above relation is the relative position of the interface traps with respect to extrinsic Fermi level, as is shown in Figure 13.

Metal

w

iO-,

Ec

' * ,' m E,

Si

Fig. 13. Energy band diagram in a MOS structure for n-type silicon.

380


As was mentioned above, the capacitance is extracted in terms of the surface potential. Therefore, it is necessary to know the surface potential in terms of gate voltage. The methods for band bending measurement and also more detailed explanation about C-V measurement can be found in.52

3.3. Floating gate measurement

This technique is a simple and sensitive method used for measuring the small gate current which is caused by injection of carriers from substrate into the oxide. The device under test (DUT) is first biased at the operating point which is to be studied. At a point in time assigned zero, t=0, the contact to the gate is disconnected. If experiment is done with on-wafer devices, this is done simply by lifting the gate probe. The gate capacitor which is already charged to the Vg preserves this voltage and the drain current Id continue to flow in the channel. As a result of the current which flows to the gate, Ig, the charge on the gate will change and therefore the gate voltage V„ changes. Consequently, the drain current Ij changes according to the transistor's I-V characteristics. Therefore, I-V characteristics should be recorded before the experiment and it will be used as a reference in order to find the value of Vg. Also, the value of the gate capacitor should be measured. This capacitor includes all the parasitic capacitors between the gate and other terminals of the transistors. It is usually dominated by the pad capacitor and is independent of the gate voltage. Therefore, the gate current Ig can be calculated using the following relation:

'* = <V ° 8 )

In experiments done on a NMOSFET, it has been observed that for low values of Vg

drain current increases with time whereas for high values of Vg drain current decreases with time.47'48'49,50,51 This implies injection of hot electrons at high values of Vg and injection of hot holes at low values of VgP The possibility of the hot electron injection from the gate into the gate oxide (as opposed to hot hole injection from substrate into the gate oxide) for the case of low VgS is ruled out by an experiment explained as follows. During the floating gate measurement, sometime after the probe on the gate contact has been lifted, the source contact is disconnected for a period of time while Vd is kept unchanged. This interrupts the drain current and no hot hole will be generated. However, since the drain voltage is present which causes a strong electric field in the oxide between drain and gate, no interruption of electron injection into the gate oxide is expected, if this process is present at all. In this case, the gate voltage would have changed during the period the source probe is not connected. In practice, this is not observed and it is concluded that the electron injection from gate to the gate oxide does not exist or is negligible. All the observations in this measurement confirm the hole injection at low gate voltages.53

381


4. Hot Carrier Effects on the NMOSFETs Electrical Performance.

Damages caused by hot carriers change the electrical performance of the device. In circuits made of MOSFETS, when the power supply is applied the transistors, they will be biased at some operating point and electric fields will appear inside the device. As explained before, hot carriers are created as a result of these electric fields and device characteristics change gradually, which in turn, affect the overall performance of the circuit. In order to be able to predict the hot carrier effects on circuit performance, it is useful to study the effects of hot carriers on a single device first. There have been experimental studies on the MOSFETs with both conventional26,28'54'55 and LDD structures47'48'49'50'56'57'61'62 which show how the device parameters change with time when they are under DC hot-carrier stress. The general degradation dynamic in conventional MOSFETs can be explained as:

AVlh = At" (19)

in which threshold voltage could be replaced by transconductance gm or saturation current Id-sat-1°tms relation, the power n is strongly dependent on Vg and has little dependence on Vd. The value of n is around 0.5-0.7 when V^Vdl2 and about 0.2 when V^Vd.

63 The pre-exponential coefficient A is dependent on Vd and the technology. Also, in these studies device life time x is defined as the time required for a certain amount of change to appear in one of the device's parameters such as its threshold voltage or its transconductance. The life time has been found to be proportional to drain current Id and substrate current Isub

as:28

%1A, W

1jub -<p,/<p,

(20)

in which Wis the gate width, (ftit = 3.7 eV is the critical electron energy for generating an interface trap and (p,- = 1.3 eV is the minimum energy that an electron must have to create impact ionization. This relation implies that the higher the level of hot carriers, the faster the change in the device parameters.

In LDD devices, there have been reports of an early fast mode of degradation followed by a slower degradation rate,

47'48>49>50>51 However, as will be shown later the degradation dynamics of the LDD devices measured in this work, which were fabricated with a different technology, and were subject to a different stress condition, typically show a single rate of degradation. Therefore, it is speculated that degradation dynamics can be dependent on the stress condition and fabrication technology. In the following section some important effects of hot carriers on NMOSFETs are presented. The data are the results of hot carrier experiments performed on LDD NMOSFETs fabricated in a 0.18 um technology. Transistors with different sizes were used and all have shown a similar trend.

382


4.1. Creation of hot carrier damage for reliability studies

Single NMOSFETs with the layout shown in Figure 14 were used for the hot carrier stress experiments. This layout can be used for both DC and S-parameter measurements using 3-point probes at input and output.

Substrate |

Gate

Source

Substrate

Drain

Source

Fig. 14. Layout of the device used for hot carrier stress experiments.

To study the effect of hot carriers, first they should be generated in the device. Usually, the level of hot carrier damage caused at the regular operating condition in a circuit is at a low level so that a detectable change in circuit's performance appears only after the circuit has been operating for a long time. Therefore in research works, in order to study the hot carrier effects in a reasonable time, accelerated aging process is used. Expression (20) provides a guideline for the accelerated aging process. According to this relation, by biasing the transistors at an operating point which generates strong electric field inside the device, and consequently a high substrate current Isub, it is possible to reduce the time at which the hot carrier effects can be observed. A typical operating point suitable for this purpose is shown in Figure 15. As the operating mechanism of MOSFET was explained in section 2, by biasing the device at high V&, a strong lateral electric field appears in the channel which leads to impact ionization, and therefore to substrate current Isub. The difference between Id and Is at higher Vds voltages in Figure 15 is the substrate current. The stress conditions used in this work were at the level that generated a substrate current of 5 to 10% of the drain current. By measuring the parameters of the device after each stress period, the time behavior of the hot carrier stress can be examined. The effects of stress on some of these parameters are presented in the next section.

383


20

15

E

5

0 0 1 2 3 4 5 6

Fig. 15. A typical operating point which can be used to apply hot carrier stress.

Since the main focus of this work is the effects of hot carriers on the RF performance of MOS device and circuits, the stress condition used should be representative of a real operating condition. In the next section, when some of the hot carrier effects on a low noise amplifier is studied, it will be shown that the stress condition in Figure 15 is an appropriate condition for that study. In the case of other RF building blocks like oscillators, mixers and power amplifiers, the stress conditions used for the accelerated aging process should be shown to be suitable for the study of real operating condition stress. Since applying a DC stress is convenient, it is used to study the effect of hot carrier stress in RF circuits, and it is assumed that the degradation caused by the DC stress can be used to study the degradation at the real operating conditions. As a qualitative justification of this assumption, it can be stated that regardless of how the damages (i. e., interface states and oxide trapped charges) are inflicted to the transistor, their effect on the device performance would be the same. There have been several reports64'65'66'67 which experimentally confirm that hot carrier damages as a result of AC voltages for LDD devices at different frequencies is the same as stress at quasi static condition, taking into account the different mode of stress as voltages vary, and the effective time at which each mode is applied.

4.2. Effect of hot carrier stress on parameters of a NMOSFET

In Figure 16, drain current Id versus drain-source voltage Vds before and after stress are shown for a constant value of gate voltage Vg and the specified stress condition. The I-V characteristic of the transistor after stress, when drain and source are switched are also

CTCJJ eg eg

shown for comparison/ • ' '

-

V 9

Typical

=0.8 V

stress point

X

L=0.35 \jxn, w=

d

s

=400 (im

384


10

8

I 6 - ° 4

2

0 0 1 2

v d s 0 0

Fig. 16. Comparison of I-V characteristic before and after hot carrier stress.

Difference of the currents before and after stress can be explained qualitatively as follows. The damaged area caused by hot carriers is located at the silicon-silicon dioxide interface near the drain region. For a particular value of gate voltage Vg greater than threshold voltage Vth, when drain-source voltage Vds is low, the transistor is in linear region and the entire length of the channel, including the damaged region, is in inversion. Therefore, the effect of damage on the I-V characteristic of the device appears to the full extent. As Vds increases, the device moves into the saturation region and a pinch-off region appears near drain, which includes part of the damaged region.

As Vfc increases, the pinch-off region extends toward source and a bigger part of damaged region will be placed inside the pinch-off region. Since the electrical characteristics of MOSFETs are determined by the inverted region of the channel, then the effect of damage in the channel decreases for higher Vds and the current gets closer to its value before stress. In the case of the drain and the source interchanged, as long as device is in the linear region, its characteristic is the same as that of forward connection. However, when device moves into the saturation region, since the damaged region is in the inverted part of the channel for all values of Vds, its effect appears on the device I-V characteristics and a strong asymmetry with respect to forward and reverse connection (source and drain terminals interchanged) is observed.

By comparing the I-V characteristic of the forward connection of transistor before and after stress shown in Figure 16, a considerable increase in the slope of the curve in the saturation region is observed. This slope is the output conductance of the transistor, gds, in the small signal model of the transistor. This parameter is important in the performance of

L=0.3 urn, W=120 urn

stress at: V„=3.7 V, V d 3

-

- /

=0.65 V

before stress

2000 s stress

A/ 2000 s stress, reverse connection

385


101

^ 10° O)

<

10"

L=0.3 nm

stress at:

r

• • 6

• 6 A 0

W=120 urn

V =3.7 V, V„=

• • *

• A

0

Vd.=1.5V

0.65 V

8 B S

• Vg=0.95 V

A Vg=0.85V

o V=0.75V 0

1 H i 1 • 1 1 • 1 1 ,

10° 10" 101 102 103

stress time (s)

Fig. 17. Normalized variation of the output conductance of the NMOSFET versus stress time.

the analog circuits made of MOSFETs. In Figure 17 the variation of gds versus stress time for the stress condition specified is shown.

One physical reasons for the degradation of the current in NMOSFETs as a result of hot carrier is that mobility of the carriers m, degrades in the channel underneath the damaged region. This increases the channel resistance which causes the current to decrease. Another reason for drop in the current of NMOSFETs due to hot carrier stress is that threshold voltage Vth increases which means that for a fixed gate voltage the density of carriers in the inversion layer is lower. The threshold voltage of a MOSFET can be defined as the gate voltage at which surface underneath the gate is in strong inversion. Using the MOS capacitor structure, it can be written as follows:

Vtk = 2%

j2qNAEs{2VB-Vtub) _Q1_Qu (21)

where:

(pB = VTLn(NAMj), n; = intrinsic electron concentration, VT = thermal voltage, NA = bulk dopant concentration, q = electron charge, es = silicon permittivity, Cox ~ 8 a t e oxide capacitance per unit area, (pms = metal-silicon work function difference, Qo = trapped charge in the oxide,

386


Qjt = charge in the interface traps and Vsub = source-substrate voltage.

Value of Vsub should be in a range that does not cause the source-substrate and drain-substrate junction become forward bias. According to this relation, it is seen that trapped charges and interface traps can change the value of the Vth. In Figure 18, the normalized variation of Vlh versus stress time for the stress condition specified is shown.

10

£f 10-2

10-

10-

L=0.3 (im,W=120|im

r stress at: V,,=3.7 V, Vo=0.65 V

• •

• •

• •

•

10° 101 102 103

stress time (s)

Fig. 18. Normalized variation of the threshold voltage with stress time.

10"

As a result of the change in I-V characteristic of transistors biasing of the circuit is disturbed which can affect the circuit performance.

8

105

100

S. o "» 95 •a

"3

I 90

85

L=0.3 fiin, W=120 Jim

stress at: Vd=3.7 V, V=0.6S V m

measured at Vd=0.3 V

10" 10B 10"

stress time (s)

Fig. 19. Variation of subthreshold slope versus stress time.

10*

387


The I-V characteristics of the MOSFET in the subthreshold region is also affected by hot carrier stress. In this region, the drain current Id is almost an exponential function of gate voltage Vg. Therefore, a plot of Log (Id) versus Vg in this region is a straight line. The slope of this line, called the subthreshold slope determines how well a transistor can be turned off by reducing Vg. In Figure 19, variation of subthreshold slope versus stress time are shown. The unit of measurement of subthreshold slope is millivolt per decade of drain current.

Another important parameter of a MOSFETs is its transconductance gm. The transcon-ductance is defined as the first derivative of drain current with respect to gate voltage:

6m (22)

Using the relation for the drain current in saturation, gm will be:

According to this relation, the transconductance is directly proportional to carrier mobility ^ in the channel. Since [i,, decreases with hot carrier stress, gm also drops with hot carrier stress. This effect is important in amplifiers where amplification is usually directly proportional to gm. In Figure 20, the normalized variation of gm with stress time is shown for a typical operating point of Vj-Id.

As a result of degradation in the transconductance gm and the transistor's output resistance gds the signal amplification capability of the device deteriorates. The amplification factor Uyis defined as:

H/ = 8mRds (24)

and it represents the maximum voltage gain that an individual transistor can provide. The variation of amplification factor for a typical MOSFET versus stress time is shown in Figure 21 for the stress condition specified.

An important parameter for circuits working at radio frequency is the transit frequency fT which is defined as the frequency at which the current gain of transistor becomes 1 when output is connected to ground. By using a simplified small signal model of the MOSFET, fT can be calculated and expressed in terms of the small signal model parameters of transistors as:12

/T ~ Mcgs + cgd)

388


in which Cgs and Cgd are gate-to-source and gate-to-drain capacitances, respectively. From the direct proportionality offT to gm in the above relation, it is expected that transit frequency degrades with hot carrier stress. Result of measurement confirms the same variation of fT with stress time.69'70'71-72'73

1 •!?

E

<

10" ; L=0.3 \im, W=120 nm

! stress at: V =3.7 V, V =0.65 V r d ' g

measured at: V =1.5 V, I =3 mA d a

Iff' r

1ff! r

Iff3

IO" iff' io* iff1

stress time (s)

10*

Fig. 20. Normalized variation of the threshold voltage with stress time.

90

a eo ra

l »

0 o

7 ° 7

• 7 • •

- V=1.5V • Vo=0.95 V V Vg=0.85 V o Vg=0.75V

0

7 •

o

V

•

III

L=

o

•

0.3 urn, W=120 nm

o 1 o

8 |

10° 10 1 10 2 103

stress time (s)

10<

Fig. 21. Variation of amplification factor |*f with stress time for three different operating point.

389


40

30

N

(9 20

10

L=0.3 urn, W=120 um stress at: V =3.7 V, V=0.65 V

o before stress

a 2000 s stress

-J 1 l-LJ.

10

V=1 .5V

10J

ld (mA)

Fig. 22. Transit frequencyfy versus drain biasing current for fresh and stressed device.

In Figure 22, the transit frequency fT is plotted as a function of drain biasing current Id

for a device before and after stress is shown. In Figure 23, the normalized variation offT

versus stress time is shown at 3 different operating point for the specified stress condition. It is also possible to plot transit frequency versus transconductance. This is shown in Figure 24 for several different operating points. On the same graph, straight lines are fitted to the operating points subject to the same amount of stress time. A small decrease can be seen in the slope of the 3 lines as the stress times increases. If the relation between fT and

TU"

r* 10-

; L=0.3 jim

stress at

;

•

i

w vd

i

=120 urn

=3.7 V, V =0.65 V 9

. s8

i

i i i i i i i t t

•

' '

9 I 9 • •

Vd=1.5V

• ld=5mA v ld=3 mA

o ld=2 mA

i i m i l i i i i n

10c 104 101 102 103

stress time (s)

Fig. 23. Normalized variation offT with stress time at 3 different operating points of an NMOSFET.

390


40

30

N

U 20

10

L=0.3 tun, W=120 \tm

stress at: V==3.7 V, V =0.65 V

measured at: V =1.5 V, I =10-0.5 mA

• before stress A SO s stress O 2000 s stress

10 20 30

9m (mA/V)

40

Fig. 24. Variation offT versus gm for different stress time.

gm is considered, then the decrease in the slope indicates that the sum of Cgs and Cgd

increases by stress. In order to verify this, the values of small signal model parameters of MOSFET should be extracted.

The small signal models suggested for MOSFETs suitable for the radio frequency range are basically the low frequency models of the transistor to which the parasitic resistances of gate, source and drain and also the effect of substrate network are added. '77 A small signal model used here for parameter extraction is shown in Figure 25.

S •-

-gd

•L eJJs gnSJ . :Rds

Rsbi

h—W—J-AW 1 Rdbi

RD

->VW—»D

-db

Rrfb

-«B

Fig. 25. Variation off? versus gm for different stress time.

391


In order to extract the model parameters at each operating point, the measured S-parameters of the transistor at different operating points are converted into their equivalent Y-parameters. Using the circuit model shown in Figure 25, the following relations for Yn

and Y12 can be written:74

y = J(0 SS— = (a2R c 2 +/(oC (26) J g gg

and:

- / ' ( O C „ J 9

Yu = ——^-=-uRc,CC ffd-j(oC.d (27) 1 +MR.C,

g gg

in which C„=Cgs+Cgd+Cgt, are shown in Figure 25. The above equation shows that the value of Cgd can be extracted from the imaginary part of Y12 when it is plotted versus frequency. Having Cgd and knowing that in saturation region Cgi, «Cgs and Cgd, then the value of Cgs is obtained from equation (26). Following this extraction procedure, the variation of Cgs and Cgd versus stress time are plotted, as shown in Figure 26 and Figure 27. It is seen that Cgs increases with stress and Cgd is almost constant with stress. This observation is in agreement with the results of low frequency gate-source capacitance measurement reported in reference 75, which states that capacitance of the unstressed junction in the device (i. e., Cgs) increases with stress. A possible explanation for this is as follows. The small signal capacitance Cgs is defined as:

C„ = -*-* (28) 8s dVs

in which Qg is the charge on the gate and Vs is the voltage applied to the source of the transistor TViis rannr.itnnr.p ran rip shnwn tr» hfv sistor. This capacitance can be shown to be:

" f vac(x)dx J* = o

Cgs = — - ^ f v„ r(x)A (29) sig

in which L and Wars the length and width of the device, respectively, Cox is the gate oxide capacitance per unit area, vac(x) is the small signal potential along the channel, and vsig is the magnitude of the small signal voltage applied to the source in order to measure the capacitance Cgs. In an unstressed device with no negative trapped charge at the drain side, vac(x) changes uniformly from vsig at source to 0 at drain. In a stressed device, however, due to presence of negative trapped charge near drain, the surface potential vac(x) at the drain vicinity has a higher value than that of the unstressed device. This causes an overall increase in the value of integral in equation (29), which results in a higher value of Cgs. This increase of Cgs can be interpreted as the NMOSFET's input becoming more capaci-

392


tive after hot-carrier stress, and it may be important in some applications where input

matching is important and therefore should be taken into account.

235

230

225

220

215

L=0.3nm,W=120um

measured at: V,=1.5 V, ld=3 mA

LU 1— ' i—' i i i u i i

Fig. 26. Variation of C„s versus stress time.

10° 101 10* 108 10^

stress time (s)

0 3

60

55

SO

L=0.3M«i,W=120jim

measured at: Vd=1.5 V, ld=3 mA

io» IOI1 1©2 io» vr stress time (s)

Fig. 27. Variation of Cgd versus stress time.

It should be pointed out that depending on the biasing point, Cg(j shows a slight increase or decrease with stress time, as confirmed by the data in reference 76, but its variation compared to that of Cgs is too small to have any significant effect on the unity current-gain frequency.

Another important RF parameter of MOSFET is the maximum oscillation frequency fmax defined as the frequency at which the maximum available power gain of the device

393


GAmax drops to one. The available power gain GA in a two-port network is defined as the ratio of the power available from the two-port network to the power available from the

,78 source. In this definition, it is assumed that both the source and the load are conjugate matched to the two-port. This power gain can be expressed in terms of S-parameters as:

A, max = \S2\

M2

K • JK^ (30)

in which:

and:

2|512521 |

A - SuS22-Sl2S2l

(31)

(32)

The normalized variation offmax versus stress time for three different operating points and for the particular stress condition of Fg=0.65 V and V^l.l V are shown in Figure 28.

10°

a E

=s 10-1

E

10-

L=0.3 nm, W=120 urn

. -

•

7

Vd=1.5V

• ld=5mA

v ld=3 mA

o I =2 mA

10c 10" 101 102 103

stress time (s)

Fig. 28. Normalized variation of fmax versus stress time for three different operating points.

Another change which occurs in the MOSFET performance due to hot carrier stress is its linearity. If gate voltage V=VG0+vg, in which VG0 is constant and vg is the small signal component, is considered as the input to the device and drain current Id as output and Vd is kept constant, then Id can be written as a function of v„:

7 « = ^ | F

d,s,b

a0 + a{vg + a2vg + (33)

394


in which a,- are the Taylor series coefficient of the function/fTy and are defined as:

l]dVg' (34)

Vd, s, b, G0

If the small signal vs is a sinusoidal signal:

vg = Vpsma>t (35)

then the current Ij can be written as:

Id = c0 + V [c2lcos2j'(Of + c 2 ,_ 1 s in(2 j - l)o>f] (36)

i = l

The coefficient C], c2 and c} can be written as:

c =J.ay ia V*HaV<> (38)

e* '-L4a>yip-T?>y5p-%aSp-- (39)

When K is small enough, the coefficients c;, c2 and c^ will be equal to the first terms in the above relations. In many applications, because of the symmetry in the circuits, the even harmonics are cancelled out and only odd harmonics are left. At this point, the criteria for linearity can be defined as the extrapolated value of Vp at which amplitude of the first and third harmonics would be equal.80 This value is obtained by equating the first terms of series expansions of c} and c3 shown above. Solving this equation, the value of Vp which is called input referred third order intercept voltage and denoted by Vip3 will be:

24g„

A/ Sm3

According to this definition, the higher the Vip3 value, the higher is the linearity of the

device.

Having defined a figure of merit for device linearity, this value is measured for one device before and after hot-carrier stress and is shown in Figure 29. The parameter which has major effect on the linearity of the device is its carrier mobility m, in NMOSFETs, and effect of hot-carrier stress on linearity is believed to be mostly because of its effect on u^.

395


103

10 =

101

1 0 c

L=0.3nmW=120nm

stress at: Vd=3.7 V, Vg=0.65 V

2000 s stress

: J / "

I I s^'' fi\ s?

jr^

i

/

V I .2 V 1

10 0.20 0.40 0.60 0.80 1.00

Vg s(V)

Fig. 29. Comparison of third intercept point before and after hot-carrier stress for the stress condition

shown.

5. Hot Carrier Effects on the Performance of NMOSFET LNA

In the previous sections, the effects of hot carrier stress on the characteristics of a single NMOSFET were explained. Obviously, when these effects appear in the devices used in a circuit, it is expected that the performance of the circuit will be affected as well. As the MOSFET channel length is decreased further, they become more suitable for RF circuits like low noise amplifiers (LNA), oscillators and mixers. Therefore, it is important to know

0.7 V 1.5 V 0.7 V 1.5 V

L d =7nH Lg=8.3 nH L s =2nH Rb=10KQ C c=40pF L=0.3 um, W=120 urn

Fig. 30. Schematic of LNA used for investigating the effect of hot carrier stress o LNA performance.

396


how the performance of the RF circuits made of NMOSFET will be affected by hot carrier

stress.

For this purpose, a test circuit will be considered and the variation of its parameters as a result of hot carriers are studied. In the following, hot carrier effects on a typical LNA are investigated.

5.1. Effect of hot carriers on LNA performance

In Figure 30, the schematic of a two stage LNA made of NMOSFETs and its biasing voltages are shown. Each of the two stages in the circuit are in a common source configuration with inductors Lj as the load.

In the first stage, the inductor Ls is inserted in the source of the transistor M] in order to provide matching at the input of the amplifier. Matching at the input is the condition that signal source impedance is conjugate of the input impedance of the amplifier. At this condition, the maximum power transfer from the signal source to the amplifier occur. The use of an inductor in the source of a MOS transistor for matching purposes is called inductive source degeneration. To qualitatively understand how this technique can be used in matching of the amplifier's input, the simplified small signal model for MOSFET shown in Figure 31 is used to calculate the input impedance of the amplifier.

G • -

4 - • D

£m

Fig. 31. Simplified small signal model of a MOSFET.

Using this model and assuming that the resistor Rb in Figure 30 is large enough that does not affect the input impedance, then the following can be written:81'82

sL* + 'L> + 7T + cLL' S^gs ^gs

(41)

It is seen that by choosing the value of Ls properly, the real component of the input impedance can be adjusted to the desirable value. Also, the imaginary component of the input impedance disappears at the frequency at which the reactances of s(Lg+LJ and 1/ sCgs cancel each other. The inductor Lg at the gate of Ml provides a degree of freedom in determining the frequency at which input impedance becomes purely real, and by adjust-

397

1284 5. Naseh & M. J. Deen

ing its value, this frequency can be adjusted. Capacitors Cc are coupling capacitors and their values are large enough that at the frequency of interest, they will have a small impedance. It should be emphasized that in real circuits and devices, the presence of gate-to-drain capacitor Cgcj and drain-source resistor Rds means that the load at the drain of the transistor Mj also affects the input impedance of the amplifier. However, simulation of the input impedance, using the small signal model of Figure 25, shows that essence of the inductive source degeneration technique for amplifier's input matching is still valid and by choosing a proper value for Ls, it is possible to satisfy the matching conditions.

The feasibility and performance of the circuit in Figure 30 for RF signal amplification has already been confirmed and reported by measurement on a similar circuit. In order to analyze the performance of the circuit, the operating point of each transistor and their small signal model at those operating point should be known. The biasing current of each transistor for the biasing voltages shown in Figure 30 before hot carrier stress is obtained from the previously measured DC characteristics of the transistors and is 3 mA.

0.005 0.003 0.001

-0.001 -0.003

-0.005 I

0.05 0.04

: 0.03 0.02 0.01 0.00

D 2

---

4 6 8 1

8 10

8 10

0 2 4 6 8 10

Frequncy (GHz)

0.002 0.000

0 2 4 6 8 10 Frequency (GHz)

Fig. 32. Comparison of the Y-parameters of the small signal model (dashed line) and measurement (square

symbols). The squares almost completely overlap the dashed lines, and this indicates good agreement

between model and measurements.

398


The parameters of the small signal model of the transistors at this biasing point are extracted from their S-parameter measurement using the procedures similar to that of. In order to make sure that the extracted small signal model is valid, a comparison of the Y-parameters calculated from the small signal model and the Y-parameters derived from measured S-parameters of the transistors before hot-carrier stress are shown in Figure 32. In these plots model parameters are shown by dashed line and measurements by squares. There is a good agreement between the model and measurement and therefore the graphs almost completely overlap and cannot be distinguished from each other.

To investigate the effect of hot-carrier on the performance of this amplifier, it can be assumed that both transistors Mj and M2 follow the same degradation pattern, as both of them are biased at the same operating point. By setting both the input source impedance Zs

and load impedance RL equal to 50 Q, as happens in many practical cases,83 the voltage variation at the drain of the transistors M[, assuming a 1 mV p-p signal at the amplifier's input, can be shown by simulation to be about 30 mV p-p. Almost the same amount of variation appears at the gate and drain voltage of M2. This level of variation compared to the gate and drain biasing voltages of the transistors are very small and negligible. Therefore, the DC bias voltages across the transistors can be used to determine what mode of hot carrier stress (e. g., CHE, DAHC, etc.) exists in the transistors. For the biasing voltages shown in Figure 30, the DAHC mechanism is dominant. Therefore, the accelerated aging condition specified in Figure 16 is used to do the analysis. It can further be assumed that all the other elements and biasing voltages in the circuit are not affected by the hot carrier stress. Therefore, for the purpose of this investigation, it is enough to replace each of the MOS transistors in the circuit with their small signal model before and after stress. The inductors in the circuit are considered on chip inductors and in the simulation, the inductors are replaced with their 7t-model equivalent circuit obtained from S-parameter measurement of the real spiral inductors which had been fabricated with the same technology. It is assumed that Rb and Cc can be modeled by a single resistor and capacitor, respectively.

It should be mentioned that since after hot carrier stress, the I-V characteristics of the device changes, then the biasing current of the transistors change to 2 mA for the biasing voltages shown in Figure 30. The small signal model used for the transistors in the simulation are extracted at the new operating point.

One important issue in the LNA is the matching at the input of the circuit. The reflection coefficient at the input of the amplifier defined as:

Z - Z r . = - ^ — i (42) in z. +z

in s

and it can be a considered as the criteria for measurement of mismatch at amplifier's input. Zs is the signal source impedance. In Figure 33, the magnitude of r / n versus frequency is

399


0.3

^ ° 2

I 0.1

0.0 2.00 2.05 2.10 2.15 2.20 2.25 2.30

Frequency (GHz)

Fig. 33. Reflection coefficient of the input of the LNA before and after hot carrier stress. Stress condition:

Vg = 0.65 V and Vd = 3.7 V.

plotted. It is assumed that both the signal source and the load impedances are 50 Q . It is clearly seen that after the hot carrier stress the matching at the LNA's input is disturbed.

There are two points which need to be explained. First, it was observed that the value of the load connected to the output of the amplifier affects the value of the input impedance of the amplifier. This means that the NMOSFETs used in the circuit are not unilateral devices. By considering the small-signal model of the transistors, it can be stated that the gate-to-drain capacitor Cg(j, which has an impedance less than 2 kQ at 2 GHz, provides a path between output and input of each transistor. Also, the output resistance of the MOS-FETs Rfc provides another connection between output and input of the device. This is to be expected as device channel length becomes shorter, which causes a more pronounced channel length modulation effect. This is especially important in the design of the first stage of the LNA where the presence of the inductor at the transistor's source provides feedback from the output to the input. This importance can be further confirmed by the trend of variation of input impedance versus frequency, before and after stress. As mentioned before, the gate-to-source capacitor Cgs increases with stress, which then may raise the expectation that the frequency at which input impedance of LNA, Zin, becomes a pure real resistance would shift to lower frequencies after hot-carrier stress. The result of simulations show the opposite trend. In fact, it can be shown by simulation that both the decrease in gm and the decrease in Rjs shift the minimum r i n to higher frequencies. Therefore, the effects of degradation of gm and Rds on the input impedance is more prominent than that of the degradation of C„s due to hot carrier stress.

before stress after stress

J I I I L

400


The second point is that care should be taken in the use of r,-„ as a measure of mismatch. If the signal source impedance Zs has an imaginary part other than zero, a reflection coefficient r,„= 0 does not correspond to the conjugate matching of the signal source and LNA, which is the desirable condition at LNA's input.

Another important parameter of the LNA is its power gain. The transducer power gain GT is defined as the ratio of the power dissipated in the load to the power available from the source, before and after stress, and it is shown in Figure 34. Clearly, this parameter has also decreased after stress and it shows a shift in frequency similar to that of the input reflection coefficient. The drop in the power gain is due to both the increase in input mismatch and the decrease in the overall voltage gain of each transistor.

CO •o

(9

I 1

25

20

15

10

-

-

/

/

/

/ ' " \ \

1

after stress

i i \

1 2 2 3 3 4 4

Frequency (GHz)

Fig. 34. Transducer power gain before and after stress. Stress condition: Vg = 0.65 V and ^ = 3 . 7 V .

Another important parameter of the amplifier is its stability. The parameter u has been shown to be an appropriate measure of two-port networks stability:84

1-IS,

in which:

Is^- iSj^ l + |s12s21|

A ^ l 1^22 ~ ^12^21 '

(43)

(44)

If the value of \i is more than 1, then the two-port network is unconditionally stable, and also a higher value of [i indicates a more stable two-port. From Figure 35, it is seen that before stress the LNA has conditional stability but after stress it becomes uncondi-

401


tionally stable. This probably can be attributed to the decrease in the gain of the LNA, as generally, higher gain is associated with lower stability.

1.80

1.60

§ 1.40

2 1.20

S

1.00

0.80 1 2 3

Frequency (GHz)

Fig. 35. Stability factor \i versus frequency before and after stress. Stress condition

3.7 V.

6. Summary

In this chapter, the effects of hot carrier stress on the NMOSFETs parameters and its electrical performance were presented. First, the operating mechanisms of a MOSFET was described. Using these mechanisms, it was shown that because of presence of strong electric fields, e. g., as in pinch-off region when device is operating in saturation mode, hot carriers are generated. Different mechanism of hot-carrier generation like channel hot electron (CHE), drain avalanche hot carriers (DAHC), substrate hot electrons (SHE) and Fowler-Nordheim tunneling were explained.

Important experimental tools, such as charge pumping and C-V measurement which are used for studying the silicon-silicon dioxide interface in MOSFETs and MOS capacitors, and floating gate measurement which is used to measure the gate leakage current in MOSFETs were explained.

The results of measurements of hot-carrier effects on the RF and DC electrical parameters and characteristics of NMOSFETS were presented using the accelerated aging process. Degradation of parameters like transconductance gm, threshold voltage Vth, output conductance gds and transit frequency fT of an NMOS transistor were demonstrated. It was shown that drop in transit frequency is caused by the decrease of gm and the increase of

402

4

Vg = 0.65 V and Vd =


And finally, using the results of measurements of hot-carrier effects on NMOSFETs, the effects of hot carriers on the performance of a LNA made of NMOS transistor were simulated. It was shown that matching at the input of the LNA is disturbed by hot carriers. The gain of the amplifier drops and also the frequency of the maximum gain is shifted due to hot carriers. And as a result of drop in amplifier's gain, its stability increases.

Acknowledgements

We thank Dr. D. Landheer, National Research Council, Ottawa and Dr. N.R. Das, McMas-ter University, Hamilton, for their careful review of parts of this manuscript. We are also grateful to several of our current and previous colleagues for their interest and support, and for their comments and useful suggestions on our work over the past several years. Finally, we are grateful to the Natural Sciences and Engineering Research Council (NSERC) of Canada and Micronet, a federal network center of excellence in microelectronics for partial financial support of this work.

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Selected Topics in Electronics and Systems - Vol. 24


CMOS technology has now reached a state of evolution, in terms of both frequency and noise, where it is becoming a serious contender for radio frequency (RF) applications in the GHz range. Cutoff frequencies of about 50 GHz have been reported for 0.18 urn CMOS technology, and are expected to reach about 100 GHz when the feature size shrinks to 100 nm within a few years. This translates into CMOS circuit operating frequencies well into the GHz range, which covers the frequency range of many of today's popular wireless products, such as cell phones, GPS (Global Positioning System) and Bluetooth. Of course, the great interest in RF CMOS comes from the obvious advantages of CMOS technology in terms of production cost, high-level integration, and the ability to combine digital, analog and RF circuits on the same chip. This book discusses many of the challenges facing the CMOS RF circuit designer in terms of device modeling and characterization, which are crucial issues in circuit simulation and design.

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Cmos Rf Modeling,Characterization and Applications