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NOTES Is Based On CMOS Technology there Design By Logic Gates And Transmission Gates.BICMOS,Inverters,LOGIC GATES,MOS Capitance Estimation,Power Dissipation In Cmos,Stage Ratio,CMOS Dynamic Logic,Sense Amplifer
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AGENDA
Study of IC Technology
MOS Transistor Theory
Inverters
Building Logic Circuits with CMOS
MOS Capacitance Estimation
Power Dissipation in CMOS
Stage Ratio CMOS Dynamic Logic
Scaling of MOS Transistor Dimensions
CMOS Processing Technology
Sense Amplifier
1
Study of IC Technology
IC Technology
Microelectronics Technology
Feature Size
2
IC Technology• Depending on the no. of transistors to be fabricated IC technologycan be categorized as
Integration level Year No. of transistors DRAM Integration
SSI 1950s Less than 102
MSI 1960s 102 103
LSI 1970s 103 105 4K, 16K, 64K
VLSI 1980s 105 107 256K, 1M, 4M
ULSI 1990s 107 109 16M, 64M, 256M
SLSI 2000s Over 109 1G, 4G and Above
• The important factor in achieving such complexity is scaling downof the feature size.
3
IC Technology
Integration of a large function on a single chip provides:-
• Less area/ Volume and therefore, compactness
• Less Power consumption
• Less testing requirements at system level
• Higher reliability, mainly due to improved on-chip interconnection
• Higher speed, due to significant reduced interconnection length
• Significant cost saving
4
Microelectronics Technology
Micro Electronics
Inert Substrate
(Good Resistors)
MOS
N P CMOS
Active Substrate
Silicon GaAs
Fast
Bipolar
ECLTTL
Current : Majority None thro‟Current : Majority + Minority5 gate thro‟ base
Microelectronics Technology
Two basic technologies used for manufacturing IC‟s are• Bipolar
• MOS• Bipolar : The main technology is low-power-schottky TTLDisadvantage: High power dissipation.
Used for SSI and MSI.• MOS : LSI technology uses MOSFETS since these can be packedin small area.
• P-MOS Technology : It uses P-MOSFET ‟s.Mobility of holes - 240 cm2/v*sec
Holes are majority carriers & hence this is relatively slow.• N-MOS Technology : It uses N-MOSFET ‟s
Mobility of electrons -650 cm2 /v*secSince electrons are majority carriers this technology isfaster than P-MOS.• CMOS Technology : It uses combination of P-channeland N-channel MOS.
6
CMOS Technology
NMOS
S GGate Oxide
D D
PMOS
G S
Polysilicon
Thick SiO2 (Isolation) SiO2
n+ n+ p+ p+
n well
p-type body
As shown above PMOS transistor is formed in a separate n-type regionknown as n-well.
7
Attributes Of CMOS Technology
• Wide supply voltage range from 3 to 15 volt.
• Voltage required to switch gate is fixed percentage of VDD.
• Packaging density : Requires 2n devices for n input gate
• Fully restored logic level : Output settles at VDD or Vss. Therefore
called as restoring logic.
• Characteristics of CMOS technology lies between that of P-MOS
and N-MOS. It is faster than P-MOS but slower than N-MOS.
• Mainly used in systems that require portability or less power
consumption.
• It needs more processing steps as compared to N-MOS or P-MOS.
8
Comparison - CMOS and BipolarTechnologies
FACTORS CMOS BIPOLAR
Static power dissipation Low High
Input impedance High Low
Noise margin High Low
Packaging density High Low
Fan-out Low High
Direction Bi-directional Unidirectionaldevices devices
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BI-CMOS Technology
• BI-CMOS TECHNOLOGY :• It combines both bipolar and CMOS transistors on single substrate.• MOSFET‟s have limited driving capabilities while bipolar transistorsprovide higher gain and better high frequency characteristics.
• The output drive capabilities of CMOS gate can be enhanced ifoutput stage is BJT.
• Used for implementing high performance digital systems.
• GaAs ( Gallium Arsenide ) TECHNOLOGY:• Silicon MOS technology is main media for computers, but thespeed requirements for Supercomputers which are suppose to
operate at 10 BFLOPS (Billion Floating Point Operations persecond ) uses gallium arsenide technology.
10
Feature Size
Typically L = 1 to 10 µm, W= 2 to 500 µm and the thickness of oxide layer is inthe range 0.02 to 0.1 µm.
11
Feature Size• Value of gate length (L) is called as feature size of manufacturingtechnology.
• Thus feature size is function of IC technology.
N-MOSFETlayout
12
Year Vs Feature Size
YEAR FEATURE SIZE
1970 7 - 10
1970-80 5
1980s < 2
1990s <1 (sub micronprocess)
Currently Feature size is in the range 0.25 to 0.15
13
DEVICE COUNT
• How many devices that can be fabricated on a 4 inch silicon waferwith 5 technology ?
• N = No of devices = r 2 / (5 X 5 2) = 3 X 10 8N• Thus 1/10th decrease in Feature size increase the Devicecount 100 times.
14
MOS TRANSISTOR THEORY
Structure of MOS transistor Operation of enhancement NMOS
15
Cross-sectional View of a TypicalN-MOSFET
• Central region of device consist of a Metal-Oxide-Semiconductor• Subsystem made up of a conducting region called the gate [M],on top of an insulating silicon dioxide layer [O]
• p-type silicon [S] epitaxial layer on top of a P+ - substrate.• n+ regions constitute the drain and source terminals
• It has four terminals viz. Gate-G, Drain-D, Source-S andSubstrate-B.
16
Cross-sectional View of a TypicalP-MOSFET
• p+ regions constitute the drain and source terminals
• It has four terminals viz. Gate-G, Drain-D, Source-S andSubstrate-B.
17
Metal Oxide SemiconductorField Effect Transistor
•For P-channel MOS substrate is of N type and source, drain areformed with P type material.•For N-channel MOS substrate is of P type while source & drainare formed with N type material.
• Gate is polycrystalline silicon electrode and is insulated fromsubstrate by thin layer of silicon dioxide SiO2
• Since the gate is insulated, MOSFET‟s are also called asInsulated Gate Field Effect Transistors ( IGFET )
• It is a voltage controlled device, the current through channel iscontrolled by voltage applied to gate.
• MOSFET‟s can be configured either as
Enhancement type MOSFET OR
Depletion type MOSFET
18
Enhancement NMOS
D
G
S
Drain
Gate
SourceNMOS
Drain
Gate
SourcePMOS
• Lightly doped p-type material forms substrate• Highly doped n+ regions separated by substrate form drain & source
• When gate voltage VGS = 0, drain current is zero.• Since the gate is insulated, any positive voltage applied togate, will produce electric field across substrate.
19
Enhancement MOS
• This field will end on induced negative charges in p substrate.
• These negatively charged electrons, which are minority carriers in psubstrate, form an inversion layer. Current flows from source to drainthrough this induced channel.
• More the positive voltage, More is the induced charge & hence morecurrent flows from source to drain.
• This is also called „Normally Off ‟ MOS, since drain current is zero forzero gate voltage.
• CMOS integrated circuits use enhancement type transistors only.
20
Enhancement MOS Cross-Section
Source (S)
Oxide (SiO2)
Gate (G) Drain (D)
Metal
n+ChannelRegion
Lp-type substrate
(Body)
n+
Body (B)
21
Depletion Type MOS
D
G
S
NMOS
Drain
Gate
SourceNMOS
Drain
Gate
SourcePMOS
• In Depletion MOS structure, the source & drain are diffused onP- substrate as shown above.• Positive voltages enhances number of electrons from source todrain.
• Negative voltage applied to gate reduces the drain current• This is called as „ normally ON ‟ MOS.
22
Operation Of N-MOS Transistor
• Depending on the relative voltages of the source, drain and gate, theNMOS transistor may operate in any of three regions viz :
• Cut_off: Current flow is essentially zero (also calledaccumulation region)
• Linear :(Non saturated region)-It is weak inversion regiondrain current depends on gate and drain voltage.
• Saturation : It is strong inversion region where drain currentis independent of drain-source voltage.
23
Cut-off Region
Source (S) VGS=0 VDS=0
n+ n+
p-type substrate(Body)
• With zero gate bias (VGS=0) , no current flows between sourceand drain, only the source to drain leakage current exists.
• Current-voltage relation : IDS = 0 VGS < VT
24
Linear Region• Formation of Depletion layer
Source (S) 0 VGS Vt VDS=0
Depletion Layer
n+ n+
p-type substrate(Body)
• Small positive voltage applied to gate causes electric field to beproduced across the substrate
• This in turn causes holes in P region to be repelled. This formsthe depletion layer under the gate.
25
Linear Region• Formation of Inversion layer :
Source (S) VGS > Vt VDS=0
Inversion Layer
n+ n+
p-type substrate(Body)
• As the gate voltage is further increased, at particular voltage VT,electrons are attracted to the region of substrate under gate thus formingconduction path between source and drain.
• This induced layer is called „inversion layer‟. The gate voltage necessaryto form this layer is known as „Threshold voltage‟ (VT).
• As application of electric field at gate causes formation of inversionlayer, the junction is known as field induced junction.26
Linear Region
Source (S) VGS > Vt VDS < VGS - Vt
Inversion Layer
n+ n+
p-type substrate(Body)
• When VDS is applied, the horizontal component of electric field (dueto source-drain voltage) and vertical component (due to gate-substrate voltage) interact, causing conduction to occur along thechannel.
• When effective gate voltage (VGS - VT) is greater than drainvoltage, current through the channel increases. This is nonsaturated mode. ID = f (VGS,VDS)
27
Saturation
Source (S) VGS > Vt VDS = VGS - Vt
n- channel
n+ n+
p-type substrate(Body)
As VDS is increased, the induced Channel acquires a tapered shape andits resistance increases with Increase in VDS.
Here VGS is kept constant at value > VT
28
SaturationSource (S) VGS > Vt VDS > VGS - Vt
n- channel
n+ p
p-type substrate(Body)
n+
• When VDS > VGS - VT, VGD < VT, the channel becomes pinched- off &transistor is said to be in saturation.
• Conduction is brought by drift mechanism of electrons under theinfluence of positive drain voltage and effective channel length is
modulated.
29
MOSFET Drain Current Equations
N-CHANNEL MOSFET
Cut- off Region
IDS 0
Linear Region
(VGS < VT)
(VGS VT) & (VDS < VGS - VT)
= k
W/L;
called as gain
factor of the
device
IDS = n [2.(VGS - VT) VDS - VDS2]
Saturation Region (VGS VT) & (VDS VGS - VT)
IDS = n [(VGS - VT)2 (1 + VDS)]
is an empirical constant called as „channel length modulation‟
30
MOSFET Drain Current EquationsP-CHANNEL MOSFET
Cut- off Region (VGS
IDS 0
> VT)
Linear Region (VGS VT) & (VDS > VGS - VT)
IDS = p [2.(VGS - VT) VDS - VDS2]
Saturation Region (VGS VT) & (VDS VGS - VT)
IDS = p [(VGS - VT)2 (1 + VDS)]
31 is an empirical constant called as „channel length modulation‟
Linear Region
Where = k W/L; called as gain factor of the device
k = ox/tox called process transconductance parameter
tox = Thickness of the gate insulator
L = Length of channel
ox = Permitivity of gate insulator
Since n = 2p => kn = 2kp
thus n = 2p
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Drain curve for NMOS operated withVGS> VT
33
ID-VDS characteristics
CUTOFF REGION
34
IV characteristics of NMOS
Transconductance curve
IGS = 0
+
-
+
IS = ID -
35
INVERTER
Static Load Inverters.
CMOS Inverter.
Switching Characteristics of CMOS Inverter
Noise Margin
36
Static Load Inverters
• Static load inverter are Ratioed logic gates where logic levels aredetermined by relative dimensions of composing transistors.
• Transfer function of inverter varies with load.
Resistor load (passive)
1]• When I = 1, inverter dissipates static
power• Switching point of inverter depends on
ratio of R to RON (on resistance of NMOSdevice.)
37
Active - Resistive Load2]
Enhancement NMOS
• Load is enhancement-mode NMOS device. Static powerdissipation occurs when I = 1.
• Output swings from nearly 0V to (VDD - VT(n) )• Using a transistor as a load tends to require much lesssilicon area than a resistor.
• VOL can be close to 0V, depending on ratio of RON of twoenhancement devices.
38
Active-Resistive Load3]
• Load device is always on, looks like a load resistor. Dissipatesstatic power when I = 1, VGS = 0V always
• VOH = 5V; VOL nearly 0V, depending on ratio of RON_dep toRON_enh.
• Depletion-mode devices were used before it was economical toput both p-type and n-type devices on the same die.
39
Active - Resistive Load
4]
• As shown above PMOS device is acting as static load.• Here also the load device is always on (conducting).dissipates static power when I = 1.
•VOH = 5V; VOL nearly 0V, depending on ratio of RON-P to RON-N
40
Characteristics of CMOS Inverter
Rin = Rout =0
Noise Margin = VDD /2Gain =
41
Characteristics of CMOS Inverter
42
Actual Inverter Characteristics
43
Inverter Characteristics
• VIL represents the maximum logic 0 (LOW) input voltage thatwill guarantee a logic 1 (HIGH) at the output
• VIH represents the minimum logic 1 (HIGH) input voltage thatwill guarantee a logic 0 (LOW) at the output
VOH = VDD
VOL = 0
VTH = f ( R ON-n,R ON-p )
VTH = VDD/2 if RON-n = R ON-p
44
Resolution of Gate Output Level
• When we join P and N switches, both will attempt to exert a logiclevel at the output.
• For inverter with independent control of inputs, the possible levelsat the output of the pull-up and pull-down are as shown below
pull down pull up Combinedoutput output output
0 Z 0
Z 1 1
Z Z Z
0 1 crowbarred
45
Voltage Relation for Regions OfOperation Of CMOS Inverter
CUT-OFF LINEAR SATURATION
VGS < VT
NMOSFET
VGS VT
VIN VT
VDS < VGS - VT
VGS VT
VIN VT
VDS VGS - VTVIN < V T VOUT < VIN - VT VOUT VIN - VT
VGS > VT
PMOSFET
VIN > VT + VDD
VGS VT
VIN < VT + VDD
VDS > VGS - VT
VOUT > VIN - VT
VGS VT
VIN > VT + VDD
VDS VGS - VT
VOUT VIN - VT
46
n/p Ratio• The ratio ßn (gain of NMOS) / ßp (gain of PMOS) determines the switchingpoint of the CMOS inverter.
47
Switching Characteristics of CMOS Inverter
48
Switching Characteristics ofCMOS Inverter
• The switching speed of the CMOS gate is limited by time taken tocharge and discharge the load capacitance
49
Calculation of Fall Time• Fall Time : The time required for output to fall from 90% to 10%of its steady state value.
• k is a constant that depends on threshold voltage and VDD.
• k = 3 to 4 for values of VDD = 3 to 5 volts & VT = 0.5 to 1 volt.
• The gain factor = nox/tox W/L
50
Calculation of Fall Time
t = RC time constantexponential formulas, e-t/RC
51
Calculation of Rise Time• Rise Time : The time required for the output to rise from 10%to 90% of its steady state value and is given as
• Thus to achieve high speed circuits, the load capacitance should beminimized.
• Lowering the supply voltage on a circuit will reduce the speed ofthe gates in that circuit.
52
Calculation of Rise Time
Exponential rise time
53
Calculation of Rise & Fall Time• Higher capacitance ==> more delay
• Higher on-resistance ==> more delay
• Lower on-resistance requires bigger transistors
• Slower transition times ==> more power dissipation (output stagepartially shorted)
• Faster transition times ==> worse transmission-line effects
• Higher capacitance ==> more power dissipation (fCV2 power),regardless of rise and fall time
54
Calculation of Rise & Fall Time
• For equally sized n and p transistors βn = 2βp
Hence Tfall = Trise /2
• To equalize the rise and fall times of an inverter I.e Trise = Tfall
must have ßn = ßp
• This means, that channel width for the p-device must be increasedto twice of the n-device. Hence if Lin = Lp then Wp= 2*Wn
• Thus ßn = ßp provides equal current source and sink capabilities.
• Thus equal charge and discharge times
55
Delay Time
Delay time : It defines the response of gate for change in input.
• Is measured between 50% transition points of input and outputwaveforms.
• Gate displays different response times for rising and fallingwaveforms.
• Tplh Defines response time of gate for low to high outputtransition
• Tphl Defines response time of gate for high to low outputtransition
• The overall propagation delay is average of these twoTD = (Tphl + Tplh)/2
56
CMOS Inverter - Summary
• CMOS inverter uses actively driven P-channel transistor is used aspull-up drive.
• It allows maximum logic voltage level swing.
• Eliminates the static power dissipation as no current flows fromVDD to ground in steady state.
• Number of transistors is 2N.
• It is ratio-less logic I.e.• Output logic levels are independent of ratio of pull-up andpull-down transistor sizes.
57
CMOS Inverter - Summary
• Resistance of N-channel transistor is Rn α Ln /Wn * Kn
• Resistance of P-channel transistor is Rp α Lp /Wp * Kp
• But μn = 2 μp, hence βn = 2 βp .
• Hence in order to achieve symmetrical operation(equal rise &fall time ) we must have
(Ln * Wp)/ (Lp * Wn )= kn/kp =2 Thus with this sizing N & P
transistors have equal I-V characteristics.
58
Noise Margin
Logic HighLogic High
Output range
Logic lowoutput range
VOH(MIN)
VIH(MIN)
VIL(MAX)
VOL(MAX)
input range
Logic lowinput range
Output characteristics Input characteristics
59
Noise Margin
• Determines the allowable variation in inputvoltage of gate so that output is not affected.
• Is specified in terms of two parameters
• Low noise margin - NML = VIL(MAX) - VOL(MAX)
• High noise margin - NMH = VOH(MIN) - VIH(MIN)
60
Noise in Digital Integrated Circuits
Inductive Coupling Capactive Coupling Power & Gnd Noise
61
Noise in Digital Integrated CircuitsIf Vin is very noisy signal. Passing this signal through a symmetricalinverter (Vinv1) would lead to erroneous values. Raising thethreshold to (Vinv2) yields correct response.
Response of standard InverterResponse of standard Inverterwith modified Vinv
62
Noise in Digital Integrated CircuitsEffects of βn/ βp CMOS inverter Noise margin
63
Building Logic Circuits With CMOS
MOS TRANSISTOR AS SWITCH
SERIES & PARALLEL CONNECTION OF SWITCHES COMPLEMENTARY LOGIC GATE DESIGN TRANSMISSION GATE
LOGIC DESIGN WITH TRANSMISSION GATE CMOS TRANSISTOR SIZING
64
MOS Transistors as Switch
• N-MOS source is tied to ground,used to pull signals down
Control output
G= „1‟ D=„0‟
G= „0‟ D=„Z‟
• P-MOS source is tied to VDD, usedto pull signals up.
Control Output
G= „0‟ D= „1‟
G= „1‟ D=„ Z‟
65
Why N-MOS TransistorProduces Weak „1‟?
• Apply logic‟1‟ to Gate and Drain• at time t = 0 ; VGS= VDD
• Capacitor starts charging and VGS decreases as the source voltageapproaches its final value
• Decreasing VGS reduces the channel charge, while a smaller VDS
indicate a reduction in the drain- source electric field.
•The Source will stop increasing in voltage when VGS reaches Vt
• at t ;
Vout = (VDD- Vt ) = Vmax (Known as threshold voltage loss)66
Why N-MOS TransistorProduces Strong„0‟?
• Apply logic‟1‟ to Gate and logic‟0‟ to Source• at time t = 0 ; Assume VC= VDD
• NMOS transistor will begin to discharge capacitor and continue untildrain terminal reaches a logic‟0‟
•at t ; VC = 0V
The transistor is strongly conducting with large channel charge butthere is no current flowing since VDS = 0V.
67
Why PMOS TransistorProduces Weak „0‟ ?
• Apply logic‟0‟ to Gate and logic‟0‟ to drain• at time t=0 ; Assume VC= VDD
• PMOS transistor will begin to discharge capacitor
•at t ; VC = Vt
Since the transistor must maintainmin ( VSG ) = Vt for the conducting channel to exit
68
Why PMOS TransistorProduces Strong„1‟ ?
• Apply logic‟0‟ to Gate and logic‟1‟ to source• at time t=0 ; VGS= VDD
• Capacitor starts charging and continue until drain terminal reachesa logic‟1‟
• at t ; VC = VDD
The transistor is strongly conducting with large channel charge butthere is no current flowing since VDS = 0V.
69
MOS Transistors as SwitchSWITCH G INPUT (SOURCE) OUTPUT(DRAIN)
N - Switch
Gate
G
S
I/P
D
O/PX
ZG=0VDD STRONG 0
G=1 VSS WEAK 1Source DrainP - Switch
Gate
GG=0 X Z
S D G=0
Source Drain
VDD STRONG 1
VSS WEAK 0
• Thus NMOS transistor produces active low logic at output.• While PMOS gives active high logic at output.
70
Series Connection Of Switches
• If N switches are placed inseries Y=„0‟ if A & B are „1‟.
•Thus yields an AND function.Y = A * B
• If P switches are placed inseries Y=„1‟ if A & B are „0‟.
•• Thus yields an NOR function.Y = /A * /B
71
Parallel Connection Of Switches
• When N switches are placed inparallel Y=„0‟ if either A or B is „1‟.
• Thus yields an OR function.Y = A + B
• When P switches are placed inparallel Y=„1‟ if either A or B is „0‟.
• Thus yields an NAND function.Y = /A +/B
72
Complementary Logic Gate Design
A CMOS gate is combination of two networks as shown below
VDD
I/PPUN
Y= /F
I/PPDN
VSS
• Pull Up Network (PUN) consists ofP-MOS transistors. Thus implements
the logic function F
•Pull Down Network (PDN) consists ofN-MOS transistors. Thus implements
the logic function /F.
73
CMOS NAND Gate Design
• PUP network consists of two parallel P-MOS transistors• PDN network consists of two series N-MOS transistorsWHY ???
74
CMOS NAND Circuit
75
NOR Gate Design
Y = /(A + B)
PUN = /A * /B PDN = A + B
76
NOR Circuit
77
AND Gate Design
POORLY DESIGNED AND GATE !!!78
AND Gate Design
Instead use this !
79
Designing Compound Gates
• To implement the function F = /((A+B+C)*D)
• PDN will provide 0‟s of function F.
• Hence equation of PDN is (A+B+C) * D.
• For PUN network will provide1‟s of function F
• Equation for PUN is(/A*/B*/C)+/D
80
Transmission Gate
• By combining an N-switch and P-Switch in parallel perfecttransmission of both „1‟s and „0‟s is achieved.
• When I=0 both N & P devicesare OFF
VIN VOUT
X Z
• When I=1 both N & P devicesare ON
VIN VOUT
VDD VDD
VSS VSS
81
Transmission Gate
• Schematic icons for transmission gate
Most widely used
82
Transmission Gate Characteristics
2:1 multiplexer
Y = SA +/SB
• This implementation will need total 6 Transistors• 4 Transistors for two pass gates• 2 Transistors for inversion of S
• Thus transmission gate logic uses less gates than the designwith normal gates.
83
Transmission Gate Characteristics
But it has got Demerits !
• It is non restoring logic output levels may or may not settle at VDD
or VSS (as it passes logic level at input to output ) where as CMOSgates provides restoring logic.
• It has no drive capability, drive comes from original A, B inputsWhat about CMOS gate?
• Transmission gates provide no isolation between input andoutput.
•Then Why & Where Transmission gates are used ?
84
Logic Design Using Transmission gate
2:1 Multiplexer Y = SA + /SB
A B S Y
X 0 0 0(B)
X 1 0 1(B)
0 X 1 0(A)
1 X 1 1(A)
• When S= 1, S1 is ON and S2 is OFF. Hence input A is connectedto the output.
• When S= 0, S1 is OFF and S2 is ON. Hence input B isconnected to the output.
85
2:1 Multiplexer
• Multiplexer may also be constructed using logic gates
• However these implementations are larger and consume more
power than a transmission gate implementation
Design Style Transistor CountComparison of
Multiplexers Static CMOS Gates 12 Why ?
Transmission Gates 4
86
Tristate InverterEN I O
0 X Z
1 0 1
1 1 0
Total 6 transistors !
87
D LATCH Positive level sensitive
EN Q
1 D
0 Qold
How will the circuit function ?
88
D-LATCH With En = 1
• When EN = 1, switch S1 is closed and S2 is open.
• Hence Output-Q follows Input D
89
D-LATCH With En = 0
• When EN = 0, switch S1 is open and S2 is closed.
• Hence,
• Output-Q is isolated from Input D.
• Output retains the value of D at the falling edge of EN [ WHY ???]
90
D-LATCH with Asynchronous Reset
• How to implement asynchronous clear?91
Edge Triggered D - Register
• By combining two latches in master-slave arrangement, edgetriggered register can be constructed.
• For positive edge triggered first latch(master) is negative level-sensitive latch
92
Rising Edge Triggered D Register
How will the circuit function ?
93
D-register With Clk = 0
• When CLK= 0 , S1 and S4 are closed /Qm follows D, and Q isstored in the inverter loop.
94
D-Register with CLK = 1
• When CLK= 1.
• S1 is open and S2 is closedHence /Qm LATCHES the value of D, that existed on the rising edge of CLK.[ Does it remind you of set-up hold and Metastability]
• S3 is closed and S4 is open,Hence Q gets the value of /Qm [ I.e. the value of D on the rising edge of CLK].
• Q is isolated from changes on D input.95
Edge Triggered D-Register
• In case of negative edge triggered register master is positivelevel-sensitive latch.
96
Guess The Functionality ?
97
98
CMOS Transistor Sizing
DESIGN REQUIREMENT TRANSISTOR SIZING LOGIC RESTRUCTURING CONDUCTOR SIZING
99
CMOS Transistor Sizing
Design requirements
•Speed: -In many state-of-the-art design, especially contemporary
microprocessor, speed tends to be the dominating requirement.
• Power: - In portable applications such as mobile telephones,PCs, etc., minimizing power dissipation is crucial.
• Area: - Circuit area is often the prime concern, as it has directimpact on die size and hence the cost.
100
CMOS Transistor Sizing
• Symmetrical drive capability of CMOS allows comparabletransition time for output voltages irrespective of direction oftransition.
• Primary effect of sizes of pull-up and pull-down transistors ison equivalent resistance of transistors in conduction state.
• To obtain symmetrical characteristics at output rise and fall timeshould be same which says RN = RP
• Resistance of N-channel is given as RN LN/WN*KN
• Resistance of P-channel is given as RP LP/WP*KP
101
Sizing of NAND and NOR Gates
• In case of NAND gate equivalent pull-down resistance is twice that of
either pull-down alone RDN = Rn3 + Rn4= 2* Lp/Wp * Kp.
•
102
Sizing Of NAND and NOR Gates
• In case of NOR gate the equivalent pull up resistance is twice that ofeither pull up alone Rup = Rp3 + Rp4= 2* Lp /Wp * Kp
• Hence for NOR gate Kn/Kp = 5 will give symmetrical output ??• NOR gates require greater silicon area than NAND gate for symmetric driveoperation.
• Hence NAND gates are always preferred than NOR103
Logic Restructuring• Gate delay of large fan-in gate can be improved by manipulating logicequation, I.e. restructuring logic
Consider 8-input AND gate
104
Conductor Sizing
• ELECTROMIGRATION: - Direct current flowing on a metal wire over a
substantial time period causes a transport of metal ions, ultimately causingthe wire to break or short to another wire.
Rate of electromigration depends upon temperature, crystal structure andcurrent density ( current per unit area).
Keep the current below 0.5 to 1mA /um normally prevents electromigration.Current density for contact periphery must be kept below 0.1mA /um.
Signal wires normally carry alternating current are less susceptible tomigration.
105
Conductor Sizing
• POWER AND GROUND BOUNCE: - Ohmic voltage drops can occur onpower conductors degrading VDD and ground levels leading to poorlogic levels reduction in noise margin of gates incorrectoperation of gates.
This degradation of supply voltages is termed as “power bounce”for VDD and “ ground bounce” for the GND lead.
106
Conductor SizingPOWER AND GROUND BOUNCE can be minimized by: -
• reducing the maximum distance between supply pins and circuitsupply connections using a finger shaped power distribution network.
• Providing multiple power and ground pins.• Using low resistively metal.
Finger-shaped network With multiple power & ground pins
107
MOS Device Capacitance Estimation
Switching speed of MOS system strongly depends onthe parasitic capacitances associated with MOSFETsand interconnection capacitances.
Total load capacitance on the output of a CMOS gateis the sum of
Gate Capacitances (Cg)
Diffusion Capacitances
Gate capacitance :- CG = bulk + overlap capacitance
CG = CGB + CGD + CGS
CG = COX W Leff
108
MOS Device Capacitance Estimation
109
MOS Device Capacitance Estimation
110
MOS Device Capacitance Estimation
111
MOS Device Capacitance Estimation
Diffusion Capacitances
Voltage dependent source and substrate and drain-substrate junction capacitances, Csb, Cdb. These
junctions are reversed-biased during normal operation
112
Where Does Power Go In CMOS
Power dissipated in a CMOS circuit is categorised as follows,
• Static dissipation :Due to leakage currents
• Dynamic dissipation :Due to charging and discharging of internal & load capacitance.
• Short circuit dissipation :Due to short circuit path between VDD and GND during switching
113
Static Dissipation
Static dissipation is due to,
• Leakage currents in the reversed-biased diodes formed betweenthe substrate (or well) and source/drain regions.
• Sub threshold conduction, also contributes to static dissipation.Sub threshold leakage increases exponentially as thresholdvoltage decreases.
• Total static power dissipation is given aspstatic= Σn leakage current * VDD
Where n is the number of devices in a CMOS Circuit.
114
Static Dissipation
LOWER BOUND ON THRESHOLD TO PREVENT LEAKAGE
115
Dynamic Power DissipationVDD DD
SG
Charging Current
Vin
GCL
SGND
Vout
• During low to high transition part of energy drawn from supply isdissipated in PMOS. While during high to low transition storedenergy on capacitor is dissipated in NMOS transistor.
• Dynamic power dissipation gives measure of this energyconsumption
116
Dynamic Power Dissipation
• The average dynamic power consumption for input frequency ofF is Pdynamic = CL * VDD2 * F
• Power dissipation is independent of device parameters• This can be reduced by decreasing CL , VDD or F
117
Short Circuit Dissipation
• It is the DC power consumed during switching.
• A direct current path from VDD to ground exists when both Nand P transistors are conducting simultaneously during
switching.
• Short circuit consumption is given byPsc = Imean * VDD
•Short- circuit power depends on W/ L ratios of the transistors
• Greater the rise-fall time of the signals, larger is the powerconsumed.
118
Short Circuit Dissipation
Input switching waveform & model for short circuit current.
• Ipeakis determined by the saturation current of devices, hence isproportional to the sizes of the transistor.
119
Impact of Rise/Fall Times onShort-Circuit Currents
• Power dissipation due to short circuit current is minimized byminimizing the rise and fall time of input and output signal.
120
Stage Ratio
- The object is to maximize the speed with minimum area overhead.
- Option I will be slow, since Gate1 will not have drive capability to drive thelarge inverter.
- In Option II, we have a chain of inverters of increasing size (by an order of a)
- Gate I will be fast, since it drives a minimum sized inverter (Inverter 1)
121
Stage Ratio
• When It is desired to drive large load capacitances such as long
buses, I/O buffers and off-chip capacitive loads.
• This is achieved by using a chain of inverters where each
successive inverter is made larger than the previous one.
• The ratio by which each stage is increased in size is called „ stage
ratio‟.
• The signal delays encountered in driving the off chip load directly
from a minimum sized inverter is unacceptable.
• The optimization to be achieved here is to minimize the delay
between input and output while minimizing the area and power
dissipation.
122
Stage Ratio
123
Stage Ratio
• Inverter 1 is a minimum- sized device.
• Subsequent inverter device sizes increase by a factor of „a‟
• Delay of each stage is „a * Td ‟, where Td =delay of minimum sizedinverter driving an identically sized inverter
• Hence total delay ( delay through the n stages ) is n * a * Td
• Cg is load of first driver which is minimum- sized device
• If CgN is the load capacitance of the Nth inverter then CgN = Cg * aN
• To guarantee that none of capacitances internal to the chain ofinverters exceed Cload[ why ?? ] we must have Cg * an = CL
here n = N +1
I.e an = CL/ Cg
124
Stage Ratio
Hence a = [CL/ Cg]1/n
Total delay = n * [CL/ Cg]1/n * Td
The optimum value of n isnopt = ln [CL/ Cg]
• Now optimum value of a i.e aopt can be calculated as;an = CL/ Cg
aln [CL/ Cg] = CL/ Cg
Taking natural log of both sides we get a = 2.7• But the actual stage ratio is given by
aopt = exp[(k+aopt)/aopt]Where k = Cdrain/Cgate
• For 1µ process k = 0.215, hence aopt = 2.93• For 2.5µ process k = 3.57 which gives aopt = 5.32
125
CMOS Dynamic Logic
Dynamic Charge Storage Clocked CMOS Logic
126
Dynamic Charge Storage
• Since the node is capacitive, we model it as a capacitor „C‟that can be used to hold a charge.
The logic‟1‟ is given at input Vi and control. The voltage acrossthe capacitor increases to
Vmax = (VDD - Vt )
127
Dynamic Charge Storage
Initially, Vs was at Vmax indicating that a logic 1 was stored onthe capacitor.
However, since leakage currents remove charge, Vmax cannotbe held and Vs will decrease in time.
Eventually, Vs will fall to a level where it will be incorrectlyinterpreted as a logic 0 value.
Because the stored charge will leak away over time, thiscircuit is termed a dynamic storage circuit.
128
Dynamic Charge Storage
• Since a transmission gate consist of a parallel NMOS andPMOS combination, reverse junction charge leakage will occur
whenever a TG is used to hold charge on an isolated node.When the TG is OFF, both transistor are in cut-off and twoleakage paths exit, one through each device.
The leakage current IRp through the PMOS adds charge to thenode, while the NMOS current Irn removes charge from thenode.Disadvantage :- requirement for dual polarity control signal
additional PMOS in TG.129
Dynamic Charge Storage
• The pass transistor can discharge the inverter gate to 0V togive a good low logic level. In this case, the inverter output ishigh and PMOS feedback transistor is OFF.The pass transistor can pull the inverter input voltage highenough to force the inverter‟s output to a low logic voltage.This low voltage turns on the PMOS feedback transistor,thereby pulling the inverter input to the upper supply voltageand holding it there.
130
Dynamic Charge Storage
• AdvantageArea efficient compared to the static storage circuit.Simplicity of the required circuitry.
131
Clocked CMOS Logic
C2MOS
Precharge Evaluate Logic
Domino CMOS
132
C2MOS
The clocked transistors are placed in series withthe p-channel and n-channel transistor of astandard inverter.
The layout is simplified because the source/drainregions of the two p-channel transistors can bemerged.
The output of C2MOS is available during the entireclock cycle. The load capacitor is the storage node for the
dynamic charge.
133
Precharge Evaluate Logic
The path between power and ground is brokenby two series transistor. No DC current pathfrom power to ground will exit at mutually
exclusive times.Minimum-size transistors can be usedthroughout.
The path to VDD is used to precharge the outputnode during part of the clock cycle, and thepath to ground is used to selectively dischargethe output node during another part of theclock cycle.The output is taken high during precharge timeand is logically valid during the discharge
cycle.Valid output available is less than 50% (forsquare-wave clock).
134
Precharge Evaluate Logic
Two phase operation determined by the clock signal n - block p - block
Precharge : = 0, out = 1 Precharge : = 1, out = 0Evaluate: = 1, out = F(x) Evaluate: = 0, out = F(x)
Input change during precharge and are stable during evaluate.
135
Precharge Evaluate Logic
Advantages:
Less area
Minimum-size transistors
Large number of transistors can be placed in series within thelogic section
Faster
Disadvantages:
Charge sharing
The addition of clock signals(minimum and maximum)
Output must be stored during precharge
136
Domino CMOS
P-E logic gate followed by a static inverter buffer at the output.
The buffer provides output drive capability to either VDD or
ground.
Domino CMOS is a non-inverting logic form
Use “keeper” transistor to maintain a pre-charged high.
137
Domino CMOS
Precharge : = 0, out = 0Evaluate : = 1, out = F(input)
138
Scaling of MOS Transistor Dimensions
Sub-Micron Considerations
Scaling Methods
139
Sub-micron Considerations
• When dimensions of MOS device go below 1µ then it‟s behaviordeviates substantially than actual MOS operation that has beendiscussed so far.
• For sub-micron range the channel length becomes comparable toother device parameters such as depth of drain and sourcejunctions, and width of their depletion regions.
• Such devices are called „ short channel transistors ‟ & representsthe deviation form ideal model.
140
Sub-Micron Considerations
•These second order effects that impact on device behaviorincludes
1. Variation in I-V characteristics
2. Mobility variation
3. Threshold voltage variation
4. Impact ionization- Hot electron
5. Tunneling
6. Drain punch-through
7. Channel length modulation
141
Variation in I -V Characteristics
• The I-V characteristics of short channel device deviateconsiderably from the ideal equations.
• ID= {( VGS -VT)VDS - (VDS2)/2} -----Linear region
• ID=(kn/2) W/L(VGS -VT)2 (1+ VDS)----Saturation region
• The most important reasons for this difference are the Velocitysaturation and mobility degradation.
• Velocity saturation : Carrier velocity is given as;
•n = n Ex = n*dv/dx
• This states that carrier velocity is proportional to electric field &is independent of value of that field, i.e it is constant.
142
Variation in I-V Characteristics
• But when the electric field along the channel reaches a criticalvalue Emax , velocity of carriers tend to saturate( i.e carriers reachtheir maximum limited velocity ).
• Current under the velocity saturated condition is
IDSAT =SAT* Cox * W (VGS - VDSAT - VT)• Thus the saturation current linearly depends on the gate-sourcevoltage.
• Also, ID is independent of L in velocity saturated devices.
• Reduction in the channel length causes reduction in the electronmobility even at normal electric field levels. This is called
„ mobility degradation „
143
Mobility Variation
• The mobility „M‟ describes the ease with which carriers drift in thesubstrate material
• It is defined as ratio of average carrier drift velocity „V‟ to theElectric field „E‟.
• Mobility can vary in number of ways viz :
• According to the type of charge carrier. [ WHY ??]
• Increase in doping concentration decreases mobility.
• Increase in temperature decreases mobility.
144
Threshold Voltage Variation
• As device dimensions are reduced threshold voltage becomesfunction of L,W and VDS
• The threshold voltage is not constant with respect to the voltagedifference between the substrate and the source of the MOStransistor. This is known as „ substrate bias effect‟ or „ body-
effect ‟.
145
Impact Ionization
•As the length of the gate decreases, electric field intensity atthe drain increases.
•In sub- micron devices, the field intensity can become veryhigh, to an extent that electrons are imparted with enough
energy to become „hot‟.
•These hot electrons can impact the drain, dislodging holes.
•These free holes will escape into the substrate creating asubstrate current. This effect is known as impact ionization
•This will degrade the transistor performance and can triggerlatch-up.
146
Impact Ionization
• The high- energy (hot) electrons can also penetrate the gate
oxide causing a gate current.
• This can lead to degradation of MOS device parameters.
• Hot- electron effects can be minimized by decreasing the supplyvoltage in smaller devices.
147
Tunnelling
• The gate is separated from the substrate by an oxide of thicknesstox , Generally the gate current in a MOS Transistor is zero
• When the gate oxide is very thin, a current can flow from gate tosource/drain
• This happens due to electron tunnelling through the gate oxide
• This gate-current is proportional to the area of the gate.
• This effect puts a limit on the minimum thickness of the gate oxidelayer, as processes are scaled
148
Drain Punch-Through
• If the drain is at a very high voltage with respect to source , thedepletion regions around the drain and source will meet
• This will cause a channel current to flow, irrespective of the gatevoltage, even if it is zero. This is known as punch-throughcondition.
• Punch-through can be avoided with,
• Thinner Oxides.
• Larger Substrate Doping.
• Shallower Junctions.
• Longer Channels.
149
Channel Length Modulation• In the saturation region, the ideal characteristics of a MOStransistor shows a constant current region,i.e.drain current IDS remains constant, with increase in VDS.
• This characteristics assumes that carrier mobility is constant.It does not take into account the variation in channel length
due to change in VDS.
• However, in saturation, as VDS increases, channel- length Ldecreases by a very small amount such that Leff = L - DL
• This decrease in L, increases the [W/ L] ratio, and henceincreases IDS due to increase in ß.
• For long channel lengths, influence of channel variation is oflittle consequence, but as devices are scaled down thisvariation has be taken into account.
150
Scaling Methods
• Scaling is method in which device geometries migrate tolower sizes while still maintaining the same devicecharacteristics.
• This is done by scaling the critical parameters of a devicein accordance to a given criteria.
• Scaling methods include
Lateral scaling
Constant field scaling
Constant voltage scaling
151
Lateral Scaling
LATERAL SCALING :
- Here the only parameter that is scaled is the gate length L
- This method of scaling is also called gate- shrink
- It can be easily done to an existing mask design
- Power dissipation increases by the factor
- Input capacitance of the transistor decreases by the factor
152
Constant Field Scaling
- A dimensionless scaling factor is applied to,• All dimensions (including vertical dimensions such as tox )are decreased by .
• Device voltages are decreased by • Concentration densities are increased by
• As a result,• Depletion thickness d.• Threshold voltage VT
• Drain Current IDS
also get scaled by the same factor
• Since the voltage VDD is scaled, the electric field in the device remainsconstant
• Hence, the operating characteristics of the device remain the sameeven after scaling
• Power dissipation decreases by 2
153
Constant Voltage Scaling
• Similar to constant field scaling, except that voltage VDD is keptConstant
• The current I DS increases by the factor
• Speed of the device increases by the factor
• Number of transistors per unit area increases by the factor 2
• As a result, the current density increases by the factor 3
• Proportionately wider metal wires are required for more denselypacked structures
• Power dissipation increases by the factor
• This will increase the need for cooling devices/ structures for theIC
• Power dissipation of above 1- 2 Watts require specialized coolingfins or packaging
154
CMOS Processing Technology
IC Fabrication : An Overview
Photolithography
CMOS Fabrication Process
Latch-Up in CMOS Circuits
Stick Diagrams
Layout Design Rules
Layout Examples
155
IC Fabrication
• An IC fabrication process contains a series of masking steps toCreate successive layers of insulating, conducting and semi-conducting material that define the transistors and metalinterconnect.• Techniques such as oxidation, implantation,deposition are usedto build these layers.
• The starting material used for IC fabrication is silicon wafer.Wafer is a disk of silicon, 4" to 8" in diameter, < 1mm thick,
• Wafers are very brittle, the larger the diameter, the moresusceptible to damage. Surface of the wafer is polished to a veryflat, scratch free surface.
• The single crystal silicon used as substrate is obtained frompolycrystalline silicon generally by CZ (czochralski ) process.Controlled amount of impurities are added to the melt to provide
156
IC Fabrication
the crystal with required electrical characteristics. After the crystalhas been developed several steps are involved to achieve mirror likestructure.
• Oxidation is used to deposit Silicon Dioxide (SiO2) on surface ofwafer to be used as insulting material - heat wafers inside of anoxidation atmosphere such as oxygen or water vapor.
• To build the micro(semiconductor) devices, we need junctionsformed by N and P type region. To create these regions on siliconwafer what we need is process to introduce impurity atoms intothe substrate.This may be achieved by using Epitaxy, Depositionand Ion-implantation.
157
IC Fabrication
• Epitaxy involves growing single crystal film (of the requireddopant) on silicon surface by heating wafer and exposing it to asource of the dopant.
• Deposition is to evaporate the dopant onto the surface, then heatthe surface to drive the impurities in the wafer
• Ion implantation involves exposing surface to highly energizeddopant atoms. When these atoms impinge on the surface, they travelbelow the surface forming the regions with varying doping
concentration.• During fabrication of the transistors or other structures it is neededto block some regions from receiving the dopants. Hence specialmaterial called as mask is used to block the impurities in particularregion.
158
Mask
•
•
Common material used for masks are Photoresist,Polysilicon, Silicon dioxide, Silicon nitride.
To create mask:(a) deposit mask material over entire surface
(b) cut windows in the mask to create exposed areas(c) deposit dopant
(d) remove un-required mask materialMasks plays important role in process called selective
diffusions.The selective diffusion involves
1. Patterning windows in a mask material on the surfaceof the wafer.
2. Subjecting the exposed areas to a dopant source.3. Removing any un-required mask material.
159
Photolithography
• The Process of using an optical image and a photosensitivefilm to produce a pattern on a substrate is photolithography
• Photolithography depends on a photosensitive film called aphoto-resist.
• Types of resist
• Positive resist, a resist that become soluble when exposedand forms a positive image of the plate.
• Negative resist, a resist that lose solubility whenilluminated forms a negative image of the plate.
160
Photolithography
p-type body
Substrate161
Photolithography
p-type body
Resist application162
Photolithography
p-type body
Exposure163
Photolithography
Etching
p-type body
Positive Resist164
Photolithography
Etching
p-type body
Negative Resist165
Fabrication of CMOS Devices
Technologies used for CMOS fabrications include
• N-well process
• P-well process
• Twin-tub process
• Silicon on insulator.
166
P-Wells and N-Wells
P substrate
contact [P+]
n+
GD
n+
IN
OUTS
p+
N substrate
contact [n+]
G
p+
P-well N-well
• A p- transistor is built on an n- substrate and an n- transistor isbuilt on a p-substrate
167
P-Wells and N-Wells
• In order to have both types of transistors on the same substrate, thesubstrate is divided into “well” regions (Shaded region in thestandard cells)
• Two types of wells are available - n- well and p- well
• In a p- substrate, an n- well is used to create a local region of n typesubstrate, wherein the designer can create p- transistors
• In a n- substrate, a p- well creates a local p- type substrate region, toaccommodate the n- transistors.
• Hence, every p- device is surrounded by an n- well, that must beconnected to VDD via a VDD substrate contact.
• Similarly, n- devices are surrounded by p- well connected to GNDusing a GND substrate contact.
168
CMOS Fabrication
NMOS
S GGate Oxide
D D
PMOS
G S
Polysilicon
Thick SiO2 (Isolation) SiO2
n+ n+ p+ p+
n well
p-type body
169
P-type Substrate
Thin Oxide
Silicon Crystal
p-type body
170
N-Well Diffusion
n well
p-type body
171
Si3N4 Ion Implant Barrier
Si3N4
n well
p-type body
172
N+ Guard Ring Implanted
n+ n+
n well
p-type body
173
P+ Guard Ring Implanted
p+ p+ n+ n+
n well
p-type body
174
Thick Oxide Grown
Thick Oxide
n well
p-type body
175
Si3N4 & Thin Oxide Strip
n well
p-type body
176
Gate Oxide Grown
n well
p-type body
177
Poly Layer
n well
p-type body
178
P-Channel Drain and Source
p+ p+
n well
p-type body
179
N-Channel Drain and Source
n+ n+ p+ p+
n well
p-type body
180
SiO2 Layer Deposited
n+ n+ p+ p+
n well
p-type body
181
Contact Openings (Cuts)
Contact Cuts
n+ n+ p+ p+
n well
p-type body
182
Metallisation (Metal 1)
n+ n+ p+ p+
n well
p-type body
183
The N-Well Process• Steps in N-well process :
1.Formation of n-well regions
2. Define N-MOS and P-MOS active areas.
3. Field and gate oxidations (thinox)
4. Form and pattern poly-silicon.
5. P+ diffusion
6. N+ diffusion
7. Contact cuts
8. Deposit and pattern metallization
9. Over glass with cuts for bonding pads
184
Latch-Up in CMOS Circuits
• Latch-up is condition in which parasitic components gives rise toestablishment of low-resistance conducting path between VDD &VSS
• This results in chip self-destruction or system failure.
• Latch-up may be induced by the glitches on the supply rails or byincident radiation.
185
Physical Origin Of Latch-up
V ss IN OUT
186
Latch-up Mechanism
• If sufficient current is drawn from NPNemitter then NPN ( Q2 )turns on when
Rwell
Q1
Q2
Rsubstrate
VBE 0.7V.
• When NPN turns on, note that emittercurrent increases exponentially with VBE
• Current flowing through the parasitic n-wellresistors will eventually turn on the parasitic
PNP
• As PNP turns on, the NPN base currentincreases and voltage drop across Rsubstrate
also increases, further increasing the NPNemitter current (Q2 turns on “harder”), whichfurther increases the PNP base current,
which again further increases NPN basecurrent.
187
Remedies for the Latch-up Problem
One way is to keep the p-substrate tied very closely (i.e.close
proximity) to GND (most negative supply) to reduce substrate
resistance (RS1 &RS2), and the n-well tied very closely to VDD
to reduce RW1 & RW2.
• Each well must have a substrate contact of appropriate type (n-type for n-well).
• Place substrate contacts as close as possible to the sourceconnection of transistors connected to the supply rails.
• Place a substrate contact for every 5- 10 transistors
• Lay out n and p- transistors with packing of n- devices towards Gndand p- devices towards VDD
188
CMOS Process Layers
Layer
Well (p,n)
Active Area
(n+,p+)
Select (p+,n+)Polysilicon
Metal1
Metal2
Contact To Poly
Contact To Diffusion
Via
Color Representation
Yellow
Green
Green
Red
Blue
Magenta
Black
Black
Black
189
Stick Diagram
• Before the cell can be constructed from a transistor schematic it isnecessary to develop a strategy for the cell's basic layout.
• Stick Diagrams are a means for the design engineer to visualize thecell routing and transistor placement.
• Steps involved in stick diagram construction.• STEP 1 :
-> Identify each transistor by a unique name of its gate signal-> Identify each connection to the transistor by a unique name
190
Stick Diagram
Figure 1:Schematicand Graph
191
Stick Diagram
STEP2 :
Figure.2Euler path
192
Stick Diagram
STEP2 :• Eulers paths : A path the traverses each node in the path, such
that each edge is visited only once.• The path is defined by the order of each transistor name.
• The Euler path of the Pull up network must be the same as thepath of the Pull down network.
• Euler paths are not necessarily unique.It may be necessary to redefine the function to find a Euler path.
F = E + (CD) + (AB) = (AB) +E + (CD)• Next step is to lay out the stick diagram
-> Trace two green lines horizontally to represent the NMOS andPMOS devices
-> The gate contact to the devices are represented by vertical strips-> Surround the NMOS device in a yellow box to represent the
surrounding Pwell material.
193
Stick Diagram
Figure 3: Connectionlabel layout
194
Stick Diagram
->Surround the PMOS device in a green box to represent thesurrounding Nwell material.
->Trace a blue line horizontally, above and below the PMOS andNMOS lines to represent the Metal 1 of VDD and VSS.
->Label each Poly line with the Euler path label, in order from left toright.
->Place the connection labels upon the NMOS and PMOS devices.Place the VDD, VSS and all output names upon the NMOS and
PMOS devices
195
Stick Diagram
Figure 3: Connectionlabel layout196
Figure 4: Stick Diagram, Interconnected
197
Schematic
198
Stick-diagram NAND Gate
199
Stick Diagram NOR Gate
200
Layout Design Rules
• Lithographic process is used to transfer pattern to each layer of IC.
• Limitations of patterning process gives rise toset of mask design guidelines called „ Design
Rules ‟.
• These guidelines specify minimum line width& minimum spacing allowed in a layout
drawing.
• Minimum line-width: Smallest dimensionpermitted for any object in the layoutdrawing ( minimum feature size ).
• Minimum spacing: Smallest distancepermitted between the edges of two objects.
• Violating a design rule might result in non-functional circuit or in highly reduced yield.
201
Layout Design Rules
• Even for the same minimum dimension, design rules tend todiffer from company to company and from process to process.
• One approach to address this is to use scalable design rules.These include
1. Lambda ( ) based rules.
2. Micron rules.
• Lambda ( ) based rules : These defines all the rules as functionof single parameter called .
• Scaling of the minimum dimension is accomplished simply bychanging the value of .
• Scaling factor lambda is foundry/silicon vendor dependent.
202
Layout Design Rules
• When mapping the transistor schematic/layout to a particulartechnology, the actual W, L will be calculated as:
W' (actual, microns (µ)) = W * (microns)
L' (actual, microns) = L * (microns)
( lambda ) is dimensionless unit called as scaling factor.
• Feature-size independent way of setting out mask dimensions toscale.
• For MOSIS foundry vendors, 2.0µ technology = 1.0
1.2µ technology = 0.6
0.8µ technology = 0.4.
• Typically the minimum gate length is set to 2 and width is varied.
203
Layout Design Rules
• Micron Rules :
• Linear scaling is possible over a limited range of dimensions,hence these rules are not used by industry. Normal industrialpractice is to deal with „ micron rules „
• Micron rules expresses the design rules in absolute dimensionsand hence can exploit the features of a given process to a
maximum degree.
• These are usually given as list of minimum feature sizes andspacing for al the masks required in an given process.
204
Design Rules
Examplesfrom AMS
0.6microntechnology
205
Intra-Layer Design Rules
206
Via‟s and Contacts
207
N Transistor - Layout
Bulk Source GateDrain
Thin-Oxide
208
P Transistor - Layout
Bulk Source
n-
Gate Drain
Thin-Oxide
209
Parallel/Series Transistors
210
Large MOS Transistors
211
AND Gate Layout
212
AND Gate - Layout
213
Inverter Layout
214
Inverter Layout
215
4-Input NAND Gate
216
Pseudo NMOS NAND Gate
217
Logic Graph for F = (A+B)C
218
Layout F = (A+B)C
219
Logic Graph for F = /(AB+CD)
220
Pass Transistor Based Multiplexer
F
221
Pass Transistor Based Multiplexer
222
Sense Amplifier
make DV as smallt = ---------------- as possiblep
large
Iav
small
Idea: Use Sense Amplifer
smalltransition s.a.
input output
223
Sense Amplifier
2- D Memory Organization
224
Sense Amplifier
225
Sense Amplifier
The bit lines exhibit the most sensitivity to capacitance of all thelarge nets, they offer the most opportunity for improvement.
By increasing the current flowing through the bit lines, they can bedischarged quickly and thus improve the switching time.
The sense amplifiers contain the current source for the bit lines. Byvarying the current through the bit lines, the delay due to parasitic
capacitance can be significantly reduced.
226
