CMPE 421 Advanced Parallel Computer Architecture Pipeline datapath and Control

CMPE 421Advanced Parallel Computer Architecture

Pipeline datapath and Control

A Pipeline DatapathRevised: Single Cycle Datapath

• An Instruction is divided into five pipelined stages. This means that five instructions will be in execution during any single cycle. For this reason we must separate the datapath into 5 pieces1. Instruction Fetch2. Instruction Decode/ Register Fetch3. ALU Operation4. Data Memory access5. Write result into register

Instruction Pipelining

Instruction Pipelining

• Instructions and data move from left to right through these five stages as the complete the executuion

• However, there are two exceptions to this left to right flow of instructions– The write back stage in which the result is written

back into the register file– Selecting the next value of the PC, choosing

between the incremented PC and the branch address

LW instruction for pipelined Datapath

To maintain proper time order, this stylized datapath breaks the register file into two logical parts: registers read during register fetch (ID) and registers written during write back (WB). This dual use is represented by drawing the unshaded left half of the register fi le using dashed lines in the ID stage, when it is not being written, and the unshaded right half in dashed lines in the WB stage, when it is not being read. As before, we assume the register fi le is written in the first half of the clock cycle and the register fi le is read during the second half.

• The pipeline registers, in color, separate each pipeline stage.• The pipeline register is used to pass any information needed in the next pipe stage • They are labeled by the stages that they separate; for example, the first is labeled IF/ID because it separates the

instruction fetch and instruction decode stages. The registers must be wide enough to store all the data corresponding to the lines that go through them. For example, the IF/ID register must be 64 bits wide, because it must hold both the 32-bit instruction fetched from memory and the incremented 32-bit PC address.

• We will expand these regis ters over the course of this chapter, but for now the other three pipeline registers contain 128, 97, and 64 bits, respectively

LW instruction for pipelined Datapath

INSTRUCTION FETCH

Instruction Decode

Execution stage

Memory stage

Data memory is read using the address in the EX/MEM pipeline registers, and the data is placed in the MEM/WB pipeline register. Next, data is read from the MEM/WB pipeline register and written into the register fi le in the middle of the datapath.

11

A Bug!

• When the value read from memory is written back to the register file, the inputs to the register file (write register #) are from a different instruction!

• To fix the bug we need to save the part of the lw instruction (5 bits of it specify which register should get the value from memory).

The corrected pipeline datapath to properly handle the load instrucution

The write register number now comes from the MEM/WB pipeline register along with the data. The register number is passed from the ID pipe stage until it reaches the MEM/WB pipeline register, adding fi ve more bits to the last three pipeline registers.

Five pipe stages of the store instruction

14

Store Datapath: Stage 3

15


16


Pipeline Control

• Just as control was added to single cycle and multi-cycle implementations we must add it to the pipelined processor

• Unlike single cycle and multi-cycle, no instruction determines how all the control signals should be set

• Pipelining the datapath leaves the meaning of control lines unchanged

• Control signals are pipelined too (grouped by stage)• The control unit is combinational again

Review: Single Cycle Control

Review: Single Cycle Control

Implementing Pipeline Control• Use a Main Control unit to generate signals during RF/ID

Stage– Control signals for EX (ExtOp, ALUSrc, …) used 1 cycle later– Control signals for Mem (MemWr, Branch) used 2 cycles later– Control signals for WB (MemtoReg, MemWr) used 3 cycles

later

Assumptions for pipelining the control signals• Initial design – motivated by single-cycle datapath control – use the

same control signals• Observe:

– No separate write signal for the PC as it is written every cycle– No separate write signals for the pipeline registers (IF/ID, ID/EX, EX/MEM,

MEM/WB), as they are written every cycle– No separate read signal for instruction memory as it is read every clock

cycle– No separate read signal for register file as it is read every clock cycle

• Need to set control signals during each pipeline stage• Since control signals are associated with components active during a

single pipeline stage, can group control lines into five groups according to pipeline stage

Will bemodifiedby hazarddetectionunit!!

Implementing Pipeline Control

IF/ID

Register

ID/E

x Register

Ex/M

EM

Register

ME

M/W

B R

egister

RF/ID EX MEM

RegDst

ALUOp

RegDst

ALUSrc

Branch

MemWr

MemtoReg

RegWr

MainControl

MemRead

ALUOp

RegDst

ALUSrc

MemtoReg

RegWr

MemtoReg

RegWr

MemtoReg

RegWr

Branch

MemWr

Branch

MemWr

WB

MemRead

23

Putting it All Together

P C

I n str u c ti o nm e m or y

Inst

ruct

i on

A d d

I n str u ctio n[ 2 0 – 1 6]

Me

mt o

Re

g

A L U O p

B r a n c h

R e g D s t

A L U S r c

4

1 6 3 2I n str u cti o n[ 1 5 – 0 ]

0

0

Mux

0

1

A d dA d d

r e s u lt

R e g i ste r sW riter e g i s ter

W rited a t a

R e a dd a ta 1

R e a dd a ta 2

R e a dr e g i s ter 1

R e a dr e g i s ter 2

S ig ne x t e n d

Mux

1

A L Ur e s u lt

Z e r o

Writed at a

R e a dd at a

Mux

1

A L Uc o ntr ol

S h iftle ft 2

Re

gW

rit e

M e m R e a d

C o ntr ol

A L U

I n str u ctio n[ 1 5 – 1 1]

6

E X

M

W B

M

W B

W BI F /I D

P C S r c

I D/ E X

E X /M E M

M E M/ W B

Mux

0

1

Me

mW

rite

A dd r e s s

D a tam e m o r y

A d d r e s s

24

Comparison

Clk

Cycle 1

Multiple Cycle Implementation:

IF Reg EX MEM WB

Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10

Load IF Reg EX MEM WB

IF Reg EX MEM

Load Store

Pipeline Implementation:

IF Reg EX MEM WBStore

Clk

Single Cycle Implementation:

Load Store Waste

IF

R-type

IF Reg EX MEM WBR-type

Cycle 1 Cycle 2

25

Instructionmemory

Instruction[20– 16]

Mem

toR

eg

ALUOp

Branch

RegDst

ALUSrc

4


0

Mux

0

1

Add Addresult

RegistersWriteregister

Writedata

Readdata 1

Readdata 2

Readregister 1

Readregister 2

Signextend

Mux

1

ALUresult

Zero

ALUcontrol

Shiftleft 2

Re

gWrit

e

MemRead

Control

ALU


EX

M

WB

M

WB

WB

Inst

ruct

ion

IF/ID EX/MEMID/EX

ID: before<1> EX: before<2> MEM: before<3> WB: before<4>

MEM/WB

IF: lw $10, 20($1)

000

00

0000

000

00

000

0

00

00

0

0

0

Mux

0

1

Add

PC

0

Datamemory

Address

Writedata

Readdata

Mux

1

WB

EX

M

Instructionmemory

Mem

toR

eg

ALUOp

Branch

RegDst

ALUSrc

4

0

Mux

0

1

Add Addresult

Writeregister

Writedata

Mux

1

ALUresult

Zero

ALUcontrol

Shiftleft 2

Re

gWrit

e

ALU

M

WB

WB

Inst

ruct

ion

IF/ID EX/MEMID/EX

ID: lw $10, 20($1) EX: before<1> MEM: before<2> WB: before<3>

MEM/WB

IF: sub $11, $2, $3

010

11

0001

000

00

000

0

00

00

0

0

0

Mux

0

1

Add

PC

0Writedata

Readdata

Mux

1

lwControl

Registers

Readdata 1

Readdata 2

Readregister 1

Readregister 2

X

10

20

X

1


Instruction[15– 0] Sign

extend


20

$X

$1

10

X

Me

mW

rite

MemRead

Me

mW

rite

Datamemory

Address

Address

Address

Clock 2

Clock 1

Instructionmemory

Address


Mem

toR

eg

Branch

ALUSrc

4


0

1

Add Addresult

RegistersWriteregister

Writedata

Readdata 1

Readdata 2

Readregister 1

Readregister 2

ALUresult

Shiftleft 2

Re

gWrit

e

MemRead

Control

ALU


EX

M

WB

WB

Inst

ruct

ion

IF/ID EX/MEMID/EX

ID: sub $11, $2, $3 EX: lw $10, . . . MEM: before<1> WB: before<2>

MEM/WB

IF: and $12, $4, $5

000

10

1100

010

11

000

1

00

00

0

0

0

Mux

0

1

Add

PC

0Writedata

Readdata

Mux

1

WB

EX

M

Instructionmemory

Address

Mem

toR

eg

ALUOp

Branch

RegDst

ALUSrc

4

0

0

1

Add Addresult

Writeregister

Writedata 1

ALUresult

ALUcontrol

Shiftleft 2

Re

gWrit

e

M

WB

Inst

ruct

ion

IF/ID EX/MEMID/EX

ID: and $12, $2, $3 EX: sub $11, . . . MEM: lw $10, . . . WB: before<1>

MEM/WB

IF: or $13, $6, $7

000

10

1100

000

10

101

0

11

10

0

0

0

Mux

0

1

Add

PC

0Writedata

Mux

1

andControl

Registers

Readdata 1

Readdata 2

Readregister 1

Readregister 2

12

X

X

5

4




X

$5

$4

X

12

Me

mW

rite

MemRead

Me

mW

rite

sub

11

X

X

3

2

X

$3

$2

X

11

$1

20

10

Mux

0

Mux

1

ALUOp

RegDst

ALUcontrol

M

WB

$3

$2

11

Mux

Mux

ALUAddress Read

dataData

memory

10

WB

Zero

Zero

Signextend

Signextend

Datamemory

Address

Clock 3

Clock 4

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CMPE 421 Advanced Parallel Computer Architecture Pipeline datapath and Control