CMS HL-LHC EM Calorimeter Upgrade M. Hansen, CERN

CMS HL-LHCEM Calorimeter Upgrade

M. Hansen, CERN

M. Hansen, CERN. [email protected]

Upgrade Requirements

Perform the full installation and commissioning in the planned LHC long shutdown 3

Make the system compatible with the CMS phase 2 level 1 trigger latency and rate Up to 1 MHz trigger rate Up to 12.5 us (25 us) level 1 trigger latency

Maintain or Improve availability E.g. by removing interdependency for controls

please see https://indico.cern.ch/event/433330/#preview:1607709

Mechanical compatibility with mother boards and cooling bars etc.

EB phase 2 electronics upgrade kick-off 20150723

https://indico.cern.ch/event/433330/#preview:1607709


Further upgrade Objectives

Improve the capability to detect and remove “spike” events in particular in the real time data sent to the level 1 trigger

Decrease the volume of services on YB0 in order to make the re-cabling easier and allow for a 30 month LS3 E.g by decreasing the LV current to the EB

Front End by using DCDC converters on the sLVRB (switching LVRB…), thus using less cables



Phase 2 ECAL Barrel FE electronics system

- Design idea Modularity

1 channel for readout and trigger As legacy for services (bias, LV)

Features Trigger-less Streaming

Requires 10 Gbps GBT 4 fibers per legacy tower


HSSer

HSSer

HSSer

GBT

GBT

GBT

ADC?PreAmp?

PD1

APD

PD2

APDPbW crystal

VFE card

FE card

PreAmp/ADC?

QIE?

9.6Gbps

4.8/9.6Gbps

9,6Gbps

4.8Gbps

Controls

Data stream + control handshake

Data stream

Data stream

LV regulator board, e.g 3 rad tol DCDC

External constraints

Modularity 25 readout channels organized as 5 phi strips APD and low voltage connectors fully defined Suggest to keep also the VFE – FE connector and the

LVRB – FE connectors as they perform well and are rated to 3GHz

Common developments lpGBT @ 10Gbps

Specification discussions ongoing

Versatile link+ In development

Low voltage regulator Radiation and magnetic field tolerant DCDC converter in production

EB phase 2 electronics upgrade kick-off 20150723 M. Hansen, CERN. [email protected]


LpGBT

Down-link: 2.56 Gb/s (64 –bit frame) User bandwidth with FEC12: 1.44 Gb/s or 36 bits / 40MHz

clock Up link: 10.24 Gb/s (256 –bit frame)

User bandwidth FEC12: 8 Gb/s FEC5: 9.13 Gb/s

Integration : Se further slides Phase/Frequency programmable clocks

4 independent clocks with 50ps phase resolution Frequencies: 40 / 80 / 160 / 320 / 640 / 1280 MHz

eLinks Serial protocol free bidirectional links



LpGBT

Controls: System control: IC channel: 80 Mb/s

Two I2C masters Programmable parallel port:16 x DIO Environmental parameters monitoring

10-bit ADC with 8 inputsTemperature sensor on chipProgrammable current source to drive an external temperature sensor

Experiment Control: EC channel: 80Mb/s Can control e.g a GBT-SCA

GBT Slow Control Asic

Up to 16 eLink control lanes



LpGBT eLinks

eLinks FEC5 @ 10.24 Gb/s Bandwidth options

28 links @ 320 Mb/s each gives 8 usable bits / LHC clock 14 links @ 640 Mb/s each gives 16 usable bits / LHC clock 7 links @ 1280 Mb/s each gives 32 usable bits / LHC clock

eLinks FEC12 @ 10.24 Gb/s Bandwidth options

24 links @ 320 Mb/s each gives 8 usable bits / LHC clock 12 links @ 640 Mb/s each gives 16 usable bits / LHC clock 6 links @ 1280 Mb/s each gives 32 usable bits / LHC clock

3 lpGBT links provide sufficient bandwidth for the expected FE system in either FEC5 or FEC12 mode



FE clock distribution Option 1a

Use the (non-skewable) eLink clocks as the only clock in the ADC / QIE (sampling, internally multiplied for eLink transmission)

Implement a PLL with clock skew function in each ADC in order to align sampling to beam

Requires a control interface, e.g. i2c

Option 1b As option 1a but using the skewable clocks and a DLL in each ADC

in order to fine tune the sampling phase Would use the dll in “short” setting in order to preserve sampling clock quality

Option 2 Develop a clock fan-out chip with a clock skew function for each

output Here, the ADC is somewhat (but not much) simpler but an additional ASIC is required

Option 1a, 1b appears attractive as it safely solves essentially all problems with a reduced number of ASICs



VFE to FE Data transmission

Available bandwidth (FEC12) E.g. 3 lpGBTs * (12 640 Mbit eLinks + 12 320 Mbit eLinks)

Implement one (640 Mbit) or two (640 + 320 Mbit) eLinks in every ADC / QIE for data streaming Macro exists for *** 130nm

Define CMS ECAL requirements early on in order to get incorporated

A few idle characters required in order to word-align at reception in the off detector electronics E.g. upon BC0 reception; note that the arrival time of the BC0 needs to be

skewed together with the clock Imagine e.g. an all zeros – all ones – all zeros transition as ADC response to the

BC0


Versatile link +

Plan to develop a ~uSD card sized combined receiver and 3 * transmitter Would suit us well Would take significantly less space than two

short SFPs as of the Versatile Link Studies ongoing to use Vcsel arrays

4* Tx or 4* Rx; not necessarily attractive to CMS ECAL



LVRB replacement

A radiation and magnetic field tolerant ACDC power module has been developed which meets, a priori, our requirements Investigate noise levels with an initial

demonstrator Determine grounding and shielding strategy Develop LVRB respecting the mechanical

requirements



Bulk power system

Essentially all LHC upgrade projects are planning to use DCDC POL converters in or close to the front end system

The DCDC converters developed to date allow up to 12V input, essentially non-regulated.

A common project, similar to the legacy, is starting up in order to investigate the feasibility of operating COTS bulk power supplies in the experimental cavern

I suggest we participate to that common project For info, I have an offer for a COTS bulk supply that

could allow powering a full ECAL SM with redundant power for about 5000 USD



Bias (HV) power system

Essentially, the requirements have not changed, thus the HV power system can be maintained. The key word is “maintained” The complete system will very likely need to

be renewed purely due to age. This has already started.


ADC

No or little discussion about the future ADC ADC development within the community not always

successful Previous experience very good

Buy a core and integrate in ASIC with rad tol design rules

Investigating possibility to go down the same route this time around i.e. make a common development

A specification early on is instrumental Number of channels (gains), Resolution, special

functions (e.g gain switching), etc.



Current EB R&D plan for TP

Develop the upgraded front end power system demonstrator Develop a carrier for e.g. the DCDC module described

last Tuesday afternoon by Federico Faccio Evaluate with legacy front end system Look out for issues with Noise and Thermal management

Develop a front end card Demonstrator Streaming data to the back end Look out for issues with Thermal management

Study existing CMS back end cards and define requirements for the future ECAL back end system E.g. cards developed for the CMS level 1 trigger phase 1

upgrade



Phase 2 ECAL Barrel FE electronics system


HSSer

HSSer

HSSer

lpGBT

lpGBT

lpGBTADC

- I2c interface?- Clock phase adjust?- Synch signal time skew?- Test pulse skew?- Baseline DACs?

Pre-Amplifier

- Test pulse injection?- I2c interface?- Baseline DACs?

VFE card

FE card

10.24Gbps

10.24Gbps

10.24Gbps

2.56Gbps

Controls

Data stream + control handshake

Data stream

Data stream

LV regulator board, with rad tol DCDC

The end.


GBT eLinks

Three lines: Clock, Data in, Data out Clock can be 40 MHz

Receive and transmit clock generated in internal pll

Receive clock can be as low as 80 MHz Transmit clock is the eLink speed

Sampling of Data in line is automatically optimized but no word alignment; serial stream essentially sent to logic.


Documents

CMS HL-LHC EM Calorimeter Upgrade M. Hansen, CERN