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CMS Week Sept 2002
HCAL Data ConcentratorHCAL Data ConcentratorStatus Report for RUWGStatus Report for RUWG
and Calibration WGand Calibration WG
Eric Hazen, Jim Rohlf, Shouxiang Wu
Boston University
27 Sept 2002 CMS HCAL -- J.Rohlf/E.Hazen 2
CMS Week Sept 2002
DCC Engineering StatusDCC Engineering Status
• Six prototype boards working
• Successful readout of 6 HTRs (144 channels) in test beam through SLink
• Simple event builder working – FPGA coding for more advanced version underway
• Final hardware design changes for SLink 64 ready to start
27 Sept 2002 CMS HCAL -- J.Rohlf/E.Hazen 3
CMS Week Sept 2002
DCC Block DiagramDCC Block DiagramPC-MIP Mezzanine Cards3 Channel Link Receivers
Dat
a fr
om
HT
R M
od
ule
s
Data Concentrator Logic PMC
PCI
PCI
PCI33/32
33/64
33/32to RUI
DCCFPGA
UniversePCI-VMEBridge
S-Link (64) LSC
SDRAM
TTCRx RJ-45 to aTTS(Fast status)
27 Sept 2002 CMS HCAL -- J.Rohlf/E.Hazen 4
CMS Week Sept 2002
DCC – Option IDCC – Option I
TriggerS-LINK
DAQS-LINK
FPGA
DCC LogicMezzanine Card
Spare StandardPMC Site
(33MHz 64 bit)
3x LinkReceiver
TTCRx
FE
Dat
a fr
om H
TR
Car
ds
(LV
DS
Ser
ial) V
ME
9Ux400 VME Motherboard (Design ~Frozen)
Proposed TransitionModule
FastTiming/Control
235 pin 2mmConnector
SCRAPPED
27 Sept 2002 CMS HCAL -- J.Rohlf/E.Hazen 5
CMS Week Sept 2002
DCC – Option IIDCC – Option II
Spare StandardPMC Site
(33MHz 64 bit)
3x LinkReceiver
TTCRx
VMEFastTiming/Control
235 pin 2mmConnector
DAQS-LINK64
DCC LogicMezzanine Card
FE
Dat
a fr
om H
TR
Car
ds
(LV
DS
Ser
ial)
RJ-
45
(10
pin)
TTC
aTTS
DAQ
Double-Width VME Module (one backplane slot)All I/O on Front Panel
Spare
27 Sept 2002 CMS HCAL -- J.Rohlf/E.Hazen 6
CMS Week Sept 2002
DCCDCC Development PlansDevelopment Plans
• Open issues for DCC logic board:– Readout Link… S-Link64 okay, but what clock
speed? Our DCC can only produce 200Mbyte/s.• Will run at 66MHz per discussions at CERN
– Hard Reset implementation: FPGA reconfiguration but no software re-write of registers? (Not relevant for our case)
– TTCrx BGA package required, or may we use mezzanine test board footprint?
27 Sept 2002 CMS HCAL -- J.Rohlf/E.Hazen 7
CMS Week Sept 2002
DCC Reset IssuesDCC Reset Issues
• ReSync: OK– Clear buffers, reset state machines, etc
• HardReset: ???– Reload FPGAs from flash (takes seconds)
• All flip-flops (internal registers on FPGA) are reset to power-up defaults.
• CPU must intervene to restore operation– I would expect that this is true for other subsystems?
– VME motherboard has VME-PCI bridge …and multiple PCI busses. Resetting these requires full
PCI bus re-configuration (by CPU)
– Proposal: make ReSync and HardReset identical for our DCC
27 Sept 2002 CMS HCAL -- J.Rohlf/E.Hazen 8
CMS Week Sept 2002
DCC Development PlansDCC Development Plans
• One more logic board prototype:– S-Link(64) output– aTTS outputs (RJ-45)– TTCrx BGA if required
• Overall Status:– Motherboard and Link Receivers produced
• Full qty for 32 DCCs plus spares
– Final logic board design pending final details…
27 Sept 2002 CMS HCAL -- J.Rohlf/E.Hazen 9
CMS Week Sept 2002
Proposed VME64x RulesProposed VME64x Rules
• VME64x(P) “Rules” Compliance?– Difficult for us to comply at
this late date. – All VME carrier boards have
been manufactured.
• However, most required features exist in our DCC design…
• See:– www.tundra.com
• Look for Universe II
VME 9Ux400 Motherboard Production completed
LVDS Link Receiver Production completed
DCC Logic Board Final design update underway
27 Sept 2002 CMS HCAL -- J.Rohlf/E.Hazen 10
CMS Week Sept 2002
Proposed VME64x RulesProposed VME64x Rules
• The “7 Golden Rules” per C.Schwick
1. Implement CR/CSR Space of VME64x– Universe II precludes this but provides own CSR layout
2. Implement the Serial Number– We can do this (but not at “standard” address)
3. …Plug and Play with “address relocation”…– Universe II supports address relocation and slot geographical addressing
4. Do not use dynamic function sizing…– Universe II memory footprint not known until PCI configuration is complete!
However, we can use fixed maximum size.
5. Do not use fixed base address– Fine, we don’t
6. Use re-programmable media for CR– CR is hardwired in Universe II
7. All other VME64x features are optional…– We don’t use any (except 3.3V)
27 Sept 2002 CMS HCAL -- J.Rohlf/E.Hazen 11
CMS Week Sept 2002
Proposed VME64x RulesProposed VME64x Rules
• HCAL DCC Implementation provides functionality similar to VME64x.
• Plug-and-play is supported, but requires specific software
• It is unfortunate that we cannot comply exactly with the “rules”, but our hardware is already built!
27 Sept 2002 CMS HCAL -- J.Rohlf/E.Hazen 12
CMS Week Sept 2002
Byte 3 Byte 2 Byte 0Link Header Event no. b0-7Ext. Header 1Ext. Header 2 TrgTyp | BC No. (12 bits) HTR No.Trig Towers 1-4 Tower 4 Tower 3 Tower 1 Trig Towers, cont.Trigger Feature bits bits 24-31 bits 16-23 bits 0-7Channel Data Channel Data, cont.Link Trailer Event no. b0-7 Link Errors
DataDataData
Byte 1
Word Count
Word CountNumTT | Mode (11 bits)Orbit No.
DCC Input IDEvent no. b8-24
bits 7-15
Tower 2
Data
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0ERR DAVChannel No CapID QIE Data
HCAL HTR Data FormatHCAL HTR Data Format
Format for one channel
27 Sept 2002 CMS HCAL -- J.Rohlf/E.Hazen 13
CMS Week Sept 2002
DCC Output FormatDCC Output Format
• Follows Latest RUWG Guidance– Payload format preliminary – for size estimate
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Source_id (10+2) FOVBOE_1 Evt_ty LV1_id (24) Hx $$BX_id (12)KKDDDDDDDDDDDDDDDDK EOE xxxx Evt_lgth (24) CRC (16)
HTR1 Trailer
Source_id (10+2) FOVBOE_2BOE_1 Evt_ty LV1_id (24) Hx $$
xx $$xxxx Evt_stat (8)
BX_id (12)
HTR 1 Header [1]HTR1 Header [2] HTR 1 Header [3]HTR1 Data [1] HTR1 Data [2]
DCC Event Header
HTR2 Header[1]HTR2 Header [2] HTR2 Header[3]HTR2 Data [1] HTR2 Data [2]
HTR2 Trailer
Optional pad word DCC Event Trailer
27 Sept 2002 CMS HCAL -- J.Rohlf/E.Hazen 14
CMS Week Sept 2002
DCC Event SizeDCC Event Size
• Estimate based on preliminary format– Can be reduced if necessary
(contains diagnostic / error info for each datum)
HTRs/DCC 12
324576
1324560
100%for Occupancy
32328
3848
3842748
4987
HTR L1 DataHTR L2 Data
Total (bytes/event)
15%
FED Overhead
Event HTR
32
HTR Overhead8
32DCC Overhead
PRELIMIN
ARY
~2000