174 WEST 18TH AVECOLUMBUS OHIO 43210

THE OHIO STATE UNIVERSITY

ELECTRONICS LABPHYSICS DEPARTMENT

mojo

BLOCK

1-26-2006_15:07

174 WEST 18TH AVECOLUMBUS OHIO 43210

THE OHIO STATE UNIVERSITY

ELECTRONICS LABPHYSICS DEPARTMENT

mojo

FIFO_R_ENB

FIFO_R_CLK

On FIFO

FIFO_R_CLK

FIFO_R_ENB

FIFO_EREN

Data_on_FPGA

CLKFIFO12ns clock cycle

On PCBFIFO_EREN

SLINK_CLK

SLINK_data

DCCSTX Design: This is the DCC to SLINK interface FPGA design. It receives ten DDUs, and sends to two (or one) Slink64.The maximum data rate for each input FIFO is 150MHz at 36-bit wide, as fake DDR; the output is 75MHz at 72bit wide.This FPGA can also talk directly to computer through the Gigabit Ethernet Interface

Mar. 8, 2005: Copied from DCCESTX, pinout needs be fixed by D785SMar. 17, 2005: Put in the pinout information

CLK2X

16ns clock cycleCLKGIGA/CLKSLINK

May 3, 2005: Finalize the pin location, All pins are located, Pin usage 491/556

BoardID will be stored in INPROM: XDCCYYYX: X is the board ID, 1 to 15, YYY: Date code. Day/2, Month, YearExample: 2DCC4652: DCC board #2, Date: 2005, June, either 8th or 9th

June 2005: Redo the FIFO readout timing, backpressure logicDec. 2005: Add some diagnositic display on the LED, debug the FMM signals, deleted the PROG monitoring signalsJan. 2007: Put in the Force FMM, and SlinkID option.

OPAD

INV

INV

INV

INV

OPAD

OPAD

AND3

4

3

2

1

4

3

2

1

DCBA

TITLETHE OHIO STATE UNIVERSITY

PHYSICS DEPARTMENT ELECTRONICS LAB174 WEST 18TH AVE, COLUMBUS OH 43210

PARENT PAGEBY

DATE FILE

.PAGE

PROJECT

GN

D

OPAD

AND3

OR2B1

VC

C

INV

OPAD

LVCMOS25

OBUF

LVCMOS25

OBUF

LVCMOS25

OBUF

INV

BUFG

BUFG

BUFG

BUFG

CLKOUT_PHASE_SHIFT="NONE"

STARTUP_WAIT="FALSE"PHASE_SHIFT=0DUTY_CYCLE_CORRECTION="TRUE"DSS_MODE="NONE"DLL_FREQUENCY_MODE="LOW"DFS_FREQUENCY_MODE="LOW"

CLKIN_DIVIDE_BY_2="FALSE"DESKEW_ADJUST="SYSTEM_SYNCHRONOUS"

DSSEN

CLKIN

RST

PSINCDEC

PSEN

PSCLK

CLK0

CLK90

CLK180

CLK270

CLK2X

CLK2X180

CLKDV

CLKFX

CLKFX180

LOCKED

STATUS[7:0]

PSDONE

CLKFB

DCM

Q

D

A0

A1

A2

A3

CLK

@INIT="0000"

SRL16

CLKOUT_PHASE_SHIFT="NONE"

STARTUP_WAIT="FALSE"PHASE_SHIFT=0DUTY_CYCLE_CORRECTION="TRUE"DSS_MODE="NONE"DLL_FREQUENCY_MODE="LOW"DFS_FREQUENCY_MODE="LOW"

CLKIN_DIVIDE_BY_2="FALSE"DESKEW_ADJUST="SYSTEM_SYNCHRONOUS"

DSSEN

CLKIN

RST

PSINCDEC

PSEN

PSCLK

CLK0

CLK90

CLK180

CLK270

CLK2X

CLK2X180

CLKDV

CLKFX

CLKFX180

LOCKED

STATUS[7:0]

PSDONE

CLKFB

DCMIPAD

IPADLVCMOS25

IBUFG

C1

D1

CLR

PREQD0

CE

C0

FDDRCPE

LVCMOS25

OBUF

C1

D1

CLR

PREQD0

CE

C0

FDDRCPE

C1

D1

CLR

PREQD0

CE

C0

FDDRCPE

C1

D1

CLR

PREQD0

CE

C0

FDDRCPE

C1

D1

CLR

PREQD0

CE

C0

FDDRCPE

CLKOUT_PHASE_SHIFT="NONE"

STARTUP_WAIT="FALSE"PHASE_SHIFT=0DUTY_CYCLE_CORRECTION="TRUE"DSS_MODE="NONE"DLL_FREQUENCY_MODE="LOW"DFS_FREQUENCY_MODE="LOW"

CLKIN_DIVIDE_BY_2="FALSE"DESKEW_ADJUST="SYSTEM_SYNCHRONOUS"

DSSEN

CLKIN

RST

PSINCDEC

PSEN

PSCLK

CLK0

CLK90

CLK180

CLK270

CLK2X

CLK2X180

CLKDV

CLKFX

CLKFX180

LOCKED

STATUS[7:0]

PSDONE

CLKFB

DCM

BUFG

LVCMOS25

IBUFG

IPAD

IPAD

LVDS_25

IBUFGDS BUFG

BUFG

BUFG

IPADLVCMOS25

IBUFG

LVCMOS25 SLOW

OBUFQD

C

FD

Q

D

A0

A1

A2

A3

CLK

@INIT="0000"

SRL16 Feedback clock into the FPGA

bottom 2 fifos

Middle 3 fifos

12

GUCMS CSC Electronics

DCCSTXDCC <--> SLINK data interface FPGAClock distribution

Upper five FIFO read clock

top 2 fifos

Middle 3 fifos

Lower five FIFO read clock

FPGA clock distribution

CLKFIFO is 75MHz; CLKREAD is 150MHzThe FIFO read is 150MHz SDR, and tranfer to 75MHz double_data_width through IOB, 'feksDDR'

Timing: REN by falling edge of CLKFIFO; RCLK by falling edge of CLKREAD1

It seems that the CLKSLINK is not necessary, use CLKGIGA instead

1BLOCK1-4-2007_8:41

20NSMAINCLK

LOGICH

VSLCLK

LOCKED

PRELOCKED

SLOWCLK

6

AJ15

AJ16

AH16

CLK2X

CLKCMS

CLKDV_DIVIDE=16.0CLKFX_DIVIDE=2CLKFX_MULTIPLY=2

FACTORY_JF=C080

CLK_FEEDBACK=1X

CLKIN_PERIOD=20

LOC=DCM_X2Y1

PERIOD=16NSCLKCMS

FAST 24

F15

G15

CLKDV_DIVIDE=2CLK_FEEDBACK=1X

CLKFX_DIVIDE=5

CLKIN_PERIOD=6

CLKFX_MULTIPLY=2

FACTORY_JF=C080

FACTORY_JF=C080

CLKFX_MULTIPLY=4

CLKIN_PERIOD=12

CLKFX_DIVIDE=5

CLK_FEEDBACK=1XCLKDV_DIVIDE=16

CLKI2CPERIOD=100NS

PERIOD=10NSCLKSLINK

CLKREF

CLKFIFOPERIOD=10NS

24FAST

FAST 24

24FAST

CLKGIGAPERIOD=12NSCLK2X

PERIOD=5NS

PERIOD=12NSCLK625

CLK625LOCK2

LOCK1

AF16

CLK2X

CLK2X

DCMRST40VMEREADY

LOCK1

SW1

AG16

LOGICL

LOGICH

SW2

SW3

DCMRST AF15

AG15

LOCK2

LOGICL

LOGICL

LOGICH

LOGICL

LOGICL

LOGICH

LOGICL

LOGICL

LOGICH

LOGICL

LOGICL

LOGICH

LOGICH

CLKREF

CLKREF

CLK2X

CLK2X

CLK2X

CLK2X

CLK2X

CLK2X

CLKGIGA

LOCK2

LOGICH

LOGICL

LOGICL

CLK2X

CLK2X

AH15

LOGICH

LOGICL

LOGICL

LOGICH

LOGICH

LOGICL

LOGICL

LOGICH

VSLCLK

LOGICL

LOGICL

LOGICL

AND2B1 D0

D1O

S0

M2_1

4

3

2

1

4

3

2

1

DCBA

TITLETHE OHIO STATE UNIVERSITY

PHYSICS DEPARTMENT ELECTRONICS LAB174 WEST 18TH AVE, COLUMBUS OH 43210

PARENT PAGEBY

DATE FILE

.PAGE

PROJECT

OR4B1

LVCMOS25

IBUFIPAD

IPAD

IPAD

IPAD

OPAD

OPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IOPAD

IOPAD

IOPAD

IOPAD

IOPAD

IOPAD

IOPAD

IOPAD

IOPAD

IOPAD

IOPAD

IOPAD

IOPAD

IOPAD

IOPAD

P U L L

U P

LVCMOS25

IBUFLVCMOS25

IBUFLVCMOS25

IBUF

LVCMOS25

IBUF

LVCMOS25

IBUF

LVCMOS25

IBUF

LVCMOS25

IBUF

LVCMOS25

IBUFLVCMOS25

IBUF

LVCMOS25

IBUF

LVCMOS25

IBUF

LVCMOS25

IBUF

LVCMOS25

IBUF

LVCMOS25

IBUF

P U L L

U P

LVCMOS25

IBUF

P U L L

U P

P U L L

U P

LVCMOS25

IBUF

P U L L

U P

LVCMOS25

IBUF

P U L L

U P

LVCMOS25 SLOW 12

OBUFLVCMOS25 SLOW 12

OBUF

INV

LVCMOS25

IBUF

CEO

CLRC

CE

Q[7:0]

TC

CB8CE

AND2B2

LVCMOS25 SLOW 12

OBUF

IOPAD

IPAD

IPAD

IPAD

OPAD

IPAD

IPADLVCMOS25

IBUF

CCLR

D Q

FDC

CCLR

D Q

FDCQD

C

FD

IPADLVCMOS25

IBUFC

CLR

D Q

FDC

INV

CEO

CLRC

CE

Q[7:0]

TC

CB8CEIPAD

QDPRE

C

FDP

TCCLR

C

CE

Q[15:0]

CEO

CB16CE

CCLR

D Q

FDC

INV

D0

D1O

S0

M2_1

AND2B1

BUF

BUF

ADR[23:1]

AM[5:0]

BOARDID[3:0]

DATA[15:0] DDUOK[10:1]

DETRST

DIAGOUT[15:0]

FASTCLK

FIFOUSE[9:0]

L1AMODE

RATEMON[191:0]

RESET

SLOWCLK

STATUS[31:0]

SWSET[15:0]

SW[3:1]

AS

BERR

DS0

DS1

DTACK

GA[5:0]

IACK

LWORD

SYSFAIL

TOVME

WRITE

VME

LED[2:0]

VMELPBK[9:0]

FORMEM[15:0]

CMS CSC Electronics

GU 1

GAP

TOVME: low, from PCB to VME, high, from VME to PCB

FASTCLK: 40MHz

DCCSTXDCC <--> Slink FPGAVME command decoder

On Board Reset

TTCrx Reset

VME Power-on Resetand Reset Input FPGAs (TRGCNTRL3)

P10

2A

Push Botton Reset

SLOWCLK: 2.5MHz

VMELPBK[9:0]

LED[2:0]

2BLOCK1-26-2007_16:23

IGNSLINK[1:0]IGNSLINK0

IGNSLINK1

GA[5:0]

GA5

GA4

GA2

GA1

GA3

GA0

SWSET13

SWSET13

SWSET12

SWSET0SWSET[15:0]

SWSET4

SWSET5

SWSET9

SWSET14

SWSET15

SWSET12

SWSETZN

SWSETZNSWSET0

SWSET9

SWSET[15:0]

SWSET5SW5

DISTTCRDY

SWSET4

HSW5

BXCTERM

HBXCTERM

HSW5

BOARDID[3:0]

RATEMON[191:0]

RATEMON[191:96]

RATEMON[95:0]

DDUOK[10:1]

DETRST

L1AMODE

LRESET

LOGICL

LOCKED

ASUSELOWSKEWLINES

TRESET

GLBRSTPRESET

LOGICH

FPGAREADY

E19

CLKCMS

GLBRST

B10

SW[3:1]

SW[3:1]SW1

SW2

SW3

FIFOUSE[9:0]

FIFOUSE[4:0]

FIFOUSE[9:5]

DATA1DATA0

DATA[15:0]DATA15DATA14DATA13DATA12DATA11DATA10DATA9DATA8DATA7DATA6DATA5DATA4DATA3DATA2

FPGARST

SLOWCLK

FPGARSTFPGARST

SLOWCLK

ISW4K6

F19

G16

D13

C22

G17

C16

STATUS[31:0]

LOCKED

DTACK

DTACK

ADR[23:01]

TIMER7 TIMER6

TIMER[7:0]

TIMER7

TOVME

SLOWCLK

ISYSRST

CLKCMS

DOE

SLOWCLK

AM5AM4AM3AM2AM1AM0

AM[5:0]

SYSRST

ODTACK

ADR[23:01]

ADR15ADR16ADR17ADR18ADR19

ADR23ADR22ADR21ADR20

ADR14ADR13ADR12ADR11ADR10ADR09ADR08ADR07ADR06ADR05ADR04ADR03ADR02ADR01

WRITE

WRITE

TOVME

IGA4

IGA3

IGA2

IGA1

IGA0

GA[5:0]

DATA[15:0]

AM[5:0]

DS1

DS0

LWORD

AS

BERR

IACK

SYSFAIL

BERRIBERR

SYSFAILISYSFAIL

IWRITE

IAS

IDS1

IDS0

ILWORD LWORD

DS1

DS0

INACK IACK

ISW3

ISW2

ISW1

OTOVME

IGA5

TOVME

TOVME

TIMER7

SLOWCLK

B16

E16

D16

C18

D18

H16

J16

H17

J17

D17

E17

G18

H18

C20

C21

B22

F20

A21

B21

E18

G19

B23

E20

A23

H19

D20

F24

F23

E25

E24

C15

H22

F21

G23

G22

E22

E23

H21

D21

D24

G21

C24

F22

H20

D23

G20

C23

E21

H15

J15

D15

E15

C13

F17

F16

J1

D10

H10

M8 ISW5

IGLOBALRST

LOGICH

LOGICH

FPGARST

DIAGCMD[15:0]

HBXCTERM

SWSET15

SWSET14

FORFMM[15:0]

BC0

BXCTERM

BXRST

CALIB

CLK2X

CLKCMS

CLKFIFO

CLKGIGA

CLKREF

CLKSLINK

EVCRST

FFCTRL[5:0]

FFIN[35:0]

FIFOUSE[5:1]

FMM[3:0]

GIGAACT

GIGAOK

GIGATXRST

IFFSTAT[14:0]

L1A

L1AEMPTY

L1AMODE

OFFIN[71:64]

OFFSTAT[4:0]

ONLYDATA

ORBITRST

RATEMON[95:0]

RESET

RXN

RXP

SLCTRL[3:0]

SLINKACT

SLINKID[11:0]

SL_LED

SSTAT[5:0]

SW[3:1]

TXN

TXP

VSLCLK

INFOEN[5:1]

RENOUT[5:1]

SLINK

FFOUT[71:0]

IGNSLINK[1:0]

BUF

BUF

BUF

OPAD

OPAD

OPAD

OPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

OPAD

OPAD

LVCMOS25

IBUF

LVCMOS25

IBUF

LVCMOS25

IBUF

LVCMOS25

IBUF

LVCMOS25

IBUF

LVCMOS25

IBUFLVCMOS25

IBUFLVCMOS25

IBUF

LVCMOS25

IBUFLVCMOS25

IBUFLVCMOS25

IBUF

LVCMOS25

IBUFLVCMOS25

IBUFLVCMOS25

IBUF

LVCMOS25

IBUFLVCMOS25

IBUFLVCMOS25

IBUF

LVCMOS25

IBUF

LVCMOS25

IBUF

LVCMOS25

IBUF

BUF

BUF

BUF

BUF

IPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

IPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPADIPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

4

3

2

1

4

3

2

1

DCBA

TITLETHE OHIO STATE UNIVERSITY

PHYSICS DEPARTMENT ELECTRONICS LAB174 WEST 18TH AVE, COLUMBUS OH 43210

PARENT PAGEBY

DATE FILE

.PAGE

PROJECT

IPAD

OPADIPAD

BUF

BUF

LVCMOS25

IBUF

IPAD

IPAD

LVCMOS25 SLOW 12

OBUFOPAD

IPAD

IPAD

IPAD

OPADLVCMOS25 SLOW 12

OBUF

BUF

BUF

BUF

OPADLVCMOS25 SLOW 12

OBUF

2EE=750

F5

F4

F3

F2

F1

F1

F2

F3

F4

F5

1GUCMS CSC Electronics

DCCSTXDCC <--> SLINK data interface FPGATop Level for Slink_A

72-bit data to the output FIFO

F5

F4

F3

F2

F1

EMPTYs

PAEs

The output FIFO control

The Slink Status

The output FIFO control

EREN

ERCLK

REN

RCLK

WEN

WCLK

P20For upper S_link Design, bank 5,6,7

2B

USF3

USF2

USF1

USF0

SLINK

Special functionsInput lines

S-link control

UCLK

URESET*

UCTRL*

UTEST*

The output FIFO status

PAF*

HALPF*

PAE*

EMPTY*

FULL*

LFF*

LDOWN*

LRL0

LRL1

LRL2

LRL3

LRL[3:0] Link return line

Output of the out_fifo, which are the data flow control information

LSF3

LSF2

LSF1

LSF0

From SLINK, Special functions output lines

Five input FIFO control OEN/REN

Fulls

Corresponding to SlinkAct1 and GigaAct1 in PCB schematics

Five input FIFO data

The FA* data names match with A marker in PCB design

2F0=752

3BLOCK3-22-2007_2:44

LOGICL

LOGICH

IGNSLINK[1:0]

FAOUT[71:0]

RATEMON[95:0]

CLKSLINK

SW[3:1]

OFACTRL[5:0]

SLINKACTA

H4

SL_LEDA

FPGARST

LOGICH

EXTROUTH

L1AMODE

CALIBMOD

FMMA[3:0]

EXTROUTH H3

CLK2X

FADATA[35:0]

FADATA[35:0]

FADATA28

FADATA29

FADATA31

FADATA32

FADATA33

FADATA34

FADATA35

FADATA30

FADATA27

FADATA26

FADATA24

FADATA23

FADATA22

FADATA21

FADATA20

FADATA19

FADATA18

FADATA17

FADATA16

FADATA15

FADATA13

FADATA12

FADATA11

FADATA9

FADATA8

FADATA7

FADATA6

FADATA5

FADATA4

FADATA3

FADATA2

FADATA1

FADATA0

FADATA10

FADATA14

FADATA25

AF17

A17

A18

M7SLINKACTA

SACTRL1

SACTRL2

SACTRL3

SACTRL[3:0]

SACTRL0F29

Y27

OFAD[71:64]OFAD71

OFAD70

OFAD69

OFAD68

OFAD67

OFAD66

OFAD65

OFAD64

SLINKAID[11:0]

SLINKAID1

SLINKAID2

SLINKAID3

SLINKAID4

SLINKAID5

SLINKAID6

SLINKAID7

SLINKAID8

SLINKAID9

SLINKAID10

SLINKAID11

SLINKAID0

AA30AJ28

Y26

OFACTRL5

OFACTRL4

OFACTRL[5:0]

OFACTRL3

OFACTRL2

OFACTRL1

OFACTRL0

SASTAT5

SASTAT[5:0]

SASTAT4

SASTAT3

SASTAT1

SASTAT0

SASTAT2

FAOUT[71:0]FAOUT35

FAOUT34

FAOUT33

FAOUT32

FAOUT31

FAOUT30

FAOUT29

FAOUT28

FAOUT27

FAOUT26

FAOUT25

FAOUT24

FAOUT23

FAOUT22

FAOUT21

FAOUT20

FAOUT19

FAOUT18

FAOUT17

FAOUT16

FAOUT15

FAOUT14

FAOUT13

FAOUT12

FAOUT11

FAOUT10

FAOUT9

FAOUT8

FAOUT7

FAOUT6

FAOUT5

FAOUT4

FAOUT3

FAOUT2

FAOUT1

FAOUT0

FAOUT36

FAOUT71FAOUT[71:0]

FAOUT70

FAOUT69

FAOUT68

FAOUT67

FAOUT66

FAOUT65

FAOUT64

FAOUT63

FAOUT62

FAOUT61

FAOUT60

FAOUT59

FAOUT58

FAOUT57

FAOUT56

FAOUT55

FAOUT54

FAOUT53

FAOUT52

FAOUT51

FAOUT50

FAOUT49

FAOUT48

FAOUT47

FAOUT46

FAOUT45

FAOUT44

FAOUT43

FAOUT42

FAOUT41

FAOUT40

FAOUT39

FAOUT38

FAOUT37

IFAOEN5IFAOEN[5:1]

IFAOEN4

IFAOEN3

IFAOEN2

IFAOEN1

IFAREN5IFAREN[5:1]

IFAREN4

IFAREN3

IFAREN2

IFAREN1

AG17

AB16

AC16

AD17

AE17

AF19

AF18

AG18

AH18

AG20

AJ21

AK21

D30

C27

D28

J23

E28

H25

H26

D29AH26

AK28

AD21

AE23

AA23

AE30

AB23

AE28

AB8

AE29

AE27

AF28

AE4

E27

E29

K23

W25

F28

AF25

AA24

AF4

AB24

AC21

AJ23

AE24

AG26

AD27

F27

J30

M25

K25

W28

W27

V24

V23

V25

V26

AA29

Y29

Y30

W30

U23

U24

R24

R23

P27

P26

N28

N27

P29

P28

P30

N30

P24

P23

R22

P22

M28

M27U22

T22

V27

V28

U26

U27

W29

V29

L27

L26

N29

M29

M30

L30

N26

N25U28

U29

T23

T24

T25

T26

T27

T28

N24

N23

K28

K27

J28

J27

L29

K29R28

R27

V30

U30

T29

R29

R26

R25

C30

C26

J24

C29

GIGAOKA

AB28

IFASTAT[14:0]

IFASTAT2

IFASTAT1

IFASTAT0

IFASTAT3

IFASTAT4

IFASTAT5

IFASTAT6

IFASTAT7

IFASTAT8

IFASTAT9

IFASTAT10

IFASTAT11

IFASTAT12

IFASTAT13

IFASTAT14

OFASTAT[4:0]

OFASTAT3

OFASTAT2

OFASTAT1

OFASTAT0

OFASTAT4

A20

A19

SLINKAID[11:0]

GIGAOKA

TXPA

TXNA

IFAREN[5:1]

IFAOEN[5:1]

SACTRL[3:0]

L1AEMPTYA

STUCKDA

FIFOUSE[4:0]

RXNA

RXPA

SASTAT[5:0]

LRESET

ORBITRST

OFASTAT[4:0]

OFAD[71:64]

L1ACC

IFASTAT[14:0]

EVCRST

CLKREF

CLKGIGA

CLKFIFO

CLKCMS

BXCRST

BXCTERM

BC0

AG23

AH23

AF20

AH21

AH20

AB17

AC17

AC18

AD18

AE20

AE19

AE22

AE21

AH22

AJ22

AF21

AG21

AC19

AD19

AC20

AD20

AF23

AF22

A10

AB26

AK23

K30

M26

AA28

J25

G27

E30

K24

FIFOUSE4FIFOUSE[4:0]

FIFOUSE3

FIFOUSE2

FIFOUSE0

FIFOUSE1

LOGICH

LOGICH

LOGICH

LOGICL

LOGICL

LOGICL

SL_LEDA

VSLCLK

LOGICL

LOGICL

LOGICL

LOGICL

LOGICH

LOGICH

LOGICH

LOGICL

BC0

BXCTERM

BXRST

CALIB

CLK2X

CLKCMS

CLKFIFO

CLKGIGA

CLKREF

CLKSLINK

EVCRST

FFCTRL[5:0]

FFIN[35:0]

FIFOUSE[5:1]

FMM[3:0]

GIGAACT

GIGAOK

GIGATXRST

IFFSTAT[14:0]

L1A

L1AEMPTY

L1AMODE

OFFIN[71:64]

OFFSTAT[4:0]

ONLYDATA

ORBITRST

RATEMON[95:0]

RESET

RXN

RXP

SLCTRL[3:0]

SLINKACT

SLINKID[11:0]

SL_LED

SSTAT[5:0]

SW[3:1]

TXN

TXP

VSLCLK

INFOEN[5:1]

RENOUT[5:1]

SLINK

FFOUT[71:0]

IGNSLINK[1:0]

OPAD

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

LVCMOS25 SLOW 12

OBUF

LVCMOS25 SLOW 12

OBUF

IPAD

IPAD

OPAD

OPAD

LVCMOS25

IBUF

LVCMOS25

IBUF

LVCMOS25

IBUF

LVCMOS25

IBUF

LVCMOS25

IBUF

LVCMOS25

IBUFLVCMOS25

IBUFLVCMOS25

IBUF

LVCMOS25

IBUFLVCMOS25

IBUFLVCMOS25

IBUF

LVCMOS25

IBUFLVCMOS25

IBUFLVCMOS25

IBUF

LVCMOS25

IBUFLVCMOS25

IBUFLVCMOS25

IBUF

LVCMOS25

IBUF

LVCMOS25

IBUF

LVCMOS25

IBUF

LVCMOS25

IBUFIPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPADIPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

OPAD

OPAD

OPAD

OPAD

OPAD

IPAD

IPAD

IPAD

4

3

2

1

4

3

2

1

DCBA

TITLETHE OHIO STATE UNIVERSITY

PHYSICS DEPARTMENT ELECTRONICS LAB174 WEST 18TH AVE, COLUMBUS OH 43210

PARENT PAGEBY

DATE FILE

.PAGE

PROJECT

OPAD

OPAD

LVCMOS25 SLOW 12

OBUF

2EF=751

To

The output FIFO control

EREN

ERCLK

REN

RCLK

WENF5

F4

F3

F2

F1

F1

F2

F3

F4

F5

F5

F4

F3

F2

F1

EMPTYs

PAEs

Five input FIFO data

Output of the out_fifo, which are the data flow control information

The output FIFO status

72-bit data to the output FIFO

SLink status

The output FIFO control

S-link control

WCLK

P20 SLINK

From

SLINK

For lower S_link Design, bank2, 3, 4

1GUCMS CSC Electronics

DCCSTXDCC <--> SLINK data interface FPGATop Level for Slink_B

2C

Five input FIFO control OEN/REN

Fulls

Corresponding to SlinkAct2 and GigaAct2 in PCB schematics

2F1=753

4BLOCK3-22-2007_2:45

LOGICH

LOGICL

IGNSLINK[1:0]

FBOUT[71:0]

RATEMON[191:96]

SW[3:1]

CLKSLINK

OFBCTRL[5:0]

SLINKACTB

SL_LEDB

FPGARST

EXTROUTL

L1AMODE

CALIBMOD

CLKGIGA

FMMB[3:0]

J2

K5

GIGAOKB

FBDATA[35:0]

CLK2X

FBDATA35

FBDATA0

FBDATA1

FBDATA2

FBDATA3

FBDATA4

FBDATA5

FBDATA6

FBDATA7

FBDATA8

FBDATA9

FBDATA10

FBDATA11

FBDATA12

FBDATA13

FBDATA14

FBDATA15

FBDATA16

FBDATA17

FBDATA18

FBDATA19

FBDATA20

FBDATA21

FBDATA22

FBDATA23

FBDATA24

FBDATA25

FBDATA26

FBDATA27

FBDATA28

FBDATA29

FBDATA30

FBDATA31

FBDATA32

FBDATA33

FBDATA34

FBDATA[35:0]

F1

J3

AE7

N5

R8

P4

P5

T2

J5

K7

AF14

AG14

AG8

AH8

AB15

AC15

AD14

AE14

AF12

AF13

AG13

AH13

AF11

AG11

AJ10

AK10

AH10

AH11

AB14

AC14

AC13

AD13

AE11

AE12

AE9

AE10

AH9

AJ9

AF10

AG10

AC12

AD12

AC11

AD11

AF8

AF9

D3

D2

J7

C4

H5

E4

D1

H6 AJ8

AJ3

AC10

AB7

AG5

AC6

AC5

AB2

AC2

AF1

AE3

AA6

AF2

AA5

E3

E1

F2

J6

AA3

W7

W6

Y4

Y5

F4

AF3

AB5

AB3

AB4

AB6

AK8

AD10

AH5

AK3

AE8

F3

E2

K8

W8

AA4

AA1

W5

J4

K2

N7

L2

N8

K4

M1

K3

N2

R9

M2

L5

L4

N6

L1

P7

N3

P8

N1

M3

P1

M4

P9

P2

R7

P3

N4

R3

R6

R5

R2

J8

C1

C2

D5

V5

Y2

V8

AA2

T9

V3

Y1

V4

W1

U7

V6

U8

U2

T7

U5

T8

U4

V2

U9

W2

T4

U3

T3

T5

V1

T6

U1

R4

AB1

W3

W4

V7

G14

A13

A14

A12

A11

OFBD71

OFBD64

OFBD65

OFBD66

OFBD67

OFBD68

OFBD69

OFBD70

OFBD[71:64]

SBCTRL0SBCTRL1

SBCTRL[3:0]

SBCTRL3

SBCTRL2

OFBSTAT0

OFBSTAT[4:0]

OFBSTAT4

OFBSTAT3

OFBSTAT2

OFBSTAT1

IFBSTAT14

IFBSTAT[14:0]

IFBSTAT2

IFBSTAT1

IFBSTAT0

IFBSTAT3

IFBSTAT4

IFBSTAT5

IFBSTAT6

IFBSTAT7

IFBSTAT8

IFBSTAT9

IFBSTAT10

IFBSTAT11

IFBSTAT12

IFBSTAT13

SLINKBID[11:0]

SLINKBID[11:0]

SLINKBID0

SLINKBID1

SLINKBID2

SLINKBID3

SLINKBID4

SLINKBID5

SLINKBID6

SLINKBID7

SLINKBID8

SLINKBID9

SLINKBID10

SLINKBID11

FIFOUSE[9:5]

SBSTAT[5:0]

L1ACC

BC0

OFBCTRL4

OFBCTRL5

OFBCTRL[5:0]

OFBCTRL3

OFBCTRL2

OFBCTRL1

OFBCTRL0

CLKFIFO

SBCTRL[3:0]

IFBSTAT[14:0]

OFBSTAT[4:0]

CLKREF

SBSTAT1

SBSTAT5

SBSTAT[5:0]

SBSTAT4

SBSTAT3

SBSTAT2

SBSTAT0

IFBREN[5:1]

IFBOEN[5:1]

FBOUT24

FBOUT35FBOUT[71:0]

FBOUT34

FBOUT33

FBOUT32

FBOUT31

FBOUT30

FBOUT29

FBOUT28

FBOUT27

FBOUT26

FBOUT25

FBOUT0

FBOUT1

FBOUT2

FBOUT3

FBOUT4

FBOUT5

FBOUT6

FBOUT7

FBOUT8

FBOUT9

FBOUT10

FBOUT11

FBOUT12

FBOUT13

FBOUT14

FBOUT15

FBOUT16

FBOUT17

FBOUT18

FBOUT19

FBOUT20

FBOUT21

FBOUT22

FBOUT23OFBD[71:64]

FBOUT37

FBOUT36

FBOUT71FBOUT[71:0]

FBOUT70

FBOUT69

FBOUT68

FBOUT67

FBOUT66

FBOUT65

FBOUT64

FBOUT63

FBOUT62

FBOUT61

FBOUT60

FBOUT59

FBOUT58

FBOUT57

FBOUT56

FBOUT55

FBOUT54

FBOUT53

FBOUT52

FBOUT51

FBOUT50

FBOUT49

FBOUT48

FBOUT47

FBOUT46

FBOUT45

FBOUT44

FBOUT43

FBOUT42

FBOUT41

FBOUT40

FBOUT39

FBOUT38

IFBOEN1

IFBOEN5IFBOEN[5:1]

IFBOEN4

IFBOEN3

IFBOEN2

IFBREN1

IFBREN5IFBREN[5:1]

IFBREN4

IFBREN3

IFBREN2

TXPB

TXNB

RXPB

LRESET

CLKCMS

RXNB

BXCRST

BXCTERM

GIGAOKB

EVCRST

ORBITRST

L1AEMPTYB

STUCKDB

SLINKACTB

EXTROUTL

LOGICH

LOGICH

LOGICH

LOGICH

LOGICH

LOGICL

LOGICL

LOGICL

E7SL_LEDB

VSLCLK

LOGICL

LOGICL

LOGICH

LOGICH

LOGICH

LOGICL

BC0

CALIB

CLKCMS

ENFPGA

ENTTC

ENTTCC

ENTTCD

HARD_RESET

ORBITRST

SENSEOUT

TRESET

TRGSTART

TRGSTOP

TTCCMDSI

TTCCMD[5:0]

TTCDATASI

TTCREADY

TTC_SDAT

TTC

HARD_RSTPC

CEO

CLRC

CE

Q[7:0]

TC

CB8CE

BUF

OPAD

OPAD

OPADLVCMOS25 SLOW 12

OBUF

CCLR

D Q

FDC

INVC

CLR

D Q

FDC

OPAD

LVCMOS25 SLOW 12

OBUFINVOPAD

BUF

BUF

BUF

BUF

BUF

LVCMOS25

IBUFIPAD

IPAD

LVCMOS25

IBUF

LVCMOS25

IBUFLVCMOS25

IBUFLVCMOS25

IBUF

LVCMOS25

IBUFLVCMOS25

IBUF

IPAD

IPAD

IPAD

IPAD

IPAD

IPADLVCMOS25

IBUF

LVCMOS25 SLOW 12

OBUFOPAD

OPADLVCMOS25 SLOW 12

OBUF

LVCMOS25 SLOW 12

OBUF

LVCMOS25 SLOW 12

OBUFLVCMOS25 SLOW 12

OBUF

LVCMOS25

IBUF

IPAD

IPAD

INV

INV

LVCMOS25 SLOW 12

OBUF

LVCMOS25 SLOW 12

OBUFINV

4

3

2

1

4

3

2

1

DCBA

TITLETHE OHIO STATE UNIVERSITY

PHYSICS DEPARTMENT ELECTRONICS LAB174 WEST 18TH AVE, COLUMBUS OH 43210

PARENT PAGEBY

DATE FILE

.PAGE

PROJECT

QD

C

IFD

INV

IPAD

QD

C

IFD

OPAD

OPAD

BUF

LVCMOS25 SLOW 12

OBUF

OPAD

OPAD

IPAD

BUF

BUF

BUF

OR2

QD

C

IFD

C

D Q

R

FDR

C

D Q

R

FDR

AND2

LVCMOS25 SLOW 12

OBUF

NOR2

C

CE

CLR

D Q

FDCEQD

C

FD

OR2INV

QD

C

FD

AND2

CEOCE

TC

Q0

Q1

Q2

Q3

CCLR

CB4CE

BUF

Q D

C

FD

QD

C

FD

QD

C

FD

QD

C

FD

AND3B2

AND3

IPADLVCMOS25

IBUFLVCMOS25

IBUFIPAD

LL

UP D

OWN

AND2B1

LVCMOS25 SLOW 12

OBUF

OPAD

Switch_L1A

S-FIFO

TTC Command bus

1GUCMS CSC Electronics

DCCSTXDCC <--> SLINK data interface FPGATTCrx interface

Input FIFO and Output FIFO seperately

S-FIFO

P30

2D

IN-FIFO

IN-FIFO

FIFO_PRST

FIFO_PRST

FIFO_MRST

Reset FIFO's data (FIFO Partial Reset) just before TRGSTART for a clean start

HARD_RESET

TRGSTOP

H11

5BLOCK1-4-2007_11:57

CLKCMSTTCOK

TTCREADYDISTTCRDY

RTM5

RTM6

RTM7

RTM[7:0]

VMELPBK[9:0]

VMELPBK0

VMELPBK1

VMELPBK2

F14

F11

RTM7

RTM7

RTM6

CLKCMS

FIFOPRST

ENFPGA

LRESET TRGCNTRL3

PERIODRST

PRESET

CLKCMS

LOGICH PERIODRST

CLKCMSLOGICH

L1ACC

ENTTC

ENTTC

L1ACC_TTCVMELPBK0

CLKCMS

CLKCMS

TTCCMDS

LOGICL

LOGICL

TRGSTART

FIFOMRST

TTCCMD5

TTCCMD1

TTCCMD2

TTCCMD0

TTCCMD3

TTCCMD4

TTCCMD[5:0]

E10

BC0

SENSEOUT

HARD_RESET

ENTTC

ENTTCC

ENFPGA

ENTTCC

ENTTCD

TRESETTTCCMDS

TTC_SDAT

E13

B9

TRGCNTRL4

M6

AB27

A8

CLKCMS

CLKCMS

CLKCMS

E11

G11

E12

H12

TTCCMD[5:0]

TTCREADY

TRGSTART

ENTTCD

ORBITRST

SENSEOUT

TTCDATASC8

F8

E6

E9

F7

G8

E8

G10

M5

VMELPBK7

VMELPBK9

VMELPBK[9:0]

VMELPBK8

VMELPBK3

VMELPBK4

VMELPBK5

VMELPBK6

LOGICL

TTCDATAS

TTC_SDAT

EVCRST

BXCRST

L1ACC_TTC

L1ACC

AA27

CLKCMS

CLKCMS

CLKCMS

L1AEMPTYA

L1AEMPTYB

CLKCMS

LRESETLOGICH

CLKCMS

W24

W23

W26

TRGCNTRL2DCMRST40

CALIBMOD

CLKCMS

CLKCMS

RTM6

FIFOPRST

FIFOMRST

RTM5

RTM5

HARD_RSTPC

D0

D1O

S0

M2_1

D0

D1O

S0

M2_1

D0

D1O

S0

M2_1

LVCMOS25 SLOW 12

OBUF

LVCMOS25 SLOW 12

OBUF

LVCMOS25 SLOW 12

OBUF

LVCMOS25 SLOW 12

OBUF

OPAD

OPAD

OPAD

OPAD

BUF

BUF

BUF

BUF

BUF

BUF

BUF

INV

NOR5

LVCMOS25 SLOW

OBUFLVCMOS25 SLOW

OBUFLVCMOS25 SLOW

OBUFLVCMOS25 SLOW

OBUF

OPAD

OPAD

AND3B3

CCLR

D Q

FDC

OR4 INV

INV

INV

INV

INV

INV

INV

INV

INV

INV

INV

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

IPAD

OR2

OR2

AND5

OPAD

OPAD

LVCMOS25 SLOW

OBUF

LVCMOS25 SLOW

OBUF

LVCMOS25 SLOW

OBUF

LVCMOS25 SLOW

OBUF

LVCMOS25 SLOW

OBUF

LVCMOS25 SLOW

OBUF

LVCMOS25 SLOW

OBUF

LVCMOS25 SLOW

OBUF

LVCMOS25 SLOW

OBUFOPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

TCCLR

C

CE

Q[15:0]

CEO

CB16CE

LVCMOS25

IBUFLVCMOS25

IBUFLVCMOS25

IBUFLVCMOS25

IBUFLVCMOS25

IBUF

LVCMOS25

IBUFLVCMOS25

IBUFLVCMOS25

IBUFLVCMOS25

IBUFLVCMOS25

IBUF

LVCMOS25

IBUFLVCMOS25

IBUFLVCMOS25

IBUFLVCMOS25

IBUFLVCMOS25

IBUF

LVCMOS25

IBUF

LVCMOS25

IBUF

LVCMOS25

IBUF

LVCMOS25

IBUF

4

3

2

1

4

3

2

1

DCBA

TITLETHE OHIO STATE UNIVERSITY

PHYSICS DEPARTMENT ELECTRONICS LAB174 WEST 18TH AVE, COLUMBUS OH 43210

PARENT PAGEBY

DATE FILE

.PAGE

PROJECT

LVCMOS25

IBUF

OR5

CCLR

D Q

FDC

OR2

INV

OR5

OR5

AND2B1

AND2B1

AND2B1

AND2B1

AND2B1

AND2B1

AND2B1

AND2B1

OR4

AND2B1

AND2B1 OR4

AND2B1

CCLR

D Q

FDC

OR3B1

C1

D1

CLR

PREQD0

CE

C0

FDDRCPE

LVCMOS25 SLOW

OBUF

LVCMOS25 SLOW 12

OBUF

LVCMOS25 SLOW 12

OBUF

C1

D1

CLR

PREQD0

CE

C0

FDDRCPE

LVCMOS25 SLOW

OBUF

OPAD

OPAD

OPAD

OPAD

NOR5

OR2

AND2

OR2

OR2

AND2

OR2

OR2B1

BUF

BUF

BUF

AND4B3

AND2B1

AND5

AND5

INV

OR3B1

XOR2

D0

D1O

S0

M2_1

FMM2: Ready (+-)

FMM1: Busy (+-)

...

...

...

...

...

...

...

...

y7

ac28

ad28

ae26

ae2

ad29

af29

ag29

ae1

y8

FPGA1

FPGA1

Other

Other

FPGA1

FPGA2

FPGA3

FPGA4

FPGA5

FPGA5

FPGA4

FPGA3

FPGA2

FPGA1

FPGA1

FPGA2

FPGA3

FPGA4

FPGA5

FPGA5

FPGA4

FPGA3

FPGA2

FPGA2

FPGA3

FPGA4

FPGA5

FPGA5

FPGA4

FPGA3

FPGA2

FPGA1

1GUCMS CSC Electronics

DCCSTXDCC <--> SLINK data interface FPGA

Output of the out_fifo, which are the data flow control information

2E

Possible FMM Interface

one-shot for every SLINK active

INFIFO ~PAF

INFIFO ~HF

INFPGA_OFS

INFPGA_ERR

INFPGA Out_of_sync

INFPGA Error

pin6

pin7

...

G1, now used for L1A input

pin18

pin17

pin19

pin20: Ground

connector

pin4

pin2

pin1: optional power

pin3

pin5h29

j29

h27

h28

FMM3: Warn_overflow (+-)

FMM4: Out_of_sync (+-)

3-22-2007_2:26 BLOCK 6

FORCEFMM

FORFMM2

FORCEFMMFORFMM5

FORFMM5

FORFMM4

FORFMM1

FORFMM0FORFMM[15:0]

FORFMM2

FORFMM3

FORCEBUSY FMMBUSY

STATUS31

STATUS30

STATUS29

STATUS28

STATUS[31:0]

STATUS0

STATUS1

STATUS2

STATUS3

STATUS4

STATUS5

STATUS6

STATUS7

STATUS8

STATUS9

STATUS10

STATUS11

STATUS12

STATUS13

STATUS14

STATUS15

STATUS16

STATUS17

STATUS18

STATUS19

STATUS20

STATUS21

STATUS22

STATUS23

STATUS24

STATUS25

STATUS26

STATUS27

STATUS28

STATUS29

STATUS30

STATUS31

STATUS8

STATUS9

STATUS7

STATUS6

STATUS5

STATUS4

STATUS3

STATUS2

STATUS1

STATUS0

INFIFOPAF

OFBSTAT4

OFASTAT4

OFBIGNORE

OFAIGNORE

FIFOUSE[9:0]

FIFOUSE1

FIFOUSE2

FIFOUSE3

FIFOUSE4

FIFOUSE5

FIFOUSE6

FIFOUSE7

FIFOUSE8

FIFOUSE9

FIFOUSE0

OFASTAT3

H29

J29

H27

H28

6

6

LRESET

LRESET

FMMOSYN

INFPGADB

INFPGADA

LOGICH

FMMOSYN

FMMERR

FMMERR

FMMERR

FMMERR

INFIFOPAF

INFIFOHF

FMMWARN

SFIFOPAF

INFIFOFULL

SFIFOFULL

INFIFOFULL

FIFOUSE4

FIFOUSE3

FIFOUSE2

FIFOUSE1

FIFOUSE0

FIFOUSE5

FIFOUSE9FIFOUSE[9:0]

FIFOUSE8

FIFOUSE7

FIFOUSE6IFASTAT10

IFASTAT11

IFASTAT12

IFBSTAT11

IFBSTAT12

IFBSTAT13

FIFOUSE9

IFBSTAT14

BOARDID3

LOGICH

LOGICL

FMMDISCON

FMMREADY

FMMOSYN

INFIFOHF

FMMOSYN

FMMOSYN

CLK2X

LOGICL

CLK2X

SLOWCLK

SLINKACTLOGICH

SLINKACTA

LOGICL

LOGICH

SLINKACTB

G2

M24

G28

G30

G29

L23

G4

L24

G36

6

6

6

6

6

6

6

6

F30

J26

FMMWARN

FMMBUSY

FMMBUSY

FMMBUSY

AA8

AF27

AD3

AH27

AB25

AC4

AD26

Y24

AC26

AD4

AC3

AD25

Y23

AC25

AA7

AD2

AD30

AD1

AG30

AF30

OUTSYN5

BUSYF5

ERRORF3

ERRORF5

WARNF5

WARNF4

WARNF3

WARNF2

WARNF1

ERRORF4

ERRORF2

ERRORF1

BUSYF4

BUSYF3

BUSYF2

BUSYF1

OUTSYN4

OUTSYN3

OUTSYN2

OUTSYN1

STATUS22

STATUS21

STATUS20

STATUS19

STATUS18

STATUS17

STATUS16

STATUS15

STATUS14

STATUS13

STATUS12

STATUS11

STATUS10

READYF1

READYF2

READYF3

READYF4

DISCONF1

DISCONF2

DISCONF3

DISCONF4

DISCONF5

READYF5

STATUS10

STATUS11

STATUS12

STATUS13

STATUS14

STATUS15

STATUS16

STATUS17

STATUS18

STATUS19

LOGICH

LOGICL

CLKFIFO

LOGICL

CLKFIFO

LOGICL

LOGICH

DIAGCMD15

DIAGCMD10

DIAGCMD9

DIAGCMD8

DIAGCMD7

DIAGCMD6

DIAGCMD5

DIAGCMD4

DIAGCMD3

DIAGCMD2

DIAGCMD1

DIAGCMD[15:0]DIAGCMD0

DIAGCMD11

DIAGCMD12

DIAGCMD13

FIFOUSE8

FIFOUSE7

FIFOUSE6 FIFOUSE5

FIFOUSE4FIFOUSE3

FIFOUSE2

FIFOUSE1

FIFOUSE0

IFBSTAT10

IFASTAT14IFASTAT13

SFIFOPAF

FMMERR

LOGICH

INFPGADB

FMMWARN

K26

M23

6

6

6

6

OFBSTAT3

SFIFOFULL

OFAIGNORE

OFBIGNORE

INFPGADA

INFIFOPAF

STATUS27

STATUS26

STATUS25

STATUS24

STATUS23

LRESET

FORFMM4

C11

C10

G13

H13

FORFMM3

FORCEFMM

FORFMM0

FORCEFMM

FORFMM1

FORCEFMM

CCLR

D Q

FDC

Q

D

A0

A1

A2

A3

CLK

SRL16

QCE

D

A0

A1

A2

A3

CLK

@INIT="0000"

SRL16EINV

QCE

D

A0

A1

A2

A3

CLK

@INIT="0000"

SRL16EINV

INV

INV

AND2

C

D Q

FD_1

OR2B1

LVCMOS25 SLOW 12

OBUF

4

3

2

1

4

3

2

1

DCBA

TITLETHE OHIO STATE UNIVERSITY

PHYSICS DEPARTMENT ELECTRONICS LAB174 WEST 18TH AVE, COLUMBUS OH 43210

PARENT PAGEBY

DATE FILE

.PAGE

PROJECT

CEO

CLRC

CE

Q[7:0]

TC

CB8CE

CCLR

D Q

FDC

INV QDPRE

C

FDPINV

QPRE

D

CE

C

FDPEOPAD

LVCMOS25 SLOW 12

OBUF

INV

QD

C

FDC

CLR

D Q

FDC

QCE

D

A0

A1

A2

A3

CLK

SRL16E

QCE

D

A0

A1

A2

A3

CLK

SRL16E

QCE

D

A0

A1

A2

A3

CLK

SRL16E

QCE

D

A0

A1

A2

A3

CLK

SRL16E

QCE

D

A0

A1

A2

A3

CLK

SRL16E

QCE

D

A0

A1

A2

A3

CLK

SRL16E

QCE

D

A0

A1

A2

A3

CLK

SRL16E

QCE

D

A0

A1

A2

A3

CLK

SRL16E

QCE

D

A0

A1

A2

A3

CLK

SRL16EQCE

D

A0

A1

A2

A3

CLK

SRL16E

OPAD

QCE

D

A0

A1

A2

A3

CLK

@INIT="0000"

SRL16EQCE

D

A0

A1

A2

A3

CLK

@INIT="0000"

SRL16E

Q

D

A0

A1

A2

A3

CLK

SRL16

NAND2

Design consideration:

1GUCMS CSC Electronics

DCCSTX

CLKI2C is about 4MHz from DCM. The TTCrx I2C interface gets ~1MHz clock.When the DCM ok, shift in controller register of TTCrx. One bit per four clock cycles

Address: 0101010W Data: 00000011Address: 0101011W Data: 01111000

Data to be shifted to TTCrx:

I2C stop: Data change from Low to High when CLK highI2C start: Data change from High to Low when CLK high

DCC <--> SLINK data interface FPGAI2C TTCrx initialization on Hard reset

2F

LOCK2: LOCK signal from I2C clock generating DCM

LOGICH

LOGICH

NVSLCLK

LOGICL

LOGICH

NVSLCLK

7BLOCK1-9-2007_12:43

LOGICH

@INIT=FFFF

INIT=FFFF

F12

@INIT=0000

INIT=0000

@INIT=81E1

INIT=81E1

@INIT=E1E0

INIT=E1E0

@INIT=0001

INIT=0001

@INIT=FE18

INIT=FE18

@INIT=1E1E

INIT=1E1E

@INIT=1FE0

INIT=1FE0

@INIT=1FFF

INIT=1FFF

@INIT=FFFF

INIT=FFFF

@INIT=E07F

INIT=E07F

VSLCLK

INITI2C

INITI2C

CLKI2C

START

DCMRST40

CLKI2C

INTDLY

I2CDOUT

CLKI2C

START

C9

LOCK1

START

CLKI2C

LOGICH

CLKI2C

START

I2CCLKOUT

CLKI2C

LOGICH

LOGICH

LOGICH

LOGICH

LOGICH

LOGICH

LOGICH

LOGICH

START

CLKI2C

LOGICH

LOGICH

LOGICH

LOGICH

START

CLKI2C

LOGICH

LOGICH

LOGICH

LOGICH

START

CLKI2C

LOGICH

LOGICH

LOGICH

LOGICH

START

CLKI2C

LOGICH

LOGICH

LOGICH

LOGICH

START

CLKI2C

LOGICH

LOGICH

LOGICH

LOGICH

START

CLKI2C

LOGICH

LOGICH

LOGICH

LOGICH

START

CLKI2C

LOGICH

LOGICH

LOGICH

LOGICH

START

CLKI2C

I2CDOUT

CLKI2C

START

LOGICH

LOGICH

LOGICH

LOGICH

INTDLY

LOGICH

LOGICH

LOGICH

LOCK2

CLKI2C

INITI2CLOCK1

I2CTIME5

I2CTIME7

I2CTIME[7:0]

SLOWCLK

LOGICH

PRELOCKED

LOGICH

LOGICH

LOGICH

LOGICH

LOGICH

LOGICH

PRELOCKED

LOGICH

LOGICH

PRELOCKED

LOGICH

LOGICH

LOGICH

PRELOCKED

LOGICH

LOGICL

RSTFBUSYLOGICH

LOGICH

INIT=0000

@INIT=0000

LOGICH

RSTFBUSY

FORCEBUSY

HARD_RESET

HARD_RSTPC

LVCMOS25 SLOW 12

OBUF

LVCMOS25 SLOW 12

OBUF

LVCMOS25 SLOW 12

OBUF

LVCMOS25 SLOW 12

OBUFLVCMOS25 SLOW 12

OBUF

LVCMOS25 SLOW 12

OBUF

LVCMOS25 SLOW 12

OBUF

LVCMOS25 SLOW 12

OBUF

CEO

CLRC

CE

Q[7:0]

TC

CB8CE

AND2

AND2

AND2

AND2

AND2

AND2

AND2

QD

C

FD

QD

C

FD

QD

C

FD

Q

D

A0

A1

A2

A3

CLK

@INIT="0000"

SRL16

Q

D

A0

A1

A2

A3

CLK

@INIT="0000"

SRL16

Q

D

A0

A1

A2

A3

CLK

@INIT="0000"

SRL16

Q

D

A0

A1

A2

A3

CLK

@INIT="0000"

SRL16

Q

D

A0

A1

A2

A3

CLK

@INIT="0000"

SRL16

Q

D

A0

A1

A2

A3

CLK

@INIT="0000"

SRL16

Q

D

A0

A1

A2

A3

CLK

@INIT="0000"

SRL16

Q

D

A0

A1

A2

A3

CLK

@INIT="0000"

SRL16

Q

D

A0

A1

A2

A3

CLK

@INIT="0000"

SRL16Q

D

A0

A1

A2

A3

CLK

@INIT="0000"

SRL16Q

D

A0

A1

A2

A3

CLK

@INIT="0000"

SRL16Q

D

A0

A1

A2

A3

CLK

@INIT="0000"

SRL16Q

D

A0

A1

A2

A3

CLK

@INIT="0000"

SRL16Q

D

A0

A1

A2

A3

CLK

@INIT="0000"

SRL16Q

D

A0

A1

A2

A3

CLK

@INIT="0000"

SRL16Q

D

A0

A1

A2

A3

CLK

@INIT="0000"

SRL16Q

D

A0

A1

A2

A3

CLK

@INIT="0000"

SRL16

4

3

2

1

4

3

2

1

DCBA

TITLETHE OHIO STATE UNIVERSITY

PHYSICS DEPARTMENT ELECTRONICS LAB174 WEST 18TH AVE, COLUMBUS OH 43210

PARENT PAGEBY

DATE FILE

.PAGE

PROJECT

AND2

AND2

AND2

CCLR

D Q

FDC

OR2

AND3

AND3B1

AND2

QD

C

FD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

LVCMOS25 SLOW 12

OBUF

LVCMOS25 SLOW 12

OBUF

OR3B1AND4B2

1GUCMS CSC Electronics

DCCSTXDCC <--> SLINK data interface FPGA2G

L1A delay logic, to control the FIFO readout delay

INFPGA #1 sw5

INFPGA #1 sw4

INFPGA #5

INFPGA #4

INFPGA #3

INFPGA #2

INFPGA #2

INFPGA #3

INFPGA #4

INFPGA #5

DDUTIMOK

8-14-2006_11:16 BLOCK 8

DETRST

STATUS16

STATUS10

DDUSAVE

Y7

AE2

AE26

AD28

AC28

Y8

AE1

AG29

AF29

AD29

DDUOK[10:1]

DDUOK2

DDUOK1

DDUOK3

DDUOK4

DDUOK5

DDUOK6

DDUOK7

DDUOK8

DDUOK9

DDUOK10

DDUSAVE

DDUDETECT

FINISHDT

GLBRST

FPGARST

LOGICH

CLKCMS

L1ACC

LOGICH

LOGICH

LOGICH

LOGICH

CLKCMS

CLKCMS

LOGICH

LOGICH

LOGICH

LOGICH

LOGICH

LOGICH

LOGICH

LOGICH

CLKCMS

LOGICH

LOGICH

LOGICH

LOGICH

CLKCMS

LOGICH

LOGICH

LOGICH

LOGICH

CLKCMS

LOGICH

LOGICH

LOGICH

LOGICH

CLKCMS

LOGICH

LOGICH

LOGICH

LOGICH

CLKCMS

LOGICH

LOGICH

LOGICH

LOGICH

CLKCMS

LOGICH

LOGICH

LOGICH

LOGICH

CLKCMS

CLKCMS

CLKCMS

LOGICH

LOGICH

LOGICH

LOGICH

CLKCMS

LOGICH

LOGICH

LOGICH

LOGICH

CLKCMS

LOGICH

LOGICH

LOGICH

LOGICH

CLKCMS

LOGICH

LOGICH

LOGICH

LOGICH

CLKCMS

LOGICH

LOGICH

LOGICH

LOGICH

CLKCMS

LOGICH

LOGICH

LOGICH

LOGICH

LOGICH

LOGICH

LOGICH

LOGICH

CLKCMS

CLKCMS

LOGICH

LOGICH

LOGICH

LOGICH

L1ACCM

DL1ACC

L1ACCM

CLKCMS

CLKCMS

CLKCMS

SYSRSTFINISHDT

FINISHDT

DDUSAVE

DDUSAVE

DDUSAVE

DDUSAVE

DDUSAVE

DDUSAVE

DDUSAVE

DDUSAVE

DDUSAVE

DDUTIMOK

DDUTIMOK

DDUTIMOK

SW5

SW5

SW5

SW5

SW5

BXCTERM

BXCTERM

BXCTERM

BXCTERM

BXCTERM

STATUS11

STATUS13

STATUS14

STATUS15

STATUS17

STATUS18

STATUS19

STATUS12

DDUTIM5

DDUTIM[7:0]

DDUTIM3

DDUTIM4

DDUTIM2

DDUTIM6

DDUTIM7

BUF

EBUFE4

EBUFE4

EBUFE4

EBUFE4

EBUFE4

EBUFE4

EBUFE4

EBUFE4

AND4

OR3AND2

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

INV

INV

INV

4

3

2

1

4

3

2

1

DCBA

TITLETHE OHIO STATE UNIVERSITY

PHYSICS DEPARTMENT ELECTRONICS LAB174 WEST 18TH AVE, COLUMBUS OH 43210

PARENT PAGEBY

DATE FILE

.PAGE

PROJECT

INV

XOR6

XOR2

INV

NOR6

NOR5

INV

XOR2

AND5

AND2

CCLR

D Q

FDC

AND2

AND5B2

C

QD

CLR

FDC_1INV

NAND4

BUF

AND2B1 AND2B2

D0

D1

D2

D3

D4

D5

G

Q0

Q1

Q2

Q3

Q4

Q5

ILD6

D0

D1

D2

D3

D4

D5

G

Q0

Q1

Q2

Q3

Q4

Q5

ILD6

XOR2

XOR2

XOR2

XOR2

D0

D1

D2

D3

D4

D5

G

Q0

Q1

Q2

Q3

Q4

Q5

ILD6

D0

D1

D2

D3

D4

D5

G

Q0

Q1

Q2

Q3

Q4

Q5

ILD6

D0

D1

D2

D3

D4

D5

G

Q0

Q1

Q2

Q3

Q4

Q5

ILD6

CMS CSC Electronics

Invert Geographical Address

Board selection

Geographical Address Parity check

A24 Supervisory program/data access, or non-privileged program/data access

GU10

Address Decoder

Device Code 7

Device Code 6

Device Code 5

Device Code 4

Device Code 3

Device Code 2

Command code, specific to each device, code 9

Command code, specific to each device, code 8

Command code, specific to each device, code 7

Command code, specific to each device, code 6

Command code, specific to each device, code 5

Command code, specific to each device, code 4

Command code, specific to each device, code 3

Command code, specific to each device, code 2

Command code, specific to each device, code 1

Old Crate Check, all '0' for old crate

---< Check for 16bit data transfer mode

FAMS5 is Fake AMS5, just for this DAQMB prototype

DCCSTXDCC Slink FPGA 2B

Command code, specific to each device, code 0

Broadcast: 22 for DCCs, 28 for DDUs, 30 for both DDUs and DCCs

Device Code 1

DIAGOUT[15:0]

DIAGOUT0

DIAGOUT15

DIAGOUT14

DIAGOUT13

DIAGOUT12

DIAGOUT11

DIAGOUT10

DIAGOUT9

DIAGOUT8

DIAGOUT7

DIAGOUT6

DIAGOUT5

DIAGOUT4

DIAGOUT3

DIAGOUT2

DIAGOUT1

7-1-2005_8:06 VME 1

ADR12

ADR11

ADR10

ADR9

ADR8

ADR7

ADR6

ADR13

ADR14

ADR15

ADR16

ADR17

ADR18

ADR2

ADR3

ADR4

ADR5

ADR21

ADR22

ADR23

ADR20

ADR19

ADR[23:1]

AS

AS

ADRS22

ADRS20

ADRS19

ADRS23

CGA0

CGA1

CGA2

CGA3

CGA4

ADRS21

AM0

AM2

AM3

AM4

AM5

AM[5:0]

AM1

BOARD_SEL_NEW

SWB2B3

OLDCRATE

VALIDGA

OLDCRATE

VALIDGA

DS1

DS0

BOARDENB

VALIDAM

SYSOK

AMS1

LWORD

BOARDENB

VALIDAM

SW3B2SW2

ADRS20

VMEMON12

VMEMON[15:0]

VMEMON15

VMEMON14

VMEMON13

GOODAM

GOODAM

SYSOK

ASYNSTRB

MAXDELAY=1NS

MAXDELAY=1NS

MAXDELAY=1NS

FASTCLK

FASTCLK

BROADCAST

OLDCRATE

CGAP

VALIDGA

AMS5

AMS5

TOVMEWRITE

SYSFAIL

LED2

LED[2:0]

LED0

LED1

COMMAND[9:0]

COMMAND0

COMMAND1

COMMAND2

COMMAND3

COMMAND4

COMMAND5

COMMAND6

COMMAND7

COMMAND8

COMMAND9ADRS11

GA[5:0]

GA4

GA3

GA0

GA1

GA2

GA5

CGAP

AMS0

CGA2

CGA1

CGA0

CGA3

CGA4

CGA3

CGA0

CGA1

CGA2

CGA4

AMS1AMS3

AMS4AMS3

AMS4

AMS2

AMS1

AMS0

IACK

LWORD

ADRS3

ADRS2

ADRS10

ADRS9

ADRS8

ADRS6

ADRS5

ADRS4

ADRS7

ADRS23

ADRS20

ADRS21

ADRS19

4NSUSELOWSKEWLINES

STROBE

DS1

DS0

VALIDAM

ADRS2

ADRS3

ADRS4

ADRS5

ADRS6

ADRS7

ADRS8

ADRS9

ADRS10

ADRS11

ADRS12

ADRS17

ADRS14

ADRS15

ADRS16

ADRS18

ADRS19

ADRS12

ADRS13

ADRS21

ADRS22

ADRS23

SW3

SW3B2

SW3B2

SW3B2

AMS4

AMS3

AMS5

AMS0

AS

IACK

SYSFAIL

SW3

SW2

SWB2B3

SWB2B3

SWB2B3

AS

ADRS13

ADRS14

ADRS15

ADRS16

ADRS17

ADRS18

AS

AS

LED1ASYNSTRB

LED2

LED0

DIAGOUT0

DIAGOUT1

DIAGOUT2

DIAGOUT3

DIAGOUT4

DIAGOUT5

DIAGOUT6

DIAGOUT7

DIAGOUT8

DIAGOUT9

DIAGOUT10

DIAGOUT11

DIAGOUT12

DIAGOUT13

DIAGOUT14

DIAGOUT15

DIAGOUT[15:0]

AND4B3

AND4B1

AND4B2

4

3

2

1

4

3

2

1

DCBA

TITLETHE OHIO STATE UNIVERSITY

PHYSICS DEPARTMENT ELECTRONICS LAB174 WEST 18TH AVE, COLUMBUS OH 43210

PARENT PAGEBY

DATE FILE

.PAGE

PROJECT

OR4

AND4B4

AND4B3

AND4B3

AND4B2

AND4B3

AND4B2

AND4B3

01 ||

CMS CSC Electronics

GU10A

Device code:Device Selection

2B DCCSTXRead Command DecoderDCC Slink interface FPGA

00 || This FPGA itself, XC2VP20-FF896

0F || Emergency PROM Programming, Reserved for discrete logic

02 || This FPGA's PROMs, two XC18V04-VQ44 and/or one XCF32P03 || Input FPGA's PROM, XC18V02-VQ44

05 || First Slink JTAG interface06 || Second Slink JTAG interface07 || TTCrx I2C interface08 || Temp, voltage monitoring ADC

04 || Input FPGA, middle one of the five xc2vp2

3-15-2005_14:43 VME 2

DEVICE8DEVICE2

ADRS12

ADRS12

DEVICE6

ADRS16

ADRSHIGH

ADRS12

ADRS14

ADRS13DEVICE5

DEVICE0

ADRS14

ADRS13

ADRS12

ADRS14

ADRS12

ADRS13

ADRSHIGHADRS17

ADRS18

ADRSHIGH

ADRS14

ADRS13

ADRS12

ADRS14

ADRSHIGH

ADRSHIGH

ADRS14

ADRS13

ADRS12

ADRS13

ADRSHIGH

ADRSHIGH

DEVICE4

DEVICE3

DEVICE1

ADRS13

ADRS14

ADRS12

ADRSHIGH

ADRS15

ADRSHIGH

ADRS12

ADRS14

ADRS13DEVICE7

ADRS15

ADRS18

ADRS17ADRSHIGH8

ADRS16

ADRSHIGH8

ADRS13

ADRS14

TLVCMOS25 SLOW 12

OBUFT

LVCMOS25

IBUF

LVCMOS25

IBUF

TLVCMOS25 SLOW 12

OBUFT

LVCMOS25

IBUF

TLVCMOS25 SLOW 12

OBUFT

TLVCMOS25 SLOW 12

OBUFT

LVCMOS25

IBUF

LVCMOS25

IBUF

TLVCMOS25 SLOW 12

OBUFT

LVCMOS25

IBUF

TLVCMOS25 SLOW 12

OBUFT

TLVCMOS25 SLOW 12

OBUFT

LVCMOS25

IBUF

LVCMOS25

IBUF

TLVCMOS25 SLOW 12

OBUFT

LVCMOS25

IBUF

TLVCMOS25 SLOW 12

OBUFT

TLVCMOS25 SLOW 12

OBUFT

LVCMOS25

IBUF

LVCMOS25

IBUF

TLVCMOS25 SLOW 12

OBUFT

LVCMOS25

IBUF

TLVCMOS25 SLOW 12

OBUFT

TLVCMOS25 SLOW 12

OBUFT

LVCMOS25

IBUF

TLVCMOS25 SLOW 12

OBUFT

LVCMOS25

IBUF

LVCMOS25

IBUF

4

3

2

1

4

3

2

1

DCBA

TITLETHE OHIO STATE UNIVERSITY

PHYSICS DEPARTMENT ELECTRONICS LAB174 WEST 18TH AVE, COLUMBUS OH 43210

PARENT PAGEBY

DATE FILE

.PAGE

PROJECT

LVCMOS25

IBUF

TLVCMOS25 SLOW 12

OBUFTTLVCMOS25 SLOW 12

OBUFT

CMS CSC Electronics

GUWrite Command Decoder

10BDCCSTX2BDCC Slink FPGA

7-3-2003_9:25 VME 3

DATA15

DATA0

DATA1

DATA[15:0]

DATA2

DATA3

DATA6

DATA5

DATA4

DATA9

DATA8

DATA7

DATA12

DATA11

DATA10

DATA14

DATA13

INDATA[15:0]

INDATA14

INDATA12

INDATA11

INDATA9

INDATA8

INDATA6

INDATA5

INDATA0

INDATA1

INDATA2

INDATA3

INDATA4

INDATA7

INDATA10

INDATA13

INDATA15

OUTDATA13

OUTDATA10

OUTDATA7

OUTDATA4

OUTDATA3

OUTDATA2

OUTDATA1

OUTDATA[15:0]

OUTDATA0

OUTDATA5

OUTDATA6

OUTDATA8

OUTDATA9

OUTDATA11

OUTDATA12

OUTDATA14

OUTDATA15

DATA0

DATA1

DATA2

DATA3

DATA6

DATA5

DATA4

DATA9

DATA8

DATA7

DATA12

DATA11

DATA10

TOVME

DATA15

DATA14

DATA13

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

COMMAND[9:0]

DEVICE

FASTCLK

INDATA[15:0]OUTDATA[15:0]

RST

SLOWCLK

STROBE

TCK

TDI

TMS

DTACK

WRITE

RXFPGA

TDO

COMMAND[9:0]

DEVICE DVCENB

FASTCLK

INDATA[15:0]

OUTDATA[15:0]

RST

SLOWCLK

STROBE TCK

TDI

TMS

DTACK

WRITE

TXPROM

TDO

OPAD

OPAD

OPADIPAD

IPAD

OPAD

OPAD

LVCMOS25

IBUF

LVCMOS25

IBUF

LVCMOS25 SLOW 12

OBUFLVCMOS25 SLOW 12

OBUFLVCMOS25 SLOW 12

OBUF

LVCMOS25 SLOW 12

OBUF

LVCMOS25 SLOW 12

OBUF

E

OBUFE

E

OBUFE

E

OBUFE

4

3

2

1

4

3

2

1

DCBA

TITLETHE OHIO STATE UNIVERSITY

PHYSICS DEPARTMENT ELECTRONICS LAB174 WEST 18TH AVE, COLUMBUS OH 43210

PARENT PAGEBY

DATE FILE

.PAGE

PROJECT

LVCMOS25

IBUF

LVCMOS25 SLOW 12

OBUF

OPAD

IPAD

OPAD

OPAD

OPAD

TTCI2C

COMMAND[9:0]

DEVICE

FASTCLK

INDATA[15:0]OUTDATA[15:0]

RST

SLOWCLK

STROBE

DTACK

WRITE

SDAT

SCLK

BUF

BUF

BOARDID[3:0]

COMMAND[9:0]

DETRSTDEVICE

FASTCLK

INDATA[15:0]OUTDATA[15:0]

RST

SLOWCLK

STROBE

TCK

TDITDO

TMS

DTACK

WRITE

RXPROM

MONITOR[7:0]

BUF

P15

CMS CSC Electronics

GU DCCSTX2BDCC Slink FPGAUpper level for each JTAG path

10C

P17

P16

P14

Similarly for SLINK's JTAG interface

JTAG4: TDIJTAG3: TRST*JTAG2: TMSJTAG1: TDOJTAG0: TCK

MONITOR7MONITOR[7:0]

MONITOR6

MONITOR5

MONITOR3

MONITOR4

BOARDID0BOARDID[3:0]

BOARDID2

BOARDID1

BOARDID3

MONITOR[7:0]

BOARDID[3:0]

7-1-2005_8:54 VME 4

TCKMON

DIAGOUT0

DIAGOUT1

DIAGOUT2

DIAGOUT3

DIAGOUT4

DIAGOUT5

DIAGOUT6

DIAGOUT7

DIAGOUT8

DIAGOUT9

DIAGOUT10

DIAGOUT11

DIAGOUT12

DIAGOUT13

DIAGOUT14

DIAGOUT15

DIAGOUT[15:0]

TCKMON

TMSMON

TDIMON

OUTDATA[15:0]

STROBE

DTACK

TDOMON

DEVICE7

DTACK

OUTDATA[15:0]

RESET

SLOWCLK

FASTCLK

WRITE

STROBE

INDATA[15:0]

COMMAND[9:0]

AC29

AA25

AC27

E14

D14

SLOWCLK

FASTCLK

WRITE

STROBE

DEVICE2

DTACK

INDATA[15:0]

COMMAND[9:0]

OUTDATA[15:0]

RESET

COMMAND[9:0]

INDATA[15:0]

DEVICE3

RESET

WRITE

FASTCLK

SLOWCLK

DTACK

DEVICE4

INDATA[15:0]

COMMAND[9:0]

SLOWCLK

FASTCLK

WRITE

STROBE

RESET

OUTDATA[15:0]

H14

J14

AB29

AD16 AE15

AD15

AE16

I2CCLK

I2CDAT

DETRST

TDIMON

TMSMON

DETRST

TDOMON

COMMAND[9:0]

DDUOK[10:1]

DEVICE

FASTCLK

FIFOUSE[9:0]

INDATA[15:0]

L1AMODE

MONITOR[15:0]

OUTDATA[15:0]

RATEMON[191:0]

RST

SLOWCLK

STATUS[31:0]

STROBE

SW[3:1]

VMELPBK[9:0]

DTACK

WRITE

VMEREG

SOFTSWSET[15:0]

FORFMM[15:0]

BUF

BUF

GN

D

OPAD

OPAD

ADCCLK

ADCDATA

COMMAND[9:0]

DEVICE

INDATA[15:0]

OUTDATA[15:0]

SLOWCLK

STROBE DTACK

SERADC

ADCIN

DIAGADC[15:0]RST

OPAD

OPAD

OPADIPAD

OPAD

OPAD

LVCMOS25 SLOW 12

OBUFLVCMOS25 SLOW 12

OBUFLVCMOS25 SLOW 12

OBUF

LVCMOS25

IBUF

LVCMOS25

IBUF

LVCMOS25 SLOW 12

OBUF

LVCMOS25 SLOW 12

OBUF

4

3

2

1

4

3

2

1

DCBA

TITLETHE OHIO STATE UNIVERSITY

PHYSICS DEPARTMENT ELECTRONICS LAB174 WEST 18TH AVE, COLUMBUS OH 43210

PARENT PAGEBY

DATE FILE

.PAGE

PROJECT

LVCMOS25 SLOW 12

OBUF

SLINKJTAG

COMMAND[9:0]

DEVICE

FASTCLK

INDATA[15:0]OUTDATA[15:0]

RST

SLOWCLK

STROBE

TCK

TDI

TMS

DTACK

WRITE

TDO

SLINKJTAG

COMMAND[9:0]

DEVICE

FASTCLK

INDATA[15:0]OUTDATA[15:0]

RST

SLOWCLK

STROBE

TCK

TDI

TMS

DTACK

WRITE

TDO

LVCMOS25

IBUF

LVCMOS25 SLOW 12

OBUF

IPAD OPAD

IPADLVCMOS25 SLOW 12

OBUF

LVCMOS25 SLOW 12

OBUFOPAD

BUF

The ADC1270/1271 can work at a frequency from 0.1MHz to 2.0MHzSerial ADC (MAX1270/1271) Interface clock: 1.25MHz, Divided SLOWCLOCK is used

P18

CMS CSC Electronics

GU DCCSTX2BDCC Slink FPGA

P18

P19

10D

Upper level for each JTAG path

P13

ADC Chip Select

1-26-2007_16:23 VME 5

SWSET[15:0]

DDUOK[10:1]

RATEMON[191:0]

L1AMODE

DTACK

LED[2:0]

LED1

LED2

LED0DEVICE0

COMMAND1

COMMAND[9:0]COMMAND0

COMMAND[9:0]

DEVICE0

AG28LOGICL

AH30

C5B3

VMEMON[15:0]

VMELPBK[9:0]

SW[3:1]

STATUS[31:0]

DEVICE5

FIFOUSE[9:0]

OUTDATA[15:0]

RESET

SLOWCLK

INDATA[15:0]

COMMAND[9:0]

INDATA[15:0]

STROBE

WRITE

FASTCLK

OUTDATA[15:0]

DTACK

DTACK

OUTDATA[15:0]

SLOWCLK

FASTCLK

WRITE

STROBE

RESET

DEVICE6

INDATA[15:0]

COMMAND[9:0]

SLOWCLK

FASTCLK

WRITE

STROBE

RESET

A3

G6

A28 D26

G26

B28

OUTDATA[15:0]

DTACK

COMMAND[9:0]

DEVICE8

ADCCLK

ADCDATA

ADCIN

SLOWCLK

STROBE

INDATA[15:0]

RESET

AH29

AD23

FORMEM[15:0]

AND2B1

C

CE

CLR

D Q

FDCE

AND3B2

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUFQD

C

FD

CCLR

D Q

FDC

AND3

EBUFE16

E

BUFE

4

3

2

1

4

3

2

1

DCBA

TITLETHE OHIO STATE UNIVERSITY

PHYSICS DEPARTMENT ELECTRONICS LAB174 WEST 18TH AVE, COLUMBUS OH 43210

PARENT PAGEBY

DATE FILE

.PAGE

PROJECT

OR2

CCLR

D Q

FDC

INV

AND3B1

Q[15:0]

SLI

CLRC

CE

SR16CE

BUF

BUF

BUF

BUF

BUF

BUF

C

D Q

R

FDR

OR2

AND3B1

AND2B1

Q[7:0]

CLRC

CE

L

SLI

D[7:0]

SR8CLE

BUF

AND2B1

AND2B1

AND2B1

CEO

CLRC

CE

Q[7:0]

TC

CB8CE

C

CE

CLR

D Q

FDCE

AND2

OR2

C

CE

CLR

D Q

FDCE

OR2B1

OR2 CCLR

D Q

FDC

GN

D

E

BUFE

OR2B1

VC

C

CMS CSC Electronics

GUSerial ADC Interface MAX1271

DTACK for Load Instruction/Data Register command

DCCSTX13

DCC Slink FPGA 10D

LOGICL

DTACK

RST

LOGICL

LOGICH

LOGICL

LOGICH

3-15-2005_16:05 SERADC 1

ADCIN

BUSYBUSY

SLOWCLK

ADCCLK2NS

CLKMAX

SLOWCLKSLOWCLK

CLKMAX

BUSY

SLOWCLK

SLOWCLKCLKMAX

BUSY

RST

SLOWCLK

CLKMAX

LOAD

SLOWCLK

RSTBUSY

RSTBUSY

BUSY

DIAGADC15

DIAGADC14

DIAGADC13

DIAGADC12

DIAGADC11

DIAGADC10

DIAGADC9

DIAGADC8

DIAGADC7

DIAGADC6

DIAGADC5

DIAGADC4

DIAGADC3

DIAGADC2

DIAGADC1

DIAGADC[15:0]DIAGADC0

DTACK

ADCDATA

QMAX6

QMAX[15:0]

QMAX7

QMAX8

QMAX9

OUTDATA[15:0]

OUTDATA6

OUTDATA7

OUTDATA8

OUTDATA9

RST

ADCIN

USELOWSKEWLINESCLKMAX

OUTDATA[15:0]QMAX[15:0]

BUSY

STROBE

RDMAXDK

RDMAXDK

SLOWCLK

WRITEMAX

RST

RST

RST

INDATA[15:8]

INDATA[7:0]

INDATA[15:0]

BUSYLOAD

SLOWCLK

LOAD

WRITEMAX

DONEMAX

QTIME4

QTIME1

QTIME3

QTIME[7:0]

ADCDATA

Q[7:0]

Q7

ASYNLOAD

DTACKRST

RST

READMAX

RDMAXDKSTROBE

BUSY

ADCCLK

RSTBUSY

CLKMAX BUSY

CLKMAX

BUSY

CLKMAX

RST

BUSY

AND5B4

AND5B3

AND4B4

AND4B2

4

3

2

1

4

3

2

1

DCBA

TITLETHE OHIO STATE UNIVERSITY

PHYSICS DEPARTMENT ELECTRONICS LAB174 WEST 18TH AVE, COLUMBUS OH 43210

PARENT PAGEBY

DATE FILE

.PAGE

PROJECT

Serial ADC Command Decoder:00 || Write Control Byte to MAX1271's01 || Read Data Back from 1271 Register02 ||

04 ||05 ||06 ||

CFEB JTAG command decode

CMS CSC Electronics

GUDAQMB VME InterfaceBurr-Brown ADC Readout

03 ||

08 ||09 ||

13ADCCSTX10D

2SERADC3-10-2005_14:48

CMDHIGHCOMMAND9

COMMAND8

COMMAND7

COMMAND6

COMMAND5

COMMAND4

READMAX

COMMAND3

COMMAND2

COMMAND1

COMMAND0

CMDHIGH

CMDHIGH

COMMAND0

COMMAND1

COMMAND2

COMMAND3

WRITEMAX

DEVICE

COMMAND9

COMMAND8

COMMAND7

COMMAND6

COMMAND5

COMMAND2

COMMAND1

COMMAND[9:0]

COMMAND0

COMMAND3

COMMAND4

BUF

OR2

CCLR

D Q

FDC

CCLR

D Q

FDC

OR2

AND2B1

INV

AND2B1

OR3

CCLR

D Q

FDC

BUF

NOR4

4

3

2

1

4

3

2

1

DCBA

TITLETHE OHIO STATE UNIVERSITY

PHYSICS DEPARTMENT ELECTRONICS LAB174 WEST 18TH AVE, COLUMBUS OH 43210

PARENT PAGEBY

DATE FILE

.PAGE

PROJECT

EBUFE16

TC

UP

CE

D0

D1

D2

CCLR

D3

Q0

Q1

Q2

Q3

CEO

L

CB4CLED

E

BUFE

AND2

C

CE

CLR

D Q

FDCE

AND2

SLI

Q[15:0]

L

D[15:0]

CLR

CE

C

SR16CLRE

AND2B1 C

CE

CLR

Q[15:0]

SLI

SR16LCE

INV

C

CE

CLR

D Q

FDCE

CCLR

D Q

FDC

AND4

E

BUFE

CCLR

D Q

FDC

AND2B1

QD

C

FD

C

CE

CLR

D Q

FDCEQD

C

FDQD

C

FD

QPRE

D

CE

C

FDPE

INV

OR2

OR2

OR2

AND4B2

GN

D

CMS CSC Electronics

GU

DTACK for Load Instruction/Data Register command

10C DCCSTXDCC Slink Interface FPGA14

VME-->I2C for TTCrx

I2CREAD just need supply enough clock

I2CWRITE sipplies both clock and data

VMEREAD just readout the register data, no shifting

1TTCI2C9-17-2004_7:34

LOGICL

LOGICL

LOGICL

BUSY

STROBE

LOGICL

I2CWRITE

I2CDEN

FASTCLK

SDATIN

SDATOUT

SDATOUT

STROBE

SLOWCLK

BUSY

Q0

Q[15:0]

LOAD

SHDATA

DONEDATA_1

DONEDATA+1

SHDATA

SDATIN

QC[15:0]

RDI2CBKINDATA0

INDATA[15:0]

LOADCE

LOAD

ENABLE SCLK

LOAD

DONEDATA+1

RST

RST

RST

SLOWCLK

RST

DONEDATA

SLOWCLK

RST

SLOWCLK

SLOWCLK

SHDATALOAD

SLOWCLK

DTACK

RDI2CBK

SLOWCLKENABLE

OUTDATA[15:0]

RST

COMMAND[9:0]

COMMAND9

COMMAND6

COMMAND7

COMMAND8

LOAD

SLOWCLK

ENABLE

ENABLE

SHDATA

SLOWCLK

SLOWCLK

LOAD

DTACK

STROBERDI2CBK

VMEREAD

SHDATA

BUSY

DONEDATA

LOAD

Q0

BUSY

SLOWCLK

SDAT

I2CDEN

I2CREAD

I2CWRITE

I2CREAD

RST

SLOWCLK

LOAD

RST

SLOWCLK

BUSY

DONEDATA+1

BUSYSHDATA

DONEDATA+1

I2CREAD

I2CWRITE

AND4B3

AND4B2

4

3

2

1

4

3

2

1

DCBA

TITLETHE OHIO STATE UNIVERSITY

PHYSICS DEPARTMENT ELECTRONICS LAB174 WEST 18TH AVE, COLUMBUS OH 43210

PARENT PAGEBY

DATE FILE

.PAGE

PROJECT

AND4B2

AND4B3

CMS CSC ElectronicsDCC Slink Interface FPGA

CFEB JTAG command decode

GU

CFEB JTAG commands:

DCCSTX10C

04 ||03 ||

14A

VME-->I2C for TTCrx

02 || VME Read: No I2C activity, put data on VME backplane

00 || Write to I2C: Shift data and supply clock, it is a VME WRITE01 || Read from I2C: Receive data and supply clock, but it is a VME WRITE

2TTCI2C1-22-2004_15:04

I2CWRITE

CMDHIGH

CMDHIGH

COMMAND4

COMMAND5

DEVICE

COMMAND9

COMMAND8

COMMAND7

COMMAND6

COMMAND5

COMMAND2

COMMAND1

COMMAND[9:0]

COMMAND0

COMMAND3

COMMAND4

COMMAND1

COMMAND0

COMMAND2

COMMAND2

COMMAND0

COMMAND1

CMDHIGH

I2CREAD

VMEREAD

CMDHIGH

COMMAND0

COMMAND1

COMMAND2

COMMAND3

OR2

INV

INV

AND2B1

CEO

CLRC

CE

Q[7:0]

TC

CB8CE

CCLR

D Q

FDC

OR3

CCLR

D Q

FDC

C

CE

CLR

D Q

FDCE

BUF

NOR4

4

3

2

1

4

3

2

1

DCBA

TITLETHE OHIO STATE UNIVERSITY

PHYSICS DEPARTMENT ELECTRONICS LAB174 WEST 18TH AVE, COLUMBUS OH 43210

PARENT PAGEBY

DATE FILE

.PAGE

PROJECT

EBUFE16

TC

UP

CE

D0

D1

D2

CCLR

D3

Q0

Q1

Q2

Q3

CEO

L

CB4CLED

E

BUFE

GN

D

AND2

C

CE

CLR

D Q

FDCE

OR2 C

CE

CLR

D Q

FDCE

AND2

SLI

Q[15:0]

L

D[15:0]

CLR

CE

C

SR16CLRE

GN

D

AND2B1 C

CE

CLR

Q[15:0]

SLI

SR16LCE

BUF

INV

AND4B2

C

CE

CLR

D Q

FDCE

CCLR

D Q

FDC

AND2B1

OR2

AND2B1

OR2

OR2

CCLR

D Q

FDC

VC

C

Q D

C

FD

AND2B1OR2

OR2

AND4

E

BUFE

GN

D

OR2

CCLR

D Q

FDC

OR2

AND2B1

QD

C

FD

C

CE

CLR

D Q

FDCE

C

CE

CLR

D Q

FDCE

OR2

QD

C

FDQD

C

FD

CMS CSC Electronics

GU

DTACK for Load Instruction/Data Register command

10C15

DCCSTXDCC Slink Interface FPGAVME-->JTAG for SLINk interface PROM

7-14-2003_12:22 TXPROM 1

STROBE

SLOWCLK

DATASHFT

INSTSHFTBUSY

LOAD

TIMER[7:0]

TIMER6

DEVICE

SLOWCLK

RST

Q0

Q[15:0]

DVCENB

LOAD

SLOWCLK

SHDATA

DONEDATA_1

DONEDATA+1

SHDATAX

TDO

COMMAND0

QC[15:0]

RDTDOBKINDATA0

INDATA[15:0]

LOADCE

LOAD

INSTSHFT

DATASHFT

ENABLE TCK

DONEDATA+2

LOAD

DONEDATA+1

RST

RST

RST

RST

SLOWCLK

RST

BUSY

DONEDATA

SLOWCLK

RST

SLOWCLK

SLOWCLK

SHDATALOAD

SLOWCLK

DTACK

RDTDOBK

SLOWCLKENABLE

TDI

BUSY

STROBE

OUTDATA[15:0]

RST

COMMAND[9:0]

COMMAND9

COMMAND6

COMMAND7

COMMAND8

LOAD

SLOWCLK

DHEADEN

TAILENCOMMAND1

ENABLE

ENABLE

SHDATA

DATASHFT

INSTSHFT

IHEADENCOMMAND0

STROBE

BUSY

SLOWCLK

SLOWCLK

RESETJTAG

LOAD

DONEIHEAD

RST

DONETAIL

RST

DONEDHEAD LOAD

DTACK

STROBERDTDOBK

READTDO

SHDATAX

BUSY

DONEDATA

LOAD

Q0

SLOWCLK

BUSY

INSTSHFT

DATASHFT

SLOWCLK

STROBE

AND2

CCLR

D Q

FDC

CCLR

D Q

FDC

AND2

VC

C

CCLR

D Q

FDC

OR2

CCLR

D Q

FDC

AND2

E

BUFE

E

BUFE

C

CE

CLR

D Q

FDCEQ

PRED

CE

C

FDPE

C

CE

CLR

D Q

FDCE

C

CE

CLR

D Q

FDCE

4

3

2

1

4

3

2

1

DCBA

TITLETHE OHIO STATE UNIVERSITY

PHYSICS DEPARTMENT ELECTRONICS LAB174 WEST 18TH AVE, COLUMBUS OH 43210

PARENT PAGEBY

DATE FILE

.PAGE

PROJECT

C

CE

CLR

D Q

FDCEQ

PRED

CE

C

FDPE

QPRE

D

CE

C

FDPE

C

CE

CLR

D Q

FDCE

C

CE

CLR

D Q

FDCE

C

CE

CLR

D Q

FDCE

AND3

AND2

E

BUFE

AND2

AND4B3

AND4B3

OR3

CE

TC

Q0

Q1

Q2

Q3

CR

CEO

CB4RE

AND2

QD

C

FD

QD

C

FD

AND2

CE

TC

Q0

Q1

Q2

Q3

CR

CEO

CB4RE

OR3

AND2

OR3

OR2AND2

AND2B1

CCLR

D Q

FDC

CCLR

D Q

FDC

CMS CSC ElectronicsDCC Slink Interface FPGAVME-->JTAG for SLINk interface PROM GU 10C

15ADCCSTX

7-14-2003_12:22 TXPROM 2

RST

SLOWCLK

LOAD

RST

SLOWCLK

DONEDATA+1

SLOWCLK

BUSY

DONEDATA+1

DONETAIL

DONEDATA+1

BUSY

BUSY

SHDATADHEADEN

SHDHEADDHEADEN

RST

DONEDATA_1

SHDHEAD

ENABLE

SHIHEAD

DONEDHEAD

SHDHEAD

SHDHEAD

SHIHEAD

TMS

TMS

SHDATA

TMS

SLOWCLK

ENABLE

TAILEN

SHIHEADBUSY

IHEADEN

IHEADEN

DONEDATA+1

SHTAIL

TAILEN

SLOWCLK

SHIHEAD

DONEIHEAD

IHEADEN

DHEADENSHDATAX

BUSY

LOAD

RST

RST

LOAD

SLOWCLK

TAILEN

SLOWCLK

OKRST

RST

FASTCLK

RST

RESETDONE

RESETJTAG

SLOWCLKSTROBE

RSTJTAG

FASTCLK

RST

AND2

OR2

QPRE

D

CE

C

FDPE

E

BUFEQ

PRED

CE

C

FDPE

AND2

AND2

E

BUFE

C

CE

CLR

D Q

FDCE

4

3

2

1

4

3

2

1

DCBA

TITLETHE OHIO STATE UNIVERSITY

PHYSICS DEPARTMENT ELECTRONICS LAB174 WEST 18TH AVE, COLUMBUS OH 43210

PARENT PAGEBY

DATE FILE

.PAGE

PROJECT

QPRE

D

CE

C

FDPE

INV

E

BUFE

GN

D

CEOCE

TC

Q0

Q1

Q2

Q3

CCLR

CB4CE

QPRE

D

CE

C

FDPE

QPRE

D

CE

C

FDPE

QPRE

D

CE

C

FDPE

C

CE

CLR

D Q

FDCE

AND2

CEOCE

TC

Q0

Q1

Q2

Q3

CCLR

CB4CE

C

D Q

FD_1

CMS CSC ElectronicsDCC Slink Interface FPGAVME-->JTAG for SLINk interface PROM GU 10C DCCSTX

15B7-14-2003_12:22 TXPROM 3

DONETAIL

ENABLE

RESETJTAG

SLOWCLK

RST

RESETJTAG

DTACK

SHTAIL

SHTAIL

TMS

ENABLE

RESETJTAG

SLOWCLK

OKRST

RESETDONE

TMS

RST

SLOWCLK

ENABLE

SHTAIL

SLOWCLK

AND4B1

4

3

2

1

4

3

2

1

DCBA

TITLETHE OHIO STATE UNIVERSITY

PHYSICS DEPARTMENT ELECTRONICS LAB174 WEST 18TH AVE, COLUMBUS OH 43210

PARENT PAGEBY

DATE FILE

.PAGE

PROJECT

AND2B1

AND4

AND4B1

AND4B3

CMS CSC ElectronicsDCC Slink Interface FPGA

06 || Reset JTAG State machine05 || Read TDO register

01 || Shift data with header only

GU

CFEB JTAG commands:00 || Shift data, no header, no tailer

02 || Shift data with tailer only03 || Shift data with header and tailer

07 || Shift Instruction register

04 ||

VME-->JTAG for SLINk interface PROM DCCSTX15C

10C

CFEB JTAG command decode

4TXPROM1-22-2004_15:08

COMMAND4

INSTSHFTCMDHIGH

COMMAND0

COMMAND1

COMMAND2

DATASHFTCOMMAND2

CMDHIGH

CMDHIGHCOMMAND5

COMMAND0

COMMAND2

COMMAND1

CMDHIGHREADTDO

COMMAND1

COMMAND2

COMMAND0

CMDHIGHRSTJTAG

DEVICE

COMMAND9

COMMAND8

COMMAND7

COMMAND6

COMMAND5

COMMAND2

COMMAND1

COMMAND[9:0]

COMMAND0

COMMAND3

COMMAND4

COMMAND3

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

OR2

INV

INV

AND2B1

OR3

CCLR

D Q

FDC

C

CE

CLR

D Q

FDCE

NOR4

4

3

2

1

4

3

2

1

DCBA

TITLETHE OHIO STATE UNIVERSITY

PHYSICS DEPARTMENT ELECTRONICS LAB174 WEST 18TH AVE, COLUMBUS OH 43210

PARENT PAGEBY

DATE FILE

.PAGE

PROJECT

EBUFE16

TC

UP

CE

D0

D1

D2

CCLR

D3

Q0

Q1

Q2

Q3

CEO

L

CB4CLED

E

BUFE

GN

D

AND2

C

CE

CLR

D Q

FDCE

OR2 C

CE

CLR

D Q

FDCE

AND2

GN

D

AND2B1

INV

AND4B2

C

CE

CLR

D Q

FDCE

CCLR

D Q

FDC

AND2B1

OR2

AND2B1

OR2

OR2

CCLR

D Q

FDC

AND4

E

BUFE

GN

D

OR2

CCLR

D Q

FDC

OR2

AND2B1

QD

C

FD

C

CE

CLR

D Q

FDCE

C

CE

CLR

D Q

FDCE

OR2

QD

C

FDQD

C

FD

SLI

Q[15:0]

L

D[15:0]

CLR

CE

C

SR16CLRE

C

CE

CLR

Q[15:0]

SLI

SR16LCE

T

BUFT

T

BUFT

CMS CSC ElectronicsDCC Slink Interface FPGA GU

DTACK for Load Instruction/Data Register command

DCCSTXVME-->JTAG for data input FPGA's PROM 10C16

COMMAND1

TCK

TCK

IDDETECT

Q0

Q[15:0]

1RXPROM6-29-2005_17:07

DATASHFT

TDI

TDO

STROBE

SLOWCLK

DATASHFT

INSTSHFTBUSY

LOAD

LOAD

SLOWCLK

SHDATA

DONEDATA_1

DONEDATA+1

SHDATAX

COMMAND0

QC[15:0]

RDTDOBKINDATA0

INDATA[15:0]

LOADCE

LOAD

INSTSHFT

DATASHFT

ENABLE

DONEDATA+2

LOAD

DONEDATA+1

RST

RST

RST

RST

SLOWCLK

RST

BUSY

DONEDATA

SLOWCLK

RST

SLOWCLK

SLOWCLK

SHDATALOAD

SLOWCLK

DTACK

RDTDOBK

SLOWCLKENABLE

TDI

BUSY

STROBE

OUTDATA[15:0]

RST

COMMAND[9:0]

COMMAND9

COMMAND6

COMMAND7

COMMAND8

LOAD

SLOWCLK

DHEADEN

TAILENCOMMAND1

ENABLE

ENABLE

SHDATA

DATASHFT

INSTSHFT

IHEADENCOMMAND0

STROBE

BUSY

SLOWCLK

SLOWCLK

RESETJTAG

LOAD

DONEIHEAD

RST

DONETAIL

RST

DONEDHEAD LOAD

DTACK

STROBERDTDOBK

READTDO

SHDATAX

BUSY

DONEDATA

LOAD

Q0

BUSY

INSTSHFT

DATASHFT

SLOWCLK

STROBE

TAILEN

DIAGOUT[15:0]DIAGOUT0

DIAGOUT1

DIAGOUT2

DIAGOUT3

DIAGOUT4

DIAGOUT5

DIAGOUT6

DIAGOUT7

DIAGOUT8

DIAGOUT9

DIAGOUT10

DIAGOUT11

DIAGOUT12

DIAGOUT13

DIAGOUT14

DIAGOUT15

BUSY

TDO

DONEDATA+1

INSTSHFT

RST

DONETAIL

STROBE

DTACK

LOAD

TMS

DEVICE

IDDETECT

AND2

CCLR

D Q

FDC

CCLR

D Q

FDC

AND2

CCLR

D Q

FDC

OR2

CCLR

D Q

FDC

AND2 C

CE

CLR

D Q

FDCEQ

PRED

CE

C

FDPE

C

CE

CLR

D Q

FDCE

C

CE

CLR

D Q

FDCE

4

3

2

1

4

3

2

1

DCBA

TITLETHE OHIO STATE UNIVERSITY

PHYSICS DEPARTMENT ELECTRONICS LAB174 WEST 18TH AVE, COLUMBUS OH 43210

PARENT PAGEBY

DATE FILE

.PAGE

PROJECT

C

CE

CLR

D Q

FDCEQ

PRED

CE

C

FDPE

QPRE

D

CE

C

FDPE

C

CE

CLR

D Q

FDCE

C

CE

CLR

D Q

FDCE

C

CE

CLR

D Q

FDCE

AND3

AND2

AND2

AND4B3

AND4B3

OR3

CE

TC

Q0

Q1

Q2

Q3

CR

CEO

CB4RE

CE

TC

Q0

Q1

Q2

Q3

CR

CEO

CB4RE

OR3

AND2

OR3

OR2

AND2B1

CCLR

D Q

FDC

CCLR

D Q

FDC

AND2

QD

C

FD

AND2

QD

C

FD

CCLR

D Q

FDCAND2

E

BUFE

E

BUFE

E

BUFEAND2B1

AND2B1

AND2B1

VC

C

CMS CSC ElectronicsDCC Slink Interface FPGAVME-->JTAG for data input FPGA's PROM GU 10C DCCSTX

16A

LOGICH

IDDETECT

SHIHEAD

IDDETECT

SHDHEAD

IDDETECT

SHDATA

2RXPROM6-29-2005_17:26

BUSY

RST

SLOWCLK

RST

SLOWCLK

LOAD

DONEDATA+1

SLOWCLK

DONEDATA+1

DONETAIL

DONEDATA+1

BUSY

BUSY

SHDATADHEADEN

RST

DONEDATA_1

SHDHEAD

ENABLE

SHIHEAD

DONEDHEAD

SHDHEAD

TMS

TMS

TMS

SLOWCLK

ENABLE

TAILEN

SHIHEADBUSY

IHEADEN

IHEADEN

DONEDATA+1

SHTAIL

TAILEN

SLOWCLK

SHIHEAD

DONEIHEAD

IHEADEN

DHEADENSHDATAX

BUSY

LOAD

RST

RST

LOAD

SLOWCLK

TAILEN

SLOWCLK

OKRST

RST

FASTCLK

RST

RESETDONE

RESETJTAG

SLOWCLKSTROBE

RSTJTAG

FASTCLK

RST

SLOWCLK

RST

BUSYP1

DHEADENSHDHEAD

CE

D Q

C

FDE_1

NAND3

AND2

BUF

BUF

BUF

BUF

BUF

BUF

BUF

CCLR

D Q

FDC

CE

D Q

C

FDE_1

CE

D Q

C

FDE_1

E

BUFEAND2

OR2

QPRE

D

CE

C

FDPE

QPRE

D

CE

C

FDPE

AND2

AND2 C

CE

CLR

D Q

FDCE

4

3

2

1

4

3

2

1

DCBA

TITLETHE OHIO STATE UNIVERSITY

PHYSICS DEPARTMENT ELECTRONICS LAB174 WEST 18TH AVE, COLUMBUS OH 43210

PARENT PAGEBY

DATE FILE

.PAGE

PROJECT

QPRE

D

CE

C

FDPE

INV

E

BUFE

GN

D

CEOCE

TC

Q0

Q1

Q2

Q3

CCLR

CB4CE

QPRE

D

CE

C

FDPE

QPRE

D

CE

C

FDPE

QPRE

D

CE

C

FDPE

C

CE

CLR

D Q

FDCE

AND2

CEOCE

TC

Q0

Q1

Q2

Q3

CCLR

CB4CE

C

D Q

FD_1

E

BUFE

E

BUFE

AND2B1

AND2B1

CEO

CLRC

CE

Q[7:0]

TC

CB8CE

INV

C

QD

CLR

FDC_1

INV

E

BUFE

CCLR

D Q

FDC

E

BUFEO

A3

A0

A1

A2

A4

ROM32X1

CCLR

D Q

FDC

BUF

O

A3

A0

A1

A2

A4

ROM32X1

CE

D Q

C

FDE_1

CE

D Q

C

FDE_1

CMS CSC ElectronicsDCC Slink Interface FPGAVME-->JTAG for data input FPGA's PROM GU DCCSTX

16B10C

Shift out User_Code:SIR (8) TDI (e6)SDR (32) TDI (00000000) TDO (USERCODE)LSB first

SLOWCLK

SHFTID

BOARDID1

BOARDID[3:0]BOARDID0

BOARDID3

BOARDID2

7-1-2005_11:12 RXPROM 3

0007E800 SLOWCLK

SLOWCLKSLOWCLK

TMS

MONCLK

COUNTER5

COUNTER5

COUNTER[7:0]

IDDETECT

DETRST

MONITOR0 MONITOR[7:0]

MONITOR7

MONITOR6

MONITOR5

MONITOR4

MONITOR3

MONITOR2

MONITOR1

SLOWCLK

181C01BF

TDI

IDDETECT

COUNTER4

COUNTER[7:0]COUNTER0

COUNTER1

COUNTER2

COUNTER3

TCK

IDDETECT

SLOWCLK

LOGICH

OKRST

SHTAIL

IDDETECT

TMS

RESETJTAG

TMS

DONETAIL

ENABLE

RESETJTAG

SLOWCLK

RST

DTACK

SHTAIL

ENABLE

RESETJTAG

SLOWCLK

RESETDONE

RST

SLOWCLK

ENABLE

SHTAIL

SLOWCLK

IDDETECT

LOGICH

COUNTER4

COUNTER3

COUNTER2

COUNTER1

COUNTER0

IDDETECT

SLOWCLK

SHFTID

SHFTID

DETRST

IDDETECT

MONCLK

SHFTID

SLOWCLK

SHFTID

TDOIDDETECTCOUNTER2

COUNTER4

COUNTER3SHFTID

SLOWCLK

AND4B1

4

3

2

1

4

3

2

1

DCBA

TITLETHE OHIO STATE UNIVERSITY

PHYSICS DEPARTMENT ELECTRONICS LAB174 WEST 18TH AVE, COLUMBUS OH 43210

PARENT PAGEBY

DATE FILE

.PAGE

PROJECT

AND4B3

AND2B1

AND4

AND4B1

CMS CSC ElectronicsDCC Slink Interface FPGAVME-->JTAG for data input FPGA's PROM

06 || Reset JTAG State machine05 || Read TDO register

01 || Shift data with header onlyCFEB JTAG command decode

GU

CFEB JTAG commands:00 || Shift data, no header, no tailer

02 || Shift data with tailer only03 || Shift data with header and tailer

07 || Shift Instruction register

04 ||

DCCSTX16C

10C1-22-2004_15:10 RXPROM 4

COMMAND4

INSTSHFTCMDHIGH

COMMAND0

COMMAND1

COMMAND2

DATASHFTCOMMAND2

CMDHIGH

CMDHIGHCOMMAND5

COMMAND0

COMMAND2

COMMAND1

CMDHIGHREADTDO

COMMAND1

COMMAND2

COMMAND0

CMDHIGHRSTJTAG

DEVICE

COMMAND9

COMMAND8

COMMAND7

COMMAND6

COMMAND5

COMMAND2

COMMAND1

COMMAND[9:0]

COMMAND0

COMMAND3

COMMAND4

COMMAND3

AND4

OR3

AND2B1

BUF

NOR4

4

3

2

1

4

3

2

1

DCBA

TITLETHE OHIO STATE UNIVERSITY

PHYSICS DEPARTMENT ELECTRONICS LAB174 WEST 18TH AVE, COLUMBUS OH 43210

PARENT PAGEBY

DATE FILE

.PAGE

PROJECT

SLI

Q[15:0]

L

D[15:0]

CLR

CE

C

SR16CLREEBUFE16

C

CE

CLR

D Q

FDCE

TC

UP

CE

D0

D1

D2

CCLR

D3

Q0

Q1

Q2

Q3

CEO

L

CB4CLED

GN

D

E

BUFE

GN

D

AND2

AND2

C

CE

CLR

D Q

FDCE

OR2 OR2 C

CE

CLR

D Q

FDCE

INV

BUF

C

CE

CLR

Q[15:0]

SLI

SR16LCE

AND4B2

C

CE

CLR

D Q

FDCE

CCLR

D Q

FDC

CCLR

D Q

FDC

AND2B1

OR2

AND2B1

OR2

OR2

CCLR

D Q

FDC

OR2

OR2

AND2B1

CCLR

D Q

FDC

AND2B1

C

CE

CLR

D Q

FDCE

C

CE

CLR

D Q

FDCE

OR2

INV

INV

QD

C

FDQD

C

FDQD

C

FD E

BUFE

GN

D

CMS CSC ElectronicsDCC Slink Interface FPGA GU

DTACK for Load Instruction/Data Register command

VME-->JTAG for data input FPGA

17DCCSTX10C

1RXFPGA10-3-2003_9:13

SLOWCLK

STROBE

BUSY

LOAD

DTACK

Q0

Q[15:0]

SHDATA

DONEDATA_1

DONEDATA+1

SHDATAX

RDTDOBK

RDTDOBK

INSTSHFT

DATASHFT

ENABLE TCK

DONEDATA+2

LOAD

DONEDATA+1

RST

RST

RST

RST

SLOWCLK

LOAD

RST

INDATA[15:0]

BUSY

DONEDATA

SLOWCLK

RST

SLOWCLK

SHDATALOAD

SLOWCLK

DTACK

ENABLE

TDI

BUSY

STROBE

COMMAND0

OUTDATA[15:0]

COMMAND[9:0]

COMMAND9

COMMAND6

COMMAND7

COMMAND8

LOAD

SLOWCLK

DHEADEN

TAILENCOMMAND1

ENABLE

ENABLE

SHDATA

DATASHFT

INSTSHFT

IHEADENCOMMAND0

STROBE

BUSY

SLOWCLK

LOAD

RESETJTAG

DONEIHEAD

RST

DONETAIL

RST

DONEDHEAD LOAD

SLOWCLK

READTDO

RDTDOBKSTROBE

TDO

RST

SLOWCLK

QC[15:0]

SHDATAX

BUSY

DONEDATA

LOAD

Q0

SLOWCLK

DATASHFT

INSTSHFT

LOAD

STROBE

BUSY

INSTSHFT

DATASHFT

SLOWCLK SLOWCLK

AND2

CCLR

D Q

FDC

CCLR

D Q

FDC

AND2

VC

C

CCLR

D Q

FDC

OR2

CCLR

D Q

FDC

AND2

E

BUFE

E

BUFE

C

CE

CLR

D Q

FDCEQ

PRED

CE

C

FDPE

C

CE

CLR

D Q

FDCE

C

CE

CLR

D Q

FDCE

4

3

2

1

4

3

2

1

DCBA

TITLETHE OHIO STATE UNIVERSITY

PHYSICS DEPARTMENT ELECTRONICS LAB174 WEST 18TH AVE, COLUMBUS OH 43210

PARENT PAGEBY

DATE FILE

.PAGE

PROJECT

C

CE

CLR

D Q

FDCEQ

PRED

CE

C

FDPE

QPRE

D

CE

C

FDPE

C

CE

CLR

D Q

FDCE

C

CE

CLR

D Q

FDCE

C

CE

CLR

D Q

FDCE

AND3

AND2

E

BUFE

AND2

AND4B3

AND4B3

OR3

CE

TC

Q0

Q1

Q2

Q3

CR

CEO

CB4RE

AND2

QD

C

FD

QD

C

FD

AND2

CE

TC

Q0

Q1

Q2

Q3

CR

CEO

CB4RE

OR3

OR2AND2

AND2

CCLR

D Q

FDC

OR3

AND2B1

CCLR

D Q

FDC

CMS CSC ElectronicsDCC Slink Interface FPGAVME-->JTAG for data input FPGA GU 10C DCCSTX

17A7-14-2003_12:29 RXFPGA 2

RST

SLOWCLK

DONEDATA+1

SLOWCLK

BUSY

DONEDATA+1

DONETAIL

DONEDATA+1

BUSY

BUSY

SHDATADHEADEN

SHDHEADDHEADEN

RST

DONEDATA_1

SHDHEAD

ENABLE

SHIHEAD

DONEDHEAD

SHDHEAD

SHDHEAD

SHIHEAD

TMS

TMS

SHDATA

TMS

SLOWCLK

ENABLE

TAILEN

SHIHEADBUSY

IHEADEN

IHEADEN

DONEDATA+1

SHTAIL

TAILEN

SLOWCLK

SHIHEAD

DONEIHEAD

IHEADEN

DHEADENSHDATAX

BUSY

LOAD

RST

RST

LOAD

SLOWCLK

TAILEN

SLOWCLK

OKRST

RST

FASTCLK

RST

RESETDONE

RESETJTAG

SLOWCLKSTROBE

RSTJTAG

FASTCLK

RST

LOAD

SLOWCLK

RST

AND2

OR2

QPRE

D

CE

C

FDPE

E

BUFEQ

PRED

CE

C

FDPE

AND2

AND2

E

BUFE

C

CE

CLR

D Q

FDCE

4

3

2

1

4

3

2

1

DCBA

TITLETHE OHIO STATE UNIVERSITY

PHYSICS DEPARTMENT ELECTRONICS LAB174 WEST 18TH AVE, COLUMBUS OH 43210

PARENT PAGEBY

DATE FILE

.PAGE

PROJECT

QPRE

D

CE

C

FDPE

INV

E

BUFE

GN

D

CEOCE

TC

Q0

Q1

Q2

Q3

CCLR

CB4CE

QPRE

D

CE

C

FDPE

QPRE

D

CE

C

FDPE

QPRE

D

CE

C

FDPE

C

CE

CLR

D Q

FDCE

AND2

C

D Q

FD_1

CEOCE

TC

Q0

Q1

Q2

Q3

CCLR

CB4CE

CMS CSC ElectronicsDCC Slink Interface FPGAVME-->JTAG for data input FPGA GU

17BDCCSTX10C

7-14-2003_12:29 RXFPGA 3

DONETAIL

ENABLE

RESETJTAG

SLOWCLK

RST

RESETJTAG

DTACK

SHTAIL

SHTAIL

TMS

ENABLE

RESETJTAG

SLOWCLK

OKRST

RESETDONE

TMS

RST

SLOWCLK

SLOWCLKENABLE

SHTAIL

AND4B1

4

3

2

1

4

3

2

1

DCBA

TITLETHE OHIO STATE UNIVERSITY

PHYSICS DEPARTMENT ELECTRONICS LAB174 WEST 18TH AVE, COLUMBUS OH 43210

PARENT PAGEBY

DATE FILE

.PAGE

PROJECT

AND4B3

AND2B1

AND4

AND4B1

CMS CSC ElectronicsDCC Slink Interface FPGAVME-->JTAG for data input FPGA

06 || Reset JTAG State machine05 || Read TDO register

01 || Shift data with header onlyCFEB JTAG command decode

GU

CFEB JTAG commands:00 || Shift data, no header, no tailer

02 || Shift data with tailer only03 || Shift data with header and tailer

07 || Shift Instruction register

04 ||

10C DCCSTX17C

COMMAND3

1-22-2004_15:11 RXFPGA 4

COMMAND4

INSTSHFTCMDHIGH

COMMAND0

COMMAND1

COMMAND2

DATASHFTCOMMAND2

CMDHIGH

CMDHIGHCOMMAND5

COMMAND0

COMMAND2

COMMAND1

CMDHIGHREADTDO

COMMAND1

COMMAND2

COMMAND0

CMDHIGHRSTJTAG

DEVICE

COMMAND9

COMMAND8

COMMAND7

COMMAND6

COMMAND5

COMMAND2

COMMAND1

COMMAND[9:0]

COMMAND0

COMMAND3

COMMAND4

AND4

OR3

AND2B1

BUF

NOR4

4

3

2

1

4

3

2

1

DCBA

TITLETHE OHIO STATE UNIVERSITY

PHYSICS DEPARTMENT ELECTRONICS LAB174 WEST 18TH AVE, COLUMBUS OH 43210

PARENT PAGEBY

DATE FILE

.PAGE

PROJECT

SLI

Q[15:0]

L

D[15:0]

CLR

CE

C

SR16CLREEBUFE16

C

CE

CLR

D Q

FDCE

TC

UP

CE

D0

D1

D2

CCLR

D3

Q0

Q1

Q2

Q3

CEO

L

CB4CLED

GN

D

E

BUFE

GN

D

AND2

AND2

C

CE

CLR

D Q

FDCE

OR2 OR2 C

CE

CLR

D Q

FDCE

INV

BUF

C

CE

CLR

Q[15:0]

SLI

SR16LCE

AND4B2

C

CE

CLR

D Q

FDCE

CCLR

D Q

FDC

CCLR

D Q

FDC

AND2B1

OR2

AND2B1

OR2

OR2

CCLR

D Q

FDC

OR2

OR2

AND2B1

CCLR

D Q

FDC

AND2B1

C

CE

CLR

D Q

FDCE

C

CE

CLR

D Q

FDCE

OR2

INV

INV

QD

C

FDQD

C

FDQD

C

FD E

BUFE

GN

D

CMS CSC ElectronicsDCC Slink Interface FPGA GU

DTACK for Load Instruction/Data Register command

DCCSTXVME-->JTAG for data SLINK 10D1810-3-2003_9:14 SLINKJTAG 1

SLOWCLK

STROBE

BUSY

LOAD

DTACK

Q0

Q[15:0]

SHDATA

DONEDATA_1

DONEDATA+1

SHDATAX

RDTDOBK

RDTDOBK

INSTSHFT

DATASHFT

ENABLE TCK

DONEDATA+2

LOAD

DONEDATA+1

RST

RST

RST

RST

SLOWCLK

LOAD

RST

INDATA[15:0]

BUSY

DONEDATA

SLOWCLK

RST

SLOWCLK

SHDATALOAD

SLOWCLK

DTACK

ENABLE

TDI

BUSY

STROBE

COMMAND0

OUTDATA[15:0]

COMMAND[9:0]

COMMAND9

COMMAND6

COMMAND7

COMMAND8

LOAD

SLOWCLK

DHEADEN

TAILENCOMMAND1

ENABLE

ENABLE

SHDATA

DATASHFT

INSTSHFT

IHEADENCOMMAND0

STROBE

BUSY

SLOWCLK

LOAD

RESETJTAG

DONEIHEAD

RST

DONETAIL

RST

DONEDHEAD LOAD

SLOWCLK

READTDO

RDTDOBKSTROBE

TDO

RST

SLOWCLK

QC[15:0]

SHDATAX

BUSY

DONEDATA

LOAD

Q0

SLOWCLK

DATASHFT

INSTSHFT

LOAD

STROBE

BUSY

INSTSHFT

DATASHFT

SLOWCLK SLOWCLK

AND2

CCLR

D Q

FDC

CCLR

D Q

FDC

AND2

VC

C

CCLR

D Q

FDC

OR2

CCLR

D Q

FDC

AND2

E

BUFE

E

BUFE

C

CE

CLR

D Q

FDCEQ

PRED

CE

C

FDPE

C

CE

CLR

D Q

FDCE

C

CE

CLR

D Q

FDCE

4

3

2

1

4

3

2

1

DCBA

TITLETHE OHIO STATE UNIVERSITY

PHYSICS DEPARTMENT ELECTRONICS LAB174 WEST 18TH AVE, COLUMBUS OH 43210

PARENT PAGEBY

DATE FILE

.PAGE

PROJECT

C

CE

CLR

D Q

FDCEQ

PRED

CE

C

FDPE

QPRE

D

CE

C

FDPE

C

CE

CLR

D Q

FDCE

C

CE

CLR

D Q

FDCE

C

CE

CLR

D Q

FDCE

AND3

AND2

E

BUFE

AND2

AND4B3

AND4B3

OR3

CE

TC

Q0

Q1

Q2

Q3

CR

CEO

CB4RE

AND2

QD

C

FD

QD

C

FD

AND2

CE

TC

Q0

Q1

Q2

Q3

CR

CEO

CB4RE

OR3

OR2AND2

AND2

CCLR

D Q

FDC

OR3

AND2B1

CCLR

D Q

FDC

CMS CSC ElectronicsDCC Slink Interface FPGA GU DCCSTXVME-->JTAG for Slink 10D

18A2SLINKJTAG7-24-2003_15:22

RST

SLOWCLK

DONEDATA+1

SLOWCLK

BUSY

DONEDATA+1

DONETAIL

DONEDATA+1

BUSY

BUSY

SHDATADHEADEN

SHDHEADDHEADEN

RST

DONEDATA_1

SHDHEAD

ENABLE

SHIHEAD

DONEDHEAD

SHDHEAD

SHDHEAD

SHIHEAD

TMS

TMS

SHDATA

TMS

SLOWCLK

ENABLE

TAILEN

SHIHEADBUSY

IHEADEN

IHEADEN

DONEDATA+1

SHTAIL

TAILEN

SLOWCLK

SHIHEAD

DONEIHEAD

IHEADEN

DHEADENSHDATAX

BUSY

LOAD

RST

RST

LOAD

SLOWCLK

TAILEN

SLOWCLK

OKRST

RST

FASTCLK

RST

RESETDONE

RESETJTAG

SLOWCLKSTROBE

RSTJTAG

FASTCLK

RST

LOAD

SLOWCLK

RST

AND2

OR2

QPRE

D

CE

C

FDPE

E

BUFEQ

PRED

CE

C

FDPE

AND2

AND2

E

BUFE

C

CE

CLR

D Q

FDCE

4

3

2

1

4

3

2

1

DCBA

TITLETHE OHIO STATE UNIVERSITY

PHYSICS DEPARTMENT ELECTRONICS LAB174 WEST 18TH AVE, COLUMBUS OH 43210

PARENT PAGEBY

DATE FILE

.PAGE

PROJECT

QPRE

D

CE

C

FDPE

INV

E

BUFE

GN

D

CEOCE

TC

Q0

Q1

Q2

Q3

CCLR

CB4CE

QPRE

D

CE

C

FDPE

QPRE

D

CE

C

FDPE

QPRE

D

CE

C

FDPE

C

CE

CLR

D Q

FDCE

AND2

C

D Q

FD_1

CEOCE

TC

Q0

Q1

Q2

Q3

CCLR

CB4CE

CMS CSC ElectronicsDCC Slink Interface FPGA GU DCCSTX

18B10DVME-->JTAG for SLINK

3SLINKJTAG7-24-2003_15:22

DONETAIL

ENABLE

RESETJTAG

SLOWCLK

RST

RESETJTAG

DTACK

SHTAIL

SHTAIL

TMS

ENABLE

RESETJTAG

SLOWCLK

OKRST

RESETDONE

TMS

RST

SLOWCLK

SLOWCLKENABLE

SHTAIL

AND4B1

4

3

2

1

4

3

2

1

DCBA

TITLETHE OHIO STATE UNIVERSITY

PHYSICS DEPARTMENT ELECTRONICS LAB174 WEST 18TH AVE, COLUMBUS OH 43210

PARENT PAGEBY

DATE FILE

.PAGE

PROJECT

AND4

AND4B1

AND2B1

AND4B3

CMS CSC ElectronicsDCC Slink Interface FPGA

06 || Reset JTAG State machine05 || Read TDO register

01 || Shift data with header onlyCFEB JTAG command decode

GU

CFEB JTAG commands:00 || Shift data, no header, no tailer

02 || Shift data with tailer only03 || Shift data with header and tailer

07 || Shift Instruction register

04 ||

DCCSTX18C

10DVME-->JTAG for SLINK

CMDHIGH

1-22-2004_15:13 SLINKJTAG 4

COMMAND3

COMMAND4

INSTSHFTCMDHIGH

COMMAND0

COMMAND1

COMMAND2

DATASHFTCOMMAND2

CMDHIGH

COMMAND5

COMMAND0

COMMAND2

COMMAND1

CMDHIGHREADTDO

COMMAND1

COMMAND2

COMMAND0

CMDHIGHRSTJTAG

DEVICE

COMMAND9

COMMAND8

COMMAND7

COMMAND6

COMMAND5

COMMAND2

COMMAND1

COMMAND[9:0]

COMMAND0

COMMAND3

COMMAND4

AND2AND4B3

AND4

INVOPAD

LVCMOS25 SLOW 12

OBUF

AND4B2

AND4B1

AND4B1

AND4B2

4

3

2

1

4

3

2

1

DCBA

TITLETHE OHIO STATE UNIVERSITY

PHYSICS DEPARTMENT ELECTRONICS LAB174 WEST 18TH AVE, COLUMBUS OH 43210

PARENT PAGEBY

DATE FILE

.PAGE

PROJECT

AND4B4

AND4B3

AND4B2

AND4B2

AND4B1

AND3B2

AND4B4

AND4

AND4

E

BUFE

Q

D

A0

A1

A2

A3

CLK

@INIT="0000"

SRL16

AND2

VC

C

AND4B3

AND2

AND4B3

08 || Force FMM states

CFEB JTAG command decode

VME Registers:00 || TTCrx Command Bus

CMS CSC ElectronicsDCC Slink Interface FPGA GU DCCSTX

1910DVME Registers, address decoder

01 || Read Status, Low 16 bits02 || Read Status, High 16 bits03 || Load FIFO_In_Use register, to mask off the no_DDU_input FIFOs04 || Generate Fake L1A05 || Read back TTC_Cmd

1X || Read back Date Rate Monitor

TTCrx Reset, it will last for many us

06 || Read back fifo in use

5A || Reset TTCrx

07 || software switch, and force TTC 'not ready'.

FORCEFMM

CMDHIGHCCMDHIGH

COMMAND3

1VMEREG1-26-2007_14:57

SOFTSW

SLOWCLK

TTCRESET

STROBE

DEVICE

DEVICE

COMMAND9

COMMAND0

COMMAND9

COMMAND3

COMMAND4

COMMAND8

COMMAND7

COMMAND6

COMMAND5

COMMAND2

COMMAND1

COMMAND[9:0]

COMMAND0

COMMAND5

COMMAND6

COMMAND5

CMDHIGHD

COMMAND4

RDBKUFIFO

RDBKTTC

CMDHIGHC

CMDHIGHC

CMDHIGHC

CMDHIGHC

COMMAND2

COMMAND0

READLSTAT

LOADTTC

COMMAND0

COMMAND1

COMMAND7

COMMAND8

COMMAND9

COMMAND2

COMMAND0

COMMAND2

COMMAND1

READHSTATCOMMAND1

COMMAND1

COMMAND0

COMMAND2

LOADFFUSE

COMMAND2FORCEL1

COMMAND0

COMMAND1

CMDHIGHC

COMMAND1

COMMAND0

COMMAND2

CMDHIGHC

COMMAND0

COMMAND2

COMMAND1

CMDHIGHC

COMMAND4

CMDHIGHD

COMMAND6READRATE

COMMAND1

COMMAND2

COMMAND3

COMMAND5

COMMAND6

COMMAND7

COMMAND8

COMMAND4

B15

LOGICL DTACK

CMDHIGHC

COMMAND1

COMMAND2

COMMAND0

COMMAND4

COMMAND5

COMMAND6

COMMAND3

CMDHIGHDCMDHIGHF

COMMAND2

COMMAND1

COMMAND0

CMDHIGHF

Q[15:0]D[15:0]

CLR

CE

C

FD16CE

AND3B1

BUF

BUF

BUF

BUF

BUF

BUF

BUF

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

OPAD

AND3B1

C

QD

CLR

FDC_1

CCLR

D Q

FDCLVCMOS25 SLOW 12

OBUFQD

C

FD

QD

C

FDLVCMOS25 SLOW 12

OBUF

CCLR

D Q

FDC

LVCMOS25 SLOW 12

OBUF

LVCMOS25 SLOW 12

OBUF

LVCMOS25 SLOW 12

OBUF

LVCMOS25 SLOW 12

OBUF

LVCMOS25 SLOW 12

OBUF

LVCMOS25 SLOW 12

OBUF

GN

D

4

3

2

1

4

3

2

1

DCBA

TITLETHE OHIO STATE UNIVERSITY

PHYSICS DEPARTMENT ELECTRONICS LAB174 WEST 18TH AVE, COLUMBUS OH 43210

PARENT PAGEBY

DATE FILE

.PAGE

PROJECT

Q[15:0]D[15:0]

CLR

CE

C

FD16CE

VC

C

LVCMOS25 SLOW 12

OBUF

CCLR

D Q

FDCQD

C

FD

QD

C

FD

AND2

E

BUFE

QD

C

FD

OPAD

OPAD

BUF

BUF

BUFAND3B1

Q[15:0]D[15:0]

CLR

CE

C

FD16CE

CMS CSC ElectronicsDCC Slink Interface FPGA GU DCCSTX10D

19A

VME registers, TTC command bus loading

TTC

com

man

d bu

s

FORFMM15

FORFMM5

FORFMM4

FORFMM3

FORFMM2

FORFMM1

FORFMM[15:0]FORFMM0

FORFMM6

FORFMM7

FORFMM8

FORFMM9

FORFMM10

FORFMM11

FORFMM12

FORFMM13

FORFMM14

2-5-2007_1:42 VMEREG 2

SOFTSWSET15

SOFTSWSET[15:0]SOFTSWSET0

SOFTSWSET1

SOFTSWSET2

SOFTSWSET3

SOFTSWSET4

SOFTSWSET5

SOFTSWSET6

SOFTSWSET7

SOFTSWSET8

SOFTSWSET9

SOFTSWSET10

SOFTSWSET11

SOFTSWSET12

SOFTSWSET13

SOFTSWSET14

RSTD

INDATA[15:0]

ADDR7

CMDSTRB

LREG1

LREG0

CMDSTRB

VMELPBK[9:0]

VMELPBK1

VMELPBK9

VMELPBK8

VMELPBK7

VMELPBK6

VMELPBK5

VMELPBK4

VMELPBK3

VMELPBK2

VMELPBK0

BXNRST

LREG2

BXNRST

EVTRST

G9

D7

LOADTTC

INDATA[15:0]

FASTCLKFASTCLK

DTACKLOGICL

ADDR0

ADDR0

LREG1

LREG7

LREG[15:0]

LREG6

LREG5

LREG4

LREG3

LREG2

LREG0

LOGICL

LOGICHSTROBE

LOGICH

FASTCLK

FASTCLK

FASTCLK

ADDR0

FASTCLK

ADDR0

WRITE

C7

F9

F10

H9

D11

B8

G12

LREG6

CMDSTRB

EVTRST

LREG7

LREG3

LREG4

LREG5

FORCEL1A

CMDSTRB

WRITE

STROBE LOGICH

SOFTSW

FORCEFMM

LOGICHSTROBE

WRITE

ADDR8

INDATA[15:0]

RSTD

QPRE

D

CLRC

FDCP

QPRE

D

CLRC

FDCP

QPRE

D

CLRC

FDCP

QPRE

D

CLRC

FDCP

QPRE

D

CLRC

FDCP

QPRE

D

CLRC

FDCP

QD

C

FD

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

QD

C

FD

AND2

E

BUFE

E

BUFEAND2

QD

C

FD

EBUFE16

EBUFE16

4

3

2

1

4

3

2

1

DCBA

TITLETHE OHIO STATE UNIVERSITY

PHYSICS DEPARTMENT ELECTRONICS LAB174 WEST 18TH AVE, COLUMBUS OH 43210

PARENT PAGEBY

DATE FILE

.PAGE

PROJECT

QD

C

FD

AND2

E

BUFE

QD

C

FD

BUF

BUF

BUF

BUF

QD

C

FD

CCLR

D Q

FDC

AND3B1

CCLR

D Q

FDC

QPRE

D

CLRC

FDCP

QPRE

D

CLRC

FDCP

QPRE

D

CLRC

FDCP

QPRE

D

CLRC

FDCP

CMS CSC ElectronicsDCC Slink Interface FPGA GU DCCSTX10D

19B

VME registers, FPGA status monitoring

1-26-2007_15:00 VMEREG 3

L1AMODE

DDUOK10

FIFOUSE9

ADDR3

RSTD

INDATA9

RSTD

RSTD

RSTD

FASTCLK

LOGICH

LOGICH

RST

RSTD

RSTD

RSTDMONITOR[15:0]

MONITOR15

MONITOR14

MONITOR13

MONITOR12

MONITOR11

MONITOR10

MONITOR9

MONITOR8

MONITOR7

MONITOR6

MONITOR5

MONITOR4

MONITOR3

MONITOR2

MONITOR1

MONITOR0

VMEL1A

FIFOUSE7

FIFOUSE8

FIFOUSE3

INDATA4

ADDR3USELOWSKEWLINES

STATUS[31:0]

STATUS[15:0]

STATUS[31:16]

STATUS[31:16]

FASTCLK

OUTDATA[15:0]

READLSTAT

STROBE

DTACKLOGICL

LOGICL DTACK

STROBE

READHSTAT

OUTDATA[15:0]

FASTCLK

DTACKLOGICL

FASTCLK

ADDR3

FASTCLK

ADDR3

WRITE

STROBE

LOADFFUSE

ADDR3

ADDR3

RSTD

ADDR3

RSTD

ADDR3

ADDR3

ADDR3

ADDR3

INDATA8

INDATA7

INDATA6

INDATA5

INDATA3

INDATA2

INDATA1

FIFOUSE8

FIFOUSE7

FIFOUSE6

FIFOUSE5

FIFOUSE4

FIFOUSE2

FIFOUSE1

FIFOUSE9FIFOUSE[9:0]

FIFOUSE8

FIFOUSE7

FIFOUSE6

FIFOUSE5

FIFOUSE4

FIFOUSE3

FIFOUSE2

FIFOUSE1

FIFOUSE0

SWL1A

INDATA10

RSTD

ADDR3

ADDR3

INDATA0 FIFOUSE0

RSTD RSTD

DDUOK9

DDUOK8

DDUOK7

DDUOK6

DDUOK5

DDUOK4

DDUOK3

DDUOK2

DDUOK1

INDATA9

INDATA[15:0]

INDATA0

INDATA8

INDATA7

INDATA6

INDATA5

INDATA4

INDATA3

INDATA2

INDATA1

INDATA10

DDUOK10DDUOK[10:1]

DDUOK9

DDUOK8

DDUOK7

DDUOK6

DDUOK5

DDUOK4

DDUOK3

DDUOK2

DDUOK1

BUF

BUF

BUF

BUF

BUF

BUF

CCLR

D Q

FDC

QD

C

FD

C

CE

CLR

D Q

FDCE

INV

Q

D

A0

A1

A2

A3

CLK

@INIT="0000"

SRL16QD

C

FD

CCLR

D Q

FDC

4

3

2

1

4

3

2

1

DCBA

TITLETHE OHIO STATE UNIVERSITY

PHYSICS DEPARTMENT ELECTRONICS LAB174 WEST 18TH AVE, COLUMBUS OH 43210

PARENT PAGEBY

DATE FILE

.PAGE

PROJECT

Q[15:0]D[15:0]

CLR

CE

C

FD16CE

QD

C

FD

AND2

E

BUFE

QD

C

FD

QD

C

FDQ[7:0]

D[7:0]

CLR

CE

C

FD8CE

TC

UP

CE

CCLR

L

Q[7:0]D[7:0]

CEO

CB8CLEDC

CLR

D Q

FDC

Q

D

A0

A1

A2

A3

CLK

@INIT="0000"

SRL16

AND2B1

QD

C

FD

C

CE

CLR

D Q

FDCE

INV

INV

CCLR

D Q

FDC

CCLR

D Q

FDC

OR8

BUF

BUF

AND3B1

AND2

OR2

C

D Q

OFDOPAD

Q

D

A0

A1

A2

A3

CLK

@INIT="0000"

SRL16Q

D

A0

A1

A2

A3

CLK

@INIT="0000"

SRL16Q

D

A0

A1

A2

A3

CLK

@INIT="0000"

SRL16Q

D

A0

A1

A2

A3

CLK

@INIT="0000"

SRL16

Q

D

A0

A1

A2

A3

CLK

@INIT="0000"

SRL16Q

D

A0

A1

A2

A3

CLK

@INIT="0000"

SRL16Q

D

A0

A1

A2

A3

CLK

@INIT="0000"

SRL16

OR2

LVCMOS25

IBUFIPAD

C

D Q

R

FDR

OR3

C

QD

CLR

FDC_1

CCLR

D Q

FDC

DCC Slink Interface FPGA GU DCCSTX10D19CCMS CSC Electronics

VME registers, VME L1A generation

The DATA[15:0] to control the L1A generation mode L1A generation will auto stop. Internal BUSY will delay further VME command

Alway trigger one event at least

Data[15:8]: The L1A frequency control, Data[7:0]: Total number of L1As, if Data7=1, no stop

IOB=TRUE

IOB=TRUE

SWL1A

EXTL1A

FASTCLK

RST

G1

4VMEREG6-20-2005_8:27

DSLOWL1X

NTRG7 NTRG[7:0]

NTRG2

NTRG1

NTRG0

NTRG3

NTRG4

NTRG5

NTRG6

REMAIN4

REMAIN0

REMAIN[7:0]

REMAIN6

REMAIN5

REMAIN3

REMAIN2

REMAIN1

D8FORCEL1A

NTRG[7:0]

L1MODE[15:8]

L1MODE1

L1MODE7

L1MODE[15:0]

L1MODE6

L1MODE5

L1MODE4

L1MODE3

L1MODE2

LOGICH

LOGICH

L1MODE[15:8]

RST

RST

RSTRST

FASTCLK

SLOWCLK

FASTCLK

FINISH

FASTCLK

DVMEL1ALOAD

LOGICH

SLOWCLK

VMEL1A

FASTCLKDSLOWL1

LOGICH

DELAY5

DELAY4

DELAY4

DELAY[7:0]

SLOWL1

SLOWL1

LOAD

FASTCLK

NEMPTY

LOAD

LOGICL

VMEL1A

NOTBUSY

L1AGEN

L1AGEN

L1AGEN

FASTCLK

FORCEL1

INDATA[15:0]

DTACKLOGICL

LOGICL

STROBE

FASTCLK

L1AGEN

WRITE

DLOAD

L1AGEN

LOGICH

LOAD

FASTCLK

FASTCLK

DELAY4

DELAY4

SLOWCLK

SLOWCLK

DELAY5

DELAY5

DELAY5

DELAY5

DELAY5

DELAY5

SLOWCLK

DELAY5

LOGICH

VMEL1ALOGICH

LOGICH

LOGICH

FINISH

LOAD

FASTCLK

FINISH

LOGICH BUSY NOTBUSY

DLOAD

FASTCLK

DVMEL1A

FASTCLK

FASTCLK

VMEL1A

NTRG7

DELAY5

DELAY[7:0]

DELAY4

DELAY3

DELAY0

DELAY1

DELAY2

DELAY6

DELAY6

SLOWCLK

DELAY6

DELAY6

DELAY6

DELAY6

DELAY6

DELAY6

SLOWCLK

DELAY6

DSLOWL1X

DELAY6

SLOWCLK

DELAY6

DELAY6

DELAY6

DELAY6

DELAY6

DELAY6

SLOWCLK

DELAY6

FASTCLK

EXTL1A

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

E

BUFEAND2

QD

C

FD

EBUFE16

EBUFE16

QD

C

FD

AND2

E

BUFE

QD

C

FD

4

3

2

1

4

3

2

1

DCBA

TITLETHE OHIO STATE UNIVERSITY

PHYSICS DEPARTMENT ELECTRONICS LAB174 WEST 18TH AVE, COLUMBUS OH 43210

PARENT PAGEBY

DATE FILE

.PAGE

PROJECT

TCCLR

C

CE

Q[15:0]

CEO

CB16CE

OR2CCLR

D Q

FDC

AND2

BUF

BUF

BUFBUF

BUF

BUF

BUF

DCC Slink Interface FPGA GU DCCSTX10DCMS CSC Electronics

Switch generated L1As

19D

DELAY0

L1AMODE

LREG0 FIFOUSE0

FIFOUSE9

FIFOUSE6

FIFOUSTAT0

FIFOUSTAT11

FIFOUSTAT12

FIFOUSTAT13

FIFOUSTAT14

FIFOUSTAT15

FIFOUSTAT[15:0]

FIFOUSTAT10

FIFOUSTAT9

FIFOUSTAT8

FIFOUSTAT7

FIFOUSTAT6

FIFOUSTAT5

FIFOUSTAT4

FIFOUSTAT3

FIFOUSTAT2

FIFOUSTAT1

5VMEREG2-14-2006_7:58

TTCSTAT15

TTCSTAT[15:0]

TTCSTAT14

TTCSTAT13

TTCSTAT12

TTCSTAT11

TTCSTAT10

TTCSTAT9

TTCSTAT8

TTCSTAT7

TTCSTAT6

TTCSTAT0

TTCSTAT1

TTCSTAT2

TTCSTAT3

TTCSTAT4

TTCSTAT5

RDBKUFIFO

FASTCLK

FASTCLKSW1

SWL1A

LOGICH

SWL1ASWL1A

SW2

SW1SW[3:1]

SW3

SW2

SW3

FASTCLK

OUTDATA[15:0]

STROBE

DTACKLOGICLLOGICL DTACK

STROBE

RDBKTTC

OUTDATA[15:0]

FASTCLK

FIFOUSE1

FIFOUSE2

FIFOUSE3

FIFOUSE4

FIFOUSE5

FIFOUSE7

FIFOUSE8

LREG1

LREG2

LREG3

LREG4

LREG5

LREG6

LREG7

DELAY1

DELAY2

DELAY3

DELAY4

DELAY5

DELAY6

L1MODE6

L1MODE1

L1MODE2

L1MODE3

L1MODE4

L1MODE5

O

E

D8

D7

D9

D6

D10

D5

D11

D4

D12

D3

D13

D2

D14

D1

D15

D0

S1

S2

S3

S0

M16_1E

O

E

D8

D7

D9

D6

D10

D5

D11

D4

D12

D3

D13

D2

D14

D1

D15

D0

S1

S2

S3

S0

M16_1E

O

E

D8

D7

D9

D6

D10

D5

D11

D4

D12

D3

D13

D2

D14

D1

D15

D0

S1

S2

S3

S0

M16_1E

O

E

D8

D7

D9

D6

D10

D5

D11

D4

D12

D3

D13

D2

D14

D1

D15

D0

S1

S2

S3

S0

M16_1E

EBUFE16

QD

C

FD

AND2

E

BUFE

4

3

2

1

4

3

2

1

DCBA

TITLETHE OHIO STATE UNIVERSITY

PHYSICS DEPARTMENT ELECTRONICS LAB174 WEST 18TH AVE, COLUMBUS OH 43210

PARENT PAGEBY

DATE FILE

.PAGE

PROJECT

O

E

D8

D7

D9

D6

D10

D5

D11

D4

D12

D3

D13

D2

D14

D1

D15

D0

S1

S2

S3

S0

M16_1E

O

E

D8

D7

D9

D6

D10

D5

D11

D4

D12

D3

D13

D2

D14

D1

D15

D0

S1

S2

S3

S0

M16_1E

O

E

D8

D7

D9

D6

D10

D5

D11

D4

D12

D3

D13

D2

D14

D1

D15

D0

S1

S2

S3

S0

M16_1E

O

E

D8

D7

D9

D6

D10

D5

D11

D4

D12

D3

D13

D2

D14

D1

D15

D0

S1

S2

S3

S0

M16_1E

DCC Slink Interface FPGA GU DCCSTXCMS CSC Electronics 19E

10DDDU Date rate read out

FORFMM0

SOFTSWSET0

2-5-2007_1:45 VMEREG 6

RMOUT[15:0]

RMOUT2RMOUT0 RMOUT1

RATEMON[191:0]

RATEMON180

RATEMON164

RATEMON148

RATEMON132

RATEMON116

RATEMON100

RATEMON84

RATEMON68

RATEMON52

RATEMON36

RATEMON20

RATEMON4

RATEMON176

RATEMON160

RATEMON144

RATEMON128

RATEMON112

RATEMON96

RATEMON80

RATEMON64

RATEMON48

RATEMON32

RATEMON16

RATEMON0

RATEMON181

RATEMON165

RATEMON149

RATEMON133

RATEMON117

RATEMON101

RATEMON85

RATEMON69

RATEMON53

RATEMON37

RATEMON21

RATEMON5

RATEMON177

RATEMON161

RATEMON145

RATEMON129

RATEMON113

RATEMON97

RATEMON81

RATEMON65

RATEMON49

RATEMON33

RATEMON17

RATEMON1

RATEMON182

RATEMON166

RATEMON150

RATEMON134

RATEMON118

RATEMON102

RATEMON86

RATEMON70

RATEMON54

RATEMON38

RATEMON22

RATEMON6

RATEMON178

RATEMON162

RATEMON146

RATEMON130

RATEMON114

RATEMON98

RATEMON82

RATEMON66

RATEMON50

RATEMON34

RATEMON18

RATEMON2 RATEMON3

RATEMON19

RATEMON35

RATEMON51

RATEMON67

RATEMON83

RATEMON99

RATEMON115

RATEMON131

RATEMON147

RATEMON163

RATEMON179

RATEMON7

RATEMON23

RATEMON39

RATEMON55

RATEMON71

RATEMON87

RATEMON103

RATEMON119

RATEMON135

RATEMON151

RATEMON167

RATEMON183

COMMAND0

COMMAND3

COMMAND2

COMMAND1

READRATE

FASTCLK

OUTDATA[15:0]

STROBE

DTACKLOGICL

LOGICH LOGICH

COMMAND1

COMMAND2

COMMAND3

COMMAND0

LOGICH

COMMAND1

COMMAND2

COMMAND3

COMMAND0

LOGICH

COMMAND1

COMMAND2

COMMAND3

COMMAND0

COMMAND0

COMMAND3

COMMAND2

COMMAND1

LOGICH

COMMAND0

COMMAND3

COMMAND2

COMMAND1

LOGICH

COMMAND0

COMMAND3

COMMAND2

COMMAND1

LOGICHLOGICH

COMMAND1

COMMAND2

COMMAND3

COMMAND0

RMOUT3

RMOUT4 RMOUT5 RMOUT6 RMOUT7

SOFTSWSET1 SOFTSWSET2 SOFTSWSET3

SOFTSWSET4 SOFTSWSET5 SOFTSWSET6 SOFTSWSET7

FORFMM1 FORFMM2 FORFMM3

FORFMM4 FORFMM5 FORFMM6 FORFMM7

O

E

D8

D7

D9

D6

D10

D5

D11

D4

D12

D3

D13

D2

D14

D1

D15

D0

S1

S2

S3

S0

M16_1E

O

E

D8

D7

D9

D6

D10

D5

D11

D4

D12

D3

D13

D2

D14

D1

D15

D0

S1

S2

S3

S0

M16_1E

O

E

D8

D7

D9

D6

D10

D5

D11

D4

D12

D3

D13

D2

D14

D1

D15

D0

S1

S2

S3

S0

M16_1E

4

3

2

1

4

3

2

1

DCBA

TITLETHE OHIO STATE UNIVERSITY

PHYSICS DEPARTMENT ELECTRONICS LAB174 WEST 18TH AVE, COLUMBUS OH 43210

PARENT PAGEBY

DATE FILE

.PAGE

PROJECT

O

E

D8

D7

D9

D6

D10

D5

D11

D4

D12

D3

D13

D2

D14

D1

D15

D0

S1

S2

S3

S0

M16_1E

O

E

D8

D7

D9

D6

D10

D5

D11

D4

D12

D3

D13

D2

D14

D1

D15

D0

S1

S2

S3

S0

M16_1E

O

E

D8

D7

D9

D6

D10

D5

D11

D4

D12

D3

D13

D2

D14

D1

D15

D0

S1

S2

S3

S0

M16_1E

O

E

D8

D7

D9

D6

D10

D5

D11

D4

D12

D3

D13

D2

D14

D1

D15

D0

S1

S2

S3

S0

M16_1E

O

E

D8

D7

D9

D6

D10

D5

D11

D4

D12

D3

D13

D2

D14

D1

D15

D0

S1

S2

S3

S0

M16_1E

DCC Slink Interface FPGA GU DCCSTXCMS CSC Electronics

10DDDU Date rate read out

19F

FORFMM8

SOFTSWSET8

2-5-2007_1:45 VMEREG 7

LOGICH

RMOUT12

RMOUT11

RMOUT10

RMOUT9

RMOUT8

RMOUT7

RMOUT6

RMOUT5

RMOUT4

RMOUT3

RMOUT2

RMOUT1

RMOUT0

RMOUT13

RMOUT15RMOUT[15:0]

RMOUT14

RATEMON[191:0]

RATEMON136

RATEMON24

RATEMON191

RATEMON175

RATEMON159

RATEMON143

RATEMON127

RATEMON111

RATEMON95

RATEMON79

RATEMON63

RATEMON47

RATEMON31

RATEMON15

RATEMON187

RATEMON171

RATEMON155

RATEMON139

RATEMON123

RATEMON107

RATEMON91

RATEMON75

RATEMON59

RATEMON43

RATEMON27

RATEMON11

RATEMON190

RATEMON174

RATEMON158

RATEMON142

RATEMON126

RATEMON110

RATEMON94

RATEMON78

RATEMON62

RATEMON46

RATEMON30

RATEMON14

RATEMON186

RATEMON170

RATEMON154

RATEMON138

RATEMON122

RATEMON106

RATEMON90

RATEMON74

RATEMON58

RATEMON42

RATEMON26

RATEMON10

RATEMON189

RATEMON173

RATEMON157

RATEMON141

RATEMON125

RATEMON109

RATEMON93

RATEMON77

RATEMON61

RATEMON45

RATEMON29

RATEMON13

RATEMON185

RATEMON169

RATEMON153

RATEMON137

RATEMON121

RATEMON105

RATEMON89

RATEMON73

RATEMON57

RATEMON41

RATEMON25

RATEMON9RATEMON8

RATEMON40

RATEMON56

RATEMON72

RATEMON88

RATEMON104

RATEMON120

RATEMON188

RATEMON172

RATEMON156

RATEMON140

RATEMON124

RATEMON108

RATEMON92

RATEMON76

RATEMON60

RATEMON44

RATEMON28

RATEMON12

RATEMON184

RATEMON168

RATEMON152

RMOUT12

COMMAND0

COMMAND3

COMMAND2

COMMAND1

LOGICH

COMMAND1

COMMAND2

COMMAND3

COMMAND0

LOGICH

COMMAND1

COMMAND2

COMMAND3

COMMAND0

LOGICH

COMMAND1

COMMAND2

COMMAND3

COMMAND0

COMMAND0

COMMAND3

COMMAND2

COMMAND1

LOGICH

COMMAND0

COMMAND3

COMMAND2

COMMAND1

LOGICH

COMMAND0

COMMAND3

COMMAND2

COMMAND1

LOGICHLOGICH

COMMAND1

COMMAND2

COMMAND3

COMMAND0

RMOUT8 RMOUT9 RMOUT10 RMOUT11

RMOUT13 RMOUT14 RMOUT15

SOFTSWSET9 SOFTSWSET10 SOFTSWSET11

SOFTSWSET12 SOFTSWSET13 SOFTSWSET14 SOFTSWSET15

FORFMM9 FORFMM10 FORFMM11

FORFMM12 FORFMM13 FORFMM14 FORFMM15

D

CE

C0

Q0

Q1

CLR

PRE

MOND

IFDDRG

D

CE

C0

Q0

Q1

CLR

PRE

MOND

IFDDRG

D

CE

C0

Q0

Q1

CLR

PRE

MOND

IFDDRG

D

CE

C0

Q0

Q1

CLR

PRE

MOND

IFDDRG

D

CE

C0

Q0

Q1

CLR

PRE

MOND

IFDDRG

D

CE

C0

Q0

Q1

CLR

PRE

MOND

IFDDRG

D

CE

C0

Q0

Q1

CLR

PRE

MOND

IFDDRG

D

CE

C0

Q0

Q1

CLR

PRE

MOND

IFDDRG

D

CE

C0

Q0

Q1

CLR

PRE

MOND

IFDDRG

D

CE

C0

Q0

Q1

CLR

PRE

MOND

IFDDRG

D

CE

C0

Q0

Q1

CLR

PRE

MOND

IFDDRG

D

CE

C0

Q0

Q1

CLR

PRE

MOND

IFDDRG

D

CE

C0

Q0

Q1

CLR

PRE

MOND

IFDDRG

D

CE

C0

Q0

Q1

CLR

PRE

MOND

IFDDRG

D

CE

C0

Q0

Q1

CLR

PRE

MOND

IFDDRG

D

CE

C0

Q0

Q1

CLR

PRE

MOND

IFDDRG

D

CE

C0

Q0

Q1

CLR

PRE

MOND

IFDDRG

D

CE

C0

Q0

Q1

CLR

PRE

MOND

IFDDRG

D

CE

C0

Q0

Q1

CLR

PRE

MOND

IFDDRG

D

CE

C0

Q0

Q1

CLR

PRE

MOND

IFDDRG

D

CE

C0

Q0

Q1

CLR

PRE

MOND

IFDDRG

D

CE

C0

Q0

Q1

CLR

PRE

MOND

IFDDRG

D

CE

C0

Q0

Q1

CLR

PRE

MOND

IFDDRG

D

CE

C0

Q0

Q1

CLR

PRE

MOND

IFDDRG

D

CE

C0

Q0

Q1

CLR

PRE

MOND

IFDDRG

D

CE

C0

Q0

Q1

CLR

PRE

MOND

IFDDRG

D

CE

C0

Q0

Q1

CLR

PRE

MOND

IFDDRG

D

CE

C0

Q0

Q1

CLR

PRE

MOND

IFDDRG

D

CE

C0

Q0

Q1

CLR

PRE

MOND

IFDDRG

D

CE

C0

Q0

Q1

CLR

PRE

MOND

IFDDRG

D

CE

C0

Q0

Q1

CLR

PRE

MOND

IFDDRG

D

CE

C0

Q0

Q1

CLR

PRE

MOND

IFDDRG

D

CE

C0

Q0

Q1

CLR

PRE

MOND

IFDDRG

D

CE

C0

Q0

Q1

CLR

PRE

MOND

IFDDRG

VC

C

GN

D

4

3

2

1

4

3

2

1

DCBA

TITLETHE OHIO STATE UNIVERSITY

PHYSICS DEPARTMENT ELECTRONICS LAB174 WEST 18TH AVE, COLUMBUS OH 43210

PARENT PAGEBY

DATE FILE

.PAGE

PROJECT

D

CE

C0

Q0

Q1

CLR

PRE

MOND

IFDDRG

too many wordsone channel has

CMS CSC Electronics

GU DCCSTXDCC Slink FPGA20

2C,2DDDR Fifo input de-mux

The Clock Phase needs be adjustedDDR FIFO ReadDTBD[71:68] is used for SLINK64 user bits ?

FFIN39: Last Word bit, used in page 20E

One channel empty,other not, for too long

ALCT data

CFEB data

TMB data

DMB header

CLKFIFO2

1-31-2006_15:14 SLINK 1

MONDIN8

DTBD15

DTBD47

RESET

RESET

RESET

RESET

RESET

RESET

RESET

LOGICL

DTBD61

DTBD45

DENABLE

DENABLE

DENABLE

DENABLE

DENABLE

DENABLE

DENABLE

DENABLE

DENABLE

FFIN35

FFIN34

FFIN33

FFIN32

FFIN31

FFIN30

FFIN29

FFIN28

FFIN27

FFIN26

FFIN25

FFIN24

FFIN23

FFIN22

FFIN21

FFIN20

FFIN19

FFIN18

FFIN17

FFIN16

FFIN15

FFIN14

FFIN13

FFIN12

FFIN11

FFIN9

FFIN8

FFIN7

FFIN6

FFIN5

FFIN4

FFIN3

FFIN[35:0]FFIN0

FFIN1

FFIN2

FFIN10

LOGICL

LOGICL

DTBD66FFIN33

DTBD65

CLKFIFO

FFIN21 DTBD21

CLKFIFO

FFIN10

MONDIN10

DTBD53

DTBD10

CLKFIFO

CLKFIFO

MONDIN0

DTBD32

DTBD64

FFIN0 DTBD0

CLKFIFO

LOGICL

CLKFIFO

LOGICL

CLKFIFO

LOGICL

CLKFIFO

LOGICL

CLKFIFO

LOGICL LOGICL

CLKFIFO

LOGICL

CLKFIFO

LOGICL

CLKFIFO

LOGICL

CLKFIFO

LOGICL

CLKFIFO

CLKFIFO

LOGICL

LOGICL

CLKFIFO

LOGICL

CLKFIFO

LOGICL

CLKFIFO

LOGICL

CLKFIFO

LOGICL

CLKFIFO

CLKFIFO

LOGICL

LOGICL

CLKFIFO

LOGICL

CLKFIFO

LOGICL

LOGICL

CLKFIFO

LOGICL

CLKFIFO

CLKFIFO

LOGICL

LOGICL

CLKFIFO

LOGICL

LOGICL

CLKFIFO

LOGICL

CLKFIFO

CLKFIFO

LOGICL

LOGICL

LOGICL

CLKFIFO

CLKFIFO

LOGICL

FFIN1

FFIN2

FFIN3

FFIN4

FFIN5

FFIN6

FFIN7

FFIN8

FFIN9

FFIN11

FFIN12

FFIN13

FFIN14

FFIN15

FFIN16

FFIN17

FFIN18

FFIN19

FFIN20

FFIN22

FFIN23

FFIN24

FFIN25

FFIN26

FFIN27

FFIN28

FFIN29

FFIN30

FFIN31

FFIN32

DTBD1

DTBD2

DTBD3

DTBD4

DTBD5

DTBD6

DTBD7

DTBD8

DTBD9

DTBD11

DTBD12

DTBD13

DTBD14

DTBD16

DTBD17

DTBD18

DTBD19

DTBD20

DTBD22

DTBD23

DTBD24

DTBD25

DTBD26

DTBD27

DTBD28

DTBD29

DTBD30

DTBD31

DTBD33

DTBD34

DTBD35

DTBD36

DTBD37

DTBD38

DTBD39

DTBD40

DTBD41

DTBD42

DTBD43

DTBD44

DTBD46

DTBD48

DTBD49

DTBD50

DTBD51

DTBD52

DTBD54

DTBD55

DTBD56

DTBD57

DTBD58

DTBD59

DTBD60

DTBD62

DTBD63

MONDIN1

MONDIN21

MONDIN5

DTBD69

CLKFIFO

DTBD68FFIN34

LOGICL

CLKFIFO

CLKFIFO

DTBD67

LOGICL

LOGICH

DENABLE

DENABLE

DENABLE

DENABLE

DENABLE

DENABLE

DENABLE

DENABLE

DENABLE

DENABLE

DENABLE

DENABLE

DENABLE

DENABLE

DENABLE

DENABLE

DENABLE

DENABLE

DENABLE

DENABLE

DENABLE

DENABLE

DENABLE

DENABLE

DENABLE

DENABLE

MONDIN13

MONDIN29

RESET

RESET

RESET

RESET

RESET

RESET

RESET

RESET

RESET

RESET

RESET

RESET

RESET

RESET

RESET

RESET

RESET

RESET

RESET

RESET

RESET

RESET

RESET

RESET

RESET

RESET

RESET

RESET

MONDIN15

C

CE

CLR

D Q

FDCE

OR2

C

CE

CLR

D Q

FDCE

OR2

C

CE

CLR

D Q

FDCE

OR2

C

CE

CLR

D Q

FDCE

OR2

C

CE

CLR

D Q

FDCE

OR2

OR2

C

CE

CLR

D Q

FDCE

INV

C

CE

CLR

D Q

FDCE

OR2

C

CE

CLR

D Q

FDCE

OR2

C

CE

CLR

D Q

FDCE

OR2

C

CE

CLR

D Q

FDCE

OR2

C

CE

CLR

D Q

FDCE

OR2

C

CE

CLR

D Q

FDCE

OR2

INVC

CE

CLR

D Q

FDCE

C

CE

CLR

D Q

FDCE

OR2

C

CE

CLR

D Q

FDCE

OR2

C

CE

CLR

D Q

FDCE

OR2

C

CE

CLR

D Q

FDCE

OR2

C

CE

CLR

D Q

FDCE

OR2

C

CE

CLR

D Q

FDCE

OR2

C

CE

CLR

D Q

FDCE

INV

C

CE

CLR

D Q

FDCE

C

CE

CLR

D Q

FDCE

C

CE

CLR

D Q

FDCE

C

CE

CLR

D Q

FDCE

OR2

OR2

OR2

OR2

INV

C

CE

CLR

D Q

FDCE

C

CE

CLR

D Q

FDCE

C

CE

CLR

D Q

FDCE

C

CE

CLR

D Q

FDCE

C

CE

CLR

D Q

FDCE

C

CE

CLR

D Q

FDCE

C

CE

CLR

D Q

FDCE

C

CE

CLR

D Q

FDCE

4

3

2

1

4

3

2

1

DCBA

TITLETHE OHIO STATE UNIVERSITY

PHYSICS DEPARTMENT ELECTRONICS LAB174 WEST 18TH AVE, COLUMBUS OH 43210

PARENT PAGEBY

DATE FILE

.PAGE

PROJECT

OR2

INV

OR2

OR2

OR2

OR2

OR2

OR2

OR2

OR2

OR2

OR2

OR2

C

CE

CLR

D Q

FDCE

C

CE

CLR

D Q

FDCE

C

CE

CLR

D Q

FDCE

OR2

C

CE

CLR

D Q

FDCE

OR2

OR2

C

CE

CLR

D Q

FDCE

C

CE

CLR

D Q

FDCE

OR2

OR2

C

CE

CLR

D Q

FDCE

C

CE

CLR

D Q

FDCE

OR2

CMS CSC Electronics

GU DCCSTXDCC Slink FPGA 2C,2D20A

DDU data status

DDU status, will be stored in the SLINK tail2

3-18-2005_16:03 SLINK 2

IFFSTAT13

IFFSTAT12

IFFSTAT10 DDU5STAT[7:0]

DDU5STAT2

DDU5STAT0

DDU5STAT1

DDU5STAT3

DDU5STAT4

DDU5STAT5

DDU5STAT6

DDU5STAT7DDU2STAT7

DDU2STAT[7:0]

DDU2STAT0

DDU2STAT2

DDU2STAT1

DDU2STAT3

DDU2STAT4

DDU2STAT5

DDU2STAT6

DTBD71

IFFSTAT13

DTBD69

DTBD68

DTBD67

DTBD66

DTBD65

DDU5STAT1

DDU5STAT0

DDU4STAT[7:0]

DDU4STAT0

DDU4STAT2

DDU4STAT1

DDU4STAT3

DDU4STAT4

DDU4STAT5

DDU4STAT6

DDU4STAT7

DTBD71

IFFSTAT12

DTBD69

DTBD68

DTBD67

DTBD66

DTBD65

DDU4STAT0

DDU3STAT[7:0]

DDU3STAT0

DDU3STAT6

DDU3STAT5

DDU3STAT4

DDU3STAT3

DDU3STAT7

DDU3STAT1

DDU3STAT2

DTBD71

IFFSTAT11

DTBD69

DTBD68

DTBD67

DTBD66

DTBD65

DDU3STAT0

DDU2STAT1

DDU2STAT2

DDU2STAT3

DDU2STAT4

DDU2STAT5

DDU2STAT6

DDU2STAT7

DTBD64

DDU2STAT0

DDU1STAT[7:0]

DDU1STAT0

DDU1STAT5

DDU1STAT3

DDU1STAT1

DDU1STAT2

DDU1STAT4

DDU1STAT6

DDU1STAT7

PEREN1

DTBD64

DDU1STAT0

DDU1STAT1

CLKFIFO

HEAD1

DTBD65

DTBD67

HEAD1

CLKFIFO

DDU1STAT3

DDU1STAT2

CLKFIFO

HEAD1

DTBD66

DTBD69

HEAD1

CLKFIFO

DDU1STAT5

DDU1STAT4

CLKFIFO

HEAD1

DTBD68

DTBD71

HEAD1

CLKFIFO

DDU1STAT7

DDU1STAT6

CLKFIFO

HEAD1

IFFSTAT10

PEREN1

PEREN1

PEREN1

PEREN1

PEREN1

PEREN1

PEREN1

CLKFIFO

HEAD1

PEREN2

PEREN2

HEAD1

CLKFIFO

CLKFIFO

HEAD1

PEREN2

PEREN2

HEAD1

CLKFIFO

PEREN2

HEAD1

CLKFIFO

PEREN2

HEAD1

CLKFIFO

PEREN2

HEAD1

CLKFIFO

PEREN2

HEAD1

CLKFIFO

PEREN3

HEAD1

CLKFIFO

DTBD64

CLKFIFO

HEAD1

PEREN3

PEREN3

HEAD1

CLKFIFO

PEREN3

HEAD1

CLKFIFO

PEREN3

HEAD1

CLKFIFO

PEREN3

HEAD1

CLKFIFO

PEREN3

HEAD1

CLKFIFO

PEREN3

HEAD1

CLKFIFO

DDU3STAT1

DDU3STAT2

DDU3STAT3

DDU3STAT4

DDU3STAT5

DDU3STAT6

DDU3STAT7

DTBD64

CLKFIFO

HEAD1

PEREN4

PEREN4

HEAD1

CLKFIFO

CLKFIFO

HEAD1

PEREN4

CLKFIFO

HEAD1

PEREN4

CLKFIFO

HEAD1

PEREN4

CLKFIFO

HEAD1

PEREN4

CLKFIFO

HEAD1

PEREN4

CLKFIFO

HEAD1

PEREN4

DDU4STAT1

DDU4STAT2

DDU4STAT3

DDU4STAT4

DDU4STAT5

DDU4STAT6

DDU4STAT7

PEREN5

HEAD1

CLKFIFO

DTBD64

CLKFIFO

HEAD1

PEREN5

PEREN5

HEAD1

CLKFIFO

PEREN5

HEAD1

CLKFIFO

PEREN5

HEAD1

CLKFIFO

PEREN5

HEAD1

CLKFIFO

PEREN5

HEAD1

CLKFIFO

PEREN5

HEAD1

CLKFIFO

DDU5STAT2

DDU5STAT3

DDU5STAT4

DDU5STAT5

DDU5STAT6

DDU5STAT7

DTBD65

DTBD66

DTBD67

DTBD68

DTBD69

IFFSTAT14

DTBD71

CLKFIFO

HEAD1 IFFSTAT11 IFFSTAT14

BUF

AND4B1

OR3

VC

C

AND4B1

AND4B1

4

3

2

1

4

3

2

1

DCBA

TITLETHE OHIO STATE UNIVERSITY

PHYSICS DEPARTMENT ELECTRONICS LAB174 WEST 18TH AVE, COLUMBUS OH 43210

PARENT PAGEBY

DATE FILE

.PAGE

PROJECT

QD

C

FD

OR2

AND2

AND4B2

AND4B1

AND3

AND3

BUF8

TCCLR

C

CE

Q[15:0]

CEO

CB16CE

BUF

CCLR

CE

Q2

Q3D3

D2

D0

D1 Q1

Q0

FD4CE

C

DQ

FD_1

TCCLR

C

CE

Q[15:0]

CEO

CB16CE

TCCLR

C

CE

Q[15:0]

CEO

CB16CE

CEO

CLRC

CE

Q[7:0]

TC

CB8CE

TCCLR

C

CE

Q[15:0]

CEO

CB16CE

QD

C

FD

TCCLR

C

CE

Q[15:0]

CEO

CB16CE

QD

C

FD

QD

C

FD

C

CE

CLR

D Q

FDCE

TCCLR

C

CE

Q[15:0]

CEO

CB16CE

QD

C

FD

OR2

OR2

QD

C

FD

C

CE

CLR

D Q

FDCE

INV

OR2

QD

C

FDC

CE

CLR

D Q

FDCE

CCLR

D Q

FDCCounting to 3564

CMS CSC Electronics

GU DCCSTXDCC Slink FPGA 2C,2D

Because the input FPGA will make sure every event has data in the FIFO with proper format,

Orbit number, assuming that the BC0 will only last for one CMS clock cycle, and comes every o

Event number counter: This duplication will detect if the L1A buffer ever overflow

BX number, lower 8 bits

DDR fifo bookkeeping, event header information for every events

The Bunch number counter, max out at 3563 (sw4 low) for LHC, and 923 (sw4 high) for SPS beam tes

there is no need to check the data format, the readout can be simplified, but need check FIFO_USE

Sync L1A to CLKFIFO, L1AFF

20B

There are two modes to readout the FIFO data: (the default is mode 1, and it switchs to mode 2 upon VME)Mode one: For normal data taking, this is controlled by L1A, MODE = LOWMode two: This is controlled by fifo not-empty, mainly for calibration, or L1A is not available, MODE = HIGH

New event processing stops at ~PAF, resumes at ~HF, during this time, the current event is finished with remaining data dumped

FAKEBC0

3SLINK11-28-2005_10:40

RESET

CLKFIFO

OFFSTAT3

RADR[15:10]

RADR[15:0]

RADR[9:0]

WADR[15:10]

WADR[15:0]

WADR[9:0]

BC0

CLKCMS

L1AFF

L1A

BRAMWEN

BRAMWFF

CLKCMS

LOGICH

BRAMWEN

CLKFIFO

CLKCMS

EVTSTAT3

EVTSTAT2

EVTSTAT1

EVTSTAT0

EVTSTAT[3:0]

CLKCMS

NEVT[31:24]

NEVT[7:0]

NEVT[31:0]NEVT[23:8]

TERM3563

CLKCMS

TCR

STM

AX

DEL

AY

=1N

S

NORBIT[15:0]

CLKCMS

READSTAT3

READSTAT2

READSTAT1

READSTAT0

READSTAT[3:0]

RESET

READSTAT0READSTAT1

READSTAT2

CLKCMS

TERM923

BXCTERM

BRAMRENBRAMWEN

NORBIT[31:0]NORBIT[31:16]

NORBIT[15:0]

CLKCMS

MA

XD

ELA

Y=1

NS

NORBIT[31:16]

NEVT[23:8]NEVT[7:0]

CLKCMSCLKCMS

L1A

TERM923

BXCOUNT6

BXCOUNT4

BXCOUNT2

BXCOUNT0

BXCOUNT5

BXCOUNT1

BXCOUNT3

BXCOUNT7

BXCOUNT9

BXCOUNT8

CLKCMS

RESET

CLKCMS

CLKCMS

L1ANOL1WEN

DUMPDATA

EVCRST

BRAMWEN READSTAT3

RESET

ORBITRST

TCRSTMAXDELAY=1NS

BXRST

BC0 2NSCLKCMS

NEVT[31:24]

BXCOUNT[11:8]

BXCOUNT2

BXCOUNT0

BXCOUNT1

BXCOUNT5

BXCOUNT6

BXCOUNT7

BXCOUNT[15:0]

BXCOUNT11

BXCOUNT10

BXCOUNT8

BXCOUNT9

BXCOUNT4

BXCOUNT3

BXCOUNT[7:0]

CLKFIFO

LOGICL

LOGICH

HEAD2D56

HEAD2D[59:56]

HEAD2D57

HEAD2D58

HEAD2D59

L1A

CLKFIFO

LOGICH

CLKCMS

BRAMWFF

NOL1WEN

DUMPDATA

L1AFF

FAKEBC0

SLINKSTOP

OFFSTAT2

CLKCMS

RESET

AND2B1

QD

C

FDQ

D

A0

A1

A2

A3

CLK

@INIT="0000"

SRL16

CCLR

D Q

FDCQCE

D

A0

A1

A2

A3

CLK

@INIT="0000"

SRL16EINV INV INV

Q

D

A0

A1

A2

A3

CLK

@INIT="0000"

SRL16INV

Q

D

A0

A1

A2

A3

CLK

@INIT="0000"

SRL16

QD

C

FD

QD

C

FD

Q

D

A0

A1

A2

A3

CLK

@INIT="0000"

SRL16INV

Q

D

A0

A1

A2

A3

CLK

@INIT="0000"

SRL16INVINV

ENA

SSRA

CLKA

WEB

ENB

SSRB

CLKB

ADDRB[9:0]

ADDRA[9:0]

WEA

DIA[15:0]

DOA[15:0]

DIB[15:0]

DOPB[1:0]

DOB[15:0]

DIPB[1:0]

DIPA[1:0]

DOPA[1:0]

RAMB16_S18_S18

CCLR

CE

Q2

Q3D3

D2

D0

D1 Q1

Q0

FD4CE

Q[15:0]D[15:0]

CLR

CE

C

FD16CE

Q[15:0]D[15:0]

CLR

CE

C

FD16CE

Q[15:0]D[15:0]

CLR

CE

C

FD16CE

Q[15:0]D[15:0]

CLR

CE

C

FD16CE

4

3

2

1

4

3

2

1

DCBA

TITLETHE OHIO STATE UNIVERSITY

PHYSICS DEPARTMENT ELECTRONICS LAB174 WEST 18TH AVE, COLUMBUS OH 43210

PARENT PAGEBY

DATE FILE

.PAGE

PROJECT

ENA

SSRA

CLKA

WEB

ENB

SSRB

CLKB

ADDRB[9:0]

ADDRA[9:0]

WEA

DIA[15:0]

DOA[15:0]

DIB[15:0]

DOPB[1:0]

DOB[15:0]

DIPB[1:0]

DIPA[1:0]

DOPA[1:0]

RAMB16_S18_S18

ENA

SSRA

CLKA

WEB

ENB

SSRB

CLKB

ADDRB[9:0]

ADDRA[9:0]

WEA

DIA[15:0]

DOA[15:0]

DIB[15:0]

DOPB[1:0]

DOB[15:0]

DIPB[1:0]

DIPA[1:0]

DOPA[1:0]

RAMB16_S18_S18

ENA

SSRA

CLKA

WEB

ENB

SSRB

CLKB

ADDRB[9:0]

ADDRA[9:0]

WEA

DIA[15:0]

DOA[15:0]

DIB[15:0]

DOPB[1:0]

DOB[15:0]

DIPB[1:0]

DIPA[1:0]

DOPA[1:0]

RAMB16_S18_S18

INV

QCE

D

A0

A1

A2

A3

CLK

@INIT="0000"

SRL16E

CCLR

D Q

FDCQ

D

A0

A1

A2

A3

CLK

@INIT="0000"

SRL16

QD

C

FD AND2B1

BUF

CMS CSC Electronics

GU DCCSTXDCC Slink FPGA 2C,2DDDR fifo bookkeeping, buffer size counter

20C

SLINKACT

4SLINK12-13-2005_12:28

LOGICH

CLKCMS

LEDSRST

CLKCMSCLKCMS

LEDSRST

PSLINKACT

EVTSTAT[3:2]

EVTSTAT[1:0]

EVTSTAT[3:0]

EVTSTAT[3:2] EVTSTAT[1:0]

QO[15:0]

RADR[9:0]

NORBIT[15:0]

WADR[9:0]

READSTAT[1:0]

QO[31:16]

RADR[9:0]

READSTAT[3:2]

NORBIT[31:16]

WADR[9:0]

QE[35:34]QE35

QE34

QE[33:32]

QE[31:16]

QE[15:0]

QE[15:0]

RADR[9:0]

NEVT[15:0]

WADR[9:0]

QE[31:16]

QE[35:34]

RADR[9:0]

NEVT[31:16]

WADR[9:0]

CLKCMS

LOGICL

LOGICH

BXCOUNT[9:8]BXCOUNT[11:10]

WORDO[15:0]

WORDO[31:0]

WORDO[31:16]

QO[15:0]

RESET

CLKFIFO

LOGICH

RESET

CLKFIFO

LOGICH

WORDE[31:16]

WORDE[15:0]

WORDE[35:0]

WORDE32

WORDE33

WORDE34

WORDE35

LOGICH

CLKFIFO

RESET

LOGICH

RESET

RESET

LOGICH

CLKFIFO

CLKFIFO

CLKCMS

CLKFIFOCLKFIFO

LOGICH

LOGICL

LOGICL

BRAMWEN

LOGICL

LOGICL

LOGICH LOGICH

LOGICL

BRAMWEN

LOGICH

LOGICL

LOGICL

BRAMWEN

LOGICL

LOGICH

CLKCMS

CLKFIFO

BRAMWEN

LOGICL

LOGICH

LOGICL

LOGICL

LOGICH

CLKFIFO

CLKCMS

QE32

QE33QE[33:32]

QO[31:16]LOGICH

LOGICH

LOGICH

LOGICH LOGICH

LOGICH

LOGICH

LOGICH LOGICH

LOGICH

LOGICH

LOGICH

LOGICH

LOGICH

LOGICH

LOGICH

LOGICH

LOGICH

LOGICH

LOGICH

LOGICH

LOGICH

LOGICH

LOGICHLOGICH

LOGICH

LOGICH

LOGICHLOGICH

LOGICH

LOGICH

LOGICHPGIGAACT

LEDGRST

LOGICH

CLKCMSCLKCMS

LEDGRST

CLKCMS

GIGAACT

SINKACTLOGICH

AND3B2

AND2

AND2

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

INV

OR10

AND4B2

AND4B2

AND4B2

CEO

CLRC

CE

Q[7:0]

TC

CB8CE4

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

AND2

AND2

AND2

AND2

AND2

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

TCCLR

C

CE

Q[15:0]

CEO

CB16CE

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

4

3

2

1

4

3

2

1

DCBA

TITLETHE OHIO STATE UNIVERSITY

PHYSICS DEPARTMENT ELECTRONICS LAB174 WEST 18TH AVE, COLUMBUS OH 43210

PARENT PAGEBY

DATE FILE

.PAGE

PROJECT

TC

UP

CE

CCLR

L

Q[15:0]D[15:0]

CEO

CB16CLED

CCLR

D Q

FDC

C

CE

CLR

D Q

FDCE

C

CE

CLR

D Q

FDCEC

CLR

D Q

FDCQD

C

FD

BUF

XOR2

OR5

AND4B2

QD

C

FD

AND2

INVQD

C

FD

OR2

BUF

BUF

BUF

BUF

AND4OR2

AND2

AND2B1

$$

$$

xxxx

CMS CSC Electronics

GU DCCSTXDCC Slink FPGA 2C,2D

When BUFEOVFL is true, this is a serious error, the event readout is corruptedWhen BUFNEMPTY is true, there are events in the buffer to be read out.

DDR fifo bookkeeping, buffer size counter

Evt_typ

$$

Hx

FOV

xxxx

Word counter

S-link64 data format

D Sub-detector payloadD ......

63 60 59 56 55 32K BOE_1 Evt_ty LV1_id (24)

31 20 19 8 7 4 3 1 0BX_id (12) Source_id (10+2) FOV Hx $ $

Hx $ $

CRC(16) xxxx Evt_stat(8)Tx $ $Tx $ $

BOE_2

EOE_1 "A"

EOE_2 "B"

Read out the events in MODE 0

Dump the data when the FIFO is not empty and in MODE 1(This case should not happen)

K BOE_2 Orbit number [55:24] (32)

D Sub-detector payloadK EOE_2

20D

CALIB is any of the cal commands from TTC

TTS[3:0]

K EOE_1 xxxx Evt_length(24)

* Evt_ty: 0001 for normal physics trigger, 0010 for calibration trigger

Set to 0000 as USF(3:0) for SLINK_64ext

Dummy IO usage

BOE_1 "5"

Hx

TR

5SLINK5-11-2006_10:57

FIFOUSE[5:1]FIFOUSE5

FIFOUSE4

FIFOUSE3

FIFOUSE2

FIFOUSE1

LOGICH

LOGICH

LOGICL

IFFSTAT00.5NS

IFFSTAT10.5NS

IFFSTAT20.5NS

IFFSTAT30.5NS

IFFSTAT40.5NS

IFFSTAT10

IFFSTAT13

IFFSTAT14

IFFSTAT11

IFFSTAT12

IFFSTAT[14:0]

L1AMODE

L1AMODE

DATASLINKSTOP

DDLYEREN

LOGICH

TAILDAT[7:0]

TAILDAT7

TAILDAT6

TAILDAT5

TAILDAT4

TAILDAT3

TAILDAT2

TAILDAT1

TAILDAT0

FMM3 TAILDAT[63:56]

TAILDAT56

TAILDAT63

TAILDAT62

TAILDAT61

TAILDAT60

TAILDAT59

TAILDAT58

TAILDAT57

HEAD2D[59:56]

HEAD2D[63:56]

HEAD2D60

HEAD2D61

HEAD2D62

HEAD2D63

LOGICH

LOGICL

CLKCMS

DTBD28

DTBD45

DTBD63

BUFNEMPTY

LNEVT[7:0]

HEAD2D[7:0]

HEAD2D7

HEAD2D6

HEAD2D5

HEAD2D4

HEAD2D3

HEAD2D2

HEAD2D1

HEAD2D0

LOGICH

LOGICH

HEADDAT58

HEADDAT59

HEADDAT57

HEADDAT56

HEADDAT63

HEADDAT[63:56]

HEADDAT62

HEADDAT61

HEADDAT60

TAILD2D56

TAILD2D57

TAILD2D58

TAILD2D59

TAILD2D60

TAILD2D61

TAILD2D62

TAILD2D63

TAILD2D[63:56]

HEADDAT[7:0]

HEADDAT7

HEADDAT6

HEADDAT5

HEADDAT4

HEADDAT3

HEADDAT2

HEADDAT1

HEADDAT0

CALIB

FIFOUSE1

LOGICL

LNEVT[23:16]

LNEVT[15:0]

LNEVT[7:0]

LNEVT[23:0]LNEVT[23:8]

LOGICH

LOGICH

FINISH

BUFNEMPTY

RESET

BRAMREN

BRAMWENLOGICL

BUFEOVFL BRAMRENLOGICL

LOGICL

CALIB

LOGICL

LOGICH

LOGICL

LOGICH

LOGICH

LOGICH

LOGICH

LOGICH

LOGICH

LOGICH

LOGICH

LOGICH

LOGICL

LOGICL

LNEVT[23:8]

HEAD1

CLKFIFO

HEAD1

CLKFIFO

LOGICL

LOGICL

LOGICL

LOGICL

DUMPDATALOGICH

BUFNEMPTY

BRAMREN

L1AMODE

LOGICH

CLKCMS

LOGICH

ONLYDATA

NOL1WEN

LOGICH

CLKCMS

L1AMODE

BRAMREN

CLKCMS

CLKCMS

LOGICL

LOGICH

ODATA[71:64]

ODATA68

ODATA69

ODATA70

ODATA71

ODATA[67:64]

LOGICL

LOGICH

LOGICH

LOGICH

LOGICH

LOGICH

LOGICH

LOGICH

FIFOUSE2

FIFOUSE3

FIFOUSE4

FIFOUSE5

DTBD62

DTBD61

DTBD60

DTBD31

DTBD30

DTBD29

DTBD46

DTBD47

DTBD44

DTBD13

DTBD14

DTBD15

DTBD12

CLKCMS

L1AEMPTY

BUFEVT11

BUFEVT10

BUFEVT8

BUFEVT0

BUFEVT7

BUFEVT6

BUFEVT5

BUFEVT4

BUFEVT3

BUFEVT2

BUFEVT1

BUFEVT[15:0]

BUFEVT9

LOGICL

LOGICH

LOGICH

LOGICL

FMM2

FMM1

FMM0

DISCARD

C

CE

CLR

D Q

FDCE

EBUFE8

CCLR

D Q

FDC

EBUFE12

EBUFE12

EBUFE8

EBUFE16

EBUFE5

QD

C

FDQD

C

FD

EBUFE8

CEOCE

TC

Q0

Q1

Q2

Q3

CCLR

CB4CE

4

3

2

1

4

3

2

1

DCBA

TITLETHE OHIO STATE UNIVERSITY

PHYSICS DEPARTMENT ELECTRONICS LAB174 WEST 18TH AVE, COLUMBUS OH 43210

PARENT PAGEBY

DATE FILE

.PAGE

PROJECT

EBUFE16

QD

C

FD

QD

C

FD

EBUFE16

EBUFE8

EBUFE5

EBUFE5

EBUFE8

EBUFE8

EBUFE16

AND3B1

QD

C

FD

EBUFE8

EBUFE8

EBUFE8

EAND2_16

EBUFE8

QDPRE

C

FDP

EBUFE8

CCLR

D Q

FDC

CCLR

D Q

FDC

CCLR

D Q

FDC

EBUFE8

EBUFE8

EBUFE8

EBUFE8

EBUFE8

Q

D

A0

A1

A2

A3

CLK

@INIT="0000"

SRL16

QD

C

FDQD

C

FD

QD

C

FD

CCLR

D Q

FDC

EBUFE8

OR2B1

CCLR

D Q

FDC

EBUFE16

EBUFE16

EBUFE16

EBUFE16

QD

C

FD

OR5

OR4

OR2

AND2B1

QD

C

FD

AND2B1

INV

CCLR

D Q

FDC

OR2

CMS CSC Electronics

GU DCCSTXDCC Slink FPGA 2C,2D

Make up the SLINK64 header and trailer

DDR fifo read and Slink fifo write control

The fifo is written as 71 bit wide

Header One

Data

Trailer

Pre-trailerHeader Two

20E1-26-2006_15:04 SLINK 6

TAIL1

RESET

HEAD1

LOGICH PSLINKACT

TAILDAT[7:0]

SLINKSTOP

BUFNEMPTY

DTBD[47:32]

DTBD[15:0]

DTBD[31:16]

DTBD[63:48]

DISCARD

WORDO[31:0]

WORDO[15:0]

WORDO[31:16]

LNEVT[15:0]DDU4STAT[7:0]

HEAD2D[7:0]

HEADDAT[7:0]

WORDE[35:0]WORDE[23:16]

WORDE[15:0]

WORDE[35:24]

DREN

IFFSTAT10

IFFSTAT[14:0]IFFSTAT14

IFFSTAT13

IFFSTAT12

IFFSTAT11

RESET

ODATA[63:56]

ODATA[55:48]

ODATA[7:0]

ODATA[47:32]

ODATA[31:20]

ODATA[19:8]

ODATA[63:0]

IFFSTAT[14:0]

IFFSTAT[4:0]

IFFSTAT[9:5]

ODATA[47:32]

ODATA[63:48]ODATA[71:0]

ODATA[63:56]

ODATA[71:64]

ODATA[55:48]

ODATA[15:0]

ODATA[31:16]

FRCSTAT[7:0]

CNTEN

RSTALL

CLKFIFO

OFFSTAT[4:0]

OFFSTAT3

OFFSTAT4

OFFSTAT2

OFFSTAT1

OFFSTAT0

HEAD1

ODATA[55:48]RDTIME[7:0]

ODATA[63:56]TAILD2D[63:56]

EVTSUM[7:0]

TAIL1

LOGICH

CLKFIFOCLKFIFO

TAIL2

TAIL1

BUSYTESTBTESTA

CLKCMS

LOGICH

LOGICL

RESET

CLKCMS

HEADDAT[63:56]

DATA

HEAD3

ODATA[63:56]

ODATA[13:9]

ODATA[7:0]

ODATA[18:14]

ODATA[23:19]

ODATA[39:24]

ODATA[55:40]

ODATA[63:0]HEAD2D[63:56]HEAD1

TAIL1

ODATA[23:16]

ODATA[47:40]

ODATA[39:32]

ODATA[31:24]DDU3STAT[7:0]

DDU2STAT[7:0]

DDU1STAT[7:0]

ODATA[31:16]

FINISH

ODATA[15:8]

ODATA[7:0]

HEAD2

OFFSTAT[4:0]

HEAD2

CLKFIFO

OTDATA[31:16]

ODATA[47:32]

ODATA[55:48]LNEVT[23:16]

ODATA[63:56]TAILDAT[63:56]

START

RSTBUSY

CLKCMS

LOGICL

CLKFIFO

MAXCNT

FCNT1

FCNT0

FCNT2

CLKFIFO

LOGICL

CLKCMS

LOGICH

RSTALL

CLKFIFO

OKDATALOGICH

CLKFIFO

SLINKID[11:0]

ODATA[7:0]

ODATA[15:8]

DDU5STAT[7:0]

RSTBUSYRSTBUSY

CLKCMS

TAIL2

DATA

FORCEDONE

MAXCNT

CLKFIFO

TAIL1

TAIL2

HEAD2

HEAD1

DONE

FCNT0

FCNT1

FCNT2

CLKFIFOHEAD3

CLKFIFO

DLYDATEN

BYPASS

RESET

DISCARD

RESET

SFWEN

CLKFIFO

DDLYERENDISCARD

DREN

AND3B3

AND2B1

OR2

OR2

AND4B3

AND2B1

INV

INV

AND2B1

AND2B1

AND2B1

QPRE

D

CE

C

FDPE

QPRE

D

CE

C

FDPE

QPRE

D

CE

C

FDPE

QPRE

D

CE

C

FDPE

LVCMOS25

IBUF

LVCMOS25

IBUF

LVCMOS25

IBUF

LVCMOS25

IBUF

AND4B4

CCLR

D Q

FDC

CCLR

D Q

FDC

CCLR

D Q

FDC

CCLR

D Q

FDC

BUF

INV

OR2

C

CE

CLR

D Q

FDCE

INV

OR2

C

CE

CLR

D Q

FDCE

INV

OR2

C

CE

CLR

D Q

FDCE

INV

OR2

C

CE

CLR

D Q

FDCE

C

CE

CLR

D Q

FDCE

4

3

2

1

4

3

2

1

DCBA

TITLETHE OHIO STATE UNIVERSITY

PHYSICS DEPARTMENT ELECTRONICS LAB174 WEST 18TH AVE, COLUMBUS OH 43210

PARENT PAGEBY

DATE FILE

.PAGE

PROJECT

S0

DA[15:0]

DB[15:0]O[15:0]

M2_1_16

C

CE

D[15:0]Q[15:0]

PRE

FD16PE

QD

C

FD

CRC[15:0]DIN[63:0]

FB[15:0]

CRC16

OR2

INV

CCLR

D Q

FDC

OR2

LVCMOS25

IBUF

LVCMOS25

IBUF

LVCMOS25

IBUF

OR4

LVCMOS25

IBUF

AND4B2

AND4B2

AND4B2

AND4B2

AND4B2

QPRE

D

CE

C

FDPE

AND2B1

AND2B1

AND2B1

OR5

OR2B1

CCLR

D Q

FDC

C

QD

CLR

FDC_1

AND2B1

AND2B1

AND2B1

AND2B1

CMS CSC Electronics

GU DCCSTXDCC Slink FPGA 2C,2D

P23

Slink fifo write data and USB CRC-16

FRCSTAT3 is set high, required by not_last_trailer

20F

Slink_FIFO_Full

Slink_FIFO_PAF

Slink_FIFO_HF

FRCSTAT[7:0]

FRCSTAT0

FRCSTAT5

FRCSTAT3

FRCSTAT2

FRCSTAT4

FRCSTAT6

FRCSTAT7

FRCSTAT1

FIFOUSE5

7SLINK1-31-2006_15:09

FMM[3:0]

FMM3

FMM0

FMM1

FMM2

SLFULL

OFFSTAT2

LOGICH

RESET

IFFSTAT14

0.3NS

0.3NSIFEMPTY1

IFFSTAT0

IFFSTAT1

IFFSTAT2

IFFSTAT3

IFFSTAT4

CLK2X

CLKEN

CLKEN

CLKEN

CLKEN

CLKEN

KSFIFOOFFIN64

OFFIN[71:64]OFFIN71

OFFIN70

OFFIN69

OFFIN68

OFFIN67

OFFIN66

OFFIN65

REN1

IFFSTAT0

LAST

DONERESET

SPECSTOP1

CLK2X

STOPHASE1

FRCSTAT4

FRCSTAT2

LOGICH

HEAD1

CDATA[63:56]

CDATA[47:32]

CDATA[55:48]

CDATA[63:0]CDATA[15:0]

CDATA[31:16]

FBCRC[15:0]

DTAIL1

CTDATA[31:16]

TAIL1

CRC[15:0]

CDATA[31:16]

CLKFIFO

START

DLYDATEN

CLKFIFO

CRC[15:0]

FORCEDONE

CLKFIFO

OEF1

OEF2

CLKFIFO

HEAD1

FORCEDONE

OEF3

FRCSTAT5

CLKFIFO

HEAD1

FORCEDONE

OEF4

FRCSTAT6

CLKFIFO

HEAD1

FORCEDONE

OEF5

FRCSTAT7

CLKFIFO

HEAD1

FORCEDONE

DCLKEN

DCLKEN STOPHASE2

DCLKEN STOPHASE3

DCLKEN STOPHASE4

DCLKEN STOPHASE5

CLK2X

SPECSTOP2

CLK2X

SPECSTOP3

CLK2X

SPECSTOP4

DONE

RESET

CLK2X

SPECSTOP5

DONERESET

DONERESET

DONERESET

DONERESET

DONERESET

DONERESET

DONERESET

DONERESET

DONERESET

LAST

LAST

LAST

LAST

IFFSTAT1

IFFSTAT2

IFFSTAT3

IFFSTAT4

REN2

REN3

REN4

REN5

CLK2X

CLK2X

CLK2X

CLK2X

IFEMPTY2

IFEMPTY3

IFEMPTY4

IFEMPTY5

0.3NS

0.3NS

0.3NS

IFFSTAT10

IFFSTAT11

IFFSTAT12

IFFSTAT13

RESET

FMMBUSY

LOGICH

FMMOSYN

FMMWARN

INFIFOFULL

FMMERR

FMMOSYN

FMMERR

FMMERR

FMMERR

FMMERR

FMMOSYN

FMMOSYN

FMMOSYN

FMMWARN

FMMBUSY

FMMBUSY

FMMBUSY

FMMWARN

INFIFOFULL

OFFSTAT4

OFFSTAT3

FIFOUSE4

FIFOUSE3

FIFOUSE2

FIFOUSE1

OR2B1

XNOR2

XNOR2

XNOR2

INV

INV

INV

INV

INV

QPRE

D

CE

C

FDPE

QPRE

D

CE

C

FDPE

QPRE

D

CE

C

FDPE

QPRE

D

CE

C

FDPE

QPRE

D

CE

C

FDPE

QPRE

D

CE

C

FDPE

C

CE

CLR

D Q

FDCE

QPRE

D

CE

C

FDPE

QPRE

D

CE

C

FDPE

C

CE

CLR

D Q

FDCE

4

3

2

1

4

3

2

1

DCBA

TITLETHE OHIO STATE UNIVERSITY

PHYSICS DEPARTMENT ELECTRONICS LAB174 WEST 18TH AVE, COLUMBUS OH 43210

PARENT PAGEBY

DATE FILE

.PAGE

PROJECT

C

CE

CLR

D Q

FDCEQ

PRED

CE

C

FDPE

QPRE

D

CE

C

FDPE

AND2B1

AND2B1

AND2B1

AND2B1

AND2B1

C

CE

CLR

D Q

FDCE

LVCMOS25 12

OBUF

LVCMOS25 12

OBUF

LVCMOS25 12

OBUF

LVCMOS25 12

OBUF

LVCMOS25 12

OBUF

C

D Q

FD_1

AND3B1

OR5

QD

C

FD

C

D Q

FD_1

C

CE

D Q

FDE

C

CE

CLR

D Q

FDCE

XNOR2

XNOR2

OR2B1

QDPRE

C

FDP

OR2B1

QDPRE

C

FDP

OR2B1

OR2B1

QDPRE

C

FDP

QDPRE

C

FDP

OR2

AND3B2

QD

C

FD

OR3B1

QD

C

FD AND3B2

QDPRE

C

FDP

OR3B1

OR3B1

QD

C

FD AND3B2

OR3B1

QD

C

FD AND3B2

OR3B1

QD

C

FD AND3B2

OR2

QD

C

FD

CMS CSC Electronics

GU DCCSTXDCC Slink FPGA 2C,2DDDR fifo read control

20G1-31-2006_13:32 SLINK 8

IFEMPTY3

0.5NS

0.5NS

0.5NS0.5NS

RST_DONE

RST_DONE

IOB=TRUE

IOB=TRUE

RST_DONE

IOB=TRUE

IFFSTAT1

RST_DONE

RST_DONE

IOB=TRUE

IOB=TRUE IFEMPTY1

RST_DONE

IFEMPTY5

IFEMPTY2

REN1

DENABLE

DAV

FAST

FAST

FAST

FAST

FAST

DREN5

DREN4

RENOUT3

RENOUT4

RENOUT5

RENOUT5

RENOUT4

RENOUT3

RENOUT2

RENOUT1

RENOUT[5:1]

SPECSTOP3

STOPHASE3

REN1

IFFSTAT0

IFFSTAT4

IFFSTAT4

IFFSTAT3

IFFSTAT2 IOB=TRUE

CLK2X

IOB=TRUE

CLK2X

SPECSTOP5

CLKFIFO

SPECSTOP5

CLK2X

STOPHASE5

CLKEN

OEF5

CLK2X

CLK2X

IOB=TRUE

CLK2X

CLK2X

OEF4

CLKEN

STOPHASE4

CLK2X

SPECSTOP4

CLKFIFO

SPECSTOP4

CLK2X

CLK2X

CLKFIFOCLKEN

OEF3

CLK2X

CLK2X

IOB=TRUE

IOB=TRUE

IFFSTAT3

IFFSTAT1

IFFSTAT2

IFFSTAT3

IFFSTAT4

REN2

REN3

REN4

REN5

CLKFIFO

DONE

DREN

CLKFIFO

LAST

CLKFIFO CLKFIFO

REALLAST

DENABLE

DAV

DENABLE

DLAST

DLAST

DLAST

DREN2

DREN1

IFFSTAT0

CLK2X

CLK2X

STOPHASE1

SPECSTOP1

SPECSTOP1

CLK2X

CLK2X

SPECSTOP2

SPECSTOP2

CLK2X

STOPHASE2

CLKEN CLK2X

CLK2X

IFFSTAT1

RENOUT1

RENOUT2

CLK2X

DLAST

REN2

REN3

REN4

REN5

CLKFIFO

OEF1

CLKEN

IFFSTAT0

DREN3

SPECSTOP3

DLAST

IFFSTAT2

CLK2X

RESET

DONE

OEF2

CLKFIFO

0.5NS 0.5NS

0.5NS 0.5NS

0.5NS

0.5NS

IFEMPTY4

OR3

C

QD

CLR

FDC_1

INV

CCLR

D Q

FDC

QD

C

FD

QD

C

FD

QD

C

FD

QD

C

FD

QD

C

FD

QD

C

FD

AND3B1

AND3B1

AND3B1

AND3B1

QD

C

OFD_1

QD

C

OFD_1

QD

C

OFD_1

QD

C

OFD_1

BUF

BUF

BUF

BUF

BUF

BUF

NAND4B2

NAND4B2

NAND4B2

NAND4B1

4

3

2

1

4

3

2

1

DCBA

TITLETHE OHIO STATE UNIVERSITY

PHYSICS DEPARTMENT ELECTRONICS LAB174 WEST 18TH AVE, COLUMBUS OH 43210

PARENT PAGEBY

DATE FILE

.PAGE

PROJECT

OR5

AND4B3

AND4B3

AND4B2

AND4B3

AND4B2

BUF

BUF

TCCLR

C

CE

Q[15:0]

CEO

CB16CE

QD

C

FD

LVCMOS25

IBUF BUF

QD

C

OFD_1

AND3B1

NAND4B1

AND2

D

C

Q

CLR

CE

FDCE_1

AND2B1

CCLR

D Q

FDC

OR2

QD

C

FD

CMS CSC Electronics

GU DCCSTXDCC Slink FPGA 2C,2DDDR fifo read control

20H

Timeout on waiting

9SLINK1-31-2006_13:27

CLKENDCLKEN

DLASTMAXDELAY=0.5NS

DDONE

DREN

SLINKSTOP

BUSY

IOB=TRUE

DONE

CLKFIFO

REN1

IFFSTAT0

DLAST

DLAST

DLAST

DLAST

DLAST

DREN

CLKFIFO

LAST

USELOWSKEWLINESMAXDELAY=1NS

DLAST

TIMEOUT[15:0]

TIMEOUT12

CLKFIFO

INFOEN[5:1]

INFOEN1

INFOEN2

INFOEN3

INFOEN4

INFOEN5

FORCEDONE

EVTSUM0

EVTSUM1

EVTSUM2

EVTSUM3

EVTSUM[7:0]

EVTSUM4

EVTSUM7

EVTSUM6

EVTSUM5SLINKSTOP

FIFOUSE1

FIFOUSE2

FIFOUSE[5:1]

FIFOUSE5

FIFOUSE4

FIFOUSE3

BYPASS

FIFOUSE5

FIFOUSE4

FIFOUSE3

FIFOUSE2

FIFOUSE1

OEF1

OEF3

OEF2

OEF4

OEF5

FCNT0

FCNT1

FCNT0

FCNT2

FCNT1

FCNT2

FCNT1

FCNT0

FCNT1

FCNT0

FCNT2

FCNT2

FIFOUSE3

FIFOUSE2

FIFOUSE1

FCNT2

FCNT2

FCNT0

FCNT1

FCNT0

FCNT1

FCNT2

FCNT1

FCNT2

FCNT0

FCNT1

FCNT0

FIFOUSE4

FCNT0

FCNT1

FCNT2

FIFOUSE5

FCNT2

FCNT1

FCNT0

EVTSTAT2

EVTSTAT0

CLKFIFOFORCEDONE

DTBD71FFIN35

CLKFIFO

CLKFIFO

CLKFIFO

CLKFIFO

DONEL1

DONEL2

DONEL3

DONEL4

DONEL5

IFFSTAT1

IFFSTAT2

IFFSTAT3

IFFSTAT4

REN2

REN3

REN4

REN5

DREN5

DREN4

DREN3

DREN2

DREN1REN1

CLK2X

CLK2X

CLK2X

CLK2X

CLK2X

REN2

REN3

REN4

REN5

CLK2X

CLKFIFO

MAXDELAY=0.3NS CLKENRST

CLKFIFO

LOGICH

CLK2X

DENABLE

DDONE

CLKFIFO

RESET

RESET

RESET

INV

C1

D1

CLR

PREQD0

CE

C0

FDDRCPE

PULL

UP

INV

OR4

D0

D1O

S0

M2_1

D0

D1O

S0

M2_1

NAND3

LVCMOS25 SLOW 12

OBUF

LVCMOS25 SLOW 12

OBUF

BUF

BUF

OR2

LVCMOS25

IBUF

LVCMOS25

IBUF

LVCMOS25

IBUF

LVCMOS25

IBUF

4

3

2

1

4

3

2

1

DCBA

TITLETHE OHIO STATE UNIVERSITY

PHYSICS DEPARTMENT ELECTRONICS LAB174 WEST 18TH AVE, COLUMBUS OH 43210

PARENT PAGEBY

DATE FILE

.PAGE

PROJECT

LVCMOS25

IBUF OR2

NOR4

LVCMOS25

IBUF

OR4

OR2

LVCMOS25

IBUF

OR2

OR4

LVCMOS25

IBUF

BUF

TCCLR

C

CE

Q[15:0]

CEO

CB16CE

D0

D1O

S0

M2_1

D0

D1O

S0

M2_1

D0

D1O

S0

M2_1

D0

D1O

S0

M2_1

D0

D1O

S0

M2_1

CCLR

CE

Q2

Q3D3

D2

D0

D1 Q1

Q0

FD4CE

CCLR

CE

Q2

Q3D3

D2

D0

D1 Q1

Q0

FD4CE

INV

INV

BUF

INV

LVCMOS25 SLOW 12

OBUF

PULL

UP

C1

D1

CLR

PREQD0

CE

C0

FDDRCPE

LVCMOS25 12

OBUF

LVCMOS25 SLOW

OBUF

LVCMOS25

T

I

O

IO

SLOW

IOBUF

C

QD

CLR

FDC_1

INV

CCLR

D Q

FDC

C

D Q

FD_1AND2B1

AND2B1 OR3

OR2

QDPRE

C

FDP

CMS CSC Electronics

GU DCCSTXDCC Slink FPGA 2C,2DSLINK Control and Slink fifo readout control

ERCLK

~EREN

DTBD64: (11) CFEB dataDTBD65: (01) ALCT dataDTBD66: (10) TMB data

SLINK control bit

Data transfer error

DTBD67: (00) DMB data

Data source coding

SLINK_~FIFOREN

WCLK

~WEN

RCLK

~REN

By using same phase for FIFO read clock and SLINK write clock,The fifo data will come 0.6 to 3.6ns later than the clock,The SLINK will see a minimum of 6.4ns setup time, and 0.6ns of hold time

dummy usage of IOB

Slink Reset*

By swapping D0, D1 input, the output clock will be 180 degree shifted

Time used to transfer this event

SLINK_FIFORCLK

SLINK_FIFOWCLK

It was CLKSLINK

20I

SLINK_UCLK

IOB=TRUESLDOWNI

SLFULLI

SLFULL

IGNSLFLDN

IGNSLFULL

SLDOWN

IGNSLINK0

IGNSLINK1

IGNSLINK[1:0]

10SLINK1-4-2007_14:10

IOB=TRUEMRFIFO

MRFIFO

CLKFIFO

6

6

FAST

CLKSLINK

CLKFIFO

CLKGIGA

MAXDELAY=0.5NS

CLKSLINK

LOGICL

RDTIME[7:0]

RDTIME1

RDTIME2

RDTIME3

RDTIME4

RDTIME5

RDTIME6

RDTIME7

RDTIME0

LOGICL

CLKFIFO

SELHIGH

RTIME5

RTIME6

RTIME7

RTIME8

RTIME9

RTIME10

RTIME11

RTIME12

RTIME13

RTIME14

RTIME15

RTIME0

RTIME1

RTIME2

RTIME3

RTIME4

RTIME[15:0]

RTIME11

SELHIGH

START

DTBD35

DTBD10

DTBD8

DTBD6

DTBD4

DTBD2

DTBD[71:0]

DTBD39

DTBD47

DTBD48

DTBD49

DTBD50

DTBD51

DTBD52

DTBD53

DTBD54

DTBD55

DTBD56

DTBD57

DTBD58

DTBD59

DTBD60

DTBD61

DTBD62

DTBD63

DTBD65

DTBD70

DTBD71

DTBD69

DTBD68

DTBD67

DTBD66

DTBD64

DTBD46

DTBD45

DTBD44

DTBD43

DTBD42

DTBD41

DTBD40

DTBD38

DTBD37

DTBD36DTBD0

DTBD1DTBD[15:0]

DTBD3DTBD[31:16]

DTBD5DTBD[47:32]

DTBD7DTBD[63:48]

DTBD9DTBD[70:64]

DTBD11

DTBD12

DTBD13

DTBD14

DTBD15

DTBD16

DTBD17

DTBD18

DTBD19

DTBD20

DTBD21

DTBD22

DTBD23

DTBD24

DTBD25

DTBD26

DTBD27

DTBD28

DTBD29

DTBD30

DTBD31

DTBD32

DTBD33

DTBD34

OFFSTAT[4:0]

OFFSTAT1

OFFSTAT0

FFCTRL3

CLKGIGA

KSLINK

SLCTRL0

SLCTRL2

SLCTRL3

SLCTRL[3:0]

SLCTRL1

ODATA[63:56]

ODATA59

ODATA58

CDATA58

CDATA[63:56]

CDATA59

NDTBD64

NDTBD66

NDTBD65

NDTBD[67:64]

NDTBD67

SLDOWN

SLFULL

OFEMPTYRESET

ODATA[71:64]

ODATA67

ODATA66

ODATA65

ODATA64NDTBD64

DTBD68

DTBD67

DTBD66

DTBD66

DTBD65

DTBD64

FFCTRL[5:0]

FFCTRL5

FFCTRL0

FFCTRL1

FFCTRL2

FFCTRL3

FFCTRL4

DTBD64

DTBD64

DTBD65

DTBD69

DTBD70

NDTBD67

NDTBD65

NDTBD66

LOGICH

TAIL2

HEAD1

HEAD2

TAIL1

FFCTRL4 ERCLK

LOGICL

LOGICL

LOGICH

LOGICH

LOGICL LOGICH

LOGICH

LOGICL

LOGICL

LOGICL

RESET

CLKGIGA

FFCTRL2

LOGICH

RTIME15

RTIME14

RTIME13

RTIME12

RTIME10

RTIME9

RTIME11

RTIME10

RTIME9

RTIME8

RTIME7

RTIME6

RTIME5

LOGICH

LOGICL

LOGICH

CLKFIFO

FFCTRL0

LPBKCLK

SSTAT5

SSTAT[5:0]

SSTAT4

SSTAT3

SSTAT2

SSTAT1

SSTAT0

SLCTRL3

CLKGIGA

CLKFIFO

LOGICH

CLK2X

IGNSLINK0

IGNSLINK1

IGNSLFLDNSLDOWNI

IGNSLFULL

IGNSLFLDN

SLFULLI

C

CE

CLR

D Q

FDCEQD

C

FDINV

Q

D

A0

A1

A2

A3

CLK

@INIT="0000"

SRL16INVINV

Q

D

A0

A1

A2

A3

CLK

@INIT="0000"

SRL16

QCE

D

A0

A1

A2

A3

CLK

@INIT="0000"

SRL16E

QD

C

FD

CLKDATA

CLKGIGA

CLKREF

DATAEN

DATAIN[71:0]

DATAWEN

GIGAMON[15:0]

GIGAOK

RESET

RXN

RXP

TXN

TXP

TXRESET

GIGAPATH

BUF

BUF

BUF

BUF

BUF

BUF

BUF

AND2

BUF8

BUF8

BUF8

BUF8

BUF8

BUF8

BUF8

BUF8

4

3

2

1

4

3

2

1

DCBA

TITLETHE OHIO STATE UNIVERSITY

PHYSICS DEPARTMENT ELECTRONICS LAB174 WEST 18TH AVE, COLUMBUS OH 43210

PARENT PAGEBY

DATE FILE

.PAGE

PROJECT

EBUFE16

AND2B2

AND2B1

AND2B1

BUF8

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

Q

D

A0

A1

A2

A3

CLK

@INIT="0000"

SRL16INV

Q

D

A0

A1

A2

A3

CLK

@INIT="0000"

SRL16AND2B1

QD

C

FD

OR2B1

INV

INVC

CLR

D Q

FDC

CMS CSC Electronics

GU DCCSTXDCC Slink FPGA 2C,2DGigabit Ethernet spying data path

P25

Reserved for external use

This will enable the trigger all the times

20J

Spy path for data

1-31-2006_13:27 SLINK 11

LOGICH

SLFULL

CLKCMS

SL_LEDSLDOWN

LEDRST

CLKCMS

LOGICL

LOGICH

LOGICH

LOGICH

PGIGAACT

TXN

CLKEN

DTBD15

MONDIN15

DONE

DLAST

SLINKSTOP

OFFSTAT2

OEF1

DREN

DENABLE

DTBD47

BUSY

REN1

CLKGIGA

GIGAEN

STOPHASE1

GIGAMON0

GIGAMON15

GIGAMON9

GIGAMON8

GIGAMON7

GIGAMON[15:0]

GIGAMON1

GIGAMON2

GIGAMON3

GIGAMON4

GIGAMON5

GIGAMON6

GIGAMON10

GIGAMON11

GIGAMON12

GIGAMON13

GIGAMON14

GIGAMONA[15:0]

SPYD[71:0]

SWB2B3

SW2B3

GIGAMONA[15:0]SWB2B3

CDATA[63:0]CDATA[63:56]

CDATA[7:0]

CDATA[55:48]

CDATA[47:40]

CDATA[39:32]

CDATA[15:8]

SPYD[63:56]SPYD[71:0]

SPYD[23:16]

SPYD[31:24]

SPYD[55:48]

SPYD[47:40]

SPYD[39:32]

SPYD[15:8]

SPYD[7:0]

SPYD[71:64]

DLYDATEN

SW3

SW2

SW[3:1]

SW2

SW3

CDATA[71:64]

CTDATA[31:16]

CTDATA[23:16]

CTDATA[31:24]

RESET

RXN

CLKGIGA

CLKFIFO

CLKREF

TXP

RXP

GIGAOK

SW2

SW3

CDATA[15:0]

CDATA0

CDATA1

CDATA2

CDATA62

CDATA63CDATA[63:56]

CDATA61

SW3

SW2SW23

IFEMPTY1

GIGAEN

DISCARD

GIGATXRST

LOGICH

LOGICH

LOGICH

LOGICH

LOGICH

LOGICH

LOGICH

LOGICH

LOGICH

LOGICH

LOGICH

LOGICH

LOGICH

LOGICL

LOGICH

LOGICHCLKCMS

SLDOWN

CLKCMS

LEDRST

LEDRST

XOR2

CCLR

D Q

FDC

INV

Q[15:0]D[15:0]

CLR

CE

C

FD16CE

Q[15:0]D[15:0]

CLR

CE

C

FD16CE

Q[7:0]D[7:0]

CLR

CE

C

FD8CE

Q[7:0]D[7:0]

CLR

CE

C

FD8CE

Q[7:0]D[7:0]

C

OFD8_S6

Q[7:0]D[7:0]

C

OFD8_S6

C

D[15:0]Q[15:0]

OFD16_S6

Q[7:0]D[7:0]

C

OFD8_S6

C

D[15:0]Q[15:0]

OFD16_S6ENA

SSRA

CLKA

WEB

ENB

SSRB

CLKB

ADDRB[8:0]

ADDRA[8:0]

WEA

DIA[31:0]

DOA[31:0]

DIB[31:0]

DOPB[3:0]

DOB[31:0]

DIPB[3:0]

DOPA[3:0]

DIPA[3:0]

RAMB16_S36_S36

Q[7:0]D[7:0]

CLR

CE

C

FD8CE

Q[7:0]D[7:0]

CLR

CE

C

FD8CE

Q[7:0]D[7:0]

CLR

CE

C

FD8CE

Q[15:0]D[15:0]

CLR

CE

C

FD16CE

Q[15:0]D[15:0]

CLR

CE

C

FD16CE

Q[15:0]D[15:0]

CLR

CE

C

FD16CE4

3

2

1

4

3

2

1

DCBA

TITLETHE OHIO STATE UNIVERSITY

PHYSICS DEPARTMENT ELECTRONICS LAB174 WEST 18TH AVE, COLUMBUS OH 43210

PARENT PAGEBY

DATE FILE

.PAGE

PROJECT

Q[7:0]D[7:0]

CLR

CE

C

FD8CE

Q[15:0]D[15:0]

CLR

CE

C

FD16CE

ENA

SSRA

CLKA

WEB

ENB

SSRB

CLKB

ADDRB[8:0]

ADDRA[8:0]

WEA

DIA[31:0]

DOA[31:0]

DIB[31:0]

DOPB[3:0]

DOB[31:0]

DIPB[3:0]

DOPA[3:0]

DIPA[3:0]

RAMB16_S36_S36OR8

C

D[15:0]Q[15:0]

OFD16_S6

C

CE

CLR

D Q

FDCE

LVCMOS25

T

I

O

IO

SLOW

IOBUF

QDPRE

C

FDP

QD

C

FD

QD

C

FD

INV

INV TCCLR

C

CE CEO

Q[9:0]

CB10CE

INV

OR2

TCCLR

C

CE

Q[15:0]

CEO

CB16CE

TCCLR

C

CE

Q[15:0]

CEO

CB16CE

CEO

D[15:0]Q[15:0]

L

CLRC

CE

UP

TC

CC16CLED

CMS CSC Electronics

GU DCCSTXDCC Slink FPGA 2C,2DGigabit Ethernet spying data path

20K

~FIFOWEN

FFMWAD[8:0]

FFMWAD[15:0]

FFMRAD[15:0]

FFMRAD[8:0]

1-31-2006_13:32 SLINK 12

CLKFIFO

FFMNZ

ODATA10

ODATA[15:0]

CLKFIFO

FFMREN

CLKFIFO

IOB=TRUE

6

FFMREN

CLKFIFO

FFMO[71:0]

FFMO[67:36]

FFMO[71:68]

FFMO[35:32]

FFMO[31:0]

FFMO[71:64]

FFMO[63:56]

FFMO[55:48]

FFMO[47:32]

FFMO[31:16]

FFMO[15:0]

FFOUT[71:64]

FFOUT[55:48]

FFOUT[71:0]

FFOUT[63:56]

FFOUT[15:0]

FFOUT[31:16]

FFOUT[47:32]

FFMREN

FFMWEN

LOGICL

CLKFIFO

RESET

FFMRAD[8:0]

CLKFIFO

FFMWEN

FFMWAD[8:0]

FFMRAD[8:0]

FFMOUT[67:36]

FFMOUT[31:0]

FFMOUT[35:32]

FFMOUT[71:68]FFMOUT[71:0]

LOGICL

LOGICH

FFMWEN

CLKFIFO

CLKFIFO

RESET

FFMOUT[71:0]FFMOUT[71:64]

FFMOUT[31:16]

FFMOUT[15:0]

FFMOUT[63:56]

FFMOUT[55:48]

FFMOUT[47:32]

LOGICH

LOGICL

CLKFIFO

RESET

RESET

CDATA60CDATA61

CDATA62CDATA63

CDATA[63:56]

CDATA[71:64]

CDATA64

CDATA29

CDATA[31:16]

CDATA[47:32]

CDATA45

CDATA[55:48]

CLKFIFO

CLKFIFO

CLKFIFO

CLKFIFO

CTDATA[31:16]

CLKFIFO

LOGICL

LOGICH

CLKFIFO

CLKFIFO

LOGICH

LOGICL

OTDATA[31:16]

ODATA[47:32]

LOGICL

LOGICH

CLKFIFO

ODATA[55:48]

LOGICL

LOGICH

CLKFIFO

CLKFIFO

LOGICH

ODATA[63:56]

ODATA[71:64]

LOGICH

CLKFIFO

CDATA13

CDATA[15:0]

LOGICL

LOGICH

LOGICL

LOGICH

LOGICL

LOGICH

LOGICL

LOGICH

LOGICL

LOGICH

FFCTRL1

LOGICL

LPBKWEN

RESET

SFWEN FFMWEN

LOGICH

LOGICL

LOGICL

CLKFIFO

FFMWAD[8:0]

LOGICL

LOGICH

CLKFIFO

LOGICH

LOGICLRESET

CLKFIFO

CLKFIFO

CLKFIFO

CLKFIFO

CLKFIFO

CLKFIFO

FFMNZ

CLKFIFO

TIMEGATE

FFMCNT8

FFMRENCLKFIFOCLKFIFO

RESET

FFMWENLOGICL

FFMCNT8

FFMCNT6

FFMCNT7

FFMCNT3

FFMCNT4

FFMCNT5

FFMCNT8

FFMCNT[15:0]

FFMCNT1

FFMCNT2

FFMNZ

TIMEGATE

QD

C

FD

CLK COUT[15:0]

ENABLE

LOAD

NLC16

CLK COUT[15:0]

ENABLE

LOAD

NLC16

CLK COUT[15:0]

ENABLE

LOAD

NLC16

CLK COUT[15:0]

ENABLE

LOAD

NLC16

AND3B1

QD

C

FD

AND2

QD

C

FD

AND3B2

AND2

QD

C

FD

AND2

QD

C

FD

AND3B2

AND2

4

3

2

1

4

3

2

1

DCBA

TITLETHE OHIO STATE UNIVERSITY

PHYSICS DEPARTMENT ELECTRONICS LAB174 WEST 18TH AVE, COLUMBUS OH 43210

PARENT PAGEBY

DATE FILE

.PAGE

PROJECT

INV

QD

C

FD

AND2

AND3B2

QD

C

FD

QD

C

FD

QD

C

FD

AND3B1

CLK COUT[15:0]

ENABLE

LOAD

NLC16

Q

D

A0

A1

A2

A3

CLK

@INIT="0000"

SRL16

CLK COUT[15:0]

ENABLE

LOAD

NLC16

QD

C

FD

CCLR

D Q

FDCQD

C

FD

XOR2

CMS CSC Electronics

GU DCCSTXDCC Slink FPGA 2C,2D20L

Data rate counters

P29

STORECOUNT

STORECOUNT

CLKFIFO

STORECOUNT

CLKFIFO

DLYDATEN

CLKFIFO

STORECOUNT

DDUCNT1

DLYFCNT0

CLKFIFO

FCNT0

13SLINK8-15-2006_15:21

LOGICL

RATEMON[95:80]

RATEMON[31:16]

RATEMON[15:0]RATEMON[95:0]

RATEMON[47:32]

RATEMON[63:48]

RATEMON[79:64]

RATEMON[95:80]

RATEMON[79:64]

RATEMON[63:48]

RATEMON[47:32]

RATEMON[31:16]

RATEMON[15:0]

DDUCNT2

DDUCNT2

DREN

STORECOUNT

CLKFIFO

LOGICH

LOGICH

VSLCLK

LOGICL

CLKFIFO

FCNT1

CLKFIFO

FCNT2

DDUCNT1

DREN

DDUCNT3DREN

DDUCNT4DREN

DDUCNT5DREN

DLYFCNT1

DLYFCNT2

CLKFIFO

STORECOUNT

CLKFIFO

STORECOUNT

DDUCNT3

CLKFIFO

DDUCNT4

CLKFIFO

STORECOUNT

DDUCNT5

CLKFIFO

CLKFIFO

CLKFIFO

CLKFIFO

CLKFIFO

CLKFIFOCLKFIFO

D0

D1O

S0

M2_1

D0

D1O

S0

M2_1

D0

D1O

S0

M2_1

D0

D1O

S0

M2_1

D0

D1O

S0

M2_1

D0

D1O

S0

M2_1

D0

D1O

S0

M2_1

D0

D1O

S0

M2_1

D0

D1O

S0

M2_1

D0

D1O

S0

M2_1

D0

D1O

S0

M2_1

D0

D1O

S0

M2_1

D0

D1O

S0

M2_1

D0

D1O

S0

M2_1

ANDOR0

ANDOR0

ANDOR0

ANDOR0

ANDOR0

ANDOR0

ANDOR0

ANDOR0

ANDOR0

ANDOR0

4

3

2

1

4

3

2

1

DCBA

TITLETHE OHIO STATE UNIVERSITY

PHYSICS DEPARTMENT ELECTRONICS LAB174 WEST 18TH AVE, COLUMBUS OH 43210

PARENT PAGEBY

DATE FILE

.PAGE

PROJECT

ANDOR0

ANDOR0

ANDOR0

ANDOR0

ANDOR0

CEOCE

TC

Q0

Q1

Q2

Q3

CCLR

CB4CEANDOR0

ANDOR0

OR2

QD

C

FD

ANDOR0

OR2B1AND2B1

D0

D1O

S0

M2_1D0

D1O

S0

M2_1O

A3

A2

A1

A0

ROM16X1

O

A3

A2

A1

A0

ROM16X1

O

A3

A2

A1

A0

ROM16X1

O

A3

A2

A1

A0

ROM16X1

O

A3

A2

A1

A0

ROM16X1

O

A3

A2

A1

A0

ROM16X1

O

A3

A2

A1

A0

ROM16X1

O

A3

A2

A1

A0

ROM16X1

O

A3

A2

A1

A0

ROM16X1

O

A3

A2

A1

A0

ROM16X1

O

A3

A2

A1

A0

ROM16X1

O

A3

A2

A1

A0

ROM16X1

O

A3

A2

A1

A0

ROM16X1

O

A3

A2

A1

A0

ROM16X1

O

A3

A2

A1

A0

ROM16X1

O

A3

A2

A1

A0

ROM16X1

O

A3

A2

A1

A0

ROM16X1

O

A3

A2

A1

A0

ROM16X1

GU

CMS CSC ElectronicsDCC SLINK Interface FPGAGigabit spying data path, ethernet package assembly DCCSTX

2520H

HEADD2

@INIT="0800"

INIT="0800"

@INIT="F81F"

INIT="F81F"

@INIT="0FF0"

INIT="0FF0"

@INIT="0F00"

INIT="0F00"

@INIT="0FF0"

INIT="0FF0"

@INIT="0300"

INIT="0300"

@INIT="FFFF"

INIT="FFFF"

@INIT="0F00"

INIT="0F00"

@INIT="FFFF"

INIT="FFFF"

@INIT="0F80"

INIT="0F80"

@INIT="0FF0"

INIT="0FF0"

@INIT="0010"

INIT="0010"

@INIT="FFEF"

INIT="FFEF"

@INIT="FF1F"

INIT="FF1F"

@INIT="FFFF"

INIT="FFFF"

@INIT="FF1F"

INIT="FF1F"

@INIT="08F0"

INIT="08F0"

@INIT="FF1F"

INIT="FF1F"

GIGAPATH10-15-2006_4:28 1

PKCNT11

D2CDAT10

D2CDAT[15:0]

D2CDAT0

D2CDAT9

D2CDAT8

D2CDAT11

D2CDAT7

D2CDAT12

D2CDAT13

D2CDAT14

D2CDAT15

D2CDAT1

D2CDAT6

D2CDAT5

D2CDAT4

D2CDAT3

D2CDAT2

PKCNT7

ENPKCNT

ENPKCNT

PKCNT15

ROMENDATAEN

DDDDAT15

DDDDAT[15:0]

DDDDAT0

DDDDAT1

DDDDAT2

DDDDAT3

DDDDAT4

DDDDAT5

DDDDAT6

DDDDAT7

DDDDAT8

DDDDAT9

DDDDAT10

DDDDAT11

DDDDAT12

DDDDAT13

DDDDAT14

D2CDAT0

D2CDAT[15:0]

D2CDAT2

D2CDAT15

D2CDAT14

D2CDAT13

D2CDAT12

D2CDAT11

D2CDAT10

D2CDAT9

D2CDAT8

D2CDAT7

D2CDAT6

D2CDAT5

D2CDAT4

D2CDAT3

D2CDAT1

CMPOUT1

CMPOUT[15:0]

CMPOUT0

CMPOUT2

CMPOUT3

CMPOUT4

CMPOUT5

CMPOUT6

CMPOUT7

CMPOUT8

CMPOUT9

CMPOUT10

CMPOUT11

CMPOUT12

CMPOUT13

CMPOUT14

CMPOUT15

DATAEN

HDTLEN

CLKGIGA

ROMEN

DATAEN

ROMEN

ROMEN

ROMEN

ROMEN

ROMEN

HEADD14

HEADD15

DATAEN

CMPK1

CMPK[1:0]

CMPK0HEADK0

HEADK1

HEADK0

HEADK1

RADD3

RADD2

RADD1

RADD0

RADD0

RADD1

RADD2

RADD3

RADD3

RADD2

RADD1

RADD0

RADD3

RADD2

RADD1

RADD0

RADD3

RADD2

RADD1

RADD0

RADD3

RADD2

RADD1

RADD0

RADD3

RADD2

RADD1

RADD0

RADD3

RADD2

RADD1

RADD0

RADD3

RADD2

RADD1

RADD0

RADD3

RADD2

RADD1

RADD0

RADD3

RADD2

RADD1

RADD0

DATAEN

LOGICL

LOGICL

PHEADD15

PHEADD14

PHEADD13

PHEADD12

PHEADD11

PHEADD10

PHEADD9

PHEADD8

DATAEN

DATAEN

DATAEN

DATAEN

DATAEN

DATAEN

DATAEN

DATAEN

DATAEN

DATAEN

DATAEN

DATAEN

DATAEN

DATAEN

HEADD13

HEADD12

HEADD11

HEADD10

HEADD9

HEADD8

HEADD7

HEADD6

HEADD5

HEADD4

HEADD3

HEADD2

HEADD1

HEADD0

ROMEN

ROMEN

ROMEN

ROMEN

ROMEN

ROMEN

ROMEN

ROMEN

ROMEN

ROMEN

ROMEN

ROMEN

PKGOK

READEN

RESET

FINISH

CLKGIGA

HEADD6

HEADD5

HEADD4

HEADD3

HEADD1

HEADD0PKCNT8

ENPKCNT

PKCNT9

ENPKCNT

PKCNT10

ENPKCNT

ENPKCNT

PKCNT12

ENPKCNT

PKCNT13

ENPKCNT

PKCNT14

ENPKCNT

HEADD7

RADD0

RADD1

RADD2

RADD3

RADD0

RADD1

RADD2

RADD3

RADD0

RADD1

RADD2

RADD3

RADD0

RADD1

RADD2

RADD3

RADD0

RADD1

RADD2

RADD3

RADD0

RADD1

RADD2

RADD3

RADD0

RADD1

RADD2

RADD3

RADD0

RADD1

RADD2

RADD3

PHEADD0

PHEADD7

PHEADD1

PHEADD2

PHEADD3

PHEADD4

PHEADD5

PHEADD6

HEADD15

HEADD8

HEADD9

HEADD10

HEADD11

HEADD12

HEADD13

HEADD14

ENPKCNT

ENPKCNT

ENPKCNT

ENPKCNT

ENPKCNT

ENPKCNT

ENPKCNT

PKCNT6

PKCNT5

PKCNT4

PKCNT3

PKCNT2

PKCNT1

PKCNT0

EMPTYREADEN

RST

WREN

CLKW

CLKR

DOUTX[15:0]

DOUTX[17:16]

DIN[71:0]

FIFO16K

AND3B1

OR3

OR2

CCLR

D Q

FDC

CCLR

D Q

FDC

CCLR

D Q

FDC

QD

C

FD

AINIT

RD_CLK

RD_EN

WR_CLK

WR_EN

FULL

EMPTY

DIN[0:0]DOUT[0:0]

FIFO32

AND3B1

C

CE

CLR

D Q

FDCE

AND3

4

3

2

1

4

3

2

1

DCBA

TITLETHE OHIO STATE UNIVERSITY

PHYSICS DEPARTMENT ELECTRONICS LAB174 WEST 18TH AVE, COLUMBUS OH 43210

PARENT PAGEBY

DATE FILE

.PAGE

PROJECT

C

CE

CLR

D Q

FDCE

TCCLR

C

CE

Q[15:0]

CEO

CB16CE

C

QD

CLR

FDC_1

OR2CCLR

D Q

FDC

OR2

OR2

AND4B2OR2

AND3

TCCLR

C

CE

Q[15:0]

CEO

CB16CE

TCCLR

C

CE

Q[15:0]

CEO

CB16CE

INV

OR2

OR2

AND3

QD

C

FD

Q

D

A0

A1

A2

A3

CLK

@INIT="0000"

SRL16

Q

D

A0

A1

A2

A3

CLK

@INIT="0000"

SRL16

AND4B1

AND3B1

AND4B3

TCCLR

C

CE

Q[15:0]

CEO

CB16CE

AND4B3

AND4B1

CCLR

D Q

FDC

OR2

AND4

QD

C

FD

AND5

Readout logic to Gigabit Ethernet Buffer

CMS CSC ElectronicsDCC SLINK Interface FPGA GUGigabit spying data path, ethernet package control DCCSTX

25A

If the FIFO stay not empty for more than 1ms, dump the data

20H

Extract Header Information(Trailer word of SLINK64 package, Bxxx)

2GIGAPATH2-16-2006_14:04

RADD1

RADD0

PKCNT6PKCNT5PKCNT4PKCNT3PKCNT2PKCNT1PKCNT0

PKCNT15PKCNT[15:0]

PKCNT14PKCNT13PKCNT12PKCNT11PKCNT10PKCNT9PKCNT8PKCNT7

CLKGIGA

RADD3

RADD2

RADD3

READEN

D2CEMPTY

PAUSE

RESTART

PAUSE

CLKGIGA

D2CDAT15

D2CDAT14

D2CDAT13

D2CDAT12

D2CDAT[15:0]

DATAIN60

DATAIN61

DATAIN[71:0]DATAIN63

DATAIN62

COUNT9

COUNT[15:0]COUNT10

D2CEMPTY

CLKGIGA

D2CEMPTY

HEADOUT

HEADIN

RADD2

PAUSE

READEN

READEN

CLKGIGA

LOGICH

RESET

FINISH

RESET

PKGOK

RADD3

RADD0

LOGICH

LOGICH

CLKDATA

HEADIN

CLKGIGA

HEADOUT

CLKGIGA

READEN

D2CDAT15

DATAIN63 HDIN

DATAEN

DATAEN

RESET

CLKDATA

RESET

READEN

HDOUT

HEADIN

RESET

NOEVENT

START

START

CLKGIGA

CLKGIGA

RADD1

RADD2

RADD3

OEHEADHDTLEN

PAUSEFIFOREN

LOGICH OETAIL

LOGICH

LOGICH

LOGICH

PKGOK

CLKGIGA

LOGICH FIFOREN

RESTART

DATAEN

RADD1

CLKGIGA

RADD0

RADD2

READENREADEN

CLKGIGA

RADD3

OEHEAD

START

LOGICH

RESETD2CEMPTY

FIFOREN

GIGAOK

CLKGIGA LOGICH

LOGICH

LOGICH

LOGICH

CLKGIGA

RADD0

RADD2

RADD1ENPKCNT

RADD1

RADD0

RESET

D2CDAT[15:0]

DATAIN[71:0]

D2CDAT[17:16]CLKGIGA

DATAWEN

D2CEMPTYCLKDATA

RESET

FIFOREN

NEVT10

NEVT11

NEVT1

NEVT3

NEVT4

NEVT2

NEVT[15:0]

NEVT9

NEVT8

GN

D

VC

C

INV

C

QD

CLR

FDC_1

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

Q[15:0]D[15:0]

CLR

CE

C

FD16CE

QD

C

FD

NOR2

QD

C

FD

QD

C

FD

OR2

QD

C

FD

4

3

2

1

4

3

2

1

DCBA

TITLETHE OHIO STATE UNIVERSITY

PHYSICS DEPARTMENT ELECTRONICS LAB174 WEST 18TH AVE, COLUMBUS OH 43210

PARENT PAGEBY

DATE FILE

.PAGE

PROJECT

OR5

BUF

BUF

BUF

BUF

Q[7:0]D[7:0]

CLR

CE

C

FD8CE

Q[7:0]D[7:0]

CLR

CE

C

FD8CE

BREFCLK

BREFCLK2

CONFIGENABLE

CONFIGIN

ENMCOMMAALIGN

ENPCOMMAALIGN

LOOPBACK[1:0]

POWERDOWN

REFCLK

REFCLK2

REFCLKSEL

RXN

RXP

RXPOLARITY

RXRESET

RXUSRCLK

RXUSRCLK2

TXBYPASS8B10B[1:0]

TXCHARDISPMODE[1:0]

TXCHARDISPVAL[1:0]

TXCHARISK[1:0]

TXDATA[15:0]

TXFORCECRCERR

TXINHIBIT

TXPOLARITY

TXRESET

TXUSRCLK

TXUSRCLK2

CONFIGOUT

RXBUFSTATUS[1:0]

RXCHARISCOMMA[1:0]

RXCHARISK[1:0]

RXCHECKINGCRC

RXCLKCORCNT[2:0]

RXCOMMADET

RXCRCERR

RXDATA[15:0]

RXDISPERR[1:0]

RXLOSSOFSYNC[1:0]

RXNOTINTABLE[1:0]

RXREALIGN

RXRECCLK

RXRUNDISP[1:0]

TXBUFERR

TXKERR[1:0]

TXN

TXP

TXRUNDISP[1:0]

GT_ETHERNET_2

CCLR

D Q

FDC

QD

C

FD

CCLR

D Q

FDCQD

C

FDQD

C

FD

CMS CSC ElectronicsDCC SLINK Interface FPGA GUGigabit spying data path, RocketIO interface DCCSTX

25B20H

TXRESET

TXRST

CLKGIGA

CLKGIGA

TXRST

3GIGAPATH6-22-2005_12:51

LOGICL

LOGICL

RXDAT[15:0]

BUSL[1:0]

BUSL0

BUSL1

DATAWEN

TXK1

D2CDAT1

GIGAMON[15:0]

GIGAMON0

GIGAMON1

GIGAMON2

GIGAMON3

GIGAMON4

GIGAMON5

GIGAMON6

GIGAMON7

GIGAMON8

GIGAMON9

GIGAMON10

GIGAMON11

GIGAMON12

GIGAMON13

GIGAMON14

GIGAMON15

CMPOUT[15:0]CMPOUT[15:8]

CMPOUT[7:0]

CMPK[1:0]

CMPK1

CMPK0

CLKGIGA

TXDATA[15:0]TXDATA[15:8]

TXDATA[7:0]

TXK1

TXK0

TXK[1:0]

CLKGIGA

CLKGIGA

RXCRCERR

RXNTBL[1:0]

RXNTBL0

RXNTBL1

RXDSPE1RXDSPE[1:0]

RXDSPE0

TXKERR1

TXKERR[1:0]

TXKERR0

RXDATA[15:0]

CLKGIGA

LOGICL

RXDAT[15:0]

LOGICH

RXK0

RXK1

RXK[1:0]

RX_DAV

LOGICL

LOGICL

CLKGIGA

CLKGIGA

LOGICL

LOGICH

RX_ERR

TX_ERR

CLKGIGA

LOGICH

LOGICL

CLKGIGA

D2CEMPTY

FIFOREN

TXDATA[15:0]

TXDATA15

TXDATA14

TXDATA1

TXDATA0

D2CDAT0

DATAIN3

DATAIN[71:0]

DATAIN2

DATAIN1

DATAIN0

MAXDELAY=1NS

CLKMIRRUSELOWSKEWLINES

CLKDATACLKDATA

LOGICH

CLKMIRR

TXP

TXN

TXKERR[1:0]

RXCLK

RXNTBL[1:0]

RXLSYN[1:0]

RXDSPE[1:0]

RXCRCERR

RXK[1:0]

RXBUFSTAT[1:0]

CLKGIGA

LOGICL

LOGICL

LOGICL

TXDATA[15:0]

TXK[1:0]

BUSL[1:0]

BUSL[1:0]

BUSL[1:0]

CLKGIGA

CLKGIGA

RESET

LOGICL

RXP

RXN

LOGICL

CLKREF

CLKREF

BUSL[1:0]

LOGICH

LOGICL

LOGICH

LOGICH

CLKGIGA

AND7B4

AND7B4

AND7B3

AND7B3

INV

VC

C

C

CE

CLR

D Q

FDCE

C

CE

CLR

D Q

FDCE

CCLR

D Q

FDC

QD

C

FD

QD

C

FD

QD

C

FD

4

3

2

1

4

3

2

1

DCBA

TITLETHE OHIO STATE UNIVERSITY

PHYSICS DEPARTMENT ELECTRONICS LAB174 WEST 18TH AVE, COLUMBUS OH 43210

PARENT PAGEBY

DATE FILE

.PAGE

PROJECT

QD

C

FD

AND7B5

VC

C

QD

C

FD

AND2

AND2B1

OR2B1

CEOCE

TC

Q0

Q1

Q2

Q3

CCLR

CB4CE

CEO

CLRC

CE

Q[7:0]

TC

CB8CE

AND5B2

AND4B2

C

CE

CLR

D Q

FDCE

AND2B1

AND2

AND2B1

OR2

AND3

OR4

QD

C

FD

CCLR

D Q

FDC

AND7B5

OR2B2

OR2B1

INV

INV

INV

AND6

NAND2

INV

INV

TCCLR

C

CE

Q[15:0]

CEO

CB16CE

CCLR

D Q

FDC

QD

C

FD VC

CCEOCE

TC

Q0

Q1

Q2

Q3

CCLR

CB4CE

QD

C

FD

CEOCE

TC

Q0

Q1

Q2

Q3

CCLR

CB4CE

QD

C

FD

AND7B5

CALIB lasts for 25ns after CAL commands

Start_trigger code 0x06

GUCMS CSC Electronics

DCCSTXDCC <--> SLINK data interface FPGATTCrx interface

BC0 code 0x01

L1_reset code 0x03

Start_trigger code 0x06

Stop_trigger code 0x07

Hard_reset code 0x04

302A

Orbit Reset code 0x10

Calib_code 0x14, 0x15, 0x16

Hard_reset code 0x34, for DDU only

1-4-2007_11:59 TTC 1

HARD_RSTPC

HARD_RESET

ORBITRST

LOGICH

TIMER10

TIMER[15:0]

CLKCMS

CLKCMS

TTCCMD2

TTCCMD0

TTCCMD1

TTCCMDS

NEWFRAME

INDVDAT

ENTTC

ENDFRAME

CLKCMS

ENDFRAMETTC_SDAT

CLKCMS

DNEWFRAMETTC_SDAT

SENSEOUT

TTCREADYCLKCMS

TTCCMD[5:0]TTCCMD0

TTCCMD5

TTCCMD4

TTCCMD3

TTCCMD2

TTCCMD1

TTCCMDSI

ENTTCC

CLKCMS

TRGSTOP

TRGSTART

TRESET

BC0

CLKCMS

TTCCMDS

TTCCMDS

TTCCMDS

TTCCMD1

TTCCMD0

TTCCMD2

TTCCMD5

TTCCMD4

TTCCMD3

TTCCMD1

TTCCMD2

TTCCMDS

TTCCMD0

TTCCMD3

TTCCMD5

TTCCMD4

TTCCMD1

TTCCMD0

TTCCMD2

TTCCMD3

TTCCMD5

TTCCMD4

CLKCMS

CLKCMS

CLKCMS

TTCDATASI

TTCCMD4

TTCCMD5

TTCCMD3

ENTTCD

ENFPGA

TTCCMDS

TTCCMD2

TTCCMD3

TTCCMD0

TTCCMD5

TTCCMD1

TTCCMDS

TTCCMD4

CLKCMS

NEWFRAME

NEWFRAME

DNEWFRAME

TTC_SDAT

CLKCMS

CLKCMS

ENDFRAME

TTC_SDAT

DATACNT2

DATACNT1

DATACNT0DATACNT[7:0]

DATACNT3

DATACNT4

ENDFRAME

CLKCMS

NEWFRAME

INDVDAT

NEWFRAME

TTCCMDS

TTCCMD1

TTCCMD3

TTCCMD4

TTCCMD[5:0]

TTCCMD5

TTCCMD2

TTCCMD0

CLKCMS

CALIBS

CALIB

CLKCMS

CLKCMS

CLKCMS

CLKCMS

TTCCMDS

TTCCMD2

TTCCMD5

TTCCMD4

TTCCMD1

TTCCMD0

TTCCMD3

XOR10G

XOR13G

XOR4

XOR4

XOR8

XOR8

XOR8

XOR8

XOR8

XOR8

4

3

2

1

4

3

2

1

DCBA

TITLETHE OHIO STATE UNIVERSITY

PHYSICS DEPARTMENT ELECTRONICS LAB174 WEST 18TH AVE, COLUMBUS OH 43210

PARENT PAGEBY

DATE FILE

.PAGE

PROJECT

XOR4

XOR4

XOR4

CMS CSC ElectronicsDCC Slink Interface FPGA GU DCCSTX

23

Shared by crc0, 1, 15, 8

Shared by crc0, 1, 15, 7

Shared by crc0, 1, 15, 6

Shared by crc0, 1, 15, 9

Shared by crc2,3

Shared by crc4,5

Shared by crc0, 1, 15

Shared by crc0, 1, 15

Shared by crc0, 1

Shared by crc3, 4

CRC-16 Primitive Polynomial: X^16+X^15+X^2+1, same as USB standard

SLINK CRC16 Calculation, common components

Shared by crc2, 15

Shared by crc10, 11

Shared by crc12, 13

20E1CRC161-26-2004_16:47

DIN39

INT7

INT11

DIN41

INT9

DIN51

DIN22

DIN7

DIN37

DIN48

DIN48

DIN52

DIN63

DIN62

DIN61

DIN60

DIN59

DIN58

DIN57

DIN56

DIN55

DIN54

DIN53

DIN51

DIN50

DIN49

DIN47

DIN46

DIN45

DIN44

DIN43

DIN42

DIN41

DIN40

DIN39

DIN38

DIN37

DIN36

DIN35

DIN34

DIN33

DIN32

DIN31

DIN30

DIN29

DIN28

DIN27

DIN26

DIN25

DIN24

DIN23

DIN22

DIN21

DIN20

DIN19

DIN18

DIN17

DIN16

DIN13

DIN14

DIN15

DIN[63:0]

DIN12

DIN11

DIN10

DIN9

DIN8

DIN7

DIN6

DIN5

DIN4

DIN3

DIN2

DIN0

DIN1

CRC1

CRC0

CRC2

CRC15CRC[15:0]

CRC14

CRC13

CRC12

CRC11

CRC10

CRC9

CRC8

CRC7

CRC6

CRC5

CRC4

CRC3

FB15

FB1

FB[15:0]

FB14

FB13

FB12

FB10

FB9

FB8

FB7

FB6

FB5

FB2

FB3

FB4

FB11

FB0

DIN63

DIN52

FB0

FB4

INT1

INT2

DIN62

DIN5

DIN47

DIN36

DIN21

DIN6

DIN19

DIN33

DIN32

DIN34

DIN35

DIN46

DIN20

DIN61

INT3

DIN50

DIN49

INT4

DIN53

FB15

DIN38

DIN23

DIN8

FB5

FB1

DIN1

FB9

DIN29

DIN30

DIN31

FB13

DIN61

INT5

DIN57

DIN59

INT6

DIN63

FB15

DIN33

DIN32

DIN31

FB11

DIN3

DIN25

DIN24

DIN26

DIN31

DIN39

DIN18

DIN54

DIN40

DIN16

DIN17

DIN3

DIN12

DIN11

DIN10

DIN4

DIN9

FB13

FB14

FB6

FB3

FB2

DIN2

DIN1

INT10

DIN55

DIN27

DIN13

DIN0

DIN14

DIN60

DIN42

INT12

DIN62

DIN58

DIN2

FB10

DIN38

DIN37

DIN9

INT8

INT13

DIN11

DIN39

DIN40

DIN41

XOR3

XOR4

XOR9

4

3

2

1

4

3

2

1

DCBA

TITLETHE OHIO STATE UNIVERSITY

PHYSICS DEPARTMENT ELECTRONICS LAB174 WEST 18TH AVE, COLUMBUS OH 43210

PARENT PAGEBY

DATE FILE

.PAGE

PROJECT

XOR9

XOR9

XOR7

XOR4

XOR4

XOR3

XOR8G

XOR8G

XOR9G

XOR7

XOR8G

XOR8G

XOR4 XOR9

XOR9

XOR9

XOR9

XOR9

XOR4

XOR13G

CMS CSC ElectronicsDCC Slink Interface FPGA GU DCCSTXSLINK CRC16 Calculation 20C

23A7-15-2004_15:16 CRC16 2

M15

M14

DIN41

DIN57

DIN53

DIN42

DIN38

DIN52

DIN56

DIN40

DIN51

DIN55

INT8

FB6

INT2

INT3

CRC3

FB14

M12

M11

M02

INT3CRC5

INT1

CRC8

CRC7

FB15

FB13

CRC0

INT6

M5

DIN44

INT5

FB8

DIN46

DIN56

DIN56

CRC1

INT1

DIN15

DIN0

DIN30

DIN43

DIN60

DIN45

FB7

FB12

FB7

DIN44

DIN42

DIN28

FB8

DIN14

INT2

INT4

INT7

INT9

INT10

INT10

INT9

INT7

INT4

INT2

INT1

CRC2DIN28

DIN16

INT11

INT12

DIN17

DIN32

DIN47

DIN43

DIN15

INT5

CRC4

INT6

FB0

DIN30

DIN18

DIN16

INT12

DIN48

FB12

DIN49

DIN60

DIN45

DIN34

FB1

DIN4

DIN19

DIN17

CRC6

DIN18

DIN60

DIN5

FB2

DIN4

FB12

FB13

DIN33

FB3

DIN34

DIN61

DIN35

FB14

FB14

DIN36

DIN62

DIN35

DIN20

DIN34

DIN6

CRC9

INT4

DIN21

DIN36

DIN35

DIN37

DIN63

DIN7

DIN24

DIN36

DIN22

DIN8

FB2

CRC10

CRC11

FB7

FB3

DIN10

DIN23

DIN25

CRC12

FB8

FB4

DIN10

DIN24

DIN26

CRC13

FB9

FB5

DIN12

DIN25

DIN27

CRC14

FB10

FB6

DIN12

DIN13

DIN26

DIN42

DIN43

DIN54

DIN58

DIN40

DIN28

INT1

INT2

INT3

INT4

INT7

INT9

INT11

CRC15

FB12

FB12

FB14

M01

INT3

DIN54

DIN50

INT8

INT13

INT13

FB11

DIN15

DIN29

DIN59

DIN45

DIN44

DIN30

TCCLR

C

CE

Q[15:0]

CEO

CB16CE

TCCLR

C

CE

Q[15:0]

CEO

CB16CE

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF BUF

BUF

BUF

BUF

BUF

BUF

BUF

BUF

4

3

2

1

4

3

2

1

DCBA

TITLETHE OHIO STATE UNIVERSITY

PHYSICS DEPARTMENT ELECTRONICS LAB174 WEST 18TH AVE, COLUMBUS OH 43210

PARENT PAGEBY

DATE FILE

.PAGE

PROJECT

AND2B1

BUF

CMS CSC Electronics

GU GU's LibGU's libraryInput data width conversion

101

DIN58

DIN26

DIN10

DIN43

DIN27

DIN11

DIN42

DIN59DIN[71:0]

DINT[35:32]

DINT32

DINT35

DINT34

DINT33

DINT[39:36]DINT39

DINT38

DINT37

DINT36

DINT[59:56]

DINT56

DINT58

DINT59

DINT57

DINT[63:60]

DINT62

DINT61

DINT60

DINT63DIN63

DIN47

DIN31

DIN15

DIN62

DIN46

DIN30

DIN14

DIN[71:0]

2-13-2004_8:29 FIFO16K 1

DOUTX[15:0]

DOUTX[17:16]

DOUTX17DOUTX[17:0]

DOUTX16

DOUTX15

DOUTX14

DOUTX13

DOUTX12

DOUTX11

DOUTX10

DOUTX9

DOUTX8

DOUTX7

DOUTX6

DOUTX5

DOUTX4

DOUTX3

DOUTX2

DOUTX1

DOUTX0

DINT[71:68]DINT71

DINT70

DINT69

DINT68

DINT[55:52]DINT55

DINT54

DINT53

DINT52

DIN12

DIN61DIN[71:0]

DIN28

DIN44

DIN60

DIN13

DIN29

DIN45

DIN[71:0]DIN57

DIN8

DIN24

DIN40

DIN56

DIN9

DIN25

DIN41

DINT[31:28]DINT31

DINT30

DINT29

DINT28

DIN[71:0]DIN55

DIN6

DIN22

DIN38

DIN54

DIN7

DIN23

DIN39

DIN[71:0]DIN51

DIN2

DIN18

DIN34

DIN50

DIN3

DIN19

DIN35

DINT[19:16]

DINT16

DINT19

DINT18

DINT17

DINT[23:20]DINT23

DINT22

DINT21

DINT20

DIN[71:0]DIN53

DIN4

DIN20

DIN36

DIN52

DIN5

DIN21

DIN37

DINT[7:4]DINT7

DINT6

DINT5

DINT4

DINT[3:0]

DINT0

DINT3

DINT2

DINT1

DIN[71:0]DIN49

DIN0

DIN16

DIN32

DIN48

DIN1

DIN17

DIN33DIN71

DIN[71:0]

DIN70

DIN69

DIN68

DIN67

DIN66

DIN65

DIN64

RDEN

RA[15:0]

WA[15:0]

EMPTY1

READEN

WREN

RST

CLKW

RDEN

CLKR

RST

DINT15

DINT14

DINT13

DINT12

DINT[15:12]

DINT9

DINT11

DINT10

DINT8

DINT[11:8] DINT[27:24]DINT27

DINT26

DINT25

DINT24

DINT48

DINT51

DINT50

DINT49

DINT[51:48]

DINT64

DINT67

DINT66

DINT65

DINT[67:64]

DINT41

DINT42

DINT43

DINT40

DINT[43:40]

DINT44

DINT45

DINT46

DINT47 DINT[47:44]

ENA

SSRA

CLKA

WEB

ENB

SSRB

CLKB

ADDRB[11:0]

DIB[3:0]

ADDRA[13:0]

WEA

DIA[0:0]

DOA[0:0]

DOB[3:0]

RAMB16_S1_S4

ENA

SSRA

CLKA

WEB

ENB

SSRB

CLKB

ADDRB[11:0]

DIB[3:0]

ADDRA[13:0]

WEA

DIA[0:0]

DOA[0:0]

DOB[3:0]

RAMB16_S1_S4

ENA

SSRA

CLKA

WEB

ENB

SSRB

CLKB

ADDRB[11:0]

DIB[3:0]

ADDRA[13:0]

WEA

DIA[0:0]

DOA[0:0]

DOB[3:0]

RAMB16_S1_S4

4

3

2

1

4

3

2

1

DCBA

TITLETHE OHIO STATE UNIVERSITY

PHYSICS DEPARTMENT ELECTRONICS LAB174 WEST 18TH AVE, COLUMBUS OH 43210

PARENT PAGEBY

DATE FILE

.PAGE

PROJECT

GN

D

VC

C

ENA

SSRA

CLKA

WEB

ENB

SSRB

CLKB

ADDRB[11:0]

DIB[3:0]

ADDRA[13:0]

WEA

DIA[0:0]

DOA[0:0]

DOB[3:0]

RAMB16_S1_S4

ENA

SSRA

CLKA

WEB

ENB

SSRB

CLKB

ADDRB[11:0]

DIB[3:0]

ADDRA[13:0]

WEA

DIA[0:0]

DOA[0:0]

DOB[3:0]

RAMB16_S1_S4

ENA

SSRA

CLKA

WEB

ENB

SSRB

CLKB

ADDRB[11:0]

DIB[3:0]

ADDRA[13:0]

WEA

DIA[0:0]

DOA[0:0]

DOB[3:0]

RAMB16_S1_S4

ENA

SSRA

CLKA

WEB

ENB

SSRB

CLKB

ADDRB[11:0]

DIB[3:0]

ADDRA[13:0]

WEA

DIA[0:0]

DOA[0:0]

DOB[3:0]

RAMB16_S1_S4

ENA

SSRA

CLKA

WEB

ENB

SSRB

CLKB

ADDRB[11:0]

DIB[3:0]

ADDRA[13:0]

WEA

DIA[0:0]

DOA[0:0]

DOB[3:0]

RAMB16_S1_S4

CMS CSC Electronics

GU GU's LibGU's library16 KB fifo for DCC spying data

101A3-1-2004_10:44 FIFO16K 2

DOUTX6

DOUTX7DOUTX5

DOUTX4DOUTX2

DOUTX3DOUTX1

DOUTX0

DINT[31:28]

DINT28

DINT[27:24]

DINT24

DINT[23:20]

DINT20

DINT[19:16]

DINT[15:12]

DINT[11:8]

DINT8

DINT[7:4]

DINT4

LHIGH

DINT0

DINT[3:0]

WA[11:0]

LHIGH

CLKR

RA[13:0]

RST

LHIGH

CLKW

WREN

RST

LLOW LLOW

RST

WREN

CLKW

RST

RA[13:0]

CLKR

LHIGH

WA[11:0]

DINT16

WA[11:0]

LHIGH

CLKR

RA[13:0]

RST

CLKW

WREN

RST

LLOW

LHIGH

WA[11:0]

LHIGH

CLKR

RA[13:0]

RST

CLKW

WREN

RST

LLOW

LHIGH

LHIGH

LLOW

RST

WREN

CLKW

RST

RA[13:0]

CLKR

LHIGH

WA[11:0]

LHIGH

LLOW

RST

WREN

CLKW

RST

RA[13:0]

CLKR

LHIGH

WA[11:0]

LHIGH

LLOW

RST

WREN

CLKW

RST

RA[13:0]

CLKR

LHIGH

WA[11:0]

WREN

LLOW

RST

RST

LHIGH

LHIGH

DINT12

CLKW

CLKR

WA[11:0]

RA[13:0]

ENA

SSRA

CLKA

WEB

ENB

SSRB

CLKB

ADDRB[11:0]

DIB[3:0]

ADDRA[13:0]

WEA

DIA[0:0]

DOA[0:0]

DOB[3:0]

RAMB16_S1_S4

ENA

SSRA

CLKA

WEB

ENB

SSRB

CLKB

ADDRB[11:0]

DIB[3:0]

ADDRA[13:0]

WEA

DIA[0:0]

DOA[0:0]

DOB[3:0]

RAMB16_S1_S4

ENA

SSRA

CLKA

WEB

ENB

SSRB

CLKB

ADDRB[11:0]

DIB[3:0]

ADDRA[13:0]

WEA

DIA[0:0]

DOA[0:0]

DOB[3:0]

RAMB16_S1_S4

ENA

SSRA

CLKA

WEB

ENB

SSRB

CLKB

ADDRB[11:0]

DIB[3:0]

ADDRA[13:0]

WEA

DIA[0:0]

DOA[0:0]

DOB[3:0]

RAMB16_S1_S4

4

3

2

1

4

3

2

1

DCBA

TITLETHE OHIO STATE UNIVERSITY

PHYSICS DEPARTMENT ELECTRONICS LAB174 WEST 18TH AVE, COLUMBUS OH 43210

PARENT PAGEBY

DATE FILE

.PAGE

PROJECT

ENA

SSRA

CLKA

WEB

ENB

SSRB

CLKB

ADDRB[11:0]

DIB[3:0]

ADDRA[13:0]

WEA

DIA[0:0]

DOA[0:0]

DOB[3:0]

RAMB16_S1_S4

ENA

SSRA

CLKA

WEB

ENB

SSRB

CLKB

ADDRB[11:0]

DIB[3:0]

ADDRA[13:0]

WEA

DIA[0:0]

DOA[0:0]

DOB[3:0]

RAMB16_S1_S4

ENA

SSRA

CLKA

WEB

ENB

SSRB

CLKB

ADDRB[11:0]

DIB[3:0]

ADDRA[13:0]

WEA

DIA[0:0]

DOA[0:0]

DOB[3:0]

RAMB16_S1_S4

ENA

SSRA

CLKA

WEB

ENB

SSRB

CLKB

ADDRB[11:0]

DIB[3:0]

ADDRA[13:0]

WEA

DIA[0:0]

DOA[0:0]

DOB[3:0]

RAMB16_S1_S4

ENA

SSRA

CLKA

WEB

ENB

SSRB

CLKB

ADDRB[11:0]

DIB[3:0]

ADDRA[13:0]

WEA

DIA[0:0]

DOA[0:0]

DOB[3:0]

RAMB16_S1_S4

ENA

SSRA

CLKA

WEB

ENB

SSRB

CLKB

ADDRB[11:0]

DIB[3:0]

ADDRA[13:0]

WEA

DIA[0:0]

DOA[0:0]

DOB[3:0]

RAMB16_S1_S4

CMS CSC Electronics

GU GU's LibGU's library16 KB fifo for DCC spying data

101B3FIFO16K3-1-2004_10:44

WA[11:0]

DINT[43:40]

DOUTX8 DOUTX10

DINT[55:52]

DINT[51:48]

DINT[47:44]DINT[39:36]

DOUTX16

DOUTX15

DOUTX14

DOUTX13

DOUTX12

DOUTX11DOUTX9

LLOW

DINT[67:64]

DINT64

DINT[63:60]

DINT56

DINT52

DINT48

DINT44

DINT40

DINT[35:32]

DINT32

LHIGH

LLOW

RST

WREN

CLKW

RST

RA[13:0]

CLKR

LHIGH

WA[11:0]

LHIGH

CLKR

RA[13:0]

RST

CLKW

WREN

RST

LHIGH

WA[11:0]

LHIGH

CLKR

RA[13:0]

RST

CLKW

WREN

RST

LLOW

LHIGH

LHIGH

LLOW

RST

WREN

CLKW

RST

RA[13:0]

CLKR

LHIGH

WA[11:0]

LHIGH

LLOW

RST

WREN

CLKW

RST

RA[13:0]

CLKR

LHIGH

WA[11:0]

WREN

LLOW

RST

RST

LHIGH

LHIGH

DINT36

CLKW

CLKR

WA[11:0]

RA[13:0]

DINT60

WA[11:0]

LHIGH

CLKR

RA[13:0]

RST

CLKW

WREN

RST

LLOW

LHIGH

LHIGH

LLOW

RST

WREN

CLKW

RST

RA[13:0]

CLKR

LHIGH

WA[11:0]

DINT[59:56]

LHIGH

LLOW

RST

WREN

CLKW

RST

RA[13:0]

CLKR

LHIGH

WA[11:0]

WREN

LLOW

RST

RST

LHIGH

LHIGH

DINT[71:68]

DINT68

CLKW

CLKR

WA[11:0]

RA[13:0]

DOUTX17

C

D Q

FD_1

CCLR

D Q

FDC

QD

C

FD

XNOR2

NOR2

XNOR2

XNOR2

XNOR2

XNOR2

XNOR2

XNOR2

4

3

2

1

4

3

2

1

DCBA

TITLETHE OHIO STATE UNIVERSITY

PHYSICS DEPARTMENT ELECTRONICS LAB174 WEST 18TH AVE, COLUMBUS OH 43210

PARENT PAGEBY

DATE FILE

.PAGE

PROJECT

XNOR2

XNOR2

XNOR2

XNOR2

XNOR2

AND12

QD

C

FD

CCLR

D Q

FDC

INV

C

QD

CLR

FDC_1

OR2

CCLR

D Q

FDCQD

C

FD

CCLR

CE

Q2

Q3D3

D2

D0

D1 Q1

Q0

FD4CE

Q[7:0]D[7:0]

CLR

CE

C

FD8CE

CCLR

CE

Q2

Q3D3

D2

D0

D1 Q1

Q0

FD4CE

Q[7:0]D[7:0]

CLR

CE

C

FD8CE

There maybe side-effect that the CMPWA is not current

CMS CSC Electronics

GU GU's LibGU's library16 KB fifo for DCC spying data

Use the following edge of CLKW for CE, to make sure proper register of WAThere maybe side-effect that the CMPWA is not current

101C

INTMED[11:4]

INTMED3

INTMED2

INTMED1

INTMED0

6-11-2004_13:24 FIFO16K 4

CLKR

CLKR

LOADONR

LOADONR

LOADONW

MAXDELAY=1NS

CLKWCLKUSELOWSKEWLINES

CLKWCLKW

LHIGH

CMPWA[13:2]

CMPWA12

CMPWA11

CMPWA10

CMPWA9

CMPWA8

CMPWA7

CMPWA6

CMPWA5

CMPWA4

CMPWA3

CMPWA2

CMPWA13

EMPTY1 EMPTY

LLOW

CLKR

LLOW

CMPWA[13:6]CMPWA[13:2]

CMPWA2

CMPWA3

CMPWA4

CMPWA5

RA12

RA[15:0]

RA11

RA10

RA9

RA8

RA7

RA6

RA5

RA4

RA3

RA2

RA0

RA1

RA13

LOADONR

LHIGH

CLKW CLKW CLKW

LOADONW

LHIGH

LOADONW

WA3

WA1

WA0

WA2

WA[11:4]WA[15:0]

CLKW

LLOW

LLOW

CLKW

LOADONW

CLKR

QD

C

FD

BUF

S1

S0

O

E

D3

D2

D1

D0M4_1E

S1

S0

O

E

D3

D2

D1

D0M4_1E

S1

S0

O

E

D3

D2

D1

D0M4_1E

S1

S0

O

E

D3

D2

D1

D0M4_1E

S1

S0

O

E

D3

D2

D1

D0M4_1E

S1

S0

O

E

D3

D2

D1

D0M4_1E

S1

S0

O

E

D3

D2

D1

D0M4_1E

S1

S0

O

E

D3

D2

D1

D0M4_1E

OR4

TCCLR

C

CE

Q[15:0]

CEO

CB16CE

TCCLR

C

CE

Q[15:0]

CEO

CB16CE

4

3

2

1

4

3

2

1

DCBA

TITLETHE OHIO STATE UNIVERSITY

PHYSICS DEPARTMENT ELECTRONICS LAB174 WEST 18TH AVE, COLUMBUS OH 43210

PARENT PAGEBY

DATE FILE

.PAGE

PROJECT

OR4

OR5

AND2B1OR2

OR2

S1

S0

O

E

D3

D2

D1

D0M4_1E

S1

S0

O

E

D3

D2

D1

D0M4_1E

S1

S0

O

E

D3

D2

D1

D0M4_1E

S1

S0

O

E

D3

D2

D1

D0M4_1E

S1

S0

O

E

D3

D2

D1

D0M4_1E

S1

S0

O

E

D3

D2

D1

D0M4_1E

Q[15:0]D[15:0]

CLR

CE

C

FD16CE

BUFV

CC

GN

D

QD

C

FD

CMS CSC Electronics

GU DCCSTXDCC Slink FPGA29

Data rate counters 20L

RESET

CLK

LOAD

LOGICL

CLK

LOAD

PREL[15:0]

COUNT[31:16]COUNT[15:0]

1RATECOUNT8-15-2006_15:16

CLK

COUT[15:0]

SEL0

SEL1

PREL4

PREL0

COUNT0

COUNT13

COUNT4

COUNT8

COUNT21

COUNT25 COUNT18

LOGICH

SEL1

SEL0

SEL1

SELA

SELB

SELB

SELC

SELB

SELC

SELASELA

CLK

ENABLE

SEL0

SEL0

SEL1

LOGICH

SEL0

SEL1

LOGICH

SEL0

SEL1

LOGICH

SEL0

SEL1

LOGICH

SEL0

SEL1

LOGICH

SEL0

SEL1

LOGICH LOGICH

SEL1

SEL0

LOGICH

SEL1

SEL0

LOGICH

SEL1

SEL0

LOGICH

SEL1

SEL0

LOGICH

SEL1

SEL0

LOGICH

SEL1

SEL0

SEL0

SEL1

LOGICH

COUNT24

COUNT23

COUNT22

COUNT21

COUNT20

COUNT19

COUNT17

COUNT16

COUNT15

COUNT14

COUNT13

COUNT12

COUNT20

COUNT19

COUNT18

COUNT17

COUNT16

COUNT15

COUNT14

COUNT13

COUNT12

COUNT11

COUNT10

COUNT9

COUNT5

COUNT6

COUNT7

COUNT8

COUNT9

COUNT10

COUNT11

COUNT12

COUNT13

COUNT14

COUNT15

COUNT16

COUNT17

COUNT12

COUNT11

COUNT10

COUNT9

COUNT8

COUNT7

COUNT6

COUNT5

COUNT4

COUNT3

COUNT2

COUNT1

PREL1

PREL2

PREL3

PREL5

PREL6

PREL7

PREL8

PREL9

PREL10

PREL11

PREL12

PREL13

RESETRESET

COUNT1

COUNT2

COUNT3

COUNT4

COUNT5

COUNT6

COUNT7

COUNT8

COUNT9

COUNT10

COUNT11

COUNT12

COUNT13

COUNT25

COUNT24

COUNT23

COUNT22

COUNT21

COUNT20

COUNT19

COUNT18

COUNT17

COUNT16

COUNT15

COUNT14

COUNT0

COUNT26

COUNT[31:16]

COUNT[15:0]COUNT[31:0]

PREL3

PREL4

PREL5

PREL6

PREL7

PREL8

PREL9

PREL10

PREL11

PREL12

PREL13

PREL15

PREL14

PREL0

PREL1

PREL2

PREL[15:0]

CLK

OR2

D0

D1O

S0

M2_1

D0

D1O

S0

M2_1

D0

D1O

S0

M2_1

C

CE

CLR

D Q

FDCE

C

CE

CLR

D Q

FDCE

D0

D1O

S0

M2_1

C

CE

CLR

D Q

FDCE

C

CE

CLR

D Q

FDCE

C

CE

CLR

D Q

FDCED0

D1O

S0

M2_1

D0

D1O

S0

M2_1

C

CE

CLR

D Q

FDCE

C

CE

CLR

D Q

FDCED0

D1O

S0

M2_1

D0

D1O

S0

M2_1

C

CE

CLR

D Q

FDCED0

D1O

S0

M2_1

C

CE

CLR

D Q

FDCE

D0

D1O

S0

M2_1

C

CE

CLR

D Q

FDCE

D0

D1O

S0

M2_1

C

CE

CLR

D Q

FDCE

D0

D1O

S0

M2_1

C

CE

CLR

D Q

FDCE

D0

D1O

S0

M2_1

C

CE

CLR

D Q

FDCE

C

CE

CLR

D Q

FDCED0

D1O

S0

M2_1

D0

D1O

S0

M2_1

C

CE

CLR

D Q

FDCE

C

CE

CLR

D Q

FDCED0

D1O

S0

M2_1

Comments:

Date:

Title:

Ver:

Rev:

C

B

A

1234

A

B

C

Sheet Size: C

13th January 1993

A

Para-Out Shift Reg w/ Enable & Async Clr

Copyright (c) 1993, Xilinx Inc.drawn by KS

virtex2p Family SR16CRE Macro, Right Shift16-Bit Loadable Ser/Para-In, right shift

1, Modified from XILINX, SR16CLE

MQ8

Q8

Q9

MQ9

MQ10

Q10

Q11

MQ11

Q12

MQ12

Q13

MQ13

Q14

MQ14

Q15

MQ15

Q7

MQ7

MQ6

Q6

Q5

MQ5

MQ4

Q4

Q3

Q2

MQ0

Q11

Q10

Q[15:0]

Q8

Q12

Q15 Q7

Q4

Q1

Q0

Q2

Q3

Q5

Q6Q14

Q13

Q9

Q8

MD11

MD10

MD9

CLR

C

MD0

MD1

MD2

MD3

MD8

L_OR_CECE

SLIMD15

MD14

MD12

MD5MD13

L

MD7

MD6

MD4

Q1

Q0

MQ3

MQ2

MQ1

D0

D5

D6

D7

D4

D3

D2

D1D9

D12

D14

D15

D13

D11

D10

D8

D[15:0]

AND2

I1

I2

I3

I4

O

FMAP

Date:

Comments:

Title:

Ver:

Rev:

A

B

4 3 2

4 3 2 1

1

A

B

Sheet Size: A

AND2

OR2

A

115th March 1993

Copyright (c) 1993, Xilinx Inc.drawn by KS

2 to 1 multiplexer with default 0

2 to 1 Multiplexer

O

I0

I1

I2

I3

O

I3

I2

I1

I0

QD

C

FD

CE

D Q

CLR

PRE

C

FDCPE_1

LVCMOS25

IBUF

Date:

Comments:

Title:

Ver:

Rev:

A

B

4 3 2

4 3 2 1

1

A

B

Sheet Size: A

C

CE

D Q

CLR

PRE

FDCPE

IFDDRCPE

August 19, 1999

IOB=TRUE

CLR

C0

CE

MOND

PRE

D

IOB=TRUE Q0PRE_Q0

C0

Q1

Q

G

D

ILD

Q

G

D

ILD

Q

G

D

ILD

Q

G

D

ILD

Sheet Size: A

Date: Ver:

A

B

C

D D

C

B

A

2 1

12

Comments:

Title:

Rev:

Q

G

D

ILD

Q

G

D

ILD

drawn by KSCopyright (c) 1993, Xilinx Inc.

Data Latch

A

125th January 1993

VIRTEX Family ILD4 Macro

4-Bit Input Transparent

Q5

Q4

G

D2

D1

D3

Q1

Q0

Q2

Q3

D0

Q3

Q2

Q1

Q0

Q4D4

Q5D5