A high-resolution time interpolator based on multisampled Delay-Locked Loops

Ecole micro-électronique IN2P3 — Fréjus 2015

CNRS-IN2P3-LPC Caen-ENSICAEN-Université de Caen

L.Leterrier, P.Vallerand* (*now at LAL Orsay)

Contact : leterrier@lpccaen.in2p3.fr

Interpolator performances :

Architecture and principle :

This prototype block is a high-resolution time interpolator, designed by LPC Caen in AMS CMOS 0.35µm technology, to provide a time interval measurement between an incoming clock signal at a typical frequency of 160MHz and an external hit. This interpolator is based on a Delay-Locked Loop and a Delay Line (DL) controlled by a second DLL depending on the first one. After decoding, the bin size obtained corresponds to the clock period divided by 128. At 160MHz, it is about equal to 50ps.

Synoptic of Interpolator block

Layout of Interpolator block (size = 271µm x 710µm)

The delay cell has been designed to have the same propagation time for the rising and falling edge. It is based on the association of two degenerated inverters, only from NMOS side.

Delay cell:

Schema of delay cell

DNL measurement of 32-cell DLL for each register (LSB ≈ 195.3ps) :

clock

Hit

16 bits

M

U

X

fclock = 160 MHz

PD

CP Tcell

Delay Locked Loop - 32 delay cells

Delay Line – 5 delay cells

Delay Locked Loop - 5 delay cells

32 bits

32 bits

32 bits

32 bits

32 bits hit1

hit2

hit3

hit4

Tcell’

Tcell’

Tcell 200 ps

Tcell’ 250 ps

dummy cell

PD

CP

dummy cell

hit register 3

hit register 2

hit register 1

Tcell’

M

U

X

hit register 4

Sliding Scale

delay_0_4

select

16-bit tristate bus

LVDS clock input

LVDS Hit input

195ps

Slope 0.27ps/mV

Delay min 130ps

Dispersion Δr_f 1.5ps

Dela

y

Curve of delay cell (post layout simulation)

Voltage control

Layout of delay cell

Phase Tuning System (PTS) :

2 delay cells between the delay line and the phase detector compensate the sum of all delay cell intrinsic dispersions Δτi impacting the last cell delay. This system is implemented on all DLLs and can be disabled by user. Example of DLL 32 cells (last cell delay T32) : Expression of T32 without phase tuning : Expression of T32 with phase tuning : with τ360 = τ0 – (± Δτcompensation)

Synoptic and functional chronograms

32

1i

iclk_ref

32

1i

iclk_ref

clk_ref32 Δτ32

TΔτ

32

31.TTT

32

TΔτΔτ

32

TT

clk_refoncompensati

32

1i

iclk_ref

32

1,087V

Sliding Scale System (SSS) :

The principle is to encode a same time interval from different instants of the main DLL, in order to smooth the Differential Non-Linearity (DNL) ; it is a statistical correction. In our case, this system is necessary because the 4-cell DLL is very sensitive to the DNL error of the 32-cell DLL, which could result in missing codes in the worst case. The system integrated in the interpolator block allows to encode at two instants spaced about 1ns (a calibration is necessary to determine the distance between these two instants). It is implemented in the 5-cell DL and can be disabled by user.

Principle of decoding to obtain a bin step about 50ps

DNL max (ps) REG1 REG2 REG3 REG4

without TPS 36,9 31,8 30,4 35,3

with TPS 28,5 29,5 29,3 31,2

with TPS + SSS 25,6 23,4 26,0 25,1

DNL measurement after decoding (LSB ≈ 48.9ps) :

with TPS 24,3

with TPS + SSS 16,1

DNL max (ps)

The above graphs show the positive effect of the PT and SS systems on the DNL. The combination of these systems is essential to ensure the functionality of the interpolator. Without the PT and SS systems, there are missing codes after decoding. So, for the next results, these systems are used!

INL and Resolution measurements :

Time (ps)

Cod

e

INLmax < 1.73 LSB (84.6ps)

The INL and conversion error graphs include 1,250,000 measurements generated with a time step of 5ps, accumulating 1,000 measurements per time step.

Characterization of these DNLs was performed using statistical code density tests from 1,000,000 random hits, in order to ensure a measurement accuracy < ±1%.

Resol < 0.51 LSB rms (24.9ps rms)

Characterization of this DNL was performed using statistical code density tests from 1,500,000 random hits, in order to ensure a measurement accuracy < ±1%.

Num

ber

of p

oint

s

Conversion error histogram Time (ps) IN

L (

LS

B)

This time interpolator takes four « pictures » of the main DLL. The time interval between each picture is equal to 5/4 of the propagation time of a delay cell. The main DLL has 32 delay cells running at 160MHz which gives a time step ≈ 195.3ps.

Phase detector

Phase detector

Charge pump

clk360

clk0

The DLLs and 5-cell DL share the same power supply, the rest is supplied via a different path.