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ECS 401 – COMPUTER ORGANIZATIONUNIT - I

© MANISH MAHAJAN

Unit-I Introduction

• Number representation– Fixed and floating point number representation– IEEE standard for floating point

representation. – Error detection and correction codes:

Hamming code. • Digital computer

– Generation– Computer types and classifications, – Functional units and their interconnections– Buses, bus architecture, types of buses and

bus arbitration. • Register, bus and memory transfer.

DIGITALLOGIC

DESIGN

COMPUTERCONCEPTS

& CPROGRAMMING

Unit-II Central Processing Unit

• Arithmetic & Logic Operations– Addition and subtraction of signed numbers,

look ahead carry adders. – Multiplication: Signed operand multiplication,

Booths algorithm and array multiplier. – Division and logic operations. – Floating point arithmetic operation

• Processor organization– General register organization– Stack organization– Addressing modes.

Unit-III Control Unit

• Instructions– Instruction types, formats, – Instruction cycles and subcycles ( fetch and execute

etc),– Micro-operations, execution of a complete instruction.

• Hardwire and microprogrammed control: – Microprogramme sequencing, – Wide branch addressing, – Microinstruction with next address field, pre-fetching

microinstructions, – Concept of horizontal and vertical microprogramming.


© MANISH MAHAJAN

Unit-IV Memory• Memories

– Basic concept and hierarchy, – Semiconductor RAM memories, – 2D & 2 1/2D memory organization. – Rom memories.

• Cache memories: – Concept– Design issues - performance, address mapping and

replacement• Auxiliary memories

– Magnetic disk, magnetic tape and optical disks • Virtual memory

– Concept – Implementation.

Unit-V Input / Output

• Peripheral devices– I/O interface, I/O ports

• Interrupts– Interrupt hardware, types of interrupts and

exceptions. • Modes of data transfer

– Programmed I/O– Interrupt initiated I/O – Direct memory access– I/O channels and processors.

• Serial communication– Synchronous & asynchronous communication– Standard communication interfaces.

Books

1. Mano,” Computer System Architecture”, PHI 2. Vravice,Hamacher & Zaky, “Computer Organization”,

TMH 3. John P Hayes, “ Computer Organization”, McGraw Hill • REFERENCE1. P Pal Chaudhry, ‘ Computer Organization & Design’,

PHI 2. William Stalling, “ Computer Organization”, PHI 3. Patterson, Computer Organisation and Design,

Elsevier Pub. 2009

Why Study CO

• To understand why an algorithm is infeasible, or to understand why the implementation of a feasible algorithm is running too slowly.

• if you want to write compilers, you must understand the hardware environment within which the compiler will function.

• To design peripheral equipment or the software that drives peripheral equipment, you must know every detail of how a particular computer deals with its input/output (I/O)

• To model large, complex, real-world systems


© MANISH MAHAJAN

Computer Organization

• Computer organization addresses issues such as control signals (how the computer is controlled), signaling methods, and memory types.

• It encompasses all physical aspects of computer systems. It helps us to answer the question: How does a computer work?

Computer Architecture

• Structure and behavior of the computer system• Logical aspects of system implementation as seen by

the programmer. • Computer architecture includes many elements such as

instruction sets and formats, operation codes, data types, the number and types of registers, addressing modes, main memory access methods, and various I/O mechanisms.

• The architecture of a system directly affects the logical execution of programs.

• Studying computer architecture helps us to answer the question: How do I design a computer?

Architecture & Organization

• Architecture is those attributes visible to the programmer– Instruction set, number of bits used for data representation, I/O

mechanisms, addressing techniques.

– e.g. Is there a multiply instruction?

• Organization is how features are implemented. – Refers to the operational units and their interconnections that

realize the architectural specifications

– Control signals, interfaces, memory technology.

– e.g. Is there a hardware multiply unit or is it done by repeatedaddition?

• First Generation (1945 - 1955)– Programs and data located in same memory– Assembly language was used to write programs– Vacuum Tube Technology for performing basic

processing – Mercury delay line memory was used– Type writers as I/O devices

History of Computer


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Main Memory

(Programs and data for

execution)

Instruction

Data

Central Processing Unit (CPU)

Program Control

Data Processing

Programs, data, operator

commands

Input-output equipment

Secondary memory,

keyboard, printer etc.

Organization of a first-generation computer

History of Computers

• Second Generation (1955 – 1965)– Transistor replaced vacuum tubes– Magnetic core memories and magnetic

storage devices were more widely used– High level language such as FORTRAN was

developed– Compilers were developed– Separate I/O processors were developed

along with CPU– IBM became major manufacturer

History of Computer

• Third Generation ( 1965-1975)– Many transistors on a single chip (IC) enabled lower cost , faster

processors and memory elements– IC memories replaced magnetic core memories– Introduction of micro-programming , parallelism , pipelining– Effective time sharing in operating system– Development of Cache & Virtual memory

• Fourth Generation (1975-1996)– Still advancement in IC technology (VLSI) that is Very Large Scale

Integration– Microprocessor concept - Motorola, Texas Instruments were the major

companies– Parallelism, Pipelining , Cache , Virtual Memories evolved to produce

high performance – Computing systems of today

History of Computer

A typical computer system

Video Monitor

Secondary Memory

Keyboard

Communication Network

Video Control

Hard Disk

Control

Keyboard Control

Network Control

IO expansion

slots

IO Devices

IO (local) Bus

Peripheral (IO) interface control unit

CPU

Cache

Microprocessor

Main

Memory

System Bus

Bus Interface Unit

A Typical Computer System


© MANISH MAHAJAN

What is “Computer Architecture”

Computer Architecture =

Instruction Set Architecture + Machine Organization

Organization vs. Architecture• Architecture ≅≅≅≅ Specification

– Attributes visible to the programmer

– Attributes:• Instruction set

• Number of bits representing data

• I/O mechanism

• Addressing modes used

– Has direct impact on logical program execution

Organization vs. Architecture

• Organization ≅≅≅≅ Implementation– Operational units and their interconnection that

realizes the architecture

– Attributes:

• HW details

• Control signals

• I/O interfaces

• Memory technology used


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Function

• All computer functions are:– Data processing– Data storage– Data movement– Control

Functional View

Operations (a) Data movement Operations (b) Storage


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Operation (c) Processing from/to storage Operation (d) Processing from storage to I/O

Structure - Top Level

Computer

Main Memory

InputOutput

SystemsInterconnection

Peripherals

Communicationlines

CentralProcessing Unit

Computer

Structure - The CPU

Computer Arithmeticand Login Unit

ControlUnit

Internal CPUInterconnection

Registers

CPU

I/O

Memory

SystemBus

CPU


© MANISH MAHAJAN

Structure - The Control Unit

CPU

ControlMemory

Control Unit Registers and Decoders

SequencingLogic

ControlUnit

ALU

Registers

InternalBus

Control Unit

The Von Neumann ModelThe Input Unit provides instructions and data to the system, which are subsequently stored in the Memory Unit . The instructions and data are processed by the Arithmetic and Logic Unit (ALU) under the direction of the Control Unit . The results are sent to the Output Unit . The ALU and control unit are frequently referred to collectively as the central processing unit (CPU)

The stored program is the most important aspect of the Von Neumann model. A program is stored in the computer’s memory along with the data to be processed.

The System Bus ModelThis model partitions a computer system into three subunits: CPU, Memory, and Input/Output (I/O). This refinement of the von Neumann model combines the ALU and the control unit into one functional unit, the CPU. The input and output units are also combined into a single I/O unit.

Most important to the system bus model, the communications among the components are by means of a shared pathway called the system bus , which is made up of the data bus (which carries the information being transmitted), the address bus (which identifies where the information is being sent), and the control bus (which describes aspects of how the information is being sent, and in what manner).

Level of System Design


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Levels, abstractions and virtual machines

Application

High-level language

Assembly language

Operating System machine

Conventional machine level

Microarchitecture

Digital Logic


Application

High-level language

Assembly language



Microarchitecture

Digital Logic


ApplicationAdd A=2 and B=3


Application

High-level language

Add 2 and 3

C:=A+B;C, C++, BASIC, PASCAL, Java,

etc..


© MANISH MAHAJAN


Application

High-level language

Assembly language

Add 2 and 3

C:=A+B;

ldc num1ldc num2addldc 100stnl 0…

ldc num1ldc num2add


Application

High-level language

Assembly language


C:=A+B;

Add A=2 and B=3

system calls

ldc num1ldc num2add

Pentium MMX, SPARC, etc…


Application

High-level language

Assembly language



C:=A+B;

Add A=2 and B=3

ldc num1ldc num2add

system calls

1s and 0s


Application

High-level language

Assembly language



C:=A+B;

Add A=2 and B=3

ldc num1ldc num2add

system calls

1s and 0s

MicroarchitectureArrays & flow


© MANISH MAHAJAN


Application

High-level language

Assembly language



C:=A+B;

Add A=2 and B=3

ldc num1ldc num2add

system calls

1s and 0s

MicroarchitectureArrays & flow

Digital LogicLogic gates

REGISTER TRANSFER AND MICROOPERATIONS

• Register Transfer Language

• Register Transfer

• Bus and Memory Transfers

• Arithmetic Microoperations

• Logic Microoperations

• Shift Microoperations

• Arithmetic Logic Shift Unit

SIMPLE DIGITAL SYSTEMS

• Combinational and sequential circuits can be used to create simple digital systems.

• These are the low-level building blocks of a digital computer.• Registers + Operations performed on the data stored in them = Digital Module• Modules are interconnected with common data and control paths to form a digital

computer system

• Simple digital systems are frequently characterized in terms of– the registers they contain, and– the operations that they perform.

• Typically,– What operations are performed on the data in the registers– What information is passed between registers

MICROOPERATIONS (1)Register Transfer Language

• The operations on the data in registers are called microoperations.

• The functions built into registers are examples of microoperations– Shift

– Load– Clear

– Increment– …

• The result of the operation may replace the previous binary information of a register or may be transferred to another register.

101101110011 010110111001Shift Right Operation


© MANISH MAHAJAN

Microoperation

• Micro-operations are the basis for microprocessors. An instruction is fetched from memory, decoded and executed by performing a sequence of microoperations.

• A microprocessor performs the micro-operations in order to realize the instruction.

MICROOPERATION

An elementary operation performed (during one clock pulse), on the information stored in one or more registers

R ←←←← f(R, R)

f: shift, load, clear, increment, add, subtract, c omplement,and, or, xor, …

ALU(f)

Registers(R)

1 clock cycle

ORGANIZATION OF A DIGITAL SYSTEM

-Set of registers and their functions

-Information stored in these registers-Can be binary, BCD, Alphanumeric characters or cont rol info

- Microoperations set

•Set of allowable microoperations provided by the orga nization of the computer

•Depend on the type of information encountered

- Control signals that initiate the sequence of micr ooperations(to perform the functions)

• Definition of the (internal) organization of a comp uter

Register Transfer Language

ORGANIZATION OF A DIGITAL SYSTEMRegister Transfer Language

The microoperations performed on the information sto red in registers depend on the type of data that reside in the registers. The binary information commonly found in registers of digital computers can be classified into three c ategories:

1. Numerical data such as binary numbers or binary-c oded decimal numbers used in arithmetic computations.

2. Nonnumerical data such as alphanumeric characters or other binary-coded symbols used for special applications.

3. Instruction codes, addresses, and other control i nformation used to specify the data-processing requirements in the system.


© MANISH MAHAJAN

REGISTER TRANSFER LEVELRegister Transfer Language

• Viewing a computer, or any digital system, in this way is called the register transfer level

• This is because we’re focusing on– The system’s registers– The data transformations in them, and– The data transfers between them.

REGISTER TRANSFER LANGUAGERegister Transfer Language

• Rather than specifying a digital system in words, a specific notation is used, register transfer language

• For any function of the computer, the register transfer languagecan be used to describe the (sequence of) microoperations

• Register transfer language– A symbolic language– A convenient tool for describing the internal organization of digital

computers

– Can also be used to facilitate the design process of digital systems.

MICROOPERATIONS

• Computer system microoperations are of four types:

- Register transfer microoperations

- Arithmetic microoperations

- Logic microoperations

- Shift microoperations

Arithmetic Microoperations

DESIGNATION OF REGISTERSRegister Transfer Language

• Registers are designated by capital letters, sometimes followed by numbers (e.g., A, R13, IR)

• Often the names indicate function:– MAR - memory address register– PC - program counter– IR - instruction register

• Registers and their contents can be viewed and represented in various ways– A register can be viewed as a single entity:

MAR


© MANISH MAHAJAN

DESIGNATION OF REGISTERSRegister Transfer Language

R1Register

Numbering of bits

Showing individual bits

Subfields

PC(H) PC(L)15 8 7 0

- a register- portion of a register- a bit of a register

• Common ways of drawing the block diagram of a regis ter

7 6 5 4 3 2 1 0

R215 0

• Designation of a register

REGISTER TRANSFERRegister Transfer

• Copying the contents of one register to another is a register transfer

• A register transfer is indicated as

R2 ← R1

– In this case the contents of register R2 are copied (loaded) into register R1

– A simultaneous transfer of all bits from the source R1 to the destination register R2, during one clock pulse

– Note that this is a non-destructive; i.e. the contents of R1 are not altered by copying (loading) them to R2

REGISTER TRANSFERRegister Transfer

• A register transfer such as

R3 ← R5

Implies that the digital system has

– the data lines from the source register (R5) to the destination register (R3)

– Parallel load in the destination register (R3)– Control lines to perform the action

CONTROL FUNCTIONSRegister Transfer

• Often actions need to only occur if a certain condition is true

• This is similar to an “if” statement in a programming language

• In digital systems, this is often done via a control signal, called a control function

– If the signal is 1, the action takes place

• This is represented as:

P: R2 ← R1Which means “if P = 1, then load the contents of register R1 into

register R2”, i.e., if (P = 1) then (R2 ← R1)


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HARDWARE IMPLEMENTATION OF CONTROLLED TRANSFERS

Implementation of controlled transfer

P: R2 ← ← ← ← R1

Block diagram

Timing diagram

Clock

Register Transfer

Transfer occurs here

R2

R1

Control Circuit

LoadP

n

Clock

Load

t t+1

• The same clock controls the circuits that generate the control functionand the destination register

• Registers are assumed to use positive-edge-triggered flip-flops

Simultaneous Register Transfers

• 1- When signal P is asserted, the contents of B are copied intoboth registers A and C. Note that the order in which the statement is written does not matter. If the transfer from B to C was written first, the result would be the same

• 2 - two registers are loaded simultaneously from differentsources.

1 2

Illegal Simultaneous Transfers

• Example of an illegal operation, since A must be loaded with two different values simultaneously.

BASIC SYMBOLS FOR REGISTER TRANSFERS

Capital letters Denotes a register MAR, R2& numerals

Parentheses () Denotes a part of a register R2(0- 7), R2(L)

Arrow ←←←← Denotes transfer of information R2 ←←←← R1

Colon : Denotes termination of control function P:Comma , Separates two micro-operations A ←←←← B, B ←←←← A

Symbols Description Examples

Register Transfer


© MANISH MAHAJAN

CONNECTING REGISTRSRegister Transfer

There are occasions when a destination register rec eives information from two sources, but evidently not at the same time.

Consider the two statements:

T1: C �� A

T5 : C �� B

The connection of two source registers to the same destination register cannot be done directly, but requires a mu ltiplexer circuit to select between two possible paths.

For registers with four bits each, we need a quadru ple 2-to-1 line multiplex, in order to select either register A or register B. When T5 = 1, register B is selected, but when T1 = 1, regis ter A is selected (because T5 must be O when T1 is 1).

The multiplexer and the load input of register C ar e enabled every time T1 or T5 occurs. This causes a transfer of inf ormation from the selected source register into the destination regis ter.


Connecting Registers with Multiplexers

P: A �� BQ: A �� CR: B �� DS: C �� AT: D �� CU: D �� B

The multiplexer selects one of the four registers as the source register. Control lines for the mux are driven by external circuitry. The data is made available to all registers, but only one actually loads the data. Again, external hardware generates load signals for the four registers such that no more than one isactive at any given time.


• In a digital system with many registers, it is impractical to have data and control lines to directly allow each register to be loaded with the contents of every possible other registers

• To completely connect n registers � n(n-1) lines

• O(n2) cost– This is not a realistic approach to use in a large digital system

• Instead, take a different approach

• Have one centralized set of circuits for data transfer – the bus

• Have control circuits to select which register is the source, and which is the destination


© MANISH MAHAJAN

Bus Transfers

• The number of wires will be excessive if separate lines are usedbetween each register and all other registers in the system !

P1 P2

P3

P4P5

P6

To connect n items with direct connections, you

need n(n-1)/2 connections.

Bus System

• A more efficient scheme for transferring information between registers in a multiple-register configuration is a common bussystem

P1 P2

P3

P4P5

P6

To connect n items with bus connections, you need

only n connections.

Bus System

• A bus structure consists of a set of common lines, one for each bit of register, through which binary information is transferred one at a time

• Control signals determine which register is selected by the bus during each particular transfer

bus 8

S1S0

4-line Common

bus

Bus and Memory Transfer

4X1

MUX2

3 2 1 0

3 2 1 0

Register D

D3 D2 D1 D0

4X1

MUX3

3 2 1 0

4X1

MUX1

3 2 1 0

4X1

MUX0

3 2 1 0

D2 C2 B2 A2 D0 C0 B0 A0D1 C1 B1 A1D3 C3 B3 A3

3 2 1 0

Register C

C3 C2 C1 C0

3 2 1 0

Register B

B3 B2 B1 B0

3 2 1 0

Register A

A3 A2 A1 A0


© MANISH MAHAJAN

Bus transfers

• The transfer of information from a bus into one of many destination registers can be accomplished by connecting the bus lines to the inputs of all destination registers and activating the load control of the particular destination register selected.

• The symbolic statement for a bus transfer may mention the bus or its presence may be implied in the statement. When bus is included in the statement we write:

BUS � C, R1� BUS (however it is R1� C)

Tri State Bus Buffers

• A three-state gate is a digital circuit that exhibits three states. Two of the states are signals equivalent to logic 1 and 0 as in a conventional gate.

• The third state is called high impedance state• The high impedance state behaves like an open circuit which

means that the output is disconnected and does not have a logic significance.

Normal Input A

Control Input C

Output Y=A if C=1

High-impedance if C=0

Bus and Memory Transfers: Three-State Bus Buffers cont.

A

C=1

B A B

A

C=0

B A B

Buffer

Open Circuit

Connecting registers with 3-state buffers

2x4

decoder

s1s0

0123

Select

Enable E

A0

B0

C0

D0

Bus line for bit 0

• To construct a common bus for 4 registers of n bits each using 3-state buffers, we need n circuits with four buffers in each, as follows:


© MANISH MAHAJAN

Connecting registers with 3-state buffers

• External circuitry enables at most one of the tri-state buffers to pass its data through to the inputs of the registers. The data is made available to all registers, but only one actually loads the data. The load signals for the four registers are exactly the same as in the previous example. This makes sense since the registers only know that they are to read in data from the bus. They don’t care how the data got onto the bus in the first place.

• The primary advantage of using buffers rather than multiplexers is the reduced current load on the circuit.

BUS TRANSFER IN RTLBus and Memory Transfers

• Depending on whether the bus is to be mentioned explicitly or not, register transfer can be indicated as either

or

• In the former case the bus is implicit, but in the latter, it isexplicitly indicated

R2 ← ← ← ← R1

BUS ← ← ← ← R1, R2 ←←←← BUS

MEMORY (RAM)Bus and Memory Transfers

• Memory (RAM) can be thought as a sequential circuits containing some number of registers

• These registers hold the words of memory

• Each of the r registers is indicated by an address

• These addresses range from 0 to r-1

• Each register (word) can hold n bits of data

• Assume the RAM contains r = 2k words. It needs the following– n data input lines

– n data output lines– k address lines

– A Read control line– A Write control line

data input lines

data output lines

n

n

kaddress lines

Read

Write

RAMunit

MEMORY TRANSFERBus and Memory Transfers

• Collectively, the memory is viewed at the register level as a device, M.

• Since it contains multiple locations, we must specify which address in memory we will be using

• This is done by indexing memory references

• Memory is usually accessed in computer systems by putting the desired address in a special register, the Memory Address Register (MAR, or AR)

• When memory is accessed, the contents of the MAR get sent to the memory unit’s address lines

AR Memoryunit

Read

Write

Data inData out

M


© MANISH MAHAJAN

Memory Transfer

• Memory read : Transfer from memory• Memory write : Transfer to memory• Data being read or wrote is called a memory word

(called M) • It is necessary to specify the address of M when writing

/reading memory• This is done by enclosing the address in square brackets

following the letter M• Example: M[0016] : the memory contents at address

0x0016

MEMORY READBus and Memory Transfers

• To read a value from a location in memory and load it into a register, the register transfer language notation looks like this:

• This causes the following to occur– The contents of the MAR get sent to the memory address lines

– A Read (= 1) gets sent to the memory unit– The contents of the specified address are put on the memory’s

output data lines

– These get sent over the bus to be loaded into register R1

R1 ←←←← M[MAR]

MEMORY WRITEBus and Memory Transfers

• To write a value from a register to a location in memory looks like this in register transfer language:

• This causes the following to occur– The contents of the MAR get sent to the memory address lines

– A Write (= 1) gets sent to the memory unit– The values in register R1 get sent over the bus to the data input

lines of the memory

– The values get loaded into the specified address in the memory

M[MAR] ←←←← R1

AR

x12x0Cx0Ex10x12x14x16x18

1934456601322R1 M[AR]

R1100

R1

66

RAM

R1100

Memory Transfer


© MANISH MAHAJAN

SUMMARY OF R. TRANSFER MICROOPERATIONSBus and Memory Transfers

A ←←←← B Transfer content of reg. B into reg. A

AR ←←←← DR(AD) Transfer content of AD portion of reg. DR int o reg. AR

A ←←←← constant Transfer a binary constant into reg. A

ABUS ←←←← R1, Transfer content of R1 into bus A and, at the sa me time,

R2 ←←←← ABUS transfer content of bus A into R2 AR Address registerDR Data registerM[R] Memory word specified by reg. RM Equivalent to M[AR]

DR ←←←← M Memory read operation: transfers content ofmemory word specified by AR into DR

M ←←←← DR Memory write operation: transfers content ofDR into memory word specified by AR


• There are 4 types of microoperations:– Register transfer microoperations transfer binarı information

from one register to another

– Arithmetic microoperations perform arithmetic operations on numeric data stored in registers

– Logic microoperations perform bit manipulation operations on non-numeric data stored in registers

– Shift microoperations perform shift operations on data stored in registers

– Last three changes the data !

• The basic arithmetic microoperations are: addition, subtraction, increment, decrement, and shift

• Addition Microoperation:R3 ��R1+R2

• Subtraction Microoperation:R3 ←R1-R2 or :

R3 ←R1+R2+1

ARITHMETIC MICROOPERATIONS

1’s complement

• One’s Complement Microoperation:R2 ←R2

• Two’s Complement Microoperation:R2 ←R2+1

• Increment Microoperation:R2 ←R2+1

• Decrement Microoperation:R2 ←R2-1

ARITHMETIC MICROOPERATIONS


© MANISH MAHAJAN

Example

• For R1 = 1001 1100 and R2 = 01010110, the results of the operations are:

ADD: 1111 0010SUBTRACT: 0100 0110COMP: 1010 10012’S COMP: 1010 1010SUB (2C): 0100 0110INCR: 1001 1101DECR: 1001 1011

HALF ADDER/FULL ADDER

Half Adder

0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1

cn = xy + xcn-1+ ycn-1= xy + (x ⊕ y)cn-1

s = x’y’cn-1+x’yc’n-1+xy’c’n-1+xycn-1= x ⊕ y ⊕ cn-1 = (x ⊕ y) ⊕ cn-1

x

y

cn-1x

y

cn-1

cn s

c = xy s = xy’ + x’y= x ⊕ y

xy c

s

xy

cn-1

S

cn

Full Adder

0 0 0 00 1 0 11 0 0 11 1 1 0

x y c s

x y cn-1 cn s0

0

10

0

1

11

0

1

01

1

0

10

Binary Adder

• The binary adder is constructed with full-adder circuits connected in cascade, with the output carry from one full-adder connected to the input carry of the next full-adder

• n-bit binary adder requires n full adders

B3 A3 B2 A2 B1 A1 B0 A0

C0C1C2C3

C4 S3 S2 S1 S0

Full adder Full adder Full adder Full adder

Binary Adder Subtractor

B3 A3 B2 A2 B1 A1 B0 A0

C0C1C2C3

C4 S3 S2 S1 S0

Full adder Full adder Full adder Full adder

• Operations can be combined into one common circuit by including an EXOR gate with each full adder. If M=0 B⊕0=B adds, If M=1 B⊕1=B’and C0=1 subtracts

M


© MANISH MAHAJAN

• For unsigned numbers, this gives A – B if A≥B or the 2’s complement of (B – A) if A < B

(example: 3 – 5 = -2= 1110)• For signed numbers, the result is A – B provided that there is no

overflow. (example : -3 – 5= -8) 1101

1011 + ـــــــــــــــــــــــــــ

1000

BINARY ADDER-SUBTRACTOR

C3

C4

V =1, if overflow

0, if no overflow

Overflow detector for signed numbers

Binary Incrementer

• Input is the number that will be incremented• The output carry from one half-adder is connected to one of the

inputs of the next-higher-order half-adder. • The circuit can be extended to have n bits

• Binary Incrementer can also be implemented using a counter

• A binary decrementer can be implemented by adding 1111 to the desired register each time!

Half

adder

Half

adder

Half

adder

Half

adder

S3 S2 S1 S0

CCCC S S S S

x y x y x y x y

A3 A2 A1 A0 1

C4

BINARY ADDER / SUBTRACTOR / INCREMENTER

FA

B0 A0

S0

C0FA

B1 A1

S1

C1FA

B2 A2

S2

C2FA

B3 A3

S3

C3

C4

Binary Adder-Subtractor

FA

B0 A0

S0

C0C1FA

B1 A1

S1

C2FA

B2 A2

S2

C3FA

B3 A3

S3C4

M

Binary Incrementer

HAx y

C S

A0 1

S0

HAx y

C S

A1

S1

HAx y

C S

A2

S2

HAx y

C S

A3

S3C4

Binary Adder


ARITHMETIC CIRCUIT

• Arithmetic operations can be implemented in one composite arithmetic circuit

• The basic component of an arithmetic circuit is the parallel adder

• By controlling the data inputs of the adder, it is possible to obtain different types of arithmetic operations

• This circuit performs seven distinct arithmetic operations and the basic component of it is the parallel adder

• The output of the binary adder is calculated from the following arithmetic sum:

• D = A + Y + Cin


© MANISH MAHAJAN

Arithmetic Circuit Function Table

MicrooperationD=A+Y+CinYCin

S0

S1

Transfer AD=A1111

Decrement AD=A-11011

Increment AD=A+10101

Transfer AD=A0001

SubtractD=A+B’+1B’110

Subtract with borrow

D=A+B’B’010

Add with carryD=A+B+1B100

AddD=A+BB000

OutputInputSelect FA

FA

FA

FA

C out

C0

C1

C1

C2

C2

C3

C3

C4

4x1

mux

4x1

mux

4x1

mux

4x1

mux

S1S00123

S0S10123

S0S10123

S0S10123

X0

Y0

X1

Y1

X2

Y2

X3

Y3

D0

D1

D2

D3

CinS1S0A0

A1

A2

A3

B0

B1

B2

B3

0

Arithmetic Circuit

Logic Microoperations

• These operations consider each bit separately and treat them as binary variables

• Example: Exclusive orP: R1 � R1 ⊕ R2

• Special symbols will be adopted for the logic microoperations OR, AND and COMPLEMENT, to distinguish them from the corresponding symbols to express boolean functionsV is used for OR

Λ is used for AND

LOGIC MICROOPERATIONSLogic Microoperations

• Specify binary operations on the strings of bits in registers– Logic microoperations are bit-wise operations, i.e., they work on the

individual bits of data– useful for bit manipulations on binary data – useful for making logical decisions based on the bit value

• There are, in principle, 16 different logic functions that can be defined over two binary input variables

• However, most systems only implement four of these– AND (∧), OR (∨), XOR (⊕), Complement/NOT

• The others can be created from combination of these

0 0 0 0 0 … 1 1 10 1 0 0 0 … 1 1 11 0 0 0 1 … 0 1 11 1 0 1 0 … 1 0 1

A B F0 F1 F2 … F13 F14 F15


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Example

• For R1 = 1001 1100 and R2 = 01010110, the results of the operations are:

R1 1001 1100

R2 0101 0110AND: 0001 0100

OR: 1101 1110XOR: 1100 1010COMP: 1010 1001

List of Logic Microoperations

Set to all 1’sF �� all 1’sF15 = 1

NANDF �� A ΛΛΛΛ BF14 = (xy)’

F �� A V BF13 = x’+y

Complement AF �� AF12 = x’

F �� A V BF11 = x+y’

Complement BF �� BF10 = y’

Exclusive-NORF �� A ⊕⊕⊕⊕ BF9 = (x ⊕⊕⊕⊕ y)’

NORF �� A V BF8 = (x+y)’

ORF �� A V BF7 = x+y

Exclusive-ORF �� A ⊕⊕⊕⊕ BF6 = x ⊕⊕⊕⊕ y

Transfer BF �� BF5 = y

F ��A ΛΛΛΛ BF4 = x’y

Transfer AF �� AF3 = x

F �� A ΛΛΛΛ BF2 = xy’

ANDF �� A ΛΛΛΛ BF1 = xy

ClearF �� 0F0 = 0

NAMEMICROOPERATIONBOOLEAN FUNCTION

THE FOUR BASIC MICROOPERATIONS

OR Microoperation• Symbol: ∨∨∨∨, +

• Gate:

• Example: 1001102 ∨∨∨∨ 10101102 = 11101102

P+Q: R1←R2+R3, R4←R5 ∨∨∨∨R6

OR OR

ADD

THE FOUR BASIC MICROOPERATIONS cont.

AND Microoperation

• Symbol: ∧∧∧∧

• Gate:

• Example: 1001102 ∧∧∧∧ 10101102 = 00001102


© MANISH MAHAJAN

Complement (NOT) Microoperation

• Symbol: −−−−

• Gate:

• Example: 10101102 = 01010012


XOR (Exclusive-OR) Microoperation

• Symbol: ⊕⊕⊕⊕

• Gate:

• Example: 01001102 ⊕⊕⊕⊕ 10101102 = 11100002


OTHER LOGIC MICROOPERATIONS

NAND Microoperation

• Symbols: ∧∧∧∧ and −−−−

• Gate:

• Example: 1001102 ∧∧∧∧ 10101102 = 11110012

NOR Microoperation

• Symbols: ∨∨∨∨ and −−−−

• Gate:

• Example: 1001102 ∨∨∨∨ 10101102 = 00010012

OTHER LOGIC MICROOPERATIONS cont.


© MANISH MAHAJAN

Set (Preset) Microoperation• Force all bits into 1’s by ORing them with a value in

which all its bits are being assigned to logic-1

• Example: 1001102 ∨∨∨∨ 1111112 = 1111112

Clear (Reset) Microoperation• Force all bits into 0’s by ANDing them with a value in

which all its bits are being assigned to logic-0

• Example: 1001102 ∧∧∧∧ 0000002 = 0000002

OTHER LOGIC MICROOPERATIONS cont.Selective Set

• Sets to 1 the bits in register A where there are corresponding 1’s in register B

• It does not affect bit positions that have 0’s in B• OR microoperation can be used to implement

A 1010 (Register)

B 1100 (Logic operand)

--------------------

A 1110 (Result)

Selective Complement (Toggling)

• Complements bits in A where there are corresponding 1’s in B

• It does not affect bit positions that have 0’s in B• EXOR microoperation can be used to implement

A 1010 (Register)


--------------------

A 0110 (Result) (A ← A ⊕ B)

Selective Clear

• Clears to 0 the bits in register A only where there are corresponding 1’s in register B

• It does not affect bit positions that have 0’s in B• AND microoperation can be used to implement

A 1010 (Register)


--------------------

A 0010 (Result) (A ← A ⋅ B)


© MANISH MAHAJAN

Mask, Insert, Clear

• Mask operation is similar to the selective-clear operation except that the bits of A are cleared only where there are corresponding 0’s in B (AND)

• Insert operation inserts a new value şnto a group of bits. This is done by first masking the bits then ORing them with the required value (OR)

• Clear operation compares the words in A and B and produces an all 0’s result if the two numbers are equal (EXOR)

MASK OPERATION


• In a mask operation, the bit pattern in B is used to clear certain bits in A

1 1 0 0 At

1 0 1 0 B

1 0 0 0 At+1 (A ← A ⋅ B)

• If a bit in B is set to 0, that same position in A gets set to 0, otherwise it is unchanged

CLEAR OPERATION


• In a clear operation, if the bits in the same position in A and B are the same, they are cleared in A, otherwise they are set in A

1 1 0 0 At

1 0 1 0 B

0 1 1 0 At+1 (A ← A ⊕ B)

INSERT OPERATION


• An insert operation is used to introduce a specific bit pattern into A register, leaving the other bit positions unchanged

• This is done as

– A mask operation to clear the desired bit positions, followed by

– An OR operation to introduce the new bits into the desired positions

– Example• Suppose you wanted to introduce 1010 into the low order four

bits of A: 1101 1000 1011 0001 A (Original)101 1000 1011 1010 A (Desired)

• 1101 1000 1011 0001 A (Original)

1111 1111 1111 0000 Mask

1101 1000 1011 0000 A (Intermediate)

0000 0000 0000 1010 Added bits

1101 1000 1011 1010 A (Desired)


© MANISH MAHAJAN

Hardware Implementations

4x1

MUX

Ei

Ai

Bi0

1

2

3

S1

S2ComplementE = A11

XORE = A ⊕⊕⊕⊕ B01

ORE = A V B10

ANDE = A ΛΛΛΛ B00

OperationOutputS0S1

APPLICATIONS OF LOGIC MICROOPERATIONS


• Logic microoperations can be used to manipulate individual bits or a portions of a word in a register

• Consider the data in a register A. In another register, B, is bit data that will be used to modify the contents of A

– Selective-set A ← A + B

– Selective-complement A ← A ⊕ B

– Selective-clear A ← A • B’

– Mask (Delete) A ← A • B

– Clear A ← A ⊕ B

– Insert A ← (A • B) + C

– Compare A ← A ⊕ B– . . .

SHIFT MICROOPERATIONS

• Used for serial transfer of data

• Also used in conjunction with arithmetic, logic, and other data-processing operations

• The contents of the register can be shifted to the left or to the right

• As being shifted, the first flip-flop receives its binary information from the serial input

• There are three types of shifts

– Logical shift

– Circular shift

– Arithmetic shift

• What differentiates them is the information that goes into the serial input


r0r1r3rn-1

r0r1r2r3rn-1

Shift Right

Shift Left

Serial Input Serial Output

Serial Output Serial Input

Determines the “shift”

type

r2

**Note that the bit ri is the bit at position (i) of the register


© MANISH MAHAJAN

LOGICAL SHIFTShift Microoperations

• In a logical shift the serial input to the shift is a 0.

• A right logical shift operation:

• A left logical shift operation:

• In a Register Transfer Language, the following notation is used– shl for a logical shift left– shr for a logical shift right

– Examples:• R2 ← shr R2• R3 ← shl R3

0

0

CIRCULAR SHIFTShift Microoperations

• In a circular shift the serial input is the bit that is shifted out of the other end of the register.

• A right circular shift operation:

• A left circular shift operation:

• In a RTL, the following notation is used– cil for a circular shift left– cir for a circular shift right– Examples:

• R2 ← cir R2• R3 ← cil R3

ARITHMETIC SHIFTShift Microoperations

• An arithmetic shift is meant for signed binary numbers (integer)

• An arithmetic left shift multiplies a signed number by two

• An arithmetic right shift divides a signed number by two

• The main distinction of an arithmetic shift is that it must keep the sign of the number the same as it performs the multiplication ordivision

• A right arithmetic shift operation:

• A left arithmetic shift operation:

0

signbit

signbit

ARITHMETIC SHIFT

• An overflow may occur in arithmetic shift-left, and occurs when the sign bit is changed (sign reversal)

• An overflow flip-flop V s can be used to detect an arithmetic shift-left overflow

Vs = Rn-1 ⊕ Rn-2

Rn-2

Vs=Rn-1 1 � overflow

0 � no overflow


© MANISH MAHAJAN

ARITHMETIC SHIFTShift Microoperations

• An left arithmetic shift operation must be checked for the overflow

0

VBefore the shift, if the leftmost twobits differ, the shift will result in anoverflow

• In a RTL, the following notation is used– ashl for an arithmetic shift left– ashr for an arithmetic shift right– Examples:

• R2 ← ashr R2• R3 ← ashl R3

signbit


• Example: Assume R1=11001110, then:

– Arithmetic shift right once : R1 = 11100111

– Arithmetic shift right twice : R1 = 11110011

– Arithmetic shift left once : R1 = 10011100

– Arithmetic shift left twice : R1 = 00111000

– Logical shift right once : R1 = 01100111

– Logical shift left once : R1 = 10011100

– Circular shift right once : R1 = 01100111

– Circular shift left once : R1 = 10011101

HARDWARE IMPLEMENTATION OF SHIFT MICROOPERATIONS

Shift Microoperations

S

01

H0MUX

S

01

H1MUX

S

01

H2MUX

S

01

H3MUX

Select0 for shift right (down) 1 for shift left (up)Serial

input (I R)

A0

A1

A2

A3

Serialinput (I L)

ARITHMETIC LOGIC SHIFT UNIT

• Instead of having individual registers performing the microoperations directly, computer systems employ a number of storage registers connected to a common operational unit called an Arithmetic Logic Unit (ALU )


© MANISH MAHAJAN

ARITHMETIC LOGIC SHIFT UNIT

S3 S2 S1 S0 Cin Operation Function0 0 0 0 0 F = A Transfer A0 0 0 0 1 F = A + 1 Increment A0 0 0 1 0 F = A + B Addition0 0 0 1 1 F = A + B + 1 Add with carry0 0 1 0 0 F = A + B’ Subtract with borrow0 0 1 0 1 F = A + B’+ 1 Subtraction0 0 1 1 0 F = A - 1 Decrement A0 0 1 1 1 F = A TransferA0 1 0 0 X F = A ∧∧∧∧ B AND0 1 0 1 X F = A ∨ ∨ ∨ ∨ B OR0 1 1 0 X F = A ⊕⊕⊕⊕ B XOR0 1 1 1 X F = A’ Complement A1 0 X X X F = shr A Shift right A into F1 1 X X X F = shl A Shift left A into F

Shift Microoperations

ArithmeticCircuit

LogicCircuit

C

C 4 x 1MUX

Select

0123

F

S3S2S1S0

BA

i

A

D

A

E

shrshl

i+1 i

ii

i+1i-1

i

i BUSES

Computer Buses

– A bus is a common electrical pathway between multiple devices.• Can be internal to the CPU to transport data to and from the ALU.

• Can be external to the CPU, to connect it to memory or to I/O devices.

– Early PCs had a single external bus or system bus .

– Modern PCs have a special-purpose bus between the CPU and memory and (at least) one other bus for the I/O devices.

The System Bus


© MANISH MAHAJAN

Physical Implementations

• Parallel lines on circuit boards (ISA or PCI)

• Ribbon cables (IDE)

Physical Implementations (continued)

• Strip connectors on mother boards (PC104)

• External cabling (USB or Firewire)

Buses – Common Characteristics• Multiple devices communicating over a single set of

wires• Only one device can talk at a time or the message

is garbled• Each line or wire of a bus can at any one time

contain a single binary digit. Over time, however, a sequence of binary digits may be transferred

• These lines may and often do send information in parallel

• A computer system may contain a number of different buses

Buses – Structure

• Serial versus parallel• Around 50-100 lines although it's possible

to have as few as 3 or 4• Lines can be classified into one of four

groups– Data lines– Address Lines– Control Lines– Power


© MANISH MAHAJAN

Buses – Structure (continued)

• Bus lines (parallel)– Data– Address– Control – Power

• Bus lines (serial)– Data, address, and control are sequentially sent down

single wire– There may be additional control lines– Power

Data Bus

• Carries data– Remember that there is no difference between

“data” and “instruction” at this level

• Width is a key determinant of performance– 8, 16, 32, 64 bit

134

Address bus

• Identify the source or destination of data• e.g. CPU needs to read an instruction

(data) from a given location in memory• Bus width determines maximum memory

capacity of system– e.g. 8080 has 16 bit address bus giving 64k

address space

135

Control Bus

• Control and timing information– Memory read/write signal– I/O read/write signal– Transfer ACK– Bus Request– Bus Grant– Interrupt request– Interrupt Acknowledge– Clock signals– Reset

136


© MANISH MAHAJAN

Bus Interconnection Scheme Operation – Sending Data

• Obtain the use of the bus• Transfer the data via the bus• Possible acknowledgement

Operation – Requesting Data

• Obtain the use of the bus• Transfer the data request via the bus• Wait for other module to send data• Possible acknowledgement

Single Bus Problems

Lots of devices on one bus leads to:• Physically long buses

– Propagation delays – Long data paths mean that co-ordination of bus use can adversely affect performance

– Reflections/termination problems

• Aggregate data transfer approaches bus capacity

• Slower devices dictate the maximum bus speed


© MANISH MAHAJAN

Multiple Buses

• Most systems use multiple buses to overcome these problems

• Requires bridge to buffer (FIFO) data due to differences in bus speeds

• Sometimes I/O devices also contain buffering (FIFO)

Multiple Buses – Benefits

• Isolate processor-to-memory traffic from I/O traffic

• Support wider variety of interfaces• Processor has bus that connects as direct

interface to chip, then an expansion bus interface interfaces it to external devices (ISA)

• Cache (if it exists) may act as the interface to system bus

Computer Buses

– Some devices that attach to a bus are active and can initiate bus transfers. They are called masters .

– Some devices are passive and wait for requests. They are called slaves .

– Some devices may act as slaves at some times and masters at others.

– Memory can never be a master device.

Traditional (ISA) - (with cache)144


© MANISH MAHAJAN

High Performance Bus145

Elements of Bus Design146

Bus TypesDedicated vs. Time Multiplexed

• Dedicated– Separate data & address lines

• Time multiplexed– Shared lines– Address valid or data valid control line– Advantage - fewer lines

– Disadvantages• More complex control• Degradation of performance

Bus Width

• Bus width refers to the data and address bus widths. System performance improves with a wider data bus as we can move more bytes in parallel. We increase the addressing capacity of the system by adding more address lines.

• Wider the bus the better the data transfer rate or the wider the addressable memory space

• The address bus determines the system memory addressing capacity. A system with n address lines can directly address 2n memory words. In byte-addressable memories, that means 2n bytes


© MANISH MAHAJAN

Bus Timing

• Co-ordination of events on bus• Synchronous – a bus clock provides

synchronization of all bus operations• Asynchronous – donot use a common bus

clock signal; instead, these buses use handshaking to complete an operation by using additional synchronization signals

Synchronous Bus Timing

• Events determined by clock signals• Control Bus includes clock line• A single 1-0 cycle is a bus cycle• All devices can read clock line• Usually sync on leading/rising edge• Usually a single cycle for an event• Analogy – Orchestra conductor with baton• Usually stricter in terms of its timing

requirements

Synchronous Bus TimingMemory Read Operation

Synchronous Bus TimingMemory Write Operation


© MANISH MAHAJAN

Asynchronous Timing

• Devices must have certain tolerances to provide responses to signal stimuli

• More flexible allowing slower devices to communicate on same bus with faster devices.

• Performance of faster devices, however, is limited to speed of bus

Asynchronous Bus Operation

• In asynchronous buses, there is no clock signal. Instead, they use four-way handshaking to perform a bus transaction. This handshaking is facilitated by two synchronization signals: master synchronization (MSYN) and slave synchronization (SSYN). We can summarize the operation as follows:1. Typically, the master places all the required data to initiate a

bus transaction and asserts the master synchronization signal MSYN.

2. Asserting MSYN indicates that the slave can receive the data and initiate the necessary actions on its part. When the slave is ready with its reply, it asserts SSYN.

3. The master receives the reply and then removes the MSYN signal to indicate receipt. For example, in a memory read transaction, the CPU reads the data supplied by the memory.

4. Finally, in response to the master deasserting MSYN, the slave removes its own synchronization signal SSYN to terminate the bus transaction.

Asynchronous Timing – Read• The master places the address and

command information on the bus.

• Then it indicates to all devices that it has done so by activating the Master-ready line.

• This causes all devices on the bus to decode the address.

• The selected slave performs the required operation and informs the processor it has done so by activating the Slave-ready line.

• The master waits for Slave-ready to become asserted before it removes its signals from the bus.

• In the case of a read operation, it also strobes the data into its input buffer.

Asynchronous Timing – Read• The master places the address and

command information on the bus.

• Then it indicates to all devices that it has done so by activating the Master-ready line.

• This causes all devices on the bus to decode the address.

• The selected slave performs the required operation and informs the processor it has done so by activating the Slave-ready line.

• The master waits for Slave-ready to become asserted before it removes its signals from the bus.

• In the case of a read operation, it also strobes the data into its input buffer.


© MANISH MAHAJAN

Asynchronous Timing - Write

• In this case, the master places the output data on the data lines at the same time that it transmits the address and command information.

• The selected slave strobes the data into its output buffer when it receives the Master-ready signal and indicates that it has done so by setting the S1ave-ready signal to 1.

• The remainder of the cycle is identical to the input operation.

Synchronous OR Asynchronous?

• Asynchronous buses allow more flexibility in timing.

• In synchronous buses, all timing must be a multiple of the bus clock. For example, if memory requires slightly more time than the default amount, we have to add a complete bus cycle

• The main advantage of asynchronous buses is that they eliminate this dependence on the bus clock.

• However, synchronous buses are easier to implement, as they donot use handshaking.

Bus Arbitration

– I/O chips have to become bus master to read and write memory and to cause interrupts.

– If two or more devices want to become bus master at the same time, a bus arbitrationmechanism is needed.

– Arbitration mechanisms can be centralized or decentralized.

Static Vs Dynamic Arbitration

• In static bus arbitration, bus allocation among the masters is done in a predetermined way. For example, we might use a roundrobin allocation that rotates the bus among the masters. The main advantage of a static mechanism is that it is easy to implement. However, since bus allocation follows a predetermined pattern rather than the actual need, a master may be given the bus even if it does not need it. This kind of allocation leads to inefficient use of the bus.

• In dynamic bus arbitration, bus allocation is done in response to a request from a bus master. To implement dynamic arbitration, each master should have a bus request and grant lines. A bus master uses the bus request line to let others know that it needs the bus to perform a bus transaction. Before it can initiate the bus transaction, it should receive permission to use the bus via the bus grant line. Dynamic arbitration consists of bus allocation and release policies.


© MANISH MAHAJAN

Centralized Vs Decentralized Arbitration

• In the centralized scheme, a central arbiter receives bus requests from all masters. The arbiter, using the bus allocation policy in effect, determines which bus request should be granted. This decision is conveyed through the bus grant lines. Once the transaction is over, the master holding the bus would release the bus; the release policy determines the actual release mechanism.

• In the distributed implementation, arbitration hardware is distributed among the masters. A distributed algorithm is used to determine the master that should get the bus.

Bus Arbitration

Bus Allocation Policies

• Fixed Priority Policies– Each master is assigned a unique fixed priority. When multiple masters

request the bus, the highest priority master will get to use the bus• Rotating Priority Policies

– Priority of a master is not fixed. For example, priority of a master can be a function of the time waiting to get the bus. Thus, the longer a master waits, the higher the priority

• Fair Policies– Does not allow starvation– Some examples of fairness are :

• All bus requests in a predefined window must be satisfied before granting requests from the next window

• A bus request should not be pending for more than M milliseconds

• Hybrid Policies– Combination of Priority and Fairness– Also called Combined Policies– E.g. – PCI Bus

Bus Release Policies

• Non-Preemptive – In these policies, the current bus master voluntarily releases the bus

• Transaction-Based Release : A bus master holding the bus releases the bus when its current transaction is finished

• Demand Based Release : the current master releases the bus only if there is a request from another bus master; otherwise, it continues to use the bus. Typically, this check is done at the completion of each transaction

– A potential disadvantage of the non-preemptive policies is that a bus master may hold the bus for a longtime, depending on the transaction type. For example, long block transfers can hold the bus for extended periods of time.

• Preemptive– Preemptive policies force the current master to release the bus without

completing its current bus transaction.


© MANISH MAHAJAN

Centralized Bus Arbitration – Daisy Chaining Daisy Chain Method

• When the central arbiter receives a bus request, it sends out a bus grant signal to the first master in the chain.

• The bus grant signals are chained through the masters Each master can pass the incoming bus grant signal to its neighbor in the chain if it does not want to use the bus.

• If a master wants to use the bus, it grabs the bus grant signal and will not pass it on to its neighbor. This master can then use the bus for its bus transaction.

• Bus release is done by the release policy in effect.

• Daisy chaining is simple to implement and requires only three control lines independent of the number of hosts.

• Disadvantages– It implements a fixed priority policy– The bus arbitration time varies and is proportional to the number of masters– This scheme is not fault tolerant

Centralized Arbitration - Polling Polling

• In response to the bus request from one or more devices, the controller polls them (in a predesignedpriority order) and selects the highest priority device among them and grants the bus to it. Only one bus grant line is shown. But, only the selected device will be activated as bus master (i.e., accepts the bus grant). All the other devices will ignore it.


© MANISH MAHAJAN

Centralized Arbitration – Independent Request

Independent Requests

• The arbiter is connected to each master by separate bus request and grant lines

• When a master wants the bus, it sends its request through its own bus request line. Once the arbiter receives the bus requests from the masters, it uses the allocation policy to determine which master should get the bus next.

• Since the bus requests are received on separate lines, the arbiter can implement a variety of allocation policies: a rotating priority policy, a fair policy, or even a hybrid policy.

• It provides short, constant arbitration times and allows flexible priority assignment so that fairness can be ensured. In addition, it provides good fault tolerance. If a master fails, the arbiter can ignore it and continue to serve the other masters

• This implementation is complex. The number of control signals isproportional to the number of masters.

Decentralized Arbitration

– Decentralized bus arbitration is also possible.• A computer could have 16 prioritized bus request

lines. When a device wants to use the bus, it assert its request line.

• All devices monitor all request lines, so at the end of each bus cycle, each device knows whether it was the highest priority requester.

• This method avoids the necessity of an arbiter, but requires more bus lines.

• Another decentralized scheme equivalent to the daisy chain arbitration minus the arbiter is shown on the following slide.

Bus Arbitration


© MANISH MAHAJAN

Data Transfer Types173

Problem 4.1

Show the Block Diagram of the H/w that implements the following register transfer statement

yT2 : R2�R1 , R1�R2

Problem 4.2

The o/p of 4 registers R0, R1, R2 and R3 are connec ted through 4-to-1 line multiplexers to I/p of a fifth register R5. All the registers are 8 bit long. The required tran sfers are dictated by 4 timing variables T o through T 3 as follows

T0: R5��R0 T1: R5��R1T2: R5��R2 T3: R5��R3

The timing variables are mutually exclusive, I.e., only one variable is equal to 1 at a time. Give a block diag ram for the h/w implementation of the register transfers. Inclu de the connections necessary from the four timing variable s to the selection I/p of the multiplexers and to the load I /p of register R5

Solution


© MANISH MAHAJAN

Problem 4.3

Represent the following conditional control statement by two register transfer statements with control functions

If (P=1) then (R1�R2) else if (Q=1) then (R1�R3)

P : R1��R2P’Q : R1��R3

Problem 4.4

• Change the bus system in shown to be able to transfer information from any register to any other register? Specifically show the connections needed to provide a path from the o/p of register C to the I/p of register A

S1

S0

4-line Common

bus

4X1

MUX3

3 2 1 0

3 2 1 0

Register D

D3 D2 D1 D0

4X1

MUX3

3 2 1 0

4X1

MUX3

3 2 1 0

4X1

MUX3

3 2 1 0


3 2 1 0

Register C

C3 C2 C1 C0

3 2 1 0

Register B

B3 B2 B1 B0

3 2 1 0

Register A

A3 A2 A1 A0

Solution

• In this question we use S1 S0 to select the source register (With S1 being HSB), and use S3 S2 to select among the four registers available (with S3 being the HSB).

Problem 4.5

• Draw a bus system similar to that shown but use three state buffers and a decoder instead of the multiplexers.

S1S0

4-line Commonbus

4X1MUX3

3 2 1 0

3 2 1 0Register D

D3 D2 D1 D0

4X1MUX3

3 2 1 0

4X1MUX3

3 2 1 0

4X1MUX3

3 2 1 0


3 2 1 0Register C

C3 C2 C1 C0

3 2 1 0Register B

B3 B2 B1 B0

3 2 1 0Register A

A3 A2 A1 A0


© MANISH MAHAJAN

Solution Problem 4.6

• A digital computer has a common bus system for 16 registers of 32 bit each. The bus is constructed with multiplexers.a) How many selection I/p are there in each multiplexer?

b) What size of multiplexers are needed?

c) How many multiplexers are there in the bus?

Solutiona) 4 Selection lines to select one of the 16 register sb) 16 x 1 Multiplexersc) 32 Multiplexers, one for each bit of the register s.

Problem 4.7

The following transfer statements specify a memory. Explain the memory operation in each case?

a) R2 � M[AR]b) M[AR] � R3c) R5 � M[R5]

Solution

a) R2 �� M[AR] – This statement would transfer the contents of Memor y

word that has the address specified by AR into R2 register.

b) M[AR] �� R3– WRITE the value in register R3 into the Memory Word

that has the address specified in AR.

c) R5��M[R5]– It will firstly READ the Memory Word specified by R 5

and then transfer the value into the same register R5, this is mostly used in Indirect Addressing.


© MANISH MAHAJAN

Problem 4.8

Draw the block diagram for the h/w that implements the following statement

X + YZ: AR � AR + BRWhere AR and BR are two n bit registers

and X,Y and Z are control variables.

Solution

Problem 4.9

Show the hardware to implement the following statement

xyT0 + T1 + y’T2 : AR � AR + 1

Include the logic gates for the control functions and a block diagram for the binary counter with a count enable function.

Solution


© MANISH MAHAJAN

Problem 4.10

Consider the following register transfer statements for two 4 bit registers R1 and R2

xT : R1 � R1 + R2x’T : R1 � R2

Draw BD for the h/w implementation. Use BD for the the two 4 bit registers, a 4-bit adder and a quadruple 2-to-1 line mux that selects the I/p to R1. Show how the control variables x and T select the I/p of the mux and the load I/p of the register.

Solution

Problem 4.11

• Using a 4 bit counter with parallel load and a 4 bit adder, draw a BD to implement the following

x: R1 � R1 + R2x’y : R1 � R1 + 1

Where R1 is a counter with parallel load and R2 is a 4 bit register

Solution


© MANISH MAHAJAN

PROBLEM 4.12

For the adder subtractor ckt find the values of S3, S2, S1, S0 AND C4 for the given values of M, A and B

FAFAFAFA C0

A0B0

S0

A1B1

S1

A2B2

S2

A3B3

S3

C1C2C3

C4

4-bit adder-subtractor

M

000100001

101001011

100011001

100110000

011001110

BAM

EDCBA

SOLUTION

FAFAFAFAC0

A0B0

S0

A1B1

S1

A2B2

S2

A3B3

S3

C1C2C3

C4

4-bit adder-subtractor

M

000100001

101001011

100011001

100110000

011001110

BAM

E

D

C

B

A

PROBLEM 4.13

• Design a 4-bit combinational cktdecrementer using four full adder ckts

A – 1 = A + 2’s Complement of 1 = A + 1111

Problem 4-14

Assuming that the 4 bit arithmetic ckt is build on an IC. Show the connections among two such Ics to form an 8 bit ckt

S1S00123

4x1MUX

X0

Y0

C0

C1

D0FA

S1S00123

4x1MUX

X1

Y1

C1

C2

D1FA

S1S00123

4x1MUX

X2

Y2

C2

C3

D2FA

S1S00123

4x1MUX

X3

Y3

C3

C4

D3FA

Cout

A0

B0

A1

B1

A2

B2

A3

B3

0 1

S0S1Cin


© MANISH MAHAJAN

Solution Problem 4-15

Design an arithmetic ckt with one selection var S and two n-bit data I/p A and B. the ckt generates the following 4 arith operations in conjunction with the I/p carry Cin. Draw the logic diagram for the first two stages.

D = A + B + 1 (Subtract)D = A – 1 (Decrement)1

D = A + 1 (Increment)D = A + B (Add)0

Cin = 1Cin = 0S


Derive a Combinational ckt that selects and generates any of the 16 logic functions


© MANISH MAHAJAN


Draw a digital ckt that performs the 4 logic operations of EX-OR, EX-NOR, NOR and NAND. Use two selection var. show the logic diag of one typical stage.

Problem 4-18

Register A holds the value 11011001, determine the B operand and the logic microperation to be performed in order to change the value in A to

(a) 01101101 (b) 11111101

Problem 4-19

The 8-bit registers AR, BR, CR and DR initially have the values 11110010, 11111111, 10111001 and 11101010 respectively.

Determine the 8-bit values in each register after the execution of the following microoperations.

AR � AR + BR

CR � CR Λ DR, BR � BR + 1

AR � AR – CR


© MANISH MAHAJAN

Problem 4-20

• An 8-bit register holds the value 10011100. What is the register value after an arithmetic shift right? Starting from the initial no. 10011100 determine the register value after an arithmetic shift left, and state whether there is an overflow.

Problem 4-21

Starting from an initial value of R=11011101, determine the sequence of binary values in R after a logical shift left, followed by a circular shift right followed by a logical shift right and a circular shift left.

Problem 4-22

What is the value of o/p H if I/p A = 1001, S=1, IR= 1 and IL = 0?

S01

H0MUX

S01

H1MUX

S01

H2MUX

S01

H3MUX

Select 0 for shift right (down) 1 for shift left (up)

Serialinput (I R)

A0

A1

A2

A3

Serialinput (I L)

Problem 4-23

What is wrong with the following Microoperations1. xT: AR � AR, AR � 0

2. yT: R1 � R2, R1 � R3

3. zT: PC � AR, PC � PC + 1


© MANISH MAHAJAN

FLOATING POINT

IEEE 754

Floating-Point

• What can be represented in N bits?–Example(8-bits)

• Unsigned0 to 2N

0 t0 255

• 2’s Complement- 2N-1 to 2N-1 - 1-128 t0 127

• 1’s Complement:- 2N-1+1 to 2N-1 -1-127 t0 127

• BCD:0N/4 to 10 – 10 t0 9

Floating-Point

• What about?– Very large numbers?

9,349,398,989,787,762,244,859,087,678

– Very small number?0.0000000000000000000000045691

– Rational numbers2/3

– . . .

• We need a system to represent numbers in which the range of expressible numbers is independent of the number of significant digits

Floating-Point

• Examples of real numbers:

–π = 3.14159265…

–ε = 2.71828…

– . . .


© MANISH MAHAJAN

Floating Point Representation

• 2 parts– Signed, fixed point number �� MANTISSA– Position of the decimal (or binary) point �� EXPONENT

• Fixed point mantissa may be a fraction or an integer.

• Example: Decimal number +6132.789 can be represented as

Fraction Exponent+0.6132789 +04

The value of the exponent indicates the actual posi tion of the decimal point. 4 positions to the right.

Scientific Notation

+0.61322789E+04

Principal of Floating Point

• In the scientific notation n = f × 10e

where f is called the fraction , or mantissa , or significand and e is a positive or negative integer called the exponent .

• The computer version of this notation is called flo ating point.• Examples

– 3.14 = 0.314 × 101 = 3.1410 × 100– 0.000001 = 0.1 × 10−5 = 1.0 × 10−6– 1941 = 0.1941 × 104 = 1.941 × 103

• The range is effectively determined by the number of digits i n the exponent.

• The precision is determined by the number of digits in the fraction.– More bits for significand gives more accuracy– More bits for exponent increases range

• For Binary (–1)sign x significand x 2 exponent

Modeling the Real Number System

• Floating-point numbers can be used to model the rea l-number system of mathematics, although there are some important differences.

• The real line is divided up into seven regions:1. Large negative numbers less than −0.999 × 10 99.2. Negative numbers between −0.999 × 10 99 and −0.100 × 10−99.3. Small negative numbers with magnitudes less than −0.100 × 10 −99.4. Zero.5. Small positive numbers with magnitudes less than 0.100 × 10 −99.6. Positive numbers between 0.100×10 −99 and 0.999 × 1099.7. Large positive numbers greater than 0.999 × 10 99.

Real Numbers 7 Regions

2. Expressible-ve Numbers

6. Expressible+ve Numbers

5. +veUnderflow

7. +veOverflow

3. -veUnderflow

1. -veOverflow

4. Zero

- ∞∞∞∞ 0 +∞∞∞∞


© MANISH MAHAJAN

Overflow / Underflow

• Overflow regions:– Due to finite nature of representation in computers , overflow

(Region 1&7) and Underflow (Regions 3 & 5) cannot b e expressed

• Underflow:– Underflow errors are less serious than overflow err ors

– Underflow can be approximated to zero

Rounding

• It is quite possible for the result of a calculatio n to be one of the other numbers, even though it is in region 2 or 6.– For example, +0.100 × 10 3 divided by 3 cannot be expressed

exactly.

• The obvious thing to do is to use the nearest numbe r that can be expressed.

• This process is called rounding .

Relative Error

• The “space” between adjacent expressible numbers in regions 2 and 6 is not constant.

• The separation between +0.998 × 10 99 and +0.999×1099 is very different than that between +0.998 × 10 0 and +0.999 × 100

• However, when separation between a number and its s uccessor is expressed as a percentage of that number, there is no systematicvariation throughout region 2 or 6.

• The relative error introduced by rounding is approximately the same for small numbers as large numbers.

Effects of Changes in the System

• Changing the number of digits in the fraction or ex ponent shifts the boundaries of regions 2 and 6 and changes the numbe r of expressible points in them.

• Increasing the number of digits in the fraction inc reases the density of points and therefore improves the accura cy of approximations.

• Increasing the number of digits in the exponent inc reases the size of regions 2 and 6 by shrinking regions 1, 3, 5, an d 7.


© MANISH MAHAJAN

Normalization

• A floating point number is said to be normalized if the most significant digit of the mantissa is nonzero

• For example the decimal number 350 is normalized bu t 00035 is not.

• Regardless of where the position of the radix point is assumed to be in the mantissa, the number is normalized onl y if its leftmost digit is nonzero.

• Example:(2.0) x 10-9 Normalized

(0.2) x 10-8 Not-normalized(20.0) x 10-10 Not-normalized

Floating-Point for Binary Numbers

• Floating point:– Computer arithmetic that represents numbers in whic h

binary point is not fixed• Example: (1.0) x 2 -1

– Opposite of fixed-point notation:• Example: 123.456

• Computers support floating-point arithmetic • The fractional point is called the “binary point”

Binary Normalized Form

• Why Normalized form? – Simplifies exchange of data

– Simplifies floating-point algorithms

– Increase accuracy of numbers

• Format:

(1.xxxxxx) x 2 yyyyy

• How can we convert to normalized form– need a base that can exactly be decreased or incre ased

by the number of bits to be shifted

• Normalized numbers are generally preferable to unnormalized numbers, because there is only one normalized form, whereas there are many unnormalized forms.

Floating Point Number Representation

Decimal Value:V = M * R E

Where: M= MantissaE= ExponentR= Radix (10)

Example (decimal):1234.5678

Exponent MantissaSign Value Sign Value0 4 0 0.12345678

==> 0.12345678 x 10 +4


© MANISH MAHAJAN

Example (binary):+ 1001.11 (= 9.75)

Make a fractional number, counting the number of sh ifts:+ .100111 ==> 4 shifts

Exponent MantissaSign Value Sign Value0 100 0 1001111

Or for a 16-bit number with a sign, 5-bit exponent, 10-bit mantissa:

0 00100 1001111000

Floating Point Number Representation Single Precision Floating Point (FP) Numbers

• Current computer systems dictate that FP numbers mu st fit in 32-or 64-bit registers.

• 32-bit or single precision FP numbers are organized as follows:(-1)s x Fraction x 2 E

seee eeee emmm mmmm mmmm mmmm mmmm mmmm

• where s is the sign of the number, e represents the biased exponent (8 bits) and m represents the mantissa or significand (23 bits)

• 32-bit values range in magnitude from 10 -38 to 1038.

31 30 . . . 23 22 . . . 0

s exponent Significand (Mantissa/Fraction)

Double Precision Floating Point Numbers

• 64 bit double precision floating point numbers(Value represented in two 32-bit words) are organized as follows:– The MSB is the sign bit – The next 11 bits are the exponent – The remaining 20+32=52 bits are the significand

• The range in magnitude is from 10 -308 to 10 308

• The growth of significand and exponent is a compromise between accuracy and range.

31 30 . . . 20 19 . . . 0

s exponent Significand (Mantissa/Fraction)

Significand (Mantissa/Fraction) Continued

Biased Exponent

• Exponents can be both positive ad negative giving r ise to a need of sign bit in exponents.– eg. Exponents ranging from – 50 to 49 need 2 digits f or the

value and one bit for the sign.

• Biased Exponent eliminates the need for sign by adding a positive quantity to the exponent so that it is alw ays positive– Adding 50 to our example exponent makes the range a s 0 to

99, value requiring 2 digits and no sign bit needed .


© MANISH MAHAJAN

IEEE FP-754 Standard

• 1985 by William Kahan (Berkley)• Found virtually in every computer since 1980• Until 1980, every computer manufacturer had their o wn FP format• Some of the format did incorrect arithmetic• IEEE Standard permits FP data to be exchanged among different

computers• Three Formats:

– Single-precision (32-bits)– Double-precision (64-bits)– Extended precision (80-bits):

• Used primarily in ALU to reduce round off errors• Use excess-127 (single-precision) and Excess-1023 (d ouble-precision) code for

exponent to prevent using sign bit


• Uses normalized form– Binary point– Followed by a ‘1’ bit– the rest of the fraction

• Hidden bit:– The leading ‘1’ bit doesn’t have to be stored (assum ed to be

present)• Fractions (Significand) are defined as

– Implied 1 bit– Implied binary point– Either 32 or 52 bits

• If all bits = ‘0’s => value = 1.0• If all bits are ‘1’s => value < 2.0


• Greatly improved portability and quality of computer arithmetic

• Makes the leading 1 bit of normalized binary numbers implicit– => Numbers are expanded by 1 bit

• Numbers 24 bits long for single precision(1 implied + 23 fraction)

• Numbers are 53 bits long for double-precision (1 im plied + 52 fraction)

– Zero is represented as 00 … 00 two

– Has a symbol ( NaN = Not a number) for invalid operations (e.g. 0/0 or subtracting infinity from i nfinity)

• Allows programmers to postpone some tests and decisions to a later time in the program

– All other numbers are represented using the followi ng formula:

(-1)s x (1 + Fraction) x 2 E


• Biased notation– Represent the most negative exponent as 000 … 00 two

– IEEE 754 uses a bias of 127 for single precision• Formula for biased notation

(-1)s x (1 + Fraction) x 2 (Exponent – Bias)

• Examples:– Unbiased representation:

• -1 will be represented as (-1 + 127) = 126 ten = 0111 1110two

• -0.75 ten = - 0.11two = - 1.1two x 2-1

– Biased single precision representation• For -0.75 ten

– (-1)1 x ( 1+ .1000 0000 0000 0000 0000 000two) x 2(126-127)

• What will change for double precision?

14

13

12

11

10

9 8 7 6 5 4 3 2 1 015

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 01


© MANISH MAHAJAN


• Example:– Converting the following binary representation into

decimal floating point

– (-1)s x (1 + Fraction) x 2(Exponent – Bias)

– = (-1)1 x (1 + 0.25) x 2(129 – 127)

– = -1 x 1.25 x 22

– = -1.25 x 4– = -5.0

14

13

12

11

10

9 8 7 6 5 4 3 2 1 015

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 11

Special Numbers in IEEE Floating Point

• An all zero number is a normalized 0• Other numbers with biased exponent e = 0 are

called denormalized• Denorm numbers have a hidden bit of 0 and an

exponent of -126; they may have leading 0s• Numbers with biased exponent of 255 are used

for ±∞ and other special values, called NaN (not a number)

• For example, one NaN represents 0/0

Fig 6.16 IEEE Standard Double Precision Floating Point

• Exponent bias for normalized #s is 1023

• The denorm biased exponent of 0 corresponds to an unbiased exponent of -1022

• Infinity and NaNs have a biased exponent of 2047

• Range increases from about 10-38≤|x|≤1038 to about 10-

308≤|x|≤10308

s ê f 1 f2 . . . f 52

sig n exponent f rac t io n

1 11 6 3120

Floating Point Registers


© MANISH MAHAJAN

Floating Point Addition and Subtraction

• Registers :– AC AC + BR– AC AC - BR

• Algorithms1. Check for zeros2. Align the mantissas3. Add or subtract the mantissas4. Normalize the result

Floating-Point Addition

• Steps1. Compare exponent

2. Shift smaller number right until its exponent matches the larger number

3. Add the significands

4. Normalize the sum

5. Round the sum if needed

6. Renormalize, if necessary

Decimal Floating Point Add and Subtract Examples

Operands Alignment Normalize & round6.144 ×102 0.06144 ×104 1.003644 ×105

+9.975 ×104 +9.975 ×104 + .0005 ×105

10.03644 ×104 1.004 ×105

Operands Alignment Normalize & round1.076 ×10-7 1.076 ×10-7 7.7300 ×10-9

-9.987 ×10-8 -0.9987 ×10-7 + .0005 ×10-9

0.0773 ×10-7 7.730 ×10-9


© MANISH MAHAJAN

Floating-Point Addition

• Example: 0.5 + -0.43751. Binary normalized versions of the two numbers

• 0.5 = 1.000 x 2–1

• -0.4375 = -1.110 x 2–2

2. Shift the number with less exponent right until it s exponent matches the larger number• -1.110 x 2–2 = -0.111 x 2–1

3. Add the significands• (1.000 x 2–1) + (-0.111 x 2–1) = -0.001 x 2–1

4. Normalize the sum• -0.001 x 2–1 = -1.000 x 2–4

• Biased exponent = (-4 + 127) = 1235. Round the sum if needed

• Number is already fits in the given bits6. Result in decimal

• -1.000 x 2–4 = 0.0625

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