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Accelerating the next technology revolution
Copyright ©2009
SEMATECH, Inc. SEMATECH, and the SEMATECH logo are registered servicemarks of SEMATECH, Inc. International SEMATECH Manufacturing Initiative, ISMI, Advanced Materials Research Center
and AMRC are servicemarks of SEMATECH, Inc. All other servicemarks and trademarks are the property of their respective owners.
Collaboration in high-tech era:
Consortium model
Gennadi Bersuker
SEMATECH Fellow
23 November 2012 2
SEMATECH members
23 November 2012 5
SEMATECH Locations- Austin
• Manufacturing Programs: ISMI, 450mm, NGF, EPIT
• Front end Technologies: Logic, memory, RF/Analog/MS
• Emerging Technologies: MEMS/NEMS, sensors, CMOS+, disruptive memory/logic, PV
• Fabless Program
23 November 2012 6
SEMATECH Locations- Albany
• Lithography: EUV, immersion, Masks, alt. Litho
• Front End Technologies: Logic, memory, electrical characterization and reliability
• 3D IC: TSV
• Metrology
23 November 2012
Lithography
• EUV Manufacturability and
Extendibility
• Mask Infrastructure
• Resist/Materials Development Center
• Alternative Lithography
Metrology
Manufacturing – ISMI
• ESH Technology Center
• Mature Fabs
• Manufacturing Capabilities
• 450mm
Materials/Emerging Technologies
• CMOS – Ge, III-V, fin/NWFETs, Xj
• Memories – NAND, R/STT RAMs)
• Emerging Technologies
Interconnect
• 3D TSV Interconnects
23 November 2012 8
SEMATECH – program summary
Future interconnects - 3D TSVs: Wide I/O DRAMS for mobile phones
Credit: Micron Technology
• Small form factor
• High bandwidth
• Increased memory density
• Lower power consumption
Samsung Electronics
11/23/2012 9
23 November 2012 10
Interconnects: 3D TSV Outlook
• Near future (2012 - 2013)
– Interposer products
– Wide IO DRAM (mobile)
• Future (2013 - 2017)
– Heterogenous integration (beyond memory on logic)
– Higher (>> 5 stacking levels)
– Smaller (<< 5 micron width, >> 10 aspect ratio)
– Reduced Cu-low k levels
• Far future (2017 - 2025)
– Beyond CMOS (photonics, sensors, etc)
Source: Xilinx Source: Nokia
Beyond CMOS Materials/Structures
Driving
Electrode A
Driving
Electrode B
Sensing
Electrode B
Sensing
Electrode ALength =
2~10m
Width = 90nmGap = <100nm
Source
Bit Line
Word
Lin
e
Common
Drain
Source
Gate
Dielectric
Gate
Electrode
Bit Line
Word
Lin
e
Common
Drain
Source
Gate
Dielectric
Gate
Electrode
STTRAM
ReRAM/Nanowire 3DArray
STEEP
NEMS
TFET
Graphene
23 November 2012
Logic and Memory Scaling Trends Materials and novel structures driven
2009
Advanced Materials Advanced Structures
2010 2011 2012 2013 2014
Bulk/SOI Si Bulk/SOI Si
High
(b)
Img: ' E0985 080516013_U T_Tr ans i s tor _200_TaN _Zr O_InGaAs.Ed_r ot_s .dm3' M AG: 590kX
5 n m5 n m
Metal
High-k
InGaAs
SEMATECH Si Nanowire
Img: 'E4160 080914004_7101534A_18_CV Dot_rot_s.Ed_s.dm3' MAG: 295kX
5 n m5 n m
HfOx
Si
50nm
WOx
TiN
W
TiN
W
WOx
TiN
W
TiN
W
CT Flash ReRAM 1T DRAM
Img: 'E3866 071029014_7081412_06_L26 FIN SiGe_rot_s.Ed_s.dm3' MAG: 295kX
5 n m5 n m
Fully strained
SiGe coreSi shell
Si
BOX
Ge
Si
BOX
Ge
Si
BOX
a)
b)
c)
SiG
e Si
2010 2020
Logic
Memory
High mobility Fins/Nanowires
BoxGate-2 (substrate)
N+ N+
N+ Poly-Si
Gate Ox
Ge (SiGe)
BoxGate-2 (substrate)
N+ N+
N+ Poly-Si
Gate Ox
Ge (SiGe)
BoxGate-2 (substrate)
N+ N+
N+ Poly-Si
Gate Ox
Ge (SiGe)
<20nm ReRAM
Semi-
conducting
filament
BE
MOx
TESemi-
conducting
filament
BE
MOx
TE
Gate stack Channels, contacts, USJ
High
Fin/NW
SiSi
Im g : 'E7 8 3 9 0 9 0 5 2 0 0 0 4 _8 0 9 1 5 1 4 _0 6 _R5 1 1 _ro t_s.d m 3 ' MAG: 1 9 5 kX
2 0 n m2 0 n m
{100
}
{100}
SiGe
12
III-V Devices on Si
Metal Gate / High-k
Press release by Intel; May, 2011
Going out of plane: FinFET
Source: NY Times
11/23/2012 13
4th Gen SiGe
Device roadmap: SEMATECH view
HKMG
FinFET
45nm 32nm 22nm
HKMG
3rd Gen SiGe
HKMG
SiGe Strain
14nm
Si FinFET scaling
Ge pFETs
Tight pitch fins
11nm
High- channel
III-V/Ge FinFETs
III-V/Ge on Si
8nm <6nm
Nanowire FETs
Low Ion
Strain
tFETs
3D Architecture
Planar
High Volume Manufacturing
III-V Devices on Si
Metal Gate / High-k
11/23/2012 14
16
Power Progress
1
.
2008
Ielmini, pub. & unpub. data, Politecnico di MilanoNiOx
NiOx
NiOx
NiOxTiy
HfOx\Ti
CuOx
SEMATECH
- -
Figure Acknowledgment: Prof. D. Ielmini, Politecnio di Milano
Easily put in fabs today
Not easily put in the fab
16
• Improved forming techniques allow ~1uA reset • Possible to meet switching energy target window of ~0.05-0.10 pJ/bit
SEMATECH Confidential
19
Center for Nanoscale Materials Argonne National Laboratory
Center for Functional Nanomaterials
Brookhaven National Laboratory
Center for Nanophase Materials Sciences
Oak Ridge National Laboratory Center for Integrated
Nanotechnologies
Los Alamos National laboratory & Sandia National Laboratory
Molecular Foundry Lawrence Berkeley National Laboratory
FEP Initiating
Research Program
FEP Research
Program - 2010
US National Lab Access for SEMATECH SEMATECH High Resolution Initiative and National Lab Network
SEMATECH Confidential
23 November 2012 20
Emerging Technologies
Stanford UCB
CMU UT Austin
UCLA SUNY Alb
KAIST UCSB
Memory
UT Austin Stanford
U of Florida UCB
U of Houston Yale
Gate Stack
Yale Tx State
UT Austin UT Dallas
Harvard NCSU
UC of London Stanford
Test Technology Center
UT Dallas U of Florida
Purdue CNR
NIST IIT B
SUNY Alb U of Modena
CMOS extension
UCB CNNU
Yale MIT
Newcastle UT Austin
UT Dallas U of Florida
Non-planar CMOS
U Florida UT Austin
UCB UT Dallas
NUS SUNY Alb
Ge, III-V MOSFET
Stanford UT Austin
Tx State UT Dallas
NUS IISc
World-wide University Network
• Established an effective model for focused research – On-site projects, 1-2 year assignments at SEMATECH
• Over 80 university collaborations across SEMATECH
3D / Lithography / ISMI
UCB U Wisconsin
MIT Stanford
Suny Alb Cornell
UT Austin U Michigan
Penn State Arizona
NC State Northwestern
Arizona State Purdue
SEMATECH Confidential
23 November 2012
TEST STRUCTURES
MODELING & SIMULATIONS
• Variety of test reticles
• Variety of test structures
• Device modeling: trap energy,
density, 1T1R RRAM, Gate
stacks, finFETs, noise. Dit,
• TSUPREM, MEDICI,
SENTAURUS, SPICE3, UFPDB,
COMSOL, Matlab, Cadence, ab
initio modeling with partners
ELECTRICAL
CHARACTERIZATION
• Capacitance & FET Parameter
extraction
• Workfunction measurements
• Interface evaluation
• Pulse-based measurements
• Reliability
• Ring Oscillator/invertors test
• Cryogenic measurements
• High frequency and noise
measuremnts
PHYSICAL CHARACTERIZATION
• XRR, HRXRD, GIXRD
• TXRF, XPS
• Synchrotron XPS
• EXAFS, EBSD
• Neutron Scattering
• Spectroscopic Ellipsometry
• VUV reflectometry
• FEI Titan
• EELS, SIMS, AES
SEMATECH Capabilities
21
Device Flows
• HKMG • ReRAM test • 1T1R memory test • 3D TSV via chains • 3D –FET interaction • Flash MANOS • MIMCap /MOSCap
• FINFET • NanowireFET • CMOSFET • pFET/nFET • Rco/TLM • III-V FET • MEMs/NEMs
M/NEMS Graphene Solar Cell Tunnel FETs
Emerging Tech Capabilities
III-V on Si
ADVANCED LITHO
• 300 mm EUV ADT
• EUV METs in Albany & LBNL
• State-of-the-art immersion
• 300 mm Nano imprint
• Resist Materials Center
• Mask Blank Development
ADVANCED
MANUFACTURING
• CoO analysis
• Yield councils
• ESH Center
• Equipment Maturity Analysis
• Fab productivity
• Mature Fabs
Accelerating the next technology
revolution
Research Development Manufacturing