Com Bi National &Sequential Circuits

8/6/2019 Com Bi National &Sequential Circuits

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2. Combinational and Sequential circuits

2.1 Introduction

The logic circuits are basically two types. One is Combinational and the other is Sequential. A

Combinational circuit consists of logic gates whose outputs at any time depends only on present inputs without

regard to previous inputs. A Combinational circuit is specified logically by a set of Boolean functions.

A block diagram of a Combinational circuit is shown in fig 2.1. It has n inputs and m outputs for n

input variables. There are 2npossible combinations of binary input values. For each possible input combination

there are one and only one possible output combination.

Fig. 2.1 Block diagram of a Combinational circuit

The examples for Combinational circuits are Muliplexers, Demultiplexers, Decoders, Encoders and Adders

etc

A Sequential logic circuit is one whose output at any time depends not only on present inputs, but also

on past inputs and the circuit behaviour must be specified by a time sequence of inputs and internal states. So, a

Sequential circuit should have memory element also to remember previous inputs.

A block diagram of a Sequential circuit is shown in fig 2.1(b). It consists of combinational circuit to

which memory element are connected to form a feedback path. The memory element stores the binary

information. The binary information is stored in the memory elements at any given time defines the state of

Sequential circuit. The block diagram explains that the output of a Sequential circuit is a function of not only

present external inputs. But also of the present state of memory elements.

There are two types of Sequential circuits. They are (a) Synchronous Sequential circuit and (b)

Asynchronous Sequential circuit

Fig. 2.1(b) Block diagram of a Sequential circuit

A Synchronous Sequential circuit is a system whose behaviour can be defined from the knowledge of

its signals at discreet instants of time. An Asynchronous Sequential circuit is one whose behaviour depends on

the order in which its input signals change and can be affected at any instant of time. The memory elements

commonly used in Asynchronous Sequential circuits are time delay devices.

The examples for Sequential circuits are Flip Flops, Counters and Registers etc


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The differences between Combinational and Sequential circuits is given in table 2.1

Combinational circuit Sequential circuit

1. It is a logic circuit.

Whose output at any time depends on input

applied at that instant only.

2. It has no memory element.

3. It can be totally described by the set of

output values only.

4. As there is no memory element, Its design

is simple.

5. It is a faster device.

6. Needs more hardware for realisation.

7. It is expensive in cost.

1. It is a logic circuit.

Whose output at any time depends on both

present and as well as previous inputs.

2. It should have at least one memory element

3. It can be described totally by the set of

sequent state values as well as set of output

values.

4. Its design is complex.

5. Slow in speed.

6. Needs less hardware for its realisation.

7. Not expensive.


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2.9 Semi-conductor Memories:

Memory is a very important part of any digital system. A memory is a storing device which stores the data

and some data can be retrieved at any instant of time.

The Semi-conductor memories are broadly classified into two types.

(a) Random Access Memory (RAM).

(b) Read Only Memory (ROM).

(a) RAM: Random Access Memory is also known as Read/Write (R/W). In a Random Access Memory the

access time is independent of address location of data i.e., any memory address location can be easilyaccessed. Generally, A RAM contains binary memory cells arranged as matrix (M x N) with an address

scheme for accessing the memory cells.

Since a RAM is made up of flip-flops it cannot store the data permanently i.e.,a RAM is a volatile. So the

information stored in it will exist as long as the power is ON. As soon as the power goes OFF the stored

information is lost. Hence we always refresh the RAM.

There are two types of RAM s. They are:

(i). Static RAM (SRAM).

(ii). Dynamic RAM (DRAM).

The Static RAM do not store the information permanently because it is volatile. Whereas in a Dynamic RAM

there will be a refreshing circuit which avoids the loss of data. So by refreshing the DRAM in regularintervals we can avoid the loss of data, In a Dynamic RAM the data bit is stored on the gate to source

capacitor of a MOS transistor memory circuit. Normally the Dynamic RAM s are refreshed of every two

milli seconds.

The Dynamic RAM s are cheap when compared to Static RAM s and also they have very high package

density. Their speed is also moderately high. Whereas the Static RAM s are costlier and consume more power.

They have higher speed than Dynamic RAM s.

There is also another type of RAM called SDRAM (synchronous DRAM) . The SDRAM s are fast and

they have both the advantages of SRAM and DRAM.

Differences between static and dynamic RAMs:

S.No Static RAM Dynamic RAM

1

2

3

4

5

This is constructed using bipolar

transistors

.Information is stored in the form of

voltage levels in flip-flops.These

voltage levels do not get drifted

away

No refresh logic is needed

Power is required even when the chip is

in standby mode

Four time larger in size compared to an

equivalent dynamic cell

This is constructed using MOS transistors

Information is stored in the form of

electrical charges in capacitors.So,has

tendency of leakage.

Refresh logic is necessary .

Refresh logic is inbuilt, so draws less

power comparatively.

Four times as many bits as a static RAM

chip.


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(b) ROM: ROM stands for Read Only Memory. It is a non-volatile memory. i.e., it stores thr information even

if the power supply goes off.(or fails). They are usually designed in such a way as to store the data permanently

in the binary form. The information once written or stored in a rom cannot be normally changed.

ROM s are classified into three types. They are:

(i). PROM.

(ii).EPROM.

(iii). EEPROM.

(i)PROM: PROM Stands for Programmable Read Only Memory. The contents of the PROM are decided by theUser for programming a PROM there are certain special devices called PROM or EPROM programmers. Using

These programmers we can store any required information in ROM. The PROM s are more cost effective to

store certain fixed programs. For example, In a computer the BIOS information are in a PROM. Example for a

PROM is 71LS287 (IC).

(ii).EPROM (Erasable PROM): These types of memories can be programmed and erased any number of times.

Hence they are called as Erasable PROM s. These EPROM s are based on MOS Technology. Data is stored by

a applying a high voltage pulse to the insulated gate of MOSFET. Normally, ultra violet light is used to

erase

the contents of EPROM. On the EPROM IC a small window is provided which protects the memory from

external UV light. Most of EPROM s operate at 5V. The only disadvantage of the EPROM s is it takes moretime for the erase of data. For 64 KB EPROM the total programming time will be around 5 to 6 minutes. The

Well known EPROM IC is 27512 (64 KB, Hitachi make).

(iii). EEPROM (Electrically EPROM): It is Electrically Erasable Programmable Read Only Memory. This

avoids the problems of erasing the data with UV radiation. Here the data is erased by applying an electric field.

Normally, the EEPROM s takes very less time for both programming and erasing. Hence most of the designers

Prefer EEPROM s to EPROM s for any computer system. The popularly known EEPROM is 58064 (8KB

Hitachi makes).

CAMS (Content Access Memory (or) Content Addressable Memory): This CAM is a random Accessmemory device that can be accessed by searching data content. For this purpose it is addressed by associating

the input data to a key, simultaneously with all the stored words. The output signals indicate the match

Conditions between the key and the stored words. This operation is referred to as association and this type of

Memory is also known as Association memory

A CAM differs from the conventional memory organization in a way that the addressing of the location

Depends on the memory content whereas it is not the case with conventional memory

As the CAM has the ability to search the stored data based on its contents it is therefore a powerful tool

in many applications. CAM s is manufactured using MOS, CMOS or Bi-polar technologies. Most of the

CAM s use ECH (Emitter Coupled Logic) circuitry because of its high speed operation.

Advantages of Semi-conductor Memories:

When the performance of memory devices are compared, the semi-conductor memories are fast and more

Efficient , when compared to magnetic and optical memories. The magnetic and optical devices can

store bulk data but they are very slow in speed. The read/write timings of semiconductor devices is high. But

these devices are cost effective. i.e. ,the cost of the semi conductor memories are relatively more than that

of the magnetic and optical devices.

Memory Organization:

The basic element of a semiconductor memory is a FLIP-FLOP. The information is stored in binary form.

There are a number of locations in a memory chip, each location being meant for one word of digital

information. The number of locations and the number of bits comprising the word vary from memory to


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memory. The size of a memory chip is specified by two numbers M and N as M x N bits. The number M

specifies the number of locations available in the memory and N is the number of bits at each location. In other

words, this means that M words of N bits each can be stored in the memory. The commonly used values of the

number of words per chip are 64, 256, 512, 1024, 2048, 4096 etc. Whereas the common values for the word

size are 1, 4, and 8, etc.

The block diagram of a memory device is shown in fig. 2. . Each of the M locations of the memory is

defined by a unique address and, therefore, for accessing any one of the M locations, P inputs are required,

where 2p=M. This set of lines is referred to as address inputs or address bus. The address is specified in thebinary form. For convenience, Octal and Hexadecimal representations are commonly employed.

In fact, the address input is applied to a P to M decoder circuit, which activates one of its M outputsdepending on the address and, thus, the desired memory location is selected.

For example let us consider the internal organization of 16 4 memory chip shown in fig.

Fig 2. Internal organization of a 16 4 memory chip


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The number of inputs required to store the data into or read the data from each locations is N. One set of N lines

is required for storing the data into the memory, referred to as data inputs and another set of N lines is

required for reading the data already stored in the memory, which is referred to as data outputs. In somememory chips, the same set of lines is used for data input as well as data output and is referred to as data

bus.

A Number of control inputs are required to give command to the device to perform the desired operation.

For example , a command signal is required to tell the memory whether a write or a read operation is

desired. Other command inputs include chip enable (CE), chip select (CS), etc.

Since M=16, 2P

=M gives P=4. The address of each location is is given in table 2. .

Working: To understand the working of semiconductor memories let us consider the write and readoperation.

Write operation: To write a word in the selected memory location requires logic 1 voltage to be applied to CS

and write inputs. This combination enables the input buffers so that the 4-bit word applied to the data inputs

will be loaded into the selected location. The condition WR=1 also disables (tristate) the output buffers, so that

the data outputs are in their high-impedance state.

For writing a word into a particular memory location, following sequence of operations is to be performed.

1. The chip select signal is applied to the CS terminal.

2. The word to be stored is applied to the data - input terminals.

3. The address of the desired memory locations applied to the address - input terminals.

4. A write command signal is applied to the write - control input terminal.

In response to the above operations, the addressed memory location is cleared of any word that might have

been stored in it, and the information presented at the data input terminal replaces it.

Figure 2. Illustrates the various waveforms during the write operation. The important timing

characteristics of the write cycle are

Write cycle time (tWC): This is the minimum amount of time for which the valid address must be present forwriting a word in the memory. In other words, it is the minimum time required between successive write

operations.

Word

Number

Binary Address

A3 A2 A1 A0

0

1

2

3

4

56

7

8

9

10

11

12

13

14

15

0

0

0

0

0

00

0

1

1

1

1

1

1

1

1

0

0

0

0

1

11

1

0

0

0

0

1

1

1

1

0

0

1

1

0

01

1

0

0

1

1

0

0

1

1

0

1

0

1

0

10

1

0

1

0

1

0

1

0

1


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Write pulse time (tW): This is the minimum length of the write pulse.

Write release time (tWR): This is the minimum amount of time for which the address must be valid after the

write pulse ends.

Data set up time (tDW):This is the minimum amount of time for which the data must be validbefore the write

pulse ends.

Data hold time (t DH): This is the minimum amount of time for which the data must be valid after the write pulse

ends.

Read operation: In order to read the contents of a selected memory, the read and the chip select (CS) inputs

must be at the logical 1 level. This enables the output buffers so that the contents of the selected location will

appear at the data outputs. The condition RD=1 also tristates the input buffers so that the data inputs do not

affect the memory during a read operation.

To read (or retrieve) a data word, Known to be stored at a particular address, the following sequence of

operations is required to be performed.

1. The chip select signal is applied to the CS terminal.

2. The address of the desired memory locations applied to the address - input terminals.

3. A read command signal is applied to the read - control input terminal.

In response to the above operations, the data word is stored at the addressed location appeares on the

data output terminals.

Figure 2. Illustrates the various waveforms during the read operation. The important timing characteristics of

the read cycle are:

Read cycle time (tRC): This is the minimum amount of time for which the valid address must be present forreading word from the memory. In other words, it is the minimum time required between successive read

operations.

Access time (tA): This is the maximum time from the start of the valid address of the read cycle to the time when

the valid data is available at the data outputs. The access time is at most equal to the read - cycle time, i.e. tA

tRC. In other words, the data outputs might be ready before the memory is actually ready for the next read

operation.

Read to output valid time (tRD): This is the maximum time delay between the beginning of the read pulse and

the availability of valid data at the data outputs.

Read to output active time (tRDX): This is the minimum time delay between the beginning of the read pulse and

the output buffers coming to active state (from the high-impedance state).

Chip-select to output valid time (tCO): This is the maximum time delay between the beginning of the Chip-select

pulse and the availability of valid data at the data outputs

Chip-select to output active time (tCX): This is the minimum time delay between the beginning of the chip-select

pulse and the output buffers coming to active state.

Output tristate from read (tOTD): This is the maximum time delay between the end of the read pulse and the

output buffers going to high impedance stste.

Data hold time (tOHA): This is the minimum time for which the valid data is available at the data outputs after

the address ends.

Figure 2. Illustrates the various waveforms during the read operation. The important timing characteristics

of the read cycle are

2.12 UP-DOWN Counters:


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Generally, an up counter will count from minimum value to maximum value and the down counter will

count from maximum value to minimum value. To get a counter to count up or down certain modifications

must be done. We know that, In an up-counter the normal output of a flip-flop is connected to the clock input of

the following flip-flop and in a down-counter it is the complement output which is connected to the clock input

of the following flip-flop. The modified circuit for up-down counter is shown in fig 2.

The normal and complement outputs of flip-flops are connected to AND gates D and E and the output of the

AND gates goes to the clock input of the next flip-flop via OR gate F. When the up-down control is logic 1,

gate D and F are enabled and the normal output of each flip-flop is coupled via OR gates (F) to the clock input

of the next flip-flop. Gates E are inhibited, as one input of all these gates goes low because of the inverter. So,

The counter counts up.

When the up-down control is at logic 0,gates D are inhibited and gates E are enabled. As a consequence

the complement output of each flip-flop is coupled via OR gates (F) to the clock input of the next flip-flop. So,

the counter counts down.

This is the working of an up-down counter. The 74LS190 and 74HC190 are two several synchronous

up/down counter IC s.

2.13 Decade counter (7490):

7490 is a 4 bit ripple type decade counter. It is a 14 pin monolithic plastic dual in line package (PDIP)Chip with power dissipation of 145mW and count frequency of 42 MHZ. The device consists of master slave

flip-flops internally connected to provide a divide by two section and a divide by 5 section. Each section

has a separate clock input to initiate state changes of the counter on the high to low clock transition. State

changes of the Q-Outputs do not occur simultaneously because of internal ripple delays.

A gated AND asynchronous Master reset (MR1-MR2) is provided which overrides both clocks and

clears all the flip-flops. Also a gated AND asynchronous Master set (MS1-MS2) is provided which overrides

the clocks and the MR inputs, setting the outputs to none (1001). Since the output from the divide by two

section is not internally connected to the succeeding stages, the device may be operated in the various counting

modes. In a BCD counter (8421) the 1 input must be externally connected to the Q0 output. The 0 input

receives the incoming count producing a BCD count sequence. Mode selection function table is shown in table2.

To operate as a divide by two and divide by five counters no external inter connections are required. The

first flip-flop is used as a binary element for the divide by two functions. The CP1 input is used to obtain a

divide by five operations at the Q3output.


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Table1. Mode selection function table

Reset /set inputs Outputs

MR1 MR2 MS1 MS2 Q0 Q1 Q2 Q3

1

1

X

0

X

0

1

1

1

X

X

0

X

0

0

X

1

0

X

X

0

X

1

1

X

0

0

X

0 0 0 0

0 0 0 0

1 0 0 1

Count

Count

Count

Count

Here X is the dont care condition

Table2. BCD count sequence function table

Count Outputs

Q0 Q1 Q2 Q3

0

1

2

3

4

5

6

7

8

9

0

1

0

1

0

1

0

1

0

1

0

0

1

1

0

0

1

1

0

0

0

0

0

0

1

1

1

1

0

0

0

0

0

0

0

0

0

0

1

1


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Differences between the Synchronous and Asynchronous counters:

Asynchronous counters Synchronous counters

1. Flip-flops are connected such that the

output of the first flip-flop will

become the clock pulse for the second

flip-flop and so on.

2. It is also called a serial counter or

Ripple counter.3. Speed is low and propagation delay is

high.

4. There is a limitation for high

frequency due to propagation delay.

5. Logic circuit is simple even for more

number of states

1. Here flip-flops are connected such

that each flip-flop is triggered by

a clock pulse at the same time.

2. It is called a parallel counter.

3. Speed is high and there is no

propagation delay.

4. No limitation on high frequencies.

5. As number of states increases

design becomes complex.

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Com Bi National &Sequential Circuits