Compal LA-4732P - Schematics. 5 5 4 4 3 3 2 2 1 1 D D C C B B A A Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING

A

A

B

B

C

C

D

D

E

E

1 1

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3 3

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Title

Size Document Number Rev

Date: Sheet of

Security Classification Compal Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date Deciphered Date

Montevina UMA 0.1

Cover Sheet

Custom

1 46Wednesday, February 18, 2009

2007/08/28 2006/03/10Compal Electronics, Inc.

Compal confidentialSchematics Document

Mobile Penryn uFCPGA with Intel

Cantiga_GM+ICH9-M core logic

2009-02-16REV:1.0

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

Title


Date: Sheet of







Montevina UMA 0.1

Block Diagram

Custom



Compal confidential

Thermal Sensor

EMC1402

Fan conn

Mobile Penryn

uFCPGA-478 CPU

FSB667/800/1066 MHz 1.05V

H_A#(3..35)

H_D#(0..63)

FCBGA 1329

Intel Cantiga MCH

DMI X4

BANK 0, 1, 2, 3DDR2 SO-DIMM X2

DDR2 800MHz 1.8V

Dual Channel

LPC BUS

DC/DC Interface CKT.

RTC CKT.

mBGA-676

Intel ICH9-M

Touch Pad CONN.Int.KBD

ENE

RTL8103EL

(10/100M)

RJ45/11 CONN

PCI-E BUS*4

LED

SATA HDD Connector

SATA Master-1

SATA Slave

C-Link

Codec_IDT92HD75BAudio CKT AMP & Audio Jack

TPA6047

USB conn x1

USB2.0 X12

Azalia

BT Conn

KB926

P6, 7, 8

P9,10, 11, 12, 13, 14

P15, 16

P20,21,22,23

P24

P25

P25

P21

P28 P29

P30

P33

P32

P32

P36

P06

P06

Montevina Consumer UMA

SPI

Clock Generator

SLG8SP553VP17

CK505 72QFN

CRT

LVDS Panel

Interface

P18

SATA Slave

P30e-SATA Connector

New Card

P26

HDMI P35

P19

Support V1.3P30

USB Camera

Capsense switch Conn

SATA ODD Connector

P19

P24

P31

SPI ROM

SST25VF080

MDCP28

Mini-Card

P26P26

Mini-CardWLAN WWAN

P33

P33

USB Board ConnP30

Finger printP30

USB port x2

5 in1 SlotP27

K/B backlight ConnP33

P24

ACCELEROMETER-1

ST

CardReaderP27

GM47

A

A

1 1

Title


Date: Sheet of







Montevina UMA 0.1

Notes List

Custom



O MEANS ON X MEANS OFFVoltage Rails+0.75V

S3+3VSX

+3VALW +5VSS1 +2.5VS

+CPU_CORE+VCCPpowerplane

OS5 S4/ Battery only

+BState +1.5VS+1.5V

S5 S4/AC & Batterydon't existS5 S4/AC+5VALW

S0

Symbol Note :: means Digital Ground: means Analog Ground@ : means just reserve , no build

SERIALEEPROMSMB_EC_CK2 SOURCEKB926 BATT ThermalSensor SODIMM CLK CHIPSMBUS Control TableSMB_CK_CLK1SMB_CK_DAT1 ICH9 MINI CARDSMB_EC_DA2SMB_EC_CK1SMB_EC_DA1LCD_CLKLCD_DAT CantigaLCDV 1 0 1 0 0 1 0 0A4

I2C / SMBUS ADDRESSING1 0 1 0 0 0 0 0D2A0CLOCK GENERATOR (EXT.) HEXDDR SO-DIMM 1 ADDRESSDDR SO-DIMM 0 1 1 0 1 0 0 1 0DEVICE+1.8VOOOO

OOOO OOO OOXXXXXXXXXV V V V V VXXX XXX XXX XXX XXX XXX XXXKB926

DEBUG@ : means just reserve for debug.CONN@ : means ME partGS @ : means just reserve for G sensor ESATA @ : means just reserve for ESATABATT @ : means need be mounted when 45 level assy or rework stage.45@ : means need be mounted when 45 level assy or rework stage.FP @ : means just reserve for Finger Print

USB-1 Left sideUSB-8 MiniCard(WWAN/TV)USB-6 Bluetooth USB-5 WLANUSB-4 CameraUSB-2 Left sideUSB-10 XUSB-9 Express cardUSB-3 CardreaderUSB-7 Finger PrinterUSB assignment:USB-11 XUSB-0 Right side(with eSATA)PCIe-2 XPCIe assignment:PCIe-1 WWANPCIe-3 WLANPCIe-4 GLAN (Realtek)PCIe-5 XPCIe-6 New CardMulti @ : means just reserve for Multi Bay

Cap sensor boardXXXV

NEW CARD G sensorV VX XXX XX

NewC@ : means just reserve for New cardMain@ : means just reserve for Main streamOPP@ : means just reserve for OPP2MiniC@ : means just reserve for 2nd Mini card slotPA @ : means just reserve for PAPR @ : means just reserve for PRXXXX

INVERTER

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet of


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.


Montevina UMA 0.1

Power delevry

C



VINAC

DC BATT

B+

INVPWR_B+

B++

B+++

1.05V_B+

LVDS CON

+3VALW

+5VALW

ICH9

+3VS

Finger printer

New card

ICH9

0.3A

278mA300mA

+1.8V

LAN

+3VS_DVDDALC268

25mA

+5VS+VDDAIDT 9275B

35mA

50mA

1A

177mA

+LCDVDD1.5A

+3VS_CK505250mA

+5VAMP10mA

ODD1.8A

SATA700mA

MCH3.7A

DDR2 800Mhz 4G x2

+0.9V50mA

+VCCP

ICH9

MCH1.26A

CPU2.3A

1.17A

LVDS CON

3.39A5.89A

3.7 X 3=11.1V

1.7A

2A

1.3A0.58A

12.11A1.9A

4.7A

7A

+V_BATTERY1A

+1.5VS

ICH_VCC1_5ICH9

657mA

ICH91.56A

2.2A0.3A

RT5158

CPU_B+ +VCC_CORE10mA2A

CPU34A/1.025V

Mini card (WLAN)1A

1AMini card (TV tu/WWAN/Robeson)

+3VAUX_BT60mA

SPI ROM

+3VALW_EC20mA

10mA

PC Camera(4.75V)50mA

A

A

1 1

Title


Date: Sheet of







Montevina UMA 0.1

Notes List

Custom



5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

H_THERMDA

H_THERMDC

THERM#

SMB_EC_DA2

SMB_EC_CK2

H_PROCHOT# OCP#

H_THERMDC

H_THERMTRIP#

H_THERMDAH_THERMDA_RH_THERMDC_R

H_PROCHOT#

H_HITM#H_HIT#

H_RESET#

H_TRDY#

H_RS#1H_RS#2

H_RS#0

H_LOCK#

XDP_TDI

XDP_TMS

XDP_TRST#

XDP_TDO

H_IERR#

H_A#3

H_A#10

H_A#13

H_A#11

H_ADSTB#0

H_A#7

H_A#9

H_A#16

H_A#6

H_A#8

H_A#12

H_A#15

H_A#5

H_A#14

H_A#4

H_REQ#2

H_REQ#4

H_REQ#1

H_REQ#3

H_A#32

H_A#34H_A#35

H_A#33

H_A#18

H_A#30

H_A#27H_A#26

H_A#21

H_A#17

H_A#20

H_A#25

H_REQ#0

H_ADSTB#1

H_A#28H_A#29

H_A#19

H_A#23H_A#24

H_A#22

H_A#31

H_SMI#

H_STPCLK#H_INTR

H_IGNNE#

H_A20M#H_FERR#

H_NMICLK_CPU_BCLK#CLK_CPU_BCLK

XDP_TRST#XDP_TMSXDP_TDOXDP_TDI

XDP_DBRESET#

H_BNR#H_ADS#

H_BPRI#

H_DEFER#

H_DBSY#H_DRDY#

H_BR0#

H_INIT#H_IERR#

XDP_TCK

XDP_TCK

FAN_SPEEDFAN_SPEED

+5VS_FAN

OCP# 22

H_THERMTRIP# 9,21

H_HIT# 9H_HITM# 9

H_RESET# 9H_RS#0 9H_RS#1 9H_RS#2 9

H_TRDY# 9

H_LOCK# 9

H_A#[3..16]9

H_ADSTB#09

H_REQ#09H_REQ#19H_REQ#29

H_A#[17..35]9

H_ADSTB#19

H_REQ#49H_REQ#39

H_A20M#21H_FERR#21

H_IGNNE#21

H_STPCLK#21H_INTR21H_NMI21H_SMI#21

CLK_CPU_BCLK 17CLK_CPU_BCLK# 17

XDP_DBRESET# 22

H_ADS# 9H_BNR# 9

H_BPRI# 9

H_DEFER# 9H_DRDY# 9H_DBSY# 9

H_BR0# 9

H_INIT# 21

SMB_EC_CK2 32

SMB_EC_DA2 32

FAN_SET32

FAN_SPEED32

+3VS

+3VS

+VCCP

+VCCP

+VCCP

+VCCP

+3VS

+5VS

+5VS

+3VS

Title


Date: Sheet of







Montevina UMA 0.1

Penryn(1/3)-AGTL+/ITP-XDP

Custom



Address:100_1100H_THERMDA, H_THERMDC routingtogether, Trace width / Spacing = 10 / 10mil Fan Control circuit

This shall place near CPUPlace TP with a GND 0.1" awayITP-XDP Connector

SI-1 Change to voltage control circuit

R3 54.9_0402_1%1 2

C15101000P_0402_50V7K

1

2

U1

EMC1402-1-ACZL-TR_MSOP8

DN3

DP2

VDD1

ALERT#6

SMCLK8

THERM#4

GND5

SMDATA7

C4 2.2U_0603_6.3V4Z

1

2

R13 56_0402_1%1 2

E

B

C

Q1MMBT3904_NL_SOT23-3

@

2

3 1

C50.1U_0402_16V4Z

1

2

R15 0_0402_5%1 2C3

2200P_0402_50V7K1 2

AD

DR

GR

OU

P_

0A

DD

R G

RO

UP

_1

CO

NT

RO

LX

DP

/IT

P S

IGN

AL

S

H CLK

THERMAL

RE

SE

RV

ED

ICH

JCPU1A

Penryn

A[10]#N3

A[11]#P5

A[12]#P2

A[13]#L2

A[14]#P4

A[15]#P1

A[16]#R1

A[17]#Y2

A[18]#U5

A[19]#R3

A[20]#W6

A[21]#U4

A[22]#Y5

A[23]#U1

A[24]#R4

A[25]#T5

A[26]#T3

A[27]#W2

A[28]#W5

A[29]#Y4

A[3]#J4

A[30]#U2

A[31]#V4

RSVD[01]M4

RSVD[02]N5

RSVD[03]T2

RSVD[04]V3

RSVD[05]B2

RSVD[06]D2

RSVD[07]D22

A[4]#L5

A[5]#L4

A[6]#K5

A[7]#M3

A[8]#N2

A[9]#J1

A20M#A6

ADS#H1

ADSTB[0]#M1

ADSTB[1]#V1

RSVD[08]D3

BCLK[0]A22

BCLK[1]A21

BNR#E2

BPM[0]#AD4

BPM[1]#AD3

BPM[2]#AD1

BPM[3]#AC4

BPRI#G5

BR0#F1

DBR#C20

DBSY#E1

DEFER#H5

DRDY#F21

FERR#A5

HIT#G6

HITM#E4

IERR#D20

IGNNE#C4

INIT#B3

LINT0C6

LINT1B4

LOCK#H4

PRDY#AC2

PREQ#AC1

PROCHOT#D21

REQ[0]#K3

REQ[1]#H2

REQ[2]#K2

REQ[3]#J3

REQ[4]#L1

RESET#C1

RS[0]#F3

RS[1]#F4

RS[2]#G3

SMI#A3

STPCLK#D5

TCKAC5

TDIAA6

TDOAB3

THERMTRIP#C7

THERMDAA24

THERMDCB25

TMSAB5

TRDY#G2

TRST#AB6

A[32]#W3

A[33]#AA4

A[34]#AB2

A[35]#AA3

RSVD[09]F6

R16

10K_0402_5%1 2

R2 54.9_0402_1%1 2

R7 54.9_0402_1%1 2

C2

0.1

U_

04

02

_1

6V

4Z

1

2

R120910K_0402_5%

12

T1

R1756_0402_5%

@

12

R8 54.9_0402_1%1 2

R14 0_0402_5%1 2

R4 54.9_0402_1%1 2

R18

56_0402_5%

12

D63

DLPT05-7-F_SOT23-3

Line to be protected2

Vcc3

GND1

U51

G996RD1U_TDFN8_3X3

VEN1

VIN2

VO3

VSET4

GND8

GND7

GND6

GND5

Thermal Pad9

C1509

2.2U_0603_6.3V4Z

1

2

R6 10K_0402_5%

1 2

JFAN1

ACES_85204-03001

CONN@

11

22

33

G14

G25

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

+V_CPU_GTLREF

H_D#4

H_D#14

H_D#10H_D#9

H_D#3

H_D#13

H_D#6

H_D#2

H_D#8

H_D#12

H_D#1

H_D#5

H_D#7

H_D#11

H_D#0

H_D#15

H_D#27

H_D#25

H_D#31

H_D#24

H_D#20

H_D#30

H_D#23

H_D#19

H_D#29

H_D#16

H_D#18

H_D#22

H_D#26

H_D#28

H_D#17

H_D#21

H_DINV#0

H_DINV#1H_DSTBP#1H_DSTBN#1

H_DSTBP#0H_DSTBN#0

+VCCPA+VCCPB

VSSSENSE

VCCSENSE

VSSSENSE

VCCSENSE

+V_CPU_GTLREFTEST1

H_D#35

H_D#46H_D#47

H_D#37

H_D#34

H_D#41

H_D#45

H_D#43

H_D#33

H_D#39H_D#40

H_D#44

H_D#32

H_D#42

H_D#38

H_D#36

H_DINV#2

H_DSTBN#2H_DSTBP#2

H_DINV#3

H_DSTBN#3H_DSTBP#3

H_D#48

H_D#56

H_D#52

H_D#59

H_D#63

H_D#55

H_D#51

H_D#62

H_D#58

H_D#54

H_D#50

H_D#57

H_D#61

H_D#53

H_D#49

H_D#60

COMP0

COMP2COMP3

COMP1

H_PWRGOODH_CPUSLP#

H_DPSLP#H_DPRSTP#

H_PSI#

H_DPWR#

TEST3

TEST7CPU_BSEL0

TEST4

CPU_BSEL1

TEST5TEST6

CPU_BSEL2

TEST2

VCCSENSE 42

VSSSENSE 42

H_D#[0..15]9

H_DSTBN#09H_DSTBP#09H_DINV#09H_D#[16..31]9

H_DSTBN#19H_DSTBP#19H_DINV#19

CPU_VID0 42CPU_VID1 42CPU_VID2 42CPU_VID3 42CPU_VID4 42CPU_VID5 42CPU_VID6 42

H_D#[32..47] 9

H_DSTBN#2 9H_DSTBP#2 9H_DINV#2 9H_D#[48..63] 9

H_DSTBN#3 9H_DSTBP#3 9H_DINV#3 9

H_DPRSTP# 9,21,42H_DPSLP# 21

H_CPUSLP# 9

H_DPWR# 9H_PWRGOOD 21

H_PSI# 42CPU_BSEL217CPU_BSEL117CPU_BSEL017

+VCCP

+VCCP

+1.5VS

+VCC_CORE +VCC_CORE

+VCC_CORE

Title


Date: Sheet of







Montevina UMA 0.1


Custom



Close to CPU pin AD26within 500mils.CPU_BSEL CPU_BSEL2 CPU_BSEL1166200 0 1 CPU_BSEL0

Resistor placed within 0.5"of CPU pin.Trace should beat least 25 mils away fromany other toggling signal.COMP[0,2] trace width is 18mils. COMP[1,3] trace widthis 4 mils. Length match within 25 mils.The trace width/space/other is 20/7/25.Close to CPU pin within500mils.

Near pin B26* Route the TEST3 and TEST5 signals througha ground referenced Zo = 55-ohm trace thatends in a via that is near a GND via and isaccessible through an oscilloscopeconnection.266 1100 0 00

R271K_0402_1%

12

C7

10

U_

08

05

_6

.3V

6M

1

2

T3

T5

R28 100_0402_1%1 2

R22 1K_0402_5%@ 1 2

R200_0402_5%1 2

DA

TA

GR

P 0

DA

TA

GR

P 1

DA

TA

GR

P 2

DA

TA

GR

P 3

MISC

JCPU1B

Penryn

COMP[0]R26

COMP[1]U26

COMP[2]AA1

COMP[3]Y1

D[0]#E22

D[1]#F24

D[10]#J24

D[11]#J23

D[12]#H22

D[13]#F26

D[14]#K22

D[15]#H23

D[16]#N22

D[17]#K25

D[18]#P26

D[19]#R23

D[2]#E26

D[20]#L23

D[21]#M24

D[22]#L22

D[23]#M23

D[24]#P25

D[25]#P23

D[26]#P22

D[27]#T24

D[28]#R24

D[29]#L25

D[3]#G22

D[30]#T25

D[31]#N25

D[32]#Y22

D[33]#AB24

D[34]#V24

D[35]#V26

D[36]#V23

D[37]#T22

D[38]#U25

D[39]#U23

D[4]#F23

D[40]#Y25

D[41]#W22

D[42]#Y23

D[43]#W24

D[44]#W25

D[45]#AA23

D[46]#AA24

D[47]#AB25

D[48]#AE24

D[49]#AD24

D[5]#G25

D[50]#AA21

D[51]#AB22

D[52]#AB21

D[53]#AC26

D[54]#AD20

D[55]#AE22

D[56]#AF23

D[57]#AC25

D[58]#AE21

D[59]#AD21

D[6]#E25

D[60]#AC22

D[61]#AD23

D[62]#AF22

D[63]#AC23

D[7]#E23

D[8]#K24

D[9]#G24

TEST5AF1

DINV[0]#H25

DINV[1]#N24

DINV[2]#U22

DINV[3]#AC20

DPRSTP#E5

DPSLP#B5

DPWR#D24

DSTBN[0]#J26

DSTBN[1]#L26

DSTBN[2]#Y26

DSTBN[3]#AE25

DSTBP[0]#H26

DSTBP[1]#M26

DSTBP[2]#AA26

DSTBP[3]#AF24

GTLREFAD26

PSI#AE6

PWRGOODD6

SLP#D7

TEST3C24

BSEL[0]B22

BSEL[1]B23

BSEL[2]C21

TEST2D25

TEST4AF26

TEST6A26

TEST1C23

TEST7C3

R21 1K_0402_5%@ 1 2

R190_0402_5%1 2

C8

0.0

1U

_0

40

2_

16

V7

K

1

2

R25

54

.9_

04

02

_1

%

12

R292K_0402_1%

12

R24

27

.4_

04

02

_1

%

12

R30 100_0402_1%1 2

T4

T6

T2

R26

27

.4_

04

02

_1

%

12

R23

54

.9_

04

02

_1

%

12

JCPU1C

Penryn

.

VCC[001]A7

VCC[002]A9

VCC[003]A10

VCC[004]A12

VCC[005]A13

VCC[006]A15

VCC[007]A17

VCC[008]A18

VCC[009]A20

VCC[010]B7

VCC[011]B9

VCC[012]B10

VCC[013]B12

VCC[014]B14

VCC[015]B15

VCC[016]B17

VCC[017]B18

VCC[018]B20

VCC[019]C9

VCC[020]C10

VCC[021]C12

VCC[022]C13

VCC[023]C15

VCC[024]C17

VCC[025]C18

VCC[026]D9

VCC[027]D10

VCC[028]D12

VCC[029]D14

VCC[030]D15

VCC[031]D17

VCC[032]D18

VCC[033]E7

VCC[034]E9

VCC[035]E10

VCC[036]E12

VCC[037]E13

VCC[038]E15

VCC[039]E17

VCC[040]E18

VCC[041]E20

VCC[042]F7

VCC[043]F9

VCC[044]F10

VCC[045]F12

VCC[046]F14

VCC[047]F15

VCC[048]F17

VCC[049]F18

VCC[050]F20

VCC[051]AA7

VCC[052]AA9

VCC[053]AA10

VCC[054]AA12

VCC[055]AA13

VCC[056]AA15

VCC[057]AA17

VCC[058]AA18

VCC[059]AA20

VCC[060]AB9

VCC[061]AC10

VCC[062]AB10

VCC[063]AB12

VCC[064]AB14

VCC[065]AB15

VCC[066]AB17

VCC[067]AB18

VCC[068]AB20

VCC[069]AB7

VCC[070]AC7

VCC[071]AC9

VCC[072]AC12

VCC[073]AC13

VCC[074]AC15

VCC[075]AC17

VCC[076]AC18

VCC[077]AD7

VCC[078]AD9

VCC[079]AD10

VCC[080]AD12

VCC[081]AD14

VCC[082]AD15

VCC[083]AD17

VCC[084]AD18

VCC[085]AE9

VCC[086]AE10

VCC[087]AE12

VCC[088]AE13

VCC[089]AE15

VCC[090]AE17

VCC[091]AE18

VCC[092]AE20

VCC[093]AF9

VCC[094]AF10

VCC[095]AF12

VCC[096]AF14

VCC[097]AF15

VCC[098]AF17

VCC[099]AF18

VCC[100]AF20

VCCA[01]B26

VCCP[03]J6

VCCP[04]K6

VCCP[05]M6

VCCP[06]J21

VCCP[07]K21

VCCP[08]M21

VCCP[09]N21

VCCP[10]N6

VCCP[11]R21

VCCP[12]R6

VCCP[13]T21

VCCP[14]T6

VCCP[15]V21

VCCP[16]W21

VCCSENSEAF7

VID[0]AD6

VID[1]AF5

VID[2]AE5

VID[3]AF4

VID[4]AE3

VID[5]AF3

VID[6]AE2

VSSSENSEAE7

VCCA[02]C26

VCCP[01]G21

VCCP[02]V6

+ C6330U_D2E_2.5VM_R7

1

2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

+VCC_CORE

+VCC_CORE

+VCC_CORE

+VCC_CORE

+VCCP

+VCC_CORE

Title


Date: Sheet of







Montevina UMA 0.1


Custom



Inside CPU center cavity in 2 rows

Mid Frequence Decoupling

Place these capacitors onL8 (North side,SecondaryLayer)

ESR 1980uFNear CPU CORE regulator

Place these capacitors onL8 (North side,SecondaryLayer)Place these capacitors onL8 (North side,SecondaryLayer)Place these capacitors onL8 (North side,SecondaryLayer)

C46

0.1U_0402_10V6K

1

2

+C41

33

0U

_D

2_

2V

Y_

R7

M

1

2

C31

10U_0805_6.3V6M

1

2

JCPU1D

Penryn

.

VSS[082]P6

VSS[148]AE11

VSS[002]A8

VSS[003]A11

VSS[004]A14

VSS[005]A16

VSS[006]A19

VSS[007]A23

VSS[008]AF2

VSS[009]B6

VSS[010]B8

VSS[011]B11

VSS[012]B13

VSS[013]B16

VSS[014]B19

VSS[015]B21

VSS[016]B24

VSS[017]C5

VSS[018]C8

VSS[019]C11

VSS[020]C14

VSS[021]C16

VSS[022]C19

VSS[023]C2

VSS[024]C22

VSS[025]C25

VSS[026]D1

VSS[027]D4

VSS[028]D8

VSS[029]D11

VSS[030]D13

VSS[031]D16

VSS[032]D19

VSS[033]D23

VSS[034]D26

VSS[035]E3

VSS[036]E6

VSS[037]E8

VSS[038]E11

VSS[039]E14

VSS[040]E16

VSS[041]E19

VSS[042]E21

VSS[043]E24

VSS[044]F5

VSS[045]F8

VSS[046]F11

VSS[047]F13

VSS[048]F16

VSS[049]F19

VSS[050]F2

VSS[051]F22

VSS[052]F25

VSS[053]G4

VSS[054]G1

VSS[055]G23

VSS[056]G26

VSS[057]H3

VSS[058]H6

VSS[059]H21

VSS[060]H24

VSS[061]J2

VSS[062]J5

VSS[063]J22

VSS[064]J25

VSS[065]K1

VSS[066]K4

VSS[067]K23

VSS[068]K26

VSS[069]L3

VSS[070]L6

VSS[071]L21

VSS[072]L24

VSS[073]M2

VSS[074]M5

VSS[075]M22

VSS[076]M25

VSS[077]N1

VSS[078]N4

VSS[079]N23

VSS[080]N26

VSS[081]P3

VSS[162]A25

VSS[161]AF21

VSS[160]AF19

VSS[159]AF16

VSS[158]AF13

VSS[157]AF11

VSS[156]AF8

VSS[155]AF6

VSS[154]A2

VSS[153]AE26

VSS[152]AE23

VSS[151]AE19

VSS[083]P21

VSS[084]P24

VSS[085]R2

VSS[086]R5

VSS[087]R22

VSS[088]R25

VSS[089]T1

VSS[090]T4

VSS[091]T23

VSS[092]T26

VSS[093]U3

VSS[094]U6

VSS[095]U21

VSS[096]U24

VSS[097]V2

VSS[098]V5

VSS[099]V22

VSS[100]V25

VSS[101]W1

VSS[102]W4

VSS[103]W23

VSS[104]W26

VSS[105]Y3

VSS[107]Y21

VSS[108]Y24

VSS[109]AA2

VSS[110]AA5

VSS[111]AA8

VSS[112]AA11

VSS[113]AA14

VSS[114]AA16

VSS[115]AA19

VSS[116]AA22

VSS[117]AA25

VSS[118]AB1

VSS[119]AB4

VSS[120]AB8

VSS[121]AB11

VSS[122]AB13

VSS[123]AB16

VSS[124]AB19

VSS[125]AB23

VSS[126]AB26

VSS[127]AC3

VSS[128]AC6

VSS[129]AC8

VSS[130]AC11

VSS[131]AC14

VSS[132]AC16

VSS[133]AC19

VSS[134]AC21

VSS[135]AC24

VSS[136]AD2

VSS[137]AD5

VSS[138]AD8

VSS[139]AD11

VSS[140]AD13

VSS[141]AD16

VSS[142]AD19

VSS[143]AD22

VSS[144]AD25

VSS[145]AE1

VSS[146]AE4

VSS[106]Y6

VSS[001]A4

VSS[149]AE14

VSS[150]AE16

VSS[147]AE8

VSS[163]AF25

C25

10U_0805_6.3V6M

1

2

C17

10U_0805_6.3V6M

1

2

C50

0.1U_0402_10V6K

1

2

C9

10U_0805_6.3V6M

1

2

C29

10U_0805_6.3V6M

1

2

C24

10U_0805_6.3V6M

1

2

C20

10U_0805_6.3V6M

1

2

C40

10U_0805_6.3V6M

1

2

C18

10U_0805_6.3V6M

1

2

C33

10U_0805_6.3V6M

1

2

C45

0.1U_0402_10V6K

1

2

C27

10U_0805_6.3V6M

1

2

C13

10U_0805_6.3V6M

1

2

C34

10U_0805_6.3V6M

1

2

+C423

30

U_

D2

_2

VY

_R

7M

@1

2

C39

10U_0805_6.3V6M

1

2

C38

10U_0805_6.3V6M

1

2

C16

10U_0805_6.3V6M

1

2

C47

0.1U_0402_10V6K

1

2

C21

10U_0805_6.3V6M

1

2

C28

10U_0805_6.3V6M

1

2

C22

10U_0805_6.3V6M

1

2

C36

10U_0805_6.3V6M

1

2

+C43

33

0U

_D

2_

2V

Y_

R7

M

1

2

C11

10U_0805_6.3V6M

1

2

C14

10U_0805_6.3V6M

1

2

C10

10U_0805_6.3V6M

1

2

C35

10U_0805_6.3V6M

1

2

C48

0.1U_0402_10V6K

1

2

C15

10U_0805_6.3V6M

1

2

C26

10U_0805_6.3V6M

1

2

C49

0.1U_0402_10V6K

1

2

C32

10U_0805_6.3V6M

1

2

C30

10U_0805_6.3V6M

1

2

C19

10U_0805_6.3V6M

1

2

+C44

33

0U

_D

2_

2V

Y_

R7

M

1

2

C23

10U_0805_6.3V6M

1

2

C12

10U_0805_6.3V6M

1

2

C37

10U_0805_6.3V6M

1

2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

PM_EXTTS#0

V_DDR_MCH_REF

H_RCOMP

CLKREQ#_7

+H_SWNG

H_D#32

H_D#24

H_D#19

H_D#59

H_D#42

H_D#36

H_D#3

H_D#40

H_RCOMP

H_D#55

H_D#4

H_D#60

H_D#30

H_D#34

H_D#27

H_D#1

H_D#23

H_D#51

H_D#48

H_D#46

H_D#44

H_D#39

H_D#22

H_D#15H_D#14

H_D#9

H_D#56

H_D#54

H_D#8

H_RESET#

H_D#37

H_D#35

H_D#28

H_D#25

H_D#12

H_D#38

H_D#26

H_D#11

H_D#7

H_D#53H_D#52

H_D#41

H_D#18

H_D#10

+H_VREF

H_D#57

H_D#33

H_D#29

+H_SWNG

H_D#6

H_D#45

H_D#43

H_D#20

H_D#61

H_D#17

H_D#63

H_D#58

H_D#21

H_D#16

H_D#50

H_CPUSLP#

H_D#62

H_D#5

H_D#49

H_D#31

H_D#2

H_D#47

H_D#13

H_D#0

H_A#7

H_A#12

H_A#32

H_A#24

H_A#3

H_A#18

H_A#21

H_A#16

H_A#19

H_A#31

H_A#27

H_A#5

H_A#30

H_A#9

H_A#26

H_A#14

H_A#11

H_A#22H_A#23

H_A#34

H_A#20

H_A#8

H_A#15

H_A#6

H_A#25

H_A#17

H_A#4

H_A#13

H_A#33

H_A#29H_A#28

H_A#10

H_A#35

CLK_MCH_BCLK#

H_LOCK#

CLK_MCH_BCLK

H_ADSTB#1

H_DEFER#

H_HITM#

H_ADS#

H_BR0#

H_DBSY#

H_HIT#

H_BPRI#

H_DRDY#

H_BNR#

H_DPWR#

H_ADSTB#0

H_TRDY#

+H_VREF

H_DINV#0

H_DINV#3

H_DINV#1H_DINV#2

H_DSTBN#1

H_DSTBN#3

H_DSTBN#0

H_DSTBN#2

H_DSTBP#2

H_DSTBP#0

H_DSTBP#3

H_DSTBP#1

H_REQ#0

H_REQ#3

H_REQ#1

H_REQ#4

H_REQ#2

H_RS#1H_RS#0

H_RS#2

MCH_CLKSEL0

SMRCOMP_VOL

+CL_VREF

HDA_SDIN2_NB

MCH_ICH_SYNC#CLKREQ#_7

CL_CLK0CL_DATA0

CL_RST#M_PWROK

DMI_TXN0DMI_TXN1DMI_TXN2DMI_TXN3

DMI_TXP0DMI_TXP1DMI_TXP2DMI_TXP3

DMI_RXN0DMI_RXN1DMI_RXN2DMI_RXN3

DMI_RXP0DMI_RXP1DMI_RXP2DMI_RXP3

MCH_SSCDREFCLKMCH_SSCDREFCLK#

CLK_MCH_DREFCLK#CLK_MCH_DREFCLK

CLK_MCH_3GPLL#CLK_MCH_3GPLL

SM_PWROK

TP_SM_DRAMRST#SM_REXT

V_DDR_MCH_REF

M_CLK_DDR3

M_CLK_DDR#0M_CLK_DDR#1M_CLK_DDR#2M_CLK_DDR#3

M_CLK_DDR2

M_CLK_DDR0M_CLK_DDR1

SMRCOMP_VOHSMRCOMP_VOL

M_ODT1

SMRCOMP#

M_ODT3

M_ODT0

M_ODT2

SMRCOMP

DDR_CKE0_DIMMADDR_CKE1_DIMMA

DDR_CKE3_DIMMB

DDR_CS1_DIMMA#

DDR_CKE2_DIMMB

DDR_CS0_DIMMA#

DDR_CS3_DIMMB#DDR_CS2_DIMMB#

HDMICLK_NBHDMIDAT_NB

MCH_CLKSEL1MCH_CLKSEL2

CFG11

CFG9

CFG7

CFG10

CFG6

CFG14

CFG16CFG15

CFG17

CFG8

CFG5

CFG13

CFG18CFG19

CFG12

CFG20

H_DPRSTP#

THERMTRIP#

PM_PWROKPM_EXTTS#1PM_EXTTS#0

PM_BMBUSY#

DPRSLPVR

SMRCOMP_VOH

PLT_RST#

PM_EXTTS#1

TSATN#

H_D#[0..63]7

H_CPUSLP#7H_RESET#6

H_A#[3..35] 6

H_ADS# 6

H_ADSTB#1 6H_ADSTB#0 6

H_BPRI# 6H_BNR# 6

H_DEFER# 6H_BR0# 6

H_DBSY# 6CLK_MCH_BCLK 17CLK_MCH_BCLK# 17H_DPWR# 7H_DRDY# 6H_HIT# 6H_HITM# 6H_LOCK# 6H_TRDY# 6

H_DINV#0 7H_DINV#1 7H_DINV#2 7H_DINV#3 7

H_DSTBN#0 7H_DSTBN#1 7H_DSTBN#2 7H_DSTBN#3 7

H_DSTBP#0 7H_DSTBP#1 7H_DSTBP#2 7H_DSTBP#3 7

H_REQ#3 6H_REQ#2 6H_REQ#1 6

H_REQ#4 6

H_REQ#0 6

H_RS#2 6H_RS#1 6H_RS#0 6

MCH_CLKSEL017MCH_CLKSEL117MCH_CLKSEL217

TSATN# 32

HDA_RST#_NB 21

HDA_SYNC_NB 21HDA_SDOUT_NB 21

MCH_ICH_SYNC# 22

CL_CLK0 22CL_DATA0 22M_PWROK 22,32CL_RST# 22

DMI_TXP0 22

DMI_RXN0 22

DMI_RXP0 22

DMI_TXN0 22DMI_TXN1 22DMI_TXN2 22DMI_TXN3 22

DMI_TXP1 22DMI_TXP2 22DMI_TXP3 22

DMI_RXN1 22DMI_RXN2 22DMI_RXN3 22

DMI_RXP1 22DMI_RXP2 22DMI_RXP3 22

CLK_MCH_3GPLL 17CLK_MCH_3GPLL# 17

MCH_SSCDREFCLK 17MCH_SSCDREFCLK# 17

CLK_MCH_DREFCLK 17CLK_MCH_DREFCLK# 17

DDR_CKE0_DIMMA 15DDR_CKE1_DIMMA 15DDR_CKE2_DIMMB 16DDR_CKE3_DIMMB 16

DDR_CS0_DIMMA# 15DDR_CS1_DIMMA# 15DDR_CS2_DIMMB# 16DDR_CS3_DIMMB# 16

M_CLK_DDR0 15M_CLK_DDR1 15M_CLK_DDR2 16M_CLK_DDR3 16

M_CLK_DDR#0 15M_CLK_DDR#1 15M_CLK_DDR#2 16M_CLK_DDR#3 16

M_ODT0 15M_ODT1 15M_ODT2 16M_ODT3 16

HDMIDAT_NB 34HDMICLK_NB 34

CLKREQ#_7 17

CFG511

CFG911

CFG1111CFG1011

CFG611CFG711

CFG1311CFG1211

CFG1611

CFG1811

CFG2011CFG1911

CFG811

CFG1411CFG1511

CFG1711

PM_BMBUSY#22

H_DPRSTP#7,21,42PM_EXTTS#015

DPRSLPVR22,42

PM_EXTTS#116PM_PWROK22,32

H_THERMTRIP#6,21PLT_RST#20,25,26

HDA_BITCLK_NB 21

HDA_SDIN2 21

V_DDR_MCH_REF15,16

+VCCP+VCCP

+3VS

+1.8V

+1.8V

+VCCP

+1.8V

+VCCP

Title


Date: Sheet of







Montevina UMA 0.1

Cantiga(1/6)-AGTL/DMI/DDR

Custom



Layout Note:H_RCOMP / H_VREF / H_SWNGtrace width and spacing is 10/20 Layout Note: V_DDR_MCH_REFtrace width and spacing is 20/20.Near B3 pinwithin 100 mils from NB

Layout note: Route H_SCOMP and H_SCOMP# with tracewidth, spacing and impedance (55 ohm) same asFSB data traces0621 add CLK and DAT for DVI

0830 Add pull-up and pull-down resistor.

*R44*FollowIntel feedback

Follow Design GuideFor Cantiga: 80.6ohm 80% of 1.8V VCC_SM20% of 1.8V VCC_SM

+V_DDR_MCH_REF generated by DC-DC

T19

T7

R44499_0402_1%

12

R52

2K

_0

40

2_

1%

12

R35 80.6_0402_1%1 2T28

T26

R737 56_0402_5%1 2

T30

R40 10K_0402_5%1 2

T11

C5

32

.2U

_0

60

3_

6.3

V4

Z

1

2

R36 0_0402_5%1 2

T35

T25

R41100_0402_5%

1 2

T18

T37

T86

R46

1K

_0

40

2_

1%

12

C5

2

0.0

1U

_0

40

2_

25

V7

K

1

2

T10

C5

4

0.0

1U

_0

40

2_

25

V7

K

1

2

T20

R54

24

.9_

04

02

_1

%

12

T17

R4810K_0402_1%

12

T85

R420_0402_5%

1 2

T29R39 10K_0402_5%1 2

PM

MISC

NC

DDR CLK/ CONTROL/COMPENSATION

CLK

DMI

CFG

RSVD

GRAPHICS VID

ME

HDA

U2B

CANTIGA ES_FCBGA1329

SA_CK_0AP24

SA_CK_1AT21

SB_CK_0AV24

SA_CK#_0AR24

SA_CK#_1AR21

SB_CK#_0AU24

SA_CKE_0BC28

SA_CKE_1AY28

SB_CKE_0AY36

SB_CKE_1BB36

SA_CS#_0BA17

SA_CS#_1AY16

SB_CS#_0AV16

SB_CS#_1AR13

SM_DRAMRST#BC36

SA_ODT_0BD17

SA_ODT_1AY17

SB_ODT_0BF15

SB_ODT_1AY13

SM_RCOMPBG22

SM_RCOMP#BH21

CFG_18P29

CFG_19R28

CFG_2P25

CFG_0T25

CFG_1R25

CFG_20T28

CFG_3P20

CFG_4P24

CFG_5C25

CFG_6N24

CFG_7M24

CFG_8E21

CFG_9C23

CFG_10C24

CFG_11N21

CFG_12P21

CFG_13T21

CFG_14R20

CFG_15M20

CFG_16L21

CFG_17H21

PM_SYNC#R29

PM_EXT_TS#_0N33

PM_EXT_TS#_1P32

PWROKAT40

RSTIN#AT11

DPLL_REF_CLKB38

DPLL_REF_CLK#A38

DPLL_REF_SSCLKE41

DPLL_REF_SSCLK#F41

DMI_RXN_0AE41

DMI_RXN_1AE37

DMI_RXN_2AE47

DMI_RXN_3AH39

DMI_RXP_0AE40

DMI_RXP_1AE38

DMI_RXP_2AE48

DMI_RXP_3AH40

DMI_TXN_0AE35

DMI_TXN_1AE43

DMI_TXN_2AE46

DMI_TXN_3AH42

DMI_TXP_0AD35

DMI_TXP_1AE44

DMI_TXP_2AF46

DMI_TXP_3AH43

RESERVEDAL34

RESERVEDAN35

RESERVEDAK34

RESERVEDAM35

RESERVEDBG23

RESERVEDBF23

RESERVEDBH18

RESERVEDBF18

PM_DPRSTP#B7

SB_CK_1AU20

SB_CK#_1AV20

RESERVEDAY21

RESERVEDAH9

RESERVEDAH10

RESERVEDAH12

RESERVEDAH13

RESERVEDM36

RESERVEDN36

RESERVEDR33

RESERVEDT33

GFX_VID_0B33

GFX_VID_1B32

GFX_VID_2G33

GFX_VID_3F33

GFX_VR_ENC34

SM_RCOMP_VOHBF28

SM_RCOMP_VOLBH28

THERMTRIP#T20

DPRSLPVRR32

RESERVEDK12

CL_CLKAH37

CL_DATAAH36

CL_PWROKAN36

CL_RST#AJ35

CL_VREFAH34

NCA47

NCBG48

NCBF48

NCBD48

NCBC48

NCBH47

NCBG47

NCBE47

NCBH46

NCBF46

NCBG45

NCBH44

NCBH43

NCBH6

NCBH5

NCBG4

SDVO_CTRLCLKG36

SDVO_CTRLDATAE36

CLKREQ#K36

RESERVEDT24

ICH_SYNC#H36

TSATN#B12

PEG_CLK#E43

PEG_CLKF43

NCBH3

GFX_VID_4E33

RESERVEDB31

DDPC_CTRLCLKN28

NCBF3

NCBH2

NCBG2

NCBE2

NCBG1

NCBF1

NCBD1

NCBC1

NCF1

SM_VREFAV42

SM_PWROKAR36

SM_REXTBF17

RESERVEDM1

HDA_BCLKB28

HDA_RST#B30

HDA_SDIB29

HDA_SDOC29

HDA_SYNCA28

DDPC_CTRLDATAM28

RESERVEDB2

T13

C59

0.1

U_

04

02

_1

6V

4Z

1

2

R4510K_0402_1%

12

C58

0.1

U_

04

02

_1

6V

4Z

1

2

T12

T31

R37 499_0402_1%1 2

T23T22

T27

T15

R431K_0402_1%

12

R210

33_0402_5%

1 2

R34 80.6_0402_1%

1 2

R311K_0402_1%

12

T14

T36

R47

22

1_

06

03

_1

%

12

C560.1U_0402_16V4Z

1

2

C5

12

.2U

_0

60

3_

6.3

V4

Z

1

2

R331K_0402_1%

12

T16

C57

0.1

U_

04

02

_1

6V

4Z

1

2

T24

HOST

U2A


H_A#_10P16

H_A#_11R16

H_A#_12N17

H_A#_13M13

H_A#_14E17

H_A#_15P17

H_A#_16F17

H_A#_17G20

H_A#_18B19

H_A#_19J16

H_A#_20E20

H_A#_21H16

H_A#_22J20

H_A#_23L17

H_A#_24A17

H_A#_25B17

H_A#_26L16

H_A#_27C21

H_A#_28J17

H_A#_29H20

H_A#_3A14

H_A#_30B18

H_A#_31K17

H_A#_4C15

H_A#_5F16

H_A#_6H13

H_A#_7C18

H_A#_8M16

H_A#_9J13

H_ADS#H12

H_ADSTB#_0B16

H_ADSTB#_1G17

H_BNR#A9

H_BPRI#F11

H_BREQ#G12

HPLL_CLK#AH6

H_CPURST#C12

HPLL_CLKAH7

H_D#_0F2

H_REQ#_2F13

H_REQ#_3B13

H_D#_1G8

H_D#_10M9

H_D#_20L6

H_D#_30N10

H_D#_40AA8

H_D#_50AA2

H_D#_60AE11

H_D#_8D4

H_D#_9H3

H_DBSY#B10

H_D#_11M11

H_D#_12J1

H_D#_13J2

H_D#_14N12

H_D#_15J6

H_D#_16P2

H_D#_17L2

H_D#_18R2

H_D#_19N9

H_D#_2F8

H_D#_21M5

H_D#_22J3

H_D#_23N2

H_D#_24R1

H_D#_25N5

H_D#_26N6

H_D#_27P13

H_D#_28N8

H_D#_29L7

H_D#_3E6

H_D#_31M3

H_D#_32Y3

H_D#_33AD14

H_D#_34Y6

H_D#_35Y10

H_D#_36Y12

H_D#_37Y14

H_D#_38Y7

H_D#_39W2

H_D#_4G2

H_D#_41Y9

H_D#_42AA13

H_D#_43AA9

H_D#_44AA11

H_D#_45AD11

H_D#_46AD10

H_D#_47AD13

H_D#_48AE12

H_D#_49AE9

H_D#_5H6

H_D#_51AD8

H_D#_52AA3

H_D#_53AD3

H_D#_54AD7

H_D#_55AE14

H_D#_56AF3

H_D#_57AC1

H_D#_58AE3

H_D#_59AC3

H_D#_6H2

H_D#_61AE8

H_D#_62AG2

H_D#_63AD6

H_D#_7F6

H_DEFER#E9

H_DINV#_0J8

H_DINV#_1L3

H_DINV#_2Y13

H_DINV#_3Y1

H_DPWR#J11

H_DRDY#F9

H_DSTBN#_0L10

H_DSTBN#_1M7

H_DSTBN#_2AA5

H_DSTBN#_3AE6

H_DSTBP#_0L9

H_DSTBP#_1M8

H_DSTBP#_2AA6

H_DSTBP#_3AE5

H_AVREFA11

H_DVREFB11

H_TRDY#C9

H_HIT#H9

H_HITM#E12

H_LOCK#H11

H_REQ#_0B15

H_REQ#_1K13

H_REQ#_4B14

H_A#_32B20

H_A#_33F21

H_A#_34K21

H_A#_35L20

H_SWINGC5

H_CPUSLP#E11

H_RCOMPE3

H_RS#_0B6

H_RS#_1F12

H_RS#_2C8

R323.01K_0402_1%

12

C55

0.1

U_

04

02

_1

6V

4Z

@1

2

R55

10

0_

04

02

_1

%

12

T8

R38 10K_0402_5% 1 2

T9

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

DDR_A_BS0DDR_A_BS1DDR_A_BS2

DDR_A_MA0DDR_A_MA1

DDR_A_MA4

DDR_A_MA2DDR_A_MA3

DDR_A_MA5DDR_A_MA6DDR_A_MA7DDR_A_MA8DDR_A_MA9

DDR_A_MA12DDR_A_MA13

DDR_A_MA11DDR_A_MA10

DDR_A_DQS#0DDR_A_DQS#1




DDR_A_DQS0DDR_A_DQS1DDR_A_DQS2DDR_A_DQS3DDR_A_DQS4DDR_A_DQS5DDR_A_DQS6DDR_A_DQS7

DDR_A_DM7

DDR_A_DM5

DDR_A_DM2DDR_A_DM1

DDR_A_DM6

DDR_A_DM4

DDR_A_DM0

DDR_A_DM3

DDR_A_CAS#DDR_A_RAS#

DDR_A_WE#

DDR_A_D63DDR_A_D62DDR_A_D61DDR_A_D60DDR_A_D59DDR_A_D58DDR_A_D57DDR_A_D56DDR_A_D55DDR_A_D54

DDR_A_D51DDR_A_D50DDR_A_D49DDR_A_D48

DDR_A_D53DDR_A_D52

DDR_A_D47DDR_A_D46


DDR_A_D45DDR_A_D44

DDR_A_D39DDR_A_D38


DDR_A_D37DDR_A_D36

DDR_A_D31DDR_A_D30


DDR_A_D15DDR_A_D14

DDR_A_D11DDR_A_D10DDR_A_D9

DDR_A_D13DDR_A_D12

DDR_A_D29DDR_A_D28

DDR_A_D23DDR_A_D22


DDR_A_D21DDR_A_D20

DDR_A_D8


DDR_A_D7DDR_A_D6


DDR_A_MA14

DDR_B_RAS#

DDR_B_MA14

DDR_B_MA10

DDR_B_DQS#7

DDR_B_DQS#2

DDR_B_DQS7

DDR_B_DQS2

DDR_B_DM3

DDR_B_D51

DDR_B_D39

DDR_B_D18

DDR_B_MA7

DDR_B_DQS0

DDR_B_D7

DDR_B_D54

DDR_B_D4

DDR_B_D36

DDR_B_D21

DDR_B_MA4

DDR_B_DM0

DDR_B_D62

DDR_B_D34

DDR_B_D19

DDR_B_D13

DDR_B_MA5

DDR_B_MA11

DDR_B_BS2

DDR_B_D42

DDR_B_D35

DDR_B_D31

DDR_B_D24

DDR_B_D15

DDR_B_MA3

DDR_B_DQS#6

DDR_B_DM7

DDR_B_D50

DDR_B_D38

DDR_B_D32

DDR_B_D23

DDR_B_MA6

DDR_B_D6

DDR_B_D53

DDR_B_D33

DDR_B_D3

DDR_B_D20

DDR_B_DQS#5

DDR_B_BS1

DDR_B_D61

DDR_B_D59

DDR_B_D46

DDR_B_D12

DDR_B_DQS3

DDR_B_D47

DDR_B_D30

DDR_B_D14

DDR_B_MA0

DDR_B_DQS#0

DDR_B_DM6

DDR_B_DM4

DDR_B_D55

DDR_B_D44

DDR_B_D29

DDR_B_D27

DDR_B_D22

DDR_B_MA13

DDR_B_MA1

DDR_B_D57

DDR_B_D52

DDR_B_D2

DDR_B_D17

DDR_B_DQS#1

DDR_B_DQS1

DDR_B_D9

DDR_B_D60

DDR_B_D58

DDR_B_D45

DDR_B_DQS4

DDR_B_MA9

DDR_B_DQS#4

DDR_B_DM5

DDR_B_DM2

DDR_B_D49

DDR_B_D41

DDR_B_D28

DDR_B_D11

DDR_B_WE#

DDR_B_MA12

DDR_B_D56

DDR_B_D48

DDR_B_D16

DDR_B_D1

DDR_B_MA2

DDR_B_DQS5

DDR_B_D8

DDR_B_D63

DDR_B_D37

DDR_B_D0 DDR_B_BS0

DDR_B_D5

DDR_B_MA8

DDR_B_DQS#3

DDR_B_DQS6

DDR_B_DM1

DDR_B_CAS#

DDR_B_D43

DDR_B_D40

DDR_B_D26DDR_B_D25

DDR_B_D10

DDR_A_BS0 15DDR_A_BS1 15DDR_A_BS2 15

DDR_A_D[0..63]15

DDR_A_MA[0..14] 15

DDR_A_DQS#[0..7] 15

DDR_A_DQS[0..7] 15

DDR_A_DM[0..7] 15

DDR_A_CAS# 15DDR_A_RAS# 15

DDR_A_WE# 15

DDR_B_D[0..63]16

DDR_B_BS0 16DDR_B_BS1 16DDR_B_BS2 16

DDR_B_CAS# 16DDR_B_RAS# 16

DDR_B_WE# 16

DDR_B_DM[0..7] 16

DDR_B_DQS[0..7] 16

DDR_B_DQS#[0..7] 16

DDR_B_MA[0..14] 16

Title


Date: Sheet of







Montevina UMA 0.1

Cantiga(2/6)-DDR2 A/B CH

Custom



DDR SYSTEM MEMORY A

U2D


SA_DQ_0AJ38

SA_DQ_1AJ41

SA_DQ_10AU40

SA_DQ_11AT38

SA_DQ_12AN41

SA_DQ_13AN39

SA_DQ_14AU44

SA_DQ_15AU42

SA_DQ_16AV39

SA_DQ_17AY44

SA_DQ_18BA40

SA_DQ_19BD43

SA_DQ_2AN38

SA_DQ_20AV41

SA_DQ_21AY43

SA_DQ_22BB41

SA_DQ_23BC40

SA_DQ_24AY37

SA_DQ_25BD38

SA_DQ_26AV37

SA_DQ_27AT36

SA_DQ_28AY38

SA_DQ_29BB38

SA_DQ_3AM38

SA_DQ_30AV36

SA_DQ_31AW36

SA_DQ_32BD13

SA_DQ_33AU11

SA_DQ_34BC11

SA_DQ_35BA12

SA_DQ_36AU13

SA_DQ_37AV13

SA_DQ_38BD12

SA_DQ_39BC12

SA_DQ_4AJ36

SA_DQ_40BB9

SA_DQ_41BA9

SA_DQ_42AU10

SA_DQ_43AV9

SA_DQ_44BA11

SA_DQ_45BD9

SA_DQ_46AY8

SA_DQ_47BA6

SA_DQ_48AV5

SA_DQ_49AV7

SA_DQ_5AJ40

SA_DQ_50AT9

SA_DQ_51AN8

SA_DQ_52AU5

SA_DQ_53AU6

SA_DQ_54AT5

SA_DQ_55AN10

SA_DQ_56AM11

SA_DQ_57AM5

SA_DQ_58AJ9

SA_DQ_59AJ8

SA_DQ_6AM44

SA_DQ_60AN12

SA_DQ_61AM13

SA_DQ_62AJ11

SA_DQ_63AJ12

SA_DQ_7AM42

SA_DQ_8AN43

SA_DQ_9AN44

SA_BS_0BD21

SA_BS_1BG18

SA_BS_2AT25

SA_CAS#BD20

SA_DM_0AM37

SA_DM_1AT41

SA_DM_2AY41

SA_DM_3AU39

SA_DM_4BB12

SA_DM_5AY6

SA_DM_6AT7

SA_DQS_0AJ44

SA_DQS_1AT44

SA_DQS_2BA43

SA_DQS_3BC37

SA_DQS_4AW12

SA_DQS_5BC8

SA_DQS_6AU8

SA_DQS_7AM7

SA_DM_7AJ5

SA_DQS#_0AJ43

SA_DQS#_1AT43

SA_DQS#_2BA44

SA_DQS#_3BD37

SA_DQS#_4AY12

SA_DQS#_5BD8

SA_DQS#_6AU9

SA_DQS#_7AM8

SA_MA_0BA21

SA_MA_1BC24

SA_MA_10BC21

SA_MA_11BG26

SA_MA_12BH26

SA_MA_13BH17

SA_MA_2BG24

SA_MA_3BH24

SA_MA_4BG25

SA_MA_5BA24

SA_MA_6BD24

SA_MA_7BG27

SA_MA_8BF25

SA_MA_9AW24

SA_RAS#BB20

SA_WE#AY20

SA_MA_14AY25

DDR SYSTEM MEMORY B

U2E


SB_DQ_0AK47

SB_DQ_1AH46

SB_DQ_10BA48

SB_DQ_11AY48

SB_DQ_12AT47

SB_DQ_13AR47

SB_DQ_14BA47

SB_DQ_15BC47

SB_DQ_16BC46

SB_DQ_17BC44

SB_DQ_18BG43

SB_DQ_19BF43

SB_DQ_2AP47

SB_DQ_20BE45

SB_DQ_21BC41

SB_DQ_22BF40

SB_DQ_23BF41

SB_DQ_24BG38

SB_DQ_25BF38

SB_DQ_26BH35

SB_DQ_27BG35

SB_DQ_28BH40

SB_DQ_29BG39

SB_DQ_3AP46

SB_DQ_30BG34

SB_DQ_31BH34

SB_DQ_32BH14

SB_DQ_33BG12

SB_DQ_34BH11

SB_DQ_35BG8

SB_DQ_36BH12

SB_DQ_37BF11

SB_DQ_38BF8

SB_DQ_39BG7

SB_DQ_4AJ46

SB_DQ_40BC5

SB_DQ_41BC6

SB_DQ_42AY3

SB_DQ_43AY1

SB_DQ_44BF6

SB_DQ_45BF5

SB_DQ_46BA1

SB_DQ_47BD3

SB_DQ_48AV2

SB_DQ_49AU3

SB_DQ_5AJ48

SB_DQ_50AR3

SB_DQ_51AN2

SB_DQ_52AY2

SB_DQ_53AV1

SB_DQ_54AP3

SB_DQ_55AR1

SB_DQ_56AL1

SB_DQ_57AL2

SB_DQ_58AJ1

SB_DQ_59AH1

SB_DQ_6AM48

SB_DQ_60AM2

SB_DQ_61AM3

SB_DQ_62AH3

SB_DQ_63AJ3

SB_DQ_7AP48

SB_DQ_8AU47

SB_DQ_9AU46

SB_BS_0BC16

SB_BS_1BB17

SB_BS_2BB33

SB_CAS#BG16

SB_DM_0AM47

SB_DM_1AY47

SB_DM_2BD40

SB_DM_3BF35

SB_DM_4BG11

SB_DM_5BA3

SB_DM_6AP1

SB_DM_7AK2

SB_DQS_0AL47

SB_DQS_1AV48

SB_DQS_2BG41

SB_DQS_3BG37

SB_DQS_4BH9

SB_DQS_5BB2

SB_DQS_6AU1

SB_DQS_7AN6

SB_DQS#_0AL46

SB_DQS#_1AV47

SB_DQS#_2BH41

SB_DQS#_3BH37

SB_DQS#_4BG9

SB_DQS#_5BC2

SB_DQS#_6AT2

SB_DQS#_7AN5

SB_MA_0AV17

SB_MA_1BA25

SB_MA_10BB16

SB_MA_11AW33

SB_MA_12AY33

SB_MA_13BH15

SB_MA_2BC25

SB_MA_3AU25

SB_MA_4AW25

SB_MA_5BB28

SB_MA_6AU28

SB_MA_7AW28

SB_MA_8AT33

SB_MA_9BD33

SB_MA_14AU33

SB_RAS#AU17

SB_WE#BF14

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

CFG5

TMDS_B_HPD#

VSYNCCRT_VSYNC

HSYNC

3VDDCCL3VDDCDA

M_REDM_GREEN

CRT_HSYNC

TV_COMPSTV_LUMATV_CRMA

M_BLUE

LVDS_B1+LVDS_B2+

LVDS_B0+

LVDS_B3+

LVDS_B1-LVDS_B0-

LVDS_B2-LVDS_B3-

LVDS_A1+LVDS_A2+

LVDS_A0+

LVDS_A3+

LVDS_A0-

LVDS_A2-LVDS_A1-

LVDS_A3-

LVDS_BCLK+LVDS_BCLK-LVDS_ACLK+LVDS_ACLK-

ENAVDD

DDC2_CLKDDC2_DATA

ENBKL

LVDS_ACLK+

LVDS_ACLK-

LVDS_A0-

LVDS_A0+

LVDS_A1-

LVDS_A1+

LVDS_A2+

LVDS_A2-

TMDS_BDATA1#TMDS_BDATA2#

TMDS_BDATA0#TMDS_BCLK#

TMDS_BDATA2

TMDS_BDATA0TMDS_BCLK

TMDS_BDATA1

ENBKL

LVDS_BCLK+

LVDS_BCLK-

LVDS_B0-

LVDS_B0+

LVDS_B1-

LVDS_B1+

LVDS_B2+

LVDS_B2-

NB_BKLT_CTRL

CFG59

CRT_VSYNC18

3VDDCDA18CRT_HSYNC18

3VDDCCL18

ENAVDD19

DDC2_CLK19DDC2_DATA19

ENBKL32

M_BLUE18M_GREEN18M_RED18

TMDS_B_HPD# 34

LVDS_A0+19

LVDS_A1+19

LVDS_A2+19

LVDS_A0-19

LVDS_A1-19

LVDS_A2-19

LVDS_ACLK-19

LVDS_ACLK+19

CFG69

CFG79

CFG89

CFG99

CFG109

CFG119

CFG129

CFG139

CFG149

CFG159

CFG179

CFG189

CFG169

CFG199

CFG209

TMDS_B_CLK 34

TMDS_B_CLK# 34

TMDS_B_DATA0 34

TMDS_B_DATA0# 34

TMDS_B_DATA1 34

TMDS_B_DATA1# 34

TMDS_B_DATA2 34

TMDS_B_DATA2# 34

LVDS_B0+19

LVDS_B1+19

LVDS_B2+19

LVDS_B0-19

LVDS_B1-19

LVDS_B2-19

LVDS_BCLK-19

LVDS_BCLK+19

NB_BKLT_CTRL19+VCC_PEG

+3VS

+3VS

+3VS

+3VS

Title


Date: Sheet of







Montevina UMA 0.1

Cantiga(3/6)-VGA/LVDS/TV

Custom



PEGCOMP trace widthand spacing is 20/25 mils. 000 = FSB1066MHzCFG[4:3] ReservedCFG6 0 = The iTPM Host Interface isenable1 = The iTPM Host Interface isdisable *ReservedCFG10 (Default)11 = NormalOperation10 = All Z ModeEnabled00 = Reserved01 = XOR ModeEnabled *0 =Enable1 = Disable *CFG9 (PCIE GraphicsLane Reversal)CFG[2:0] FSB Freqselect

ReservedReservedCFG[15:14]

Strap Pin Table

ReservedCFG[18:17] (Lane number inOrder)

Others =Reserved011 = FSB667MHz010 = FSB800MHz*

1 = Reverse Lane0 = Reverse Lane,15->0,14->11 =Enabled0 = NormalOperation 0 =Disabled *

0 = DMI x2*

*

*1 = PCIE/SDVO are operatingsimu.0 = Only PCIE or SDVO isoperational. *

1 = Normal Operation,Lane Numberin order1 = DMI x40 =(TLS)chiper suite with noconfidentiality1 =(TLS)chiper suite withconfidentialityCFG5 (DMI select)

CFG19 (DMI Lane Reversal)CFG16 (FSB Dynamic ODT)CFG7

CFG20CFG11CFG[13:12](XOR/ALLZ)CFG8 Follow Intel DG &Checklist

For 3GWWAN

(Intel ManagementEngine Crypto strap)(PCIELookbackenable)(PCIE/SDVOconcurrent)

Follow Intel DG &ChecklistFollow Intel DG &ChecklistFor 3GWWAN

R6830.1_0402_1%

1 2

C277 0.1U_0402_10V7K1 2

C15000.1U_0402_10V6K

@1

2

R734.02K_0402_1%

@ 1 2

C278 0.1U_0402_10V7K1 2

R60 4.75K_0402_1%1 2

R6930.1_0402_1%

1 2

LVDS

PCI-EXPRESS GRAPHICS

TV

VGA

U2C


PEG_COMPIT37

PEG_COMPOT36

PEG_RX#_0H44

PEG_RX#_1J46

PEG_RX#_2L44

PEG_RX#_3L40

PEG_RX#_4N41

PEG_RX#_5P48

PEG_RX#_6N44

PEG_RX#_7T43

PEG_RX#_8U43

PEG_RX#_9Y43

PEG_RX#_10Y48

PEG_RX#_11Y36

PEG_RX#_12AA43

PEG_RX#_13AD37

PEG_RX#_14AC47

PEG_RX#_15AD39

PEG_RX_0H43

PEG_RX_1J44

PEG_RX_2L43

PEG_RX_3L41

PEG_RX_4N40

PEG_RX_5P47

PEG_RX_6N43

PEG_RX_7T42

PEG_RX_8U42

PEG_RX_9Y42

PEG_RX_10W47

PEG_RX_11Y37

PEG_RX_12AA42

PEG_RX_13AD36

PEG_RX_14AC48

PEG_RX_15AD40

PEG_TX#_0J41

PEG_TX#_10Y40

PEG_TX#_3M40

PEG_TX#_4M42

PEG_TX#_5R48

PEG_TX#_6N38

PEG_TX#_7T40

PEG_TX#_8U37

PEG_TX#_9U40

PEG_TX#_1M46

PEG_TX#_11AA46

PEG_TX#_12AA37

PEG_TX#_13AA40

PEG_TX#_14AD43

PEG_TX#_15AC46

PEG_TX#_2M47

PEG_TX_0J42

PEG_TX_1L46

PEG_TX_2M48

PEG_TX_3M39

PEG_TX_4M43

PEG_TX_5R47

PEG_TX_6N37

PEG_TX_7T39

PEG_TX_8U36

PEG_TX_9U39

PEG_TX_10Y39

PEG_TX_11Y46

PEG_TX_12AA36

PEG_TX_13AA39

PEG_TX_14AD42

PEG_TX_15AD46

L_CTRL_CLKM32

L_CTRL_DATAM33

L_DDC_CLKK33

L_DDC_DATAJ33

L_VDD_ENM29

LVDS_IBGC44

LVDS_VBGB43

LVDS_VREFHE37

LVDS_VREFLE38

LVDSA_CLK#C41

LVDSA_CLKC40

LVDSA_DATA#_0H47

LVDSA_DATA#_1E46

LVDSA_DATA#_2G40

LVDSA_DATA_1D45

LVDSA_DATA_2F40

LVDSB_CLK#B37

LVDSB_CLKA37

LVDSB_DATA#_0A41

LVDSB_DATA#_1H38

LVDSB_DATA#_2G37

LVDSB_DATA_1G38

LVDSB_DATA_2F37

L_BKLT_ENG32

TVA_DACF25

TVB_DACH25

TVC_DACK25

TV_RTNH24

CRT_BLUEE28

CRT_DDC_CLKH32

CRT_DDC_DATAJ32

CRT_GREENG28

CRT_HSYNCJ29

CRT_TVO_IREFE29

CRT_REDJ28

CRT_IRTNG29

CRT_VSYNCL29

LVDSA_DATA_0H48

LVDSB_DATA_0B42

L_BKLT_CTRLL32

TV_DCONSEL_0C31

TV_DCONSEL_1E32

LVDSA_DATA#_3A40

LVDSA_DATA_3B40

LVDSB_DATA#_3J37

LVDSB_DATA_3K37

C281 0.1U_0402_10V7K1 2

R406 0_0402_5%1 2

C276 0.1U_0402_10V7K1 2

R812.21K_0402_1%

@ 1 2

R772.21K_0402_1%

@ 1 2

R742.21K_0402_1%@

12

C15010.1U_0402_10V6K

@1

2

R58 10K_0402_5%1 2

T40

C274 0.1U_0402_10V7K1 2

R59 10K_0402_5%1 2

C620.1U_0402_10V6K

@1

2

R852.21K_0402_1%

@ 1 2

T39

R862.21K_0402_1%

@ 1 2

R66

15

0_

04

02

_1

%

12

R65

15

0_

04

02

_1

%

12

R782.21K_0402_1%

@ 1 2

C15030.1U_0402_10V6K

@1

2

C280 0.1U_0402_10V7K1 2

R822.21K_0402_1%

@ 1 2

R762.21K_0402_1%

@ 1 2

R714.02K_0402_1%@

12

R61

75

_0

40

2_

1%

12

C630.1U_0402_10V6K

@1

2

R832.21K_0402_1%

@ 1 2

T50

R842.21K_0402_1%

@ 1 2

C600.1U_0402_10V6K

@1

2

R57

49.9_0402_1%1 2

R724.02K_0402_1%

@ 1 2

R792.21K_0402_1%

@ 1 2

R148

100K_0402_5%

1 2

T48

T38

C15020.1U_0402_10V6K

@1

2

R802.21K_0402_1%

@ 1 2

C279 0.1U_0402_10V7K1 2

C610.1U_0402_10V6K

@1

2

R63

75

_0

40

2_

1%

12

R701.02K_0402_1%

12

T49

R64 2.2K_0402_5%@ 1 2

C275 0.1U_0402_10V7K1 2

R62

75

_0

40

2_

1%

12

R754.02K_0402_1%

@ 1 2

R872.21K_0402_1%

@ 1 2

R67

15

0_

04

02

_1

%

12

T41

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

+1.05VS_A_SM

+1.05VS_A_SM_CK

+1.8V_TXLVDS

+3VS+3VS_DAC_BG

+3VS_DAC_CRT

+3VS+3VS_TVDAC

+1.8V_TXLVDS

+1.8V

+1.05VS_HPLL

+1.05VS_MPLL

+VCCP

+1.05VS_PEGPLL +VCCP

+VCCP+V1.05VS_AXF

+VCCP+1.05VS_DMI

+1.8V+1.8V_SM_CK

+1.05VS_DPLLA +VCCP

+1.5VS+1.5VS_TVDAC

+VCC_PEG

+VCCP

+1.8V

+1.8V_LVDS

+1.5VS_PEG_BG

+1.5VS

+1.05VS_PEGPLL

+VCCP+1.05VS_DPLLB

+VCCP

+VCCP

+VCCP

+3VS

+VCCP_D

+3VS_HV

+VCCP

+3VS

+3VS

+1.5VS+1.5VS_QDAC

+3VS_DAC_CRT

+3VS_DAC_BG

+1.05VS_MPLL

+1.05VS_DPLLB

+1.05VS_HPLL

+1.05VS_DPLLA

+3VS_TVDAC

+1.5VS

+1.5VS_TVDAC

+1.5VS_QDAC

+1.05VS_PEGPLL

+1.05VS_HPLL

+1.8V_LVDS

+1.05VS_DMI

+VCC_PEG

+3VS_HV

+1.8V_TXLVDS

+1.8V_SM_CK

+V1.05VS_AXF

Title


Date: Sheet of


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.


Montevina UMA 0.1

Cantiga(4/6)-PWRCustom



40 mils

73mA

2.68mA

852mA

64.8mA

720mA

24mA

139.2mA

50mA

414uA

13.2mA

64.8mA

26mA

321.35mA

118.8mA

124mA

105.3mA

1732mA

456mA

TVA 24.15mATVB 39.48mATVX 24.15mA

26mA

50mA

58.67mA

48.363mA

157.2mA

50mA

60.31mA

**RED Mark: Means UMA & dis@ Power select**~It check by INTEL Graphics Disable Guidelines~

C1

09

0.1

U_

04

02

_1

6V

4Z

1

2

C8

4

10

U_

08

05

_1

0V

4Z

1

2

C8

6

0.1

U_

04

02

_1

6V

4Z

1

2

C97

1U_0603_10V4Z

1

2

C6

8

0.0

22

U_

04

02

_1

6V

7K

1

2

C100

10U_0805_10V4Z

1

2

C8

1

4.7

U_

08

05

_1

0V

4Z

1

2

R99

0_0805_5%

1 2

C7

4

10

U_

08

05

_1

0V

4Z

1

2

C8

2

2.2

U_

08

05

_1

6V

4Z

1

2

R93

0_0603_5%

1 2

D3

CH751H-40PT_SOD323-2

2 1

L1

BLM18PG121SN1D_06031 2

POWER

CRT

PLL

A PEG

A SM

TV

D TV/CRT

LVDS

VTTLF

PEG

SM CK

AXF

VTT

DMI

HV

A CK

A LVDS

HDA

U2H


VTTV3

VTTU3

VTTV2

VTTU2

VCCA_PEG_BGAD48

VCCA_PEG_PLLAA48

VCCA_CRT_DACB27

VCCA_CRT_DACA26

VCCA_DPLLAF47

VCCA_DPLLBL48

VCCA_HPLLAD1

VCCA_LVDSJ48

VCCA_MPLLAE1

VCCA_TV_DACB24

VCCA_TV_DACA24

VCCD_PEG_PLLAA47

VTTU6

VTTT6

VTTU5

VTTT5

VTTT8

VTTU7

VTTT7

VCCD_HPLLAF1

VTTU13

VTTT13

VTTT12

VTTU11

VTTT11

VTTU10

VTTT10

VTTU9

VTTT9

VTTU8

VTTU12

VCCA_SM_CKAP28

VCCA_SM_CKAN28

VCCA_DAC_BGA25

VCCD_TVDACM25

VTTLFA8

VTTLFL1

VTTLFAB2

VCC_DMIAH48

VCC_DMIAF48

VCC_SM_CKBF21

VCC_SM_CKBH20

VCC_SM_CKBG20

VCC_SM_CKBF20

VCCD_LVDSM38

VCCD_QDACL28

VCC_AXFB22

VCC_AXFB21

VCC_AXFA21

VCCA_SMAR20

VCCA_SMAP20

VCCA_SMAN20

VCCA_SMAR17

VCCA_SMAP17

VCCA_SMAT16

VCCA_SMAR16

VCCA_SMAP16

VCC_TX_LVDSK47

VSSA_LVDSJ47

VCC_HVC35

VCC_HVB35

VCC_PEGV48

VCCD_LVDSL37

VCC_PEGU48

VCC_PEGV47

VCC_PEGU47

VCC_PEGU46

VCCA_SMAN17

VCCA_SM_CKAP25

VCCA_SM_CKAN25

VCCA_SM_CKAN24

VCCA_SM_CK_NCTFAM28

VCCA_SM_CK_NCTFAM26

VCCA_SM_CK_NCTFAM25

VCCA_SM_CK_NCTFAL25

VCCA_SM_CK_NCTFAM24

VCCA_SM_CK_NCTFAL24

VCCA_SM_CK_NCTFAM23

VTTT2

VTTV1

VTTU1

VCC_HVA35

VCC_DMIAH47

VCC_DMIAG47

VSSA_DAC_BGB25

VCCA_SM_CK_NCTFAL23

VCC_HDAA32

R100

0_0805_5%

1 2

R103

0_0603_5%

1 2

C7

6

0.1

U_

04

02

_1

6V

4Z

1

2

C1

05

0.1

U_

04

02

_1

6V

4Z

1

2

+

C7

1

22

0U

_D

2_

4V

M

1

2

C1

16

10

00

P_

04

02

_5

0V

7K

1

2

C7

2

4.7

U_

08

05

_1

0V

4Z

1

2

C1

11

0.4

7U

_0

60

3_

10

V7

K

1

2

C1

06

0.1

U_

04

02

_1

6V

4Z

1

2

C7

3

0.1

U_

04

02

_1

6V

4Z

1

2

C99

0.1U_0402_16V4Z

1

2

C1

18

0.1

U_

04

02

_1

6V

4Z

1

2

C1

04

1U

_0

60

3_

10

V4

Z

1

2

+C9

8

22

0U

_D

2_

4V

M

1

2

C1

14

1U

_0

60

3_

10

V4

Z

1

2

C9

2

0.0

22

U_

04

02

_1

6V

7K

1

2

C1

12

0.4

7U

_0

60

3_

10

V7

K

1

2

R97

0_0603_5%

1 2

C1

01

10

U_

08

05

_1

0V

4Z

1

2

C89

0.1U_0402_16V4Z

1

2

+

C9

4

220U_D2_4VM

1

2

R106

0_0402_5%

1 2

C9

3

0.1

U_

04

02

_1

6V

4Z

1

2

C1

07

0.1

U_

04

02

_1

6V

4Z

1

2

C7

9

1U

_0

60

3_

10

V4

Z

1

2

C9

1

10

U_

08

05

_1

0V

4Z

1

2

R91

BLM18PG181SN1D_06031 2

C9

0

0.1

U_

04

02

_1

6V

4Z

1

2

C7

8

10

U_

08

05

_1

0V

4Z

1

2

R101

MBK2012121YZF_0805

1 2

R107

0_0603_5%1 2

C1

13

10

U_

08

05

_1

0V

4Z

1

2

C7

0

10

U_

08

05

_1

0V

4Z

1

2

R98

MBK2012121YZF_08051 2

C1

20

0.1

U_

04

02

_1

6V

4Z

1

2

R105

10_0402_5%

1 2

R94

10U_FLC-453232-100K_0.25A_10%1 2

C7

5

0.0

22

U_

04

02

_1

6V

7K

1

2

C1

10

0.4

7U

_0

60

3_

10

V7

K

1

2

C9

5

10

U_

08

05

_1

0V

4Z

1

2

C8

3

10

U_

08

05

_1

0V

4Z

@ 1

2

C1

19

0.0

22

U_

04

02

_1

6V

7K

1

2

R88

BLM18PG181SN1D_06031 2

R95

0_0805_5%

1 2

R108

0_0603_5%1 2

C8

7

10

U_

08

05

_1

0V

4Z

1

2

C1

03

10

U_

08

05

_1

0V

4Z

1

2

C6

9

0.1

U_

04

02

_1

6V

4Z

1

2

C1

17

0.0

22

U_

04

02

_1

6V

7K

1

2

C102

1U_0603_10V4Z

1

2

C8

5

0.1

U_

04

02

_1

6V

4Z

1

2

R104

0_0603_5%

1 2

C8

0

0.4

7U

_0

60

3_

10

V7

K

1

2

C96

4.7U_0805_10V4Z

1

2

R96

0_0603_5%

@

1 2

R9010U_FLC-453232-100K_0.25A_10%

1 2

R112

100_0603_1%1 2

R111

BLM18PG181SN1D_06031 2

C1

08

10

U_

08

05

_1

0V

4Z

1

2

C88

1000P_0402_50V7K

1

2

R102

0_0805_5%1 2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

VCCSM_LF2VCCSM_LF3

VCCSM_LF1

VCCSM_LF6VCCSM_LF7

VCCSM_LF4VCCSM_LF5

+VCCP

+VCCP

+VCCP

+VCCP

+1.8V

Title


Date: Sheet of







Montevina UMA 0.1

Cantiga(5/6)-PWR/GND

Custom



3000mA

6326.84mA

Extnal Graphic: 1210.34mAintegrated Graphic: 1930.4mA0317 change value

Reserve for WWAN

SI-1 Add C for GM47

C127

0.1U_0402_16V4Z

1

2

C1

44

1U

_0

60

3_

10

V4

Z

1

2

POWER

VCC NCTF

VCC CORE

U2F


VCC_NCTFAM32

VCC_NCTFAC30

VCC_NCTFAJ29

VCC_NCTFAK25

VCC_NCTFAA32

VCC_NCTFY32

VCC_NCTFW32

VCC_NCTFU32

VCC_NCTFAM30

VCC_NCTFAL30

VCC_NCTFAK30

VCC_NCTFAG30

VCC_NCTFAF30

VCC_NCTFAE30

VCC_NCTFAL32

VCC_NCTFW30

VCC_NCTFV30

VCC_NCTFAK32

VCC_NCTFAH29

VCC_NCTFAG29

VCC_NCTFAE29

VCC_NCTFAL28

VCC_NCTFAK28

VCC_NCTFAL26

VCC_NCTFAK26

VCC_NCTFAJ32

VCC_NCTFAK24

VCC_NCTFAH32

VCC_NCTFAG32

VCC_NCTFAE32

VCC_NCTFAC32

VCC_NCTFAC29

VCC_NCTFAA29

VCC_NCTFY29

VCC_NCTFW29

VCC_NCTFV29

VCC_NCTFU30

VCC_NCTFAL29

VCC_NCTFAK29

VCC_NCTFAH30

VCC_NCTFAB30

VCC_NCTFAA30

VCC_NCTFY30

VCCAG34

VCCAC34

VCCAB34

VCCAA34

VCCY34

VCCV34

VCCU34

VCCAM33

VCCAK33

VCCAJ33

VCCAG33

VCCAF33

VCCAE33

VCCAC33

VCCAA33

VCCY33

VCCW33

VCCV33

VCCU33

VCCAH28

VCCAF28

VCCAC28

VCCAA28

VCCAJ26

VCCAG26

VCCAE26

VCCAC26

VCCAH25

VCCAG25

VCCAF25

VCCAG24

VCCAJ23

VCCAH23

VCCAF23

VCCT32

VCC_NCTFAK23

C1

40

0.1

U_

04

02

_1

6V

4Z

1

2

POWER

VCC SM

VCC GFX

VCC GFX NCTF

VCC SM LF

U2G


VCC_SMAY32

VCC_SMBF31

VCC_SMAW29

VCC_SMBD32

VCC_SMBC32

VCC_SMBB32

VCC_SMBA32

VCC_SMAW32

VCC_SMAV32

VCC_SMAU32

VCC_SMAT32

VCC_SMAR32

VCC_SMAP32

VCC_SMAN32

VCC_SMBH31

VCC_SMBG31

VCC_SMAN33

VCC_SMBG30

VCC_SMBH29

VCC_SMBG29

VCC_SMBF29

VCC_SMBD29

VCC_SMBC29

VCC_SMBB29

VCC_SMBA29

VCC_SMAY29

VCC_SMBH32

VCC_SMAV29

VCC_SMAU29

VCC_SMAT29

VCC_SMAR29

VCC_AXG_NCTFV23

VCC_AXG_NCTFAM21

VCC_AXG_NCTFAL21

VCC_AXG_NCTFAK21

VCC_AXG_NCTFW21

VCC_AXG_NCTFV21

VCC_AXG_NCTFU21

VCC_AXG_NCTFAM20

VCC_AXG_NCTFAK20

VCC_AXG_NCTFW20

VCC_AXG_NCTFV28

VCC_AXG_NCTFU20

VCC_AXG_NCTFAM19

VCC_AXG_NCTFAL19

VCC_AXG_NCTFAK19

VCC_AXG_NCTFAJ19

VCC_AXG_NCTFAH19

VCC_AXG_NCTFAG19

VCC_AXG_NCTFAF19

VCC_AXG_NCTFAE19

VCC_AXG_NCTFAB19

VCC_AXG_NCTFW26

VCC_AXG_NCTFAA19

VCC_AXG_NCTFY19

VCC_AXG_NCTFW19

VCC_AXG_NCTFV19

VCC_AXG_NCTFU19

VCC_AXG_NCTFAM17

VCC_AXG_NCTFAK17

VCC_AXG_NCTFAH17

VCC_AXG_NCTFAG17

VCC_AXG_NCTFAF17

VCC_AXG_NCTFV26

VCC_AXG_NCTFAE17

VCC_AXG_NCTFAC17

VCC_AXG_NCTFAB17

VCC_AXG_NCTFY17

VCC_AXG_NCTFW17

VCC_AXG_NCTFV17

VCC_AXG_NCTFAM16

VCC_AXG_NCTFAL16

VCC_AXG_NCTFAK16

VCC_AXG_NCTFAJ16

VCC_AXG_NCTFW25

VCC_AXG_NCTFAH16

VCC_AXG_NCTFAG16

VCC_AXG_NCTFAF16

VCC_AXG_NCTFAE16

VCC_AXG_NCTFAC16

VCC_AXG_NCTFAB16

VCC_AXG_NCTFAA16

VCC_AXG_NCTFV25

VCC_AXG_NCTFW24

VCC_AXG_NCTFV24

VCC_AXG_NCTFW23

VCC_SMAP29

VCC_SMBG32

VCC_SMBF32

VCC_AXG_NCTFW28

VCC_SMAP33

VCC_AXGY26

VCC_AXGAE25

VCC_AXGAB25

VCC_AXGAA25

VCC_AXGAE24

VCC_AXGAC24

VCC_AXGAA24

VCC_AXGY24

VCC_AXGAE23

VCC_AXGAC23

VCC_AXGAB23

VCC_AXGAA23

VCC_AXGAJ21

VCC_AXGAG21

VCC_AXGAE21

VCC_AXGAC21

VCC_AXGAA21

VCC_AXGY21

VCC_AXGAH20

VCC_AXGAF20

VCC_AXGAE20

VCC_AXGAC20

VCC_AXGAB20

VCC_AXGAA20

VCC_AXGT17

VCC_AXGAM15

VCC_AXGAL15

VCC_AXGAJ15

VCC_AXGAH15

VCC_AXGAF15

VCC_AXGAB15

VCC_SM_LFAV44

VCC_SM_LFBA37

VCC_SM_LFAM40

VCC_SM_LFAV21

VCC_SM_LFAY5

VCC_SM_LFAM10

VCC_SM_LFBB13

VCC_AXGT16

VCC_AXGAG15

VCC_AXGAA15

VCC_AXGY15

VCC_AXGV15

VCC_AXGU15

VCC_AXGAN14

VCC_AXGAM14

VCC_AXGU14

VCC_AXGT14

VCC_AXG_SENSEAJ14

VSS_AXG_SENSEAH14

VCC_AXG_NCTFY16

VCC_AXG_NCTFW16

VCC_AXG_NCTFV16

VCC_AXG_NCTFU16

VCC_SM/NCBA36

VCC_SM/NCBB24

VCC_SM/NCBD16

VCC_SM/NCBB21

VCC_SM/NCAW16

VCC_SM/NCAW13

VCC_SM/NCAT13

VCC_AXGAE15

C1495

22

P_

04

02

_2

5V

8K

@1

2

C1

43

0.4

7U

_0

40

2_

6.3

V6

K

1

2

C134

1U_0603_10V4Z

1

2

T43PAD

C1

25

0.1

U_

04

02

_1

6V

4Z

1

2

C1

30

10

U_

08

05

_1

0V

4Z

1

2

C1

39

0.1

U_

04

02

_1

6V

4Z

1

2

C1494

22

P_

04

02

_2

5V

8K

@1

2

C1

45

1U

_0

60

3_

10

V4

Z

1

2

+

C1

26

33

0U

_D

2E

_2

.5V

M_

R7

1

2

C1

24

10

U_

08

05

_1

0V

4Z

1

2

C128

0.22U_0402_10V4Z

1

2

C1492

22

P_

04

02

_2

5V

8K

@1

2

C1493

22

P_

04

02

_2

5V

8K

@1

2

C136

10U_0805_10V4Z

1

2

+ C1508

33

0U

_D

2E

_2

.5V

M_

R7

GM47@1

2

C129

4.7U_0603_6.3V6M

1

2

C1491

22

P_

04

02

_2

5V

8K

@1

2

C1

33

0.2

2U

_0

40

2_

10

V4

Z

1

2

C1

42

0.2

2U

_0

60

3_

10

V7

K

1

2

C1

32

0.2

2U

_0

40

2_

10

V4

Z

1

2

C1

23

0.0

1U

_0

40

2_

16

V7

K

1

2

T42PAD

C1490

22

P_

04

02

_2

5V

8K

@1

2

+

C1

31

22

0U

_D

2_

4V

M

1

2

C1

22

10

U_

08

05

_1

0V

4Z

1

2

C138

0.1U_0402_16V4Z

1

2

C137

10U_0805_10V4Z

1

2

C1

41

0.2

2U

_0

60

3_

10

V7

K

1

2

+ C135

33

0U

_D

2E

_2

.5V

M_

R7

1

2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet of







Montevina UMA 0.1

Cantiga(6/6)-PWR/GND

Custom



VSS

VSS NCTF

VSS SCB

NC

U2J


VSSBG21

VSSAW21

VSSAU21

VSSAP21

VSSAN21

VSSAH21

VSSAF21

VSSAB21

VSSR21

VSSM21

VSSJ21

VSSG21

VSSBC20

VSSBA20

VSSAW20

VSSAT20

VSSAJ20

VSSAG20

VSSY20

VSSN20

VSSK20

VSSF20

VSSC20

VSSA20

VSSBG19

VSSA18

VSSBG17

VSSBC17

VSSAW17

VSSAT17

VSSR17

VSSM17

VSSH17

VSSC17

VSSBA16

VSSAU16

VSSAN16

VSSN16

VSSK16

VSSG16

VSSE16

VSSBG15

VSSW15

VSSA15

VSSBG14

VSSAA14

VSSC14

VSSBG13

VSSBC13

VSSBA13

VSSAN13

VSSAJ13

VSSAE13

VSSN13

VSSL13

VSSG13

VSSE13

VSSBF12

VSSAV12

VSSAT12

VSSAM12

VSSAA12

VSSJ12

VSSA12

VSSBD11

VSSBB11

VSSAY11

VSSAN11

VSSAH11

VSSY11

VSSN11

VSSG11

VSSC11

VSSBG10

VSSAV10

VSSAT10

VSSAJ10

VSSAE10

VSSAA10

VSSBH8

VSSB9

VSSG9

VSSAD9

VSSAM9

VSSAN9

VSSBC9

VSSM10

VSSBF9

VSSAH8

VSSY8

VSSL8

VSSE8

VSSB8

VSSAY7

VSSAU7

VSSAN7

VSSAJ7

VSSAE7

VSSAA7

VSSN7

VSSJ7

VSSBG6

VSSBD6

VSSAV6

VSSAT6

VSSAC15

VSSAM6

VSSM6

VSSC6

VSSBA5

VSSAH5

VSSAD5

VSSY5

VSSL5

VSSJ5

VSSH5

VSSF5

VSSBE4

VSSBC3

VSSAV3

VSSAL3

VSS_NCTFAF32

VSS_NCTFAB32

VSS_NCTFV32

VSS_NCTFAJ30

VSS_NCTFAM29

VSS_NCTFAF29

VSS_NCTFAB29

VSS_NCTFU26

VSS_NCTFU23

VSS_NCTFAL20

VSS_NCTFV20

VSS_NCTFAC19

VSS_NCTFAL17

VSS_NCTFAJ17

VSS_NCTFAA17

VSS_NCTFU17

VSS_SCBBH48

VSS_SCBBH1

VSS_SCBA48

VSS_SCBC1

VSS_SCBA3

NCE1

NCD2

NCC3

NCB4

NCA5

NCA6

NCA43

NCA44

NCB45

NCC46

NCD47

NCB47

NCA46

NCF48

NCE48

NCC48

NCB48

VSSR3

VSSP3

VSSBA2

VSSAR2

VSSAU2

VSSAP2

VSSF3

VSSAW2

VSSAE2

VSSAF2

VSSAH2

VSSAJ2

VSSAD2

VSSAC2

VSSY2

VSSM2

VSSK2

VSSAM1

VSSAA1

VSSP1

VSSH1

VSSBB8

VSSAV8

VSSAT8

VSSU24

VSSU28

VSSU25

VSSU29

VSSL12

VSS

U2I


VSSAU48

VSSA23

VSSAR48

VSSAL48

VSSBB47

VSSAW47

VSSAN47

VSSAJ47

VSSAF47

VSSAD47

VSSAB47

VSSY47

VSST47

VSSN47

VSSL47

VSSG47

VSSBD46

VSSBA46

VSSAV46

VSSAR46

VSSAM46

VSSV46

VSSR46

VSSP46

VSSH46

VSSF46

VSSBF44

VSSAH44

VSSAD44

VSSAA44

VSSY44

VSSU44

VSST44

VSSM44

VSSF44

VSSBC43

VSSAV43

VSSAU43

VSSAM43

VSSJ43

VSSC43

VSSBG42

VSSAY42

VSSAT42

VSSAN42

VSSAJ42

VSSAE42

VSSN42

VSSL42

VSSBD41

VSSAU41

VSSAM41

VSSAH41

VSSAD41

VSSAA41

VSSY41

VSSU41

VSST41

VSSM41

VSSG41

VSSB41

VSSBG40

VSSBB40

VSSAV40

VSSAN40

VSSH40

VSSE40

VSSAT39

VSSAM39

VSSAJ39

VSSAE39

VSSN39

VSSL39

VSSB39

VSSBH38

VSSBC38

VSSBA38

VSSAU38

VSSAH38

VSSAD38

VSSAA38

VSSY38

VSSU38

VSST38

VSSJ38

VSSF38

VSSC38

VSSBD36

VSSAM36

VSSAE36

VSSP36

VSSL36

VSSJ36

VSSF36

VSSB36

VSSAH35

VSSAA35

VSSY35

VSSU35

VSST35

VSSBF34

VSSAM34

VSSAJ34

VSSAF34

VSSAE34

VSSW34

VSSB34

VSSA34

VSSBG33

VSSBC33

VSSBA33

VSSAV33

VSSAR33

VSSAL33

VSSAH33

VSSAB33

VSSP33

VSSL33

VSSH33

VSSN32

VSSK32

VSSF32

VSSC32

VSSA31

VSSAN29

VSST29

VSSN29

VSSK29

VSSH29

VSSF29

VSSA29

VSSBG28

VSSBD28

VSSBA28

VSSAV28

VSSAT28

VSSAR28

VSSAJ28

VSSAG28

VSSAE28

VSSAB28

VSSY28

VSSP28

VSSK28

VSSH28

VSSF28

VSSC28

VSSBF26

VSSAH26

VSSAF26

VSSAB26

VSSAA26

VSSC26

VSSB26

VSSBH25

VSSBD25

VSSBB25

VSSAV25

VSSAR25

VSSAJ25

VSSAC25

VSSY25

VSSN25

VSSL25

VSSJ25

VSSG25

VSSE25

VSSBF24

VSSBF37

VSSBB37

VSSAW37

VSSAT37

VSSAN37

VSSAJ37

VSSH37

VSSC37

VSSBG36

VSSAU36

VSSAT24

VSSAH24

VSSAB24

VSSL24

VSSAY46

VSSG24

VSSE24

VSSAG23

VSSB23

VSSAY24

VSSAJ24

VSSAF24

VSSR24

VSSK24

VSSJ24

VSSF24

VSSBH23

VSSY23

VSSAK15

VSSAD12

VSSAJ6

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

V_DDR_MCH_REF

M_CLK_DDR0

M_CLK_DDR1

M_CLK_DDR#0

M_CLK_DDR#1

DDR_CKE1_DIMMA

DDR_CS0_DIMMA#

CLK_SMBCLK

DDR_A_MA1

DDR_A_MA10

DDR_A_MA3

DDR_A_MA9 DDR_A_MA7DDR_A_MA12

DDR_A_MA5

DDR_A_WE#

DDR_A_D8

DDR_A_D17DDR_A_D16

DDR_A_D27DDR_A_D26

DDR_A_DQS1

DDR_A_DQS0

DDR_A_DQS2

DDR_A_DM3

DDR_A_DM1

DDR_A_DM2

DDR_A_DM0

DDR_A_DQS4

DDR_A_DQS6

DDR_A_DQS7

CLK_SMBDATA

DDR_CKE0_DIMMA

DDR_A_MA8

DDR_CS1_DIMMA#

DDR_A_MA11

DDR_A_MA2DDR_A_MA0

DDR_A_MA4

DDR_A_MA6

DDR_A_CAS#

DDR_A_BS1DDR_A_RAS#

DDR_A_D20DDR_A_D21

DDR_A_D53DDR_A_D52

DDR_A_D55

DDR_A_DM6

DDR_A_DM4

DDR_A_DM5

DDR_A_DM7

DDR_A_MA13

DDR_A_DQS5

DDR_A_BS0

DDR_A_BS2

DDR_A_DQS#0

DDR_A_DQS#1

DDR_A_DQS#2

DDR_A_DQS3DDR_A_DQS#3

DDR_A_DQS#4

DDR_A_DQS#5

DDR_A_DQS#6

DDR_A_DQS#7

M_ODT1

M_ODT0


DDR_A_D49DDR_A_D48

DDR_A_D42

DDR_A_D39

DDR_A_D22DDR_A_D23

DDR_A_D12DDR_A_D13

DDR_A_D10 DDR_A_D14DDR_A_D11 DDR_A_D15

DDR_A_D9

DDR_A_D0DDR_A_D1

DDR_A_D3DDR_A_D2

DDR_A_D4

DDR_A_D6

DDR_A_D5

DDR_A_D7

DDR_A_D18DDR_A_D19

DDR_A_D31DDR_A_D30


DDR_A_D36

DDR_A_D38

DDR_A_D37

DDR_A_D35

DDR_A_D32DDR_A_D33

DDR_A_D34

DDR_A_D44DDR_A_D45

DDR_A_D40DDR_A_D41

DDR_A_D46

DDR_A_D60DDR_A_D61 DDR_A_D57

DDR_A_D56

DDR_A_D58DDR_A_D63

DDR_A_D59DDR_A_D62

M_ODT1DDR_CS1_DIMMA#

DDR_A_MA14

DDR_A_MA11

DDR_A_D47 DDR_A_D43

DDR_A_BS2DDR_CKE0_DIMMADDR_A_MA12DDR_A_MA9

DDR_A_MA8DDR_A_MA5DDR_A_MA1DDR_A_MA3

DDR_A_BS0DDR_A_MA10DDR_A_CAS#DDR_A_WE#

DDR_CKE1_DIMMADDR_A_MA14

DDR_A_MA6DDR_A_MA7

DDR_A_MA2DDR_A_MA4DDR_A_BS1DDR_A_MA0

DDR_A_MA13M_ODT0DDR_CS0_DIMMA#DDR_A_RAS#

DDR_A_D[0..63]10

DDR_CKE0_DIMMA9

DDR_A_BS210

DDR_A_BS010

DDR_A_WE#10

DDR_A_CAS#10

M_ODT19

DDR_CS1_DIMMA#9

M_CLK_DDR0 9M_CLK_DDR#0 9

DDR_CKE1_DIMMA 9

DDR_A_BS1 10DDR_A_RAS# 10DDR_CS0_DIMMA# 9

M_CLK_DDR#1 9

M_ODT0 9

V_DDR_MCH_REF 9,16

M_CLK_DDR1 9

PM_EXTTS#0 9

CLK_SMBDATA16,17,24CLK_SMBCLK16,17,24

DDR_A_DQS#[0..7]10

DDR_A_DM[0..7]10

DDR_A_DQS[0..7]10

DDR_A_MA[0..14]10

+1.8V

+3VS

+1.8V

+1.8V

+0.9V

+0.9V

+0.9V

Title


Date: Sheet of







Montevina UMA 0.1

DDRII-SODIMM SLOT1

Custom



Layout Note:Place these resistorclosely JP3,alltrace length Max=1.5"

Layout Note:Place nearJP3Layout Note:Place one cap close to every 2pullup resistors terminated to +0.9VS

SO-DIMM AC

16

9

0.1

U_

04

02

_1

6V

4Z

1

2

C1

60

0.1

U_

04

02

_1

6V

4Z

1

2

RP1156_0404_4P2R_5%

1 42 3

R1

16

10

K_

04

02

_5

%

12

C171

2.2

U_

06

03

_6

.3V

4Z 1

2

C172

0.1

U_

04

02

_1

6V

4Z

1

2

RP33

56_8P4R_0.05

1 82 73 64 5

C1

63

0.1

U_

04

02

_1

6V

4Z

1

2

C1

51

0.1

U_

04

02

_1

6V

4Z

1

2

RP34

56_8P4R_0.05

1 82 73 64 5

C1

70

0.1

U_

04

02

_1

6V

4Z

1

2

C1

68

0.1

U_

04

02

_1

6V

4Z

1

2

C1

61

0.1

U_

04

02

_1

6V

4Z

1

2

R117 56_0402_5%

1 2

C1

64

0.1

U_

04

02

_1

6V

4Z

1

2

C1

55

2.2

U_

08

05

_1

6V

4Z

1

2

C1

67

0.1

U_

04

02

_1

6V

4Z

1

2

C1

65

0.1

U_

04

02

_1

6V

4Z

1

2

C1

62

0.1

U_

04

02

_1

6V

4Z

1

2

+

C1

50

33

0U

_D

2E

_2

.5V

M_

R7

1

2

RP29

56_8P4R_0.05

1 82 73 64 5

RP32

56_8P4R_0.05

1 82 73 64 5

C1

66

0.1

U_

04

02

_1

6V

4Z

1

2

C1

59

0.1

Documents

Compal LA-4732P - Schematics. 5 5 4 4 3 3 2 2 1 1 D D C C B B A A Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING