Computer Architecture · 2020. 4. 8. · SCE,Sasaram2019 Page 3 Introduction to computer organization and CPU Design Historically there have been 2 types of Computers: 1. Fixed Program

SCE,Sasaram2019 Page 1

Govt. of Bihar

Department of Science and Technology

Computer Architecture

By Priya Pankaj Kumar Assistant Professor(CSE)

M.Tech(CSE)

Shershah College of Engineering, Sasaram (Affiliated By Aryabhatta Knowledge University, Patna)


Syllabus

05 1X02COMPUTER ARCHITECTURE

L-T-P : 3-0–0 Credit : 3

SL CHAPTER TOPICS LECTURES

1 Introduction Computer Arithmetic, Instruction sets, Introduction to

computer organization, CPU Design. Lecture : 8

2 Micro programmed

Control

Control Memory, Address sequencing, Micro

program example.

Lecture : 5

3 Memory and Input-

Output Systems

Hierarchical memory structure, Cache memories, set

Associative memory, Virtual Memory, Paging,

Segmentation, Input-Output Interface. Asynchronous

Data transfer, Programmed I.Q., Interrupts, Direct

Memory access

Lecture : 15

4 Introduction to

Parallel Processing

Evolution of computer systems (RISC vs. CISC),

Parallelism in uniprocessor systems, Architectural

classification schemes Lecture : 5

5 Principles of

Pipelining and

Vector Processing

Pipelining, Overlapped parallelism, Principles of

designing pipelines Processors, Vector processing

requirements Lecture : 5

6 Structures &

Algorithms for

Array Processors

SIMD Array processors, SIMD Interconnection

networks Lecture : 4

Text Books :

1. Computer System architecture, 3e by M. Morris Mano, Pearson Education.

2. Computer architecture and parallel processing by Kai Hwang, Briggs, McGraw Hill.

3. Computer Architecture by Carter, Tata McGraw Hill.

References

1. Tutorial : https://www.geeksforgeeks.org/computer-organization-and-architecture-tutorials/#bci

2. https://en.wikipedia.org/wiki/Booth%27s_multiplication_algorithm

3. https://courses.cs.washington.edu/courses/cse378/00sp/Sec5-1.htm

4.

https://www.geeksforgeeks.org/computer-organization-and-architecture-tutorials/#bci

https://en.wikipedia.org/wiki/Booth%27s_multiplication_algorithm

https://courses.cs.washington.edu/courses/cse378/00sp/Sec5-1.htm


Introduction to computer organization and CPU Design

Historically there have been 2 types of Computers:

1. Fixed Program Computers – Their function is very specific and they couldn’t be

programmed, e.g. Calculators.

2. Stored Program Computers – These can be programmed to carry out many different

tasks, applications are stored on them.

The modern computers are based on a stored-program concept introduced by John Von

Neumann. In this stored-program concept, programs and data are stored in a separate storage

unit called memories. This novel idea meant that a computer built with this architecture

would be much easier to reprogram.

The basic structure is like,

Von Neumann computer have three basic unit:

1. The Central Processing Unit (CPU)

2. The Main Memory Unit

3. The Input/Output Device

Let’s consider them in details.

Control Unit –A control unit (CU) handles all processor control signals. It directs all

input and output flow, fetches code for instructions and controlling how data moves around

the system.


Arithmetic and Logic Unit (ALU) – The arithmetic logic unit is that part of the CPU

that handles all the calculations the CPU may need, e.g. Addition, Subtraction, Comparisons.

It performs Logical Operations, Bit Shifting Operations, and Arithmetic Operation.

Figure – Basic CPU structure, illustrating ALU

Main Memory Unit (Registers) –

1. Accumulator: Stores the results of calculations made by ALU.

2. Program Counter (PC): Keeps track of the memory location of the next

instructions to be dealt with. The PC then passes this next address to Memory

Address Register (MAR).

3. Memory Address Register (MAR): It stores the memory locations of

instructions that need to be fetched from memory or stored into memory.

4. Memory Data Register (MDR): It stores instructions fetched from memory or

any data that is to be transferred to, and stored in, memory.

5. Current Instruction Register (CIR): It stores the most recently fetched

instructions while it is waiting to be coded and executed.

6. Instruction Buffer Register (IBR): The instruction that is not to be executed

immediately is placed in the instruction buffer register IBR.


Input/Output Devices – Program or data is read into main memory from the input

device or secondary storage under the control of CPU input instruction. Output

devices are used to output the information from a computer. If some results are

evaluated by computer and it is stored in the computer, then with the help of output

devices, we can present it to the user.

Buses – Data is transmitted from one part of a computer to another, connecting all

major internal components to the CPU and memory, by the means of Buses. Types:

1. Data Bus: It carries data among the memory unit, the I/O devices, and the

processor.

2. Address Bus: It carries the address of data (not the actual data) between

memory and processor.

3. Control Bus: It carries control commands from the CPU (and status signals

from other devices) in order to control and coordinate all the activities within

the computer.

Von Neumann bottleneck –

Whatever we do to enhance performance, we cannot get away from the fact that

instructions can only be done one at a time and can only be carried out sequentially.

Both of these factors hold back the competence of the CPU. This is commonly referred to as

the ‘Von Neumann bottleneck’.

Note : This architecture is very important and is used in our PCs and even in Super

Computers.

Single Accumulator based CPU organization

The computers, present in the early days of computer history, had accumulator based

CPUs. In this type of CPU organization, the accumulator register is used implicitly for

processing all instructions of a program and store the results into the accumulator. The

instruction format that is used by this CPU Organisation is One address field. Due to this the

CPU is known as One Address Machine.

The main points about Single Accumulator based CPU Organisation are:

1. In this CPU Organization, the first ALU operand is always stored into the

Accumulator and the second operand is present either in Registers or in the

Memory.

2. Accumulator is the default address thus after data manipulation the results are

stored into the accumulator.


3. One address instruction is used in this type of organization.

The format of instruction is: Opcode + Address

Op-code indicates the type of operation to be performed.

Mainly two types of operation are performed in single accumulator based CPU

organization:

1. Data transfer operation – In this type of operation, the data is transferred from a

source to a destination.

For ex: LOAD X, STORE Y

Here LOAD is memory read operation that is data is transfer from memory to

accumulator and STORE is memory write operation that is data is transfer from accumulator

to memory.

2. ALU operation – In this type of operation, arithmetic operations are performed on the

data.

For ex: MULT X

where X is the address of the operand. The MULT instruction in this example

performs the operation,

AC <-- AC * M[X]

AC is the Accumulator and M[X] is the memory word located at location X.

This type of CPU organization is first used in PDP-8 processor and is used for

process control and laboratory applications. It has been totally replaced by the introduction of

the new general register based CPU.

Advantages –

One of the operands is always held by the accumulator register. This results in short

instructions and less memory space.

Instruction cycle takes less time because it saves time in instruction fetching from

memory.

Disadvantages –

When complex expressions are computed, program size increases due to the usage of

many short instructions to execute it. Thus memory size increases.

As the number of instructions increases for a program, the execution time increases.

General Register based CPU Organization

When we are using multiple general purpose registers, instead of single accumulator

register, in the CPU Organization then this type of organization is known as General register

based CPU Organization. In this type of organization, computer uses two or three address


fields in their instruction format. Each address field may specify a general register or a

memory word. For example:

MULT R1, R2, R3

This is an instruction of an arithmetic multiplication written in assembly language. It

uses three address fields R1, R2 and R3. The meaning of this instruction is:

R1 <-- R2 * R3

This instruction also can be written using only two address fields as:

MULT R1, R2

In this instruction, the destination register is the same as one of the source registers.

This means the operation

R1 <-- R1 * R2

The use of large number of registers results in short program with limited instructions.

The advantages of General register based CPU organization –

Efficiency of CPU increases as there are large number of registers are used in this

organization.

Less memory space is used to store the program since the instructions are written in

compact way.

The disadvantages of General register based CPU organization –

Care should be taken to avoid unnecessary usage of registers. Thus, compilers need to

be more intelligent in this aspect.

Since large number of registers is used, thus extra cost is required in this organization.

Stack based CPU Organization

The computers which use Stack based CPU Organization are based on a data structure

called stack. Stack is a list of data words. It uses Last In First Out (LIFO)access method

which is the most popular access method in most of the CPU. A register is used to store the

address of the top most element of the stack which is known as Stack pointer (SP).

The main two operations that are performed on the operators of the stack are Push

and Pop. These two operations are performed from one end only


1. Push – This operation is results in inserting one operand at the top of the stack and it

decrease the stack pointer register. The format of the PUSH instruction is:

PUSH

It inserts the data word at specified address to the top of the stack. It can be

implemented as:

//decrement SP by 1

SP <-- SP - 1

//store the content of specified memory address

//into SP; i.e, at top of stack

SP <-- (memory address)

2. Pop - This operation is results in deleting one operand from the top of the stack and it

increase the stack pointer register. The format of the POP instruction is

POP

It deletes the data word at the top of the stack to the specified address. It can be

implemented as:

//transfer the content of SP (i.e, at top most data)

//into specified memory location

(memory address) <-- SP

//increment SP by 1

SP <-- SP + 1

Operation type instruction do not need address field in this CPU organization. This is

because the operation is performed on the two operands that are on the top of the stack.

For example:

SUB

This instruction contains the op-code only with no address field. It pops the two top data

from the stack, subtracting the data, and pushing the result into the stack at the top.

PDP-11, Intel’s 8085 and HP 3000 are some of the examples of the stack organized

computers.


The advantages of Stack based CPU organization –

Efficient computation of complex arithmetic expressions.

Execution of instructions is fast because operand data are stored in consecutive

memory locations.

Length of instruction is short as they do not have address field.

The disadvantages of Stack based CPU organization –

The size of the program increases.

Computer Arithmetic Information in digital computers is stored in memory or processor register. Register

contain either data or control information. Control information is a bit or a group of bits used

to specify the sequence of command signals needed for manipulation of data in other

registers. Data are numbers and other binary-coded information that are operated on to

achieve required computational results.

Data types are classified in three categories –

1. Numbers

2. Letters

3. Discrete symbols.

All types of data, except binary numbers, are represented in computer’s registers in

binary-coded form. This is because registers are made up of flip-flops. The binary number

system is the most natural system to use in a digital computer.

Number System :

A Number system of base or radix (r) is a system that uses distinct symbols for r

digits.

Numbers are represented by a string of digit symbols.

Radix should always greater than the digit value.

To determine the value that the number (string of digit symbol) represents, it is

necessary to multiply each digit by an integer (position of digit in string) power of r

and then form the sum of all weighted digits.

Eg (1234)r = 1 x r3 + 2 x r

2 +3 x r

1 +4 x r

0

Decimal Number System

Radix =10

Digits are 0,1,2,3,4,5,6,7,8, and 9

The string of digits (724.5)10 = 7 x 102 + 2 x 10

1 + 4 x 10

0 + 5 x 10

-1

Binary Number System

Radix =2


Digits are 0 and 1

The string of digits (bits in case of binary) (101101)2 = 1 x 25 + 0 x 2

4 + 1x 2

3 + 1 x 2

2

+ 0 x 21 + 1 x 2

0 = (45)10

Octal Number System

Radix = 8

Digits are 0,1,2,3,4,5,6, and 7

The string of digits (736.4)8 = 7 x 82 + 3 x 8

1 + 6 x 8

0 + 4 x 8

-1 = (478.5)10

Hexadecimal Number System

Radix =16

Digits are 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E, and F

A,B,C,D,E and F digits used corresponds to the decimal number 10,11,12,13,14, and

15 respectively.

The string of digits (F3)16 = F x 161 + 3 x 16

0 = 15 x 16 + 3 = (243)10

Note : To distinguish between different radix numbers, the digits will be enclosed in

parenthesis and the radix of the number inserted as a subscript.

Conversion from decimal to its equivalent representation in the radix ‘r’ system :

Separate the number into its integer and fraction parts.

Convert each part separately.

The conversion of a decimal integer into a base r representation is done by successive

divisions by r and accumulation of the remainders.

The conversion of a decimal fraction to radix r representation is accomplished by

successive multiplications by r and accumulation of the integer digits so obtained.

Example: Let’s convert 256 to base 6.

256 = 6 ∗ 42 + 4 d0 = 4

42 = 6 ∗ 7 + 0 d1 = 0

7 = 6 ∗ 1 + 1 d2 = 1

1 = 6 ∗ 0 + 1 d3 = 1

So the answer is 1104. Check it by converting (1104)6 to base 10

In Case of Fractional part 0.90234375 = (????)4?

Answer:

We multiply 0.90234375 by 4 and get 3.609375. So the first (leftmost) digit is 3

and we repeat the process.

0.609375 ∗ 4 = 2.4375, so the next digit is 2 and we are left with 0.4375


0.4375 ∗ 4 = 1.75, so the next digit is 1 and we are left with 0.75

0.75 ∗ 4 = 3.0, so the next digit is 3 and we are left with 0, so we are done and

answer is (.3213)4 .

The registers in a digital computer contain many bits. Specifying the content of

registers by their binary values will require a long string of binary digits.

It is more convenient to specify content of registers by their octal or hexadecimal

equivalent.

The number of digits is reduced by one third in the octal designation and by one fourth

in the hexadecimal designation.

Computer manuals invariably chose either the octal or the hexadecimal designation for

specifying contents of registers.

Eg :

Binary Number : 111111111111 : has 12 digits

Octal Representation : 7777(111 111 111 111) : has 4 digits

Hexadecimal representation: FFF(1111 1111 1111) : has 3 digits

Binary Code

A Binary code is a Group of n bits that assumes up to 2n distinct combinations of 1s

and 0s.

Each Combination represent one element of the set that is being coded.

o Eg: A set of 8 element requires a 3-bit code with each element assigned one of

the following bit combinations. –{ 000, 001, 010, 011, 100, 101, 110, 111 }

A binary code will have some unassigned bit combinations, if the number of elements

in the set is not a multiple power of 2. [The 10 decimal digits form such a set, A binary

code that distinguishes among 10 elements must contain at least 4 bits, but 6

combinations will remain unassigned. Numerous different codes can be obtained by

arranging 4 bits in 10 distinct combinations].

The bit assignment most commonly used for the decimal digits is straight binary

assignment listed below:

Decimal digits Binary Code

0 0000

1 0001

2 0010

3 0011

4 0100

5 0101

6 0110

7 0111

8 1000


9 1001

This Particular code is called binary-coded-decimal and is commonly referred by its

abbreviation BCD.

Advantages of BCD Codes

It is very similar to decimal system.

We need to remember binary equivalent of decimal numbers 0 to 9 only.

Disadvantages of BCD Codes

The addition and subtraction of BCD have different rules.

The BCD arithmetic is little more complicated. BCD needs more number of bits than

binary to represent the decimal number.

So BCD is less efficient than binary.

Alphanumeric codes

A binary digit or bit can represent only two symbols as it has only two states '0' or '1'.

But this is not enough for communication between two computers because there we

need many more symbols for communication. These symbols are required to represent

26 alphabets with capital and small letters, numbers from 0 to 9, punctuation marks

and other symbols.

The alphanumeric codes are the codes that represent numbers and alphabetic

characters. Mostly such codes also represent other characters such as symbol and

various instructions necessary for conveying information.

An alphanumeric code should at least represent 10 digits and 26 letters of alphabet i.e.

total 36 items.

The following three alphanumeric codes are very commonly used for the data

representation.

o American Standard Code for Information Interchange ASCII.( Code for 10

decimal digits, 26 upper case + 26 lower case letters and a number of special

characters, total 128 elements will be coded in ASCII).

o Extended Binary Coded Decimal Interchange Code EBCDIC.

o Five bit Baudot Code.

ASCII (American standard code for information interchange) code is a 7-bit code

whereas EBCDIC is an 8-bit code. ASCII code is more commonly used worldwide

while EBCDIC is used primarily in large IBM computers.


Number Representations

Fixed Point Representation:

Positive integers, including zero can be represented as unsigned numbers.

To represent negative integers, we need a notation.

Because of hardware limitation, A sign bit is placed in the left most position of the

number

Convention is 0 for positive and 1 for negative.

Complements

Complements are used in digital computers for simplifying the substraction operation

and logical manipulation.

There are two types of complements for each base r system.

r’s complement

(r-1)’s complement.

(r-1)’s complement

o If N is the number, n is the number of digits in given number and r is the radix,

then (r-1)’s complement of N = (rn – 1)-N.

After observation it is found that 1’s complement of a binary number is also obtain by

the reverse the digits of the number.

r’s complement

o the r’s complement is defined as rn – N. except if N=0 it is 0.

Number Representation

Floating Point Numbers

Fixed Point Numbers

Integers

Signed Unsigned

Fractions

Signed Unsigned


o Comparing with (r-1)’s complement, we note that the r’s complement is

obtained by adding 1 to (r-1)’s complement.

rn – N = [(r

n-1) – N +1]

Complement of the complement restores the number to its original value.

o Eg: the r’s complement of N = rn – N

o The complement of complement = rn – (r

n –N ) = N(original number).

Unsigned Integer Representation :

(Unsigned integer) : (an-1 an-2 ………. a1 a0)

∑ ( ∗ )

for all i ai Є (0,1)

V = Vmin if and only if for all i ai = 0

o i.e. Vmin = 0

V = Vmax if and only if for all i ai = 1

o i.e. Vmax = 20 + 2

1 + 2

2 +………..+ 2

n-1

= 2n – 1

Range of Unsigned integer in fixed point representation is 0 to 2n – 1.

Subtraction of unsigned numbers:

In schools we taught the borrow concept in subtraction

This seems easiest when we perform subtraction with paper and pencil.

When subtraction is implemented with digital hardware, this method is found to be

less efficient than the method that uses complements.

The subtraction of two n-digit unsigned numbers M-N(N≠ 0) in base r can be done as

follows.-

1. Add the minuend M to the r’s complement of the subtrahend N.

i.e. M + (rn –N ) = M-N +r

n ( if M ≥ N) or r

n – (N-M) (if M < N)

2. If M ≥ N, the sum will produce an end carry rn which is discarded, and what

is left is the result M-N.

3. If M<N , the sum does not produce an end carry and is equal to rn – (N-M),

which is the r’s complement of (N-M). To obtain the answer in a familiar

form, take the r’s complement of the sum and place a negative sign in front.

Signed Integer Representation:

Signed numbers are denoted in


1. Signed magnitude notation

2. 1’s complement notation

3. 2’s complement notation.

All the three representation used the most significant bit to denote the sign of the

number 0 for positive and 1 for negative.

For all positive numbers all the three representation having same pattern and same

value.

Signed magnitude and 1’s complement are containing two patterns for zero ( +0 , -0)

both of them cover same range[ -(2n-1

-1) to +(2n-1

-1)].

On the other hand 2’s complement contain only one pattern for 0 hence it contain one

extra negative number compare to positive number.

Range of 2’s complement numbers are : [ -(2n-1

) to +(2n-1

-1)].

The 1’s complement and 2’s complement arithmetic allow the same hardware for both

addition and subtraction whereas sign magnitude arithmetic requires different

hardware.

The sign magnitude and 2’s complement are weighted code whereas 1’s complement

is not a weighted code.

In the 2’s complement notation all the weights are positive except the weight of sign

bit [is negative].

o Eg : if (10110001)2 is in 2’s complement notation then (10110001)2 = 1 x (-27)

+ 0 x 26 +1x 2

5 + 1 x 2

4 + 0 x 2

3 + 0 x 2

2 + 0 x 2

1 + 1 x 2

0 = -79.

Sign Extension :

The sign extension allows placing the smaller number in a larger register.

The extended bit neither changes the sign of the number nor changes the value of the

number. They are only filling the position.

In case of 1’s complement notation and 2’s complement notation, The extended bits

are the copies of sign bit.

In sign magnitude notation the sign bit is moved to most significant place of extended

register while the remaining bits are filled with 0.

Eg: 1011(-3) in 8 bit register.

1. If the number (1011) is in sign magnitude notation then the number after

extension of bit will be: 10000011.

2. If the number (1011) is in 1’s complement notation then the number after


3. If the number(1011) is in 2’s complement notation then the number after



Q. Consider a fixed point signed number P = (F73A)16 is in 2’s complement notation.

then P*8 = (????)16.

Answer : P = (F73A) = ( 1111 0111 0011 1010 )

P*8 = P*23 = (1111 0111 0011 1010 ) * 2

3

= 1011 1001 1101 0000

= (B9D0)16

Signed binary arithmetic :

Addition of two Signed Binary Numbers

Consider the two signed binary numbers A & B, which are represented in 2’s

complement form. We can perform the addition of these two numbers, which is similar

to the addition of two unsigned binary numbers. But, if the resultant sum contains

carry out from sign bit, then discard (ignore) it in order to get the correct value.

If resultant sum is positive, you can find the magnitude of it directly. But, if the

resultant sum is negative, then take 2’s complement of it in order to get the magnitude.

Example 2

Let us perform the addition of two decimal numbers -7 and -4 using 2’s complement

method.

The 2’s complement representation of -7 and -4 with 5 bits each are shown below.

(−7)10 = (11001)2

(−4)10 = (11100)2

The addition of these two numbers is

(−7)10 + (−4)10 = (11001)2 + (11100)2

⇒(−7)10 + (−4)10 = (110101)2.

The resultant sum contains 6 bits. In this case, carry is obtained from sign bit. So, we can

remove it Resultant sum after removing carry is (−7)10 + (−4)10 = (10101)2.

The sign bit ‘1’ indicates that the resultant sum is negative. So, by taking 2’s

complement of it we will get the magnitude of resultant sum as 11 in decimal number

system. Therefore, addition of two negative numbers will give another negative number.

Arithmetic Overflow


If the result of an arithmetic operation is to too large (positive or negative) to fit into

the resultant bit-group, then arithmetic overflow occurs. It is normally left to the programmer

to decide how to deal with this situation.

Overflow Rule for addition

If 2 Two's Complement numbers are added, and they both have the same sign (both positive

or both negative), then overflow occurs if and only if the result has the opposite sign.

Overflow never occurs when adding operands with different signs.

i.e. Adding two positive numbers must give a positive result

Adding two negative numbers must give a negative result

Overflow occurs if

(+A) + (+B) = −C

(−A) + (−B) = +C

Example: Using 4-bit Two's Complement numbers (−8 ≤ x ≤ +7)

(−7) 1001

+(−6) 1010

------------

(−13) 1 0011 = 3 : Overflow (largest −ve number is −8)

Overflow Rule for Subtraction

If 2 Two's Complement numbers are subtracted, and their signs are different, then overflow

occurs if and only if the result has the same sign as the subtrahend.

Overflow occurs if

(+A) − (−B) = −C

(−A) − (+B) = +C

Example: Using 4-bit Two's Complement numbers (−8 ≤ x ≤ +7)

Subtract −6 from +7

(+7) 0111 0111

−(−6) 1010 -> Negate -> + 0110

---------- -----

13 1101 = −8 + 5 = −3 : Overflow

Unsigned Fraction Representation

(Unsigned fraction) : .(an-1 an-2 ………. a1 a0)

∑ ( ∗ )

for all i ai Є (0,1)

V = Vmin if and only if for all i ai = 0

o i.e. Vmin = 0


V = Vmax if and only if for all i ai = 1

o i.e. Vmax = 2-1

+ 2-2

+ 2-3

+………..+ 2-n

= [2-1

+ 2-2

+ 2-3

+….+ 2-n

……∞] – [2-(n+1)

+ 2-(n+2)

……∞]

= [

⁄ ] – 2-n

[2-1

+ 2-2

+ 2-3

+….+ 2-n

……∞]

= 1 – 2-n

The range of the Unsigned Fraction in fixed point representation is 0 to 1 – 2-n

Signed Fraction Representation

Same as Signed integer only the weights are different.

(1011)2 = 1(sign bit) , 0 x 2-1

+1 x 2-2

+1 x 2-3

= -0.375 [ in sign magnitude ].

Floating Point Representation

Floating Point number contains mantissa and Exponent.

o Eg : Floating Point number = 1.1101 x 2-3

Most of the system denote the mantissa( 01101 when normalized) as a sign magnitude

fraction and exponent(-3) in biased ( excess code) form.

The biased exponent is an unsigned number representing signed exponent.

o Eg : if exponent is in excess 127 code then 5 = 127+5=132 or -3 = 127 -3=124.

The biased value will depend on the number of bits allocated for biased exponent.

o Eg : if k bit is allocated for the exponent then biased value = 2k-1

.

IEEE Standard 754 floating point is the most common representation today for real

numbers on computers, including Intel-based PC's, Macintoshes, and most Unix

platforms.

Storage Layout of IEEE Standard Floating Point Numbers:

IEEE floating point numbers have three basic components: the sign, the exponent, and

the mantissa.

IEEE standard layout for floating point is either single precision(32-bit) or Double

Precision(64-bit).

The following table shows the layout for single (32-bit) and double (64-bit) precision

floating-point values. The number of bits for each field are shown, followed by the bit

ranges in square brackets. [00 = least-significant bit].

Floating Point Components

Sign Exponent Fraction

Single Precision 1 [31] 8 [30–23] 23 [22–00]


Double Precision 1 [63] 11 [62–52] 52 [51–00]

Normalization :

o Floating point numbers are usually normalized.

o Scientific notation where numbers are normalized to give a single digit before

the decimal point .

3123 = 3.123 x 103

o Exponent is adjusted so that leading bit (MSB) of mantissa is 1.

o Since it is always 1 there is no need to store it. Mantissa field only contain the

explicit fraction(f) bits. Full mantissa is 1.f

The Bias Value for IEEE single precision floats is 127.

The Bias Value for IEEE double precision floats is 1023.

Eg: we represent 3.625 in 32 bit format.

Changing 3 in binary=11

Changing .625 in binary

.625 X 2 1

.25 X 2 0

.5 X 2 1

Writing in binary exponent for 3.625=11.101 X 20

On normalizing

11.101 X 20=1.1101 X 2

1

On biasing exponent = 127 + 1 = 128

(128)10=(10000000) 2

For getting significand

Digits after decimal = 1101

Expanding to 23 bit = 11010000000000000000000

Setting sign bit

As it is a positive number, sign bit = 0

Finally we arrange according to representation

Sign bit exponent Significand(Mantissa)

0 10000000 11010000000000000000000

Converting floating point into decimal

Let’s convert a FP number into decimal


1 01111100 11000000000000000000000

The decimal value of an IEEE number is given by the formula:

V = (1 -2s) * (1 + f) * 2( e – bias )

where

s, f and e fields are taken as decimal here.

(1 -2s) is 1 or -1, depending upon sign bit 0 and 1

add an implicit 1 to the significand (fraction field f), as in formula

Booth’s Algorithm

Booth’s Algorithm is used to multiply two signed numbers in 2’s complement

notation.

It starts with the observation that with the ability to both add and subtract there are

multiple ways to compute a product.

Suppose we want to multiply 210 by 610 or 00102 by 01102:

00102

x 01102

+ 0000 shift (0 in multiplier)

+ 0010 add (1 in multiplier)

+ 0010 add (1 in multiplier)

+ 0000 shift (0 in multiplier)

000011002

Booth observed that an ALU that could add or subtract could get the same result in

more than one way. For example, since

610 = – 210 + 810

Or 01102 = – 00102 + 10002

we could replace a string of 1s in the multiplier with an initial subtract when we first

see a 1 and then later add when we see the bit after the last 1.

Eg: 001111010100102 = – 000000000000102 + 0000000000001002 – 000000000100002 +

000000001000002 – 000000010000002 + 000000100000002 –

000001000000002 + 010000000000002

010010112 x 001111010100102 = 01001011 x (– 000000000000102 + 0000000000001002 –

000000000100002 + 000000001000002 – 000000010000002 +

000000100000002 – 000001000000002 + 010000000000002 )

Booth's algorithm can be implemented by repeatedly adding (with ordinary unsigned

binary addition) one of two predetermined values A and S to a product P, then

performing a rightward arithmetic shift on P.

1. Let m and r be the multiplicand and multiplier respectively; and let x and y represent

the number of bits in m and r.


o Determine the values of A and S, and the initial value of P. All of these numbers

should have a length equal to (x + y + 1).

o A (positive multiplicand in x+y+1 bits ): Fill the most significant (leftmost) bits

with the value of m . Fill the remaining (y + 1) bits with zeros.

o S(2’s complement of multiplicand in x+y+1 bits ) : Fill the most significant bits

with the value of (−m) in two's complement notation. Fill the remaining (y + 1)

bits with zeros.

o P(initially it is partial product) : Fill the most significant x bits with zeros. To

the right of this, append the value of r. Fill the least significant (rightmost) bit

with a zero (booth bit ) .

2. Determine the two least significant (rightmost) bits of P .

If they are 01, find the value of P + A. Ignore any overflow.

If they are 10, find the value of P + S. Ignore any overflow.

If they are 00, do nothing. Use P directly in the next step.

If they are 11, do nothing. Use P directly in the next step.

3. Arithmetically shift the value obtained in the 2nd step by a single place to the right.

Let P now equal this new value.

4. Repeat steps 2 and 3 until they have been done y times.

5. Drop the least significant (rightmost) bit from P. This is the product of m and r.

Example:

Find 3 × (−4), with m = 3 and r = −4, and x = 4 and y = 4:

m = 0011, -m = 1101, r = 1100

A = 0011 0000 0

S = 1101 0000 0

P = 0000 1100 0

Perform the loop four times:

1. P = 0000 1100 0. The last two bits are 00.

P = 0000 0110 0. Arithmetic right shift.




P = 1101 0011 0. P = P + S.




The product is 1111 0100, which is −12.


Basic Computer Instructions

Instruction Code : An instruction code is a group of bits that instruct the computer to

perform a specific operation.

Operation Code : The operation code of an instruction is a group of bits that define

such operations as add, subtract, multiply, shift, and complement. The number of bits

required for the operation code of an instruction depends on the total number of

operations available in the computer. The operation code must consist of at least n bits

for a given 2n (or less) distinct operations.

Accumulator (AC) : Computers that have a single-processor register usually assign to

it the name accumulator (AC) accumulator and label it AC. The operation is performed

with the memory operand and the content of AC.

Stored Program Organization

The simplest way to organize a computer is to have one processor register and an

instruction code format with two parts.


The first part specifies the operation to be performed and the second specifies an

address.

The memory address tells the control where to find an operand in memory.

This operand is read from memory and used as the data to be operated on together with

the data stored in the processor register.

The following figure shows this type of organization.

Instructions are stored in one section of memory and data in another.

For a memory unit with 4096 words, we need 12 bits to specify an address since 212

=

4096.

If we store each instruction code in one 16-bit memory word, we have available four

bits for operation code (abbreviated opcode) to specify one out of 16 possible

operations, and 12 bits to specify the address of an operand.

The control reads a 16-bit instruction from the program portion of memory.

It uses the 12-bit address part of the instruction to read a 16-bit operand from the data

portion of memory.

It then executes the operation specified by the operation code.

Computers that have a single-processor register usually assign to it the name

accumulator and label it AC.

If an operation in an instruction code does not need an operand from memory, the rest

of the bits in the instruction can be used for other purposes.

For example, operations such as clear AC, complement AC, and increment AC operate

on data stored in the AC register. They do not need an operand from memory. For

these types of operations, the second part of the instruction code (bits 0 through 11) is

not needed for specifying a memory address and can be used to specify other

operations for the computer.

Direct and Indirect addressing of basic computer


The second part of an instruction format specifies the address of an operand, the

instruction is said to have a direct address.

In Indirect address, the bits in the second part of the instruction designate an address

of a memory word in which the address of the operand is found.

One bit of the instruction code can be used to distinguish between a direct and an

indirect address.

It consists of a 3-bit operation code, a 12-bit address, and an indirect address mode

bitdesignated by I.

The mode bit is 0 for a direct address and 1 for an indirect address.

The indirect address instruction needs two references to memory to fetch an operand.

4. The first reference is needed to read the address of the operand

5. Second reference is for the operand itself.

Registers of basic computer

It is necessary to provide a register in the control unit for storing the instruction code

after it is read from memory.

The computer needs processor registers for manipulating data and a register for

holding a memory address.

These requirements dictate the register configuration shown in Figure.

The data register (DR) holds the operand read from memory.

The accumulator (AC) register is a general purpose processing register.

The instruction read from memory is placed in the instruction register (IR).

The temporary register (TR) is used for holding temporary data during the processing.


The memory address register (AR or MAR) has 12 bits.

The program counter (PC) also has 12 bits and it holds the address of the next

instruction to be read from memory after the current instruction is executed.

Instruction words are read and executed in sequence unless a branch instruction is

encountered. A branch instruction calls for a transfer to a non-consecutive instruction

in the program.

Two registers are used for input and output. The input register (INPR) receives an 8-

bit character from an input device. The output register (OUTR) holds an 8-bit

character for an output device.

Common Bus System for basic computer register. What is the requirement of common bus System?

The basic computer has eight registers, a memory unit and a control unit.

Paths must be provided to transfer information from one register to another and

between memory and register.

The number of wires will be excessive if connections are between the outputs of each

register and the inputs of the other registers. An efficient scheme for transferring

information in a system with many register is to use a common bus.

The outputs of seven registers and memory are connected to the common bus. The

specific output that is selected for the bus lines at any given time is determined from

the binary value of the selection variables S2, S1, and S0.

The number along each output shows the decimal equivalent of the required binary

selection.

The connection of the registers and memory of the basic computer to a common bus

system is shown in figure.


The particular register whose LD (load) input is enabled receives the data from the bus

during the next clock pulse transition. The memory receives the contents of the bus

when its write input is activated. The memory places its 16-bit output onto the bus

when the read input is activated and S2 S1 S0 = 1 1 1.

Four registers, DR, AC, IR, and TR have 16 bits each.

Two registers, AR and PC, have 12 bits each since they hold a memory address.

When the contents of AR or PC are applied to the 16-bit common bus, the four most

significant bits are set to 0’s. When AR and PC receive information from the bus, only

the 12 least significant bits are transferred into the register.

The input register INPR and the output register OUTR have 8 bits each and

communicate with the eight least significant bits in the bus. INPR is connected to

provide information to the bus but OUTR can only receive information from the bus.

Five registers have three control inputs: LD (load), INR (increment), and CLR (clear).

Two registers have only a LD input.

AR must always be used to specify a memory address; therefore memory address is

connected to AR.

The 16 inputs of AC come from an adder or logic circuit. This circuit has three sets of

inputs.

1. Set of 16-bit inputs come from the outputs of AC.

2. Set of 16-bits come from the data register DR.

3. Set of 8-bit inputs come from the input register INPR.

The result of an addition(Manipulation) is transferred to AC and the end carry-out of

the addition is transferred to flip-flop E (extended AC bit).

The clock transition at the end of the cycle transfers the content of the bus into the

designated destination register and the output of the adder and logic circuit into AC.

Instruction Format with its types.

The basic computer has three instruction code formats, as shown in figure


Each format has 16 bits.

The operation code (opcode) part of the instruction contains three bits and the meaning

of the remaining 13 bits depends on the operation code encountered.

A memory-reference instruction uses 12 bits to specify an address and one bit to

specify the addressing mode I. I is equal to 0 for direct address and to 1 for indirect

address.

Operation

Decoder

Symbol Description

0 AND AC = AC AND M[AR]

1 ADD AC = AC + M[AR] , E = Cout

2 LDA AC = M[AR]

3 STA M[AR] = AC

4 BUN PC = AR

5 BSA M[AR] = PC , PC = AR + 1

6 ISZ M[AR] = M[AR] + 1, if M[AR] + 1 = 0 then PC = PC+1

The register reference instructions are recognized by the operation code 111 with a 0

in the leftmost bit (bit 15) of the instruction. A register-reference instruction specifies

an operation on or a test of the AC register. An operand from memory is not needed;

therefore, the other 12 bits are used to specify the operation or test to be executed.

Register-reference instructions listed below:

Assembly Code Operation Operation Performed

CLA AC 0 Clear AC

CLE Clear E

CMA Complement AC

CME Complement E

CIR Circular Right shift AC

CIL Circular Left Shift AC

INC Increment AC

SPA Skip if AC is Positive

SNA Skip if AC is Negative

SZA Skip if AC is Zero

SZE Skip if E is Zero

HLT Halt Computer

o

An input-output instruction does not need a reference to memory and is recognized

by the operation code 111 with a 1 in the leftmost bit of the instruction. The remaining

12 bits are used to specify the type of input-output operation or test performed.

o The control functions and microoperations for the input-output instructions are

listed below.


Symbol Operation Description INP AC(0-7)=INPR, FGI= 0 Input Character to AC

OUT OUTR =AC(0-7), FGO=0 Output Character From AC

SKI if(FGI = 1) then (PC= PC + 1) Skip on input flag

SKO if(FGO = 1) then (PC =PC + 1) Skip on output flag

ION IEN =1 Interrupt Enable On

IOF IEN =0 Interrupt Enable Off

Instruction cycle:

A program residing in the memory unit of the computer consists of a sequence of

instructions. In the basic computer each instruction cycle consists of the following

phases:

1. Fetch an instruction from memory.

2. Decode the instruction.

3. Read the effective address from memory if the instruction has an indirect address.

4. Execute the instruction.

After step 4, the control goes back to step 1 to fetch, decode and execute the next

instruction.

This process continues unless a HALT instruction is encountered.

Documents

Computer Architecture · 2020. 4. 8. · SCE,Sasaram2019 Page 3 Introduction to computer organization and CPU Design Historically there have been 2 types of Computers: 1. Fixed Program