Computer Architecture

QtSpim, a Mips simulator

S. Coudert and R. PacaletSeptember 18, 2018

Memory MappingMemorymapped

I/O

.textsub $4,$2,$6

.data.byte 12,48

.ktext 0x80000100sub $4,$2,$6

instructions in kernel text segment

.ktextadd $8, $1,$2

.kdata.byte 8,22,16

instructions in kernel text segment

Transmitter data

Transmitter control

Receiver data

Receiver control

data segment

text segment

Reserved

data segment

text segment

Reserved

Kernel

Kernel

Stack segment

User

User

0xFFFF000C

0xFFFF0008

0xFFFF0004

0xffff0000

0x80000000

0x90000000

0x7ffff4d4

0x10000000

0x00400000

at address 0x80000100

data in kernel data segment

data in user data segment

instructions in user text segment

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Memory Mapped IO

Transmitter / receiver used to write to console (screen) and read from keyboardReceiver ready: a character was receivedTransmitter ready: ready to send a character

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SyscallsExamples:

1 . data2 s t r :3 . a s c i i z " today "45 . t e x t67 # p r i n t s t r i n g8 l i $v0 49 l a $a0 , s t r

10 s y s c a l l1112 # p r i n t i n t 513 l i $v0 114 l a $a0 ,515 s y s c a l l1617 # read i n t18 l i $v0 519 s y s c a l l

Warning: inputsyscalls andmapped IO notcompatible!

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Exception HardwareCause register: information about cause of exception

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Status Register and interrupts

Status register: interrupt mask,...

0, Transmitter irq: when transmitter is ready1, Receiver irq: when a character arrives5, Timer irq: Relies on 2 integer registers:

• count, incremented at fixed rate• compare, set by user

Interrupt when count register = compare register

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Registers in coprocessor 0

Coprocessor 0 registers implemented by QtSpimCoprocessor 0 specific instructions

• mfc0: move from coprocessor0• mtc0: move to coprocessor0

dedicatedwires

busbus

Integer unit

Coprocessor

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Pseudo instructions

Example:1 . data2 l b l :3 . a s c i i z " message to p r i n t "4 . t e x t5 l a $a0 , l b l6 l i $v0 , 17 s y s c a l l

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A quick view of kernel memory

QtSpim defaults:• Contains default start code• Contains default exception handler

Custom code: load from file

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Default exception handler (1/5)

Data for exception handling:1 . kdata2 __m1_ : . a s c i i z " Except ion "3 __m2_ : . a s c i i z " occurred and ignored \ n "4 __e0_ : . a s c i i z " [ I n t e r r u p t ] "5 __e1_ : . a s c i i z " [ TLB ] "6 __e2_ : . a s c i i z " [ TLB ] "7 __e3_ : . a s c i i z " [ TLB ] "8 __e4_ : . a s c i i z " [ Address e r r o r i n i n s t / data fe t ch ] "9 __e5_ : . a s c i i z " [ Address e r r o r i n s to re ] "

10 __e6_ : . a s c i i z " [ Bad i n s t r u c t i o n address ] "

...1 __e29_ : . a s c i i z " "2 __e30_ : . a s c i i z " [ Cache ] "3 __e31_ : . a s c i i z " "4 __excp : . word __e0_ , __e1_ , __e2_ , __e3_ , __e4_ , __e5_ , __e6_ , __e7_ , __e8_ , __e9_5 . word __e10_ , __e11_ , __e12_ , __e13_ , __e14_ , __e15_ , __e16_ , __e17_ , __e18_ ,6 . word __e19_ , __e20_ , __e21_ , __e22_ , __e23_ , __e24_ , __e25_ , __e26_ , __e27_ ,7 . word __e28_ , __e29_ , __e30_ , __e31_8 s1 : . word 09 s2 : . word 0

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Default exception handler (2/5)Store state and Extract exception code:

1 # This i s the except ion handler code t h a t the processor runs when2 # an except ion occurs . I t on ly p r i n t s some in fo rma t i on about the3 # except ion , but can server as a model o f how to w r i t e a handler .4 #5 # Because we are running i n the kernel , we can use $k0 / $k1 w i thou t6 # saving t h e i r o ld values .78 # This i s the except ion vec to r address f o r MIPS−1 ( R2000 ) :9 # . k t e x t 0x80000080

10 # This i s the except ion vec to r address f o r MIPS32 :11 . k t e x t 0x8000018012 # Selec t the appropr ia te one f o r the mode i n which SPIM i s compiled .13 . set noat14 move $k1 $at # Save $at15 . set a t16 sw $v0 s1 # Not re−en t ran t and we can ’ t t r u s t $sp17 sw $a0 s2 # But we need to use these CPU r e g i s t e r s1819 mfc0 $k0 $13 # Cause r e g i s t e r20 s r l $a0 $k0 2 # Ex t rac t ExcCode F ie l d21 andi $a0 $a0 0x1f

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Default exception handler (3/5)Basic default handler, just print exception information:

1 # P r i n t i n f o rma t i on about except ion .2 #3 l i $v0 4 # s y s c a l l 4 ( p r i n t _ s t r )4 l a $a0 __m1_5 s y s c a l l67 l i $v0 1 # s y s c a l l 1 ( p r i n t _ i n t )8 s r l $a0 $k0 2 # Ex t rac t ExcCode F ie l d9 andi $a0 $a0 0x1f

10 s y s c a l l1112 l i $v0 4 # s y s c a l l 4 ( p r i n t _ s t r )13 andi $a0 $k0 0x3c14 lw $a0 __excp ( $a0 )15 nop16 s y s c a l l1718 bne $k0 0x18 ok_pc # Bad PC except ion requ i res spec ia l checks19 nop2021 mfc0 $a0 $14 # EPC22 andi $a0 $a0 0x3 # I s EPC word−a l igned ?23 beq $a0 0 ok_pc24 nop2526 l i $v0 10 # E x i t on r e a l l y bad PC27 s y s c a l l

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Default exception handler (4/5)

Test interrupts and prepare EPC for return:1 ok_pc :2 l i $v0 4 # s y s c a l l 4 ( p r i n t _ s t r )3 l a $a0 __m2_4 s y s c a l l56 s r l $a0 $k0 2 # Ex t rac t ExcCode F ie l d7 andi $a0 $a0 0x1f8 bne $a0 0 r e t # 0 means except ion was an i n t e r r u p t9 nop

1011 # I n t e r r u p t −s p e c i f i c code goes here !12 # Don ’ t sk ip i n s t r u c t i o n a t EPC since i t has not executed .131415 r e t :16 # Return from ( non− i n t e r r u p t ) except ion . Skip o f fend ing i n s t r u c t i o n17 # at EPC to avoid i n f i n i t e loop .18 #19 mfc0 $k0 $14 # Bump EPC r e g i s t e r20 addiu $k0 $k0 4 # Skip f a u l t i n g i n s t r u c t i o n21 # (Need to handle delayed branch case here )22 mtc0 $k0 $14

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Default exception handler (5/5)

Restore State and return1 # Restore CPU r e g i s t e r s and rese t procesor s ta te2 #3 lw $v0 s1 # Restore o ther CPU r e g i s t e r s4 lw $a0 s256 . set noat7 move $at $k1 # Restore $at8 . set a t9

10 mtc0 $0 $13 # Clear Cause r e g i s t e r1112 mfc0 $k0 $12 # Set Status r e g i s t e r13 o r i $k0 0x1 # I n t e r r u p t s enabled14 mtc0 $k0 $121516 # Return from except ion on MIPS32 :17 e re t

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Default Start Code

Starts at address __start and call label main:1 # Standard s t a r t u p code . Invoke the r o u t i n e " main " w i th arguments :2 # main ( argc , argv , envp )3 #4 . t e x t5 . g l o b l _ _ s t a r t6 _ _ s t a r t :7 lw $a0 0( $sp ) # argc8 addiu $a1 $sp 4 # argv9 addiu $a2 $a1 4 # envp

10 s l l $v0 $a0 211 addu $a2 $a2 $v012 j a l main13 nop1415 l i $v0 1016 s y s c a l l # s y s c a l l 10 ( e x i t )1718 . g l o b l __eoth19 __eoth :

Notice global labels (to be seen anywhere)

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Lab on QtSpim

Code according Mips conventions and beware your stack!

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