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Computer Architecture Fall 2008 ©
August 20th, 2008
www.qatar.cmu.edu
Introduction to Computer Architecture
Lecture 2 – Digital Logic Design
Computer Architecture Fall 2008 ©
Digital Systems
Digital vs. Analog Waveforms
Analog: values vary over a range continuously
Digital: only assumes discrete values
+5
V
–5
1 0 1
T ime
+5
V
–5
T ime
Computer Architecture Fall 2008 ©
Digital Hardware Systems
Algebra: variables, values, operations
In Boolean algebra, the values are the symbols 0 and 1 If a logic statement is false, it has value 0 If a logic statement is true, it has value 1
Operations: AND, OR, NOT
Boolean Algebra and Logical Operators
0 0 1 1
X Y X AND Y
0 1 0 1
0 0 0 1
X Y X OR Y
0 0 1 1
0 1 0 1
0 1 1 1
X NOT X
0 1
1 0
Computer Architecture Fall 2008 ©
L1
L6
L2
L3
L7
L4
L5
Example: Seven Segment Display
°Chip to drive digital display
Computer Architecture Fall 2008 ©
B3 B2 B1 B0 Val L1 L2 L3 L4 L5 L6 L7
0 0 0 0 0 1 0 1 1 1 1 1
0 0 0 1 1 0 0 0 0 0 1 1
0 0 1 0 2 1 1 1 0 1 1 0
0 0 1 1 3 1 1 1 0 0 1 1
0 1 0 0 4 0 1 0 1 0 1 1
0 1 0 1 5 1 1 1 1 0 0 1
0 1 1 0 6 1 1 1 1 1 0 1
0 1 1 1 7 1 0 0 0 0 1 1
1 0 0 0 8 1 1 1 1 1 1 1
1 0 0 1 9 1 1 1 1 0 1 1
L1
L6
L2
L3
L7
L4
L5
Example (cont.)
Computer Architecture Fall 2008 ©
Example (cont.)
° Implement L4:
Some gate level implementationof the Boolean function for L4
Computer Architecture Fall 2008 ©
Representations of Digital Design: Switches
A switch connects two points under control signal.
when the control signal is 0 (false), the switch is open
when it is 1 (true), the switch is closed
when control is 1 (true), switch is open
when control is 0 (false), switch is closed
Normally Closed
Normally Open
Open Switch
Control
Normally Open Switch
Closed Switch
T rue
False
Open Switch
Control
Normally Closed Switch
Closed Switch
T rue
False
Computer Architecture Fall 2008 ©
Switch RepresentationsExamples: routing inputs to outputs through a maze
Floating nodes: what happens if the car is not running? outputs are floating rather than forced to be false
Under all possible control signal settings (1) all outputs must be connected to some input through a path (2) no output is connected to more than one input through any path
EXAMPLE: IF car in driveway OR (car in garage AND NOT garage door closed) AND car running THEN can back out car
Car in garage Car
running
True
True
Car can back out
Garage door closed
Car in driveway
EXAMPLE: IF car in garage AND garage door open AND car running THEN back out car
T rue Car can back out
Garage door open
Car running
Car in garage
Computer Architecture Fall 2008 ©
Steering Logic: Switches
Voltage Controlled Switches
Gate
Oxide
Source DrainSilicon Bulk
Channel Region
Metal Gate, Oxide, Silicon Sandwich
Diffusion regions: negatively charged ions driven into Si surface
Si Bulk: positively charged ions
By "pulling" electrons to the surface, a conducting channel is formed
"n-Channel MOS"
n-type Si
p-type Si
Computer Architecture Fall 2008 ©
Switching or Steering Logic
Voltage Controlled Switches
Logic 0 on gate,Source and Drain connected
Gate
Source Drain
Gate
Source Drain
nMOS Transistor
pMOS Transistor
Logic 1 on gate,Source and Drain connected
Computer Architecture Fall 2008 ©
Using Switches to implement Logic
Inverter Operation
+5V
"1" "0"
+5V
"0" "1"
Input is 1Pull-up does not conductPull-down conductsOutput connected to GND
Input is 0Pull-up conductsPull-down does not conductOutput connected to VDD
Computer Architecture Fall 2008 ©
NAND Gate
NAND Gate Operation
A = 1, B = 1Pull-up network does not conductPull-down network conductsOutput node connected to GND
A = 0, B = 1Pull-up network has path to VDDPull-down network path brokenOutput node connected to VDD
+5V"1" "1"
"0"
+5V"0" "1"
"1"
Computer Architecture Fall 2008 ©
NOR Gate
NOR Gate Operation
+5V"0" "0"
"1"
+5V"1" "0"
"0"
A = 0, B = 0Pull-up network conductsPull-down network brokenOutput node at VDD
A = 1, B = 0Pull-up network brokenPull-down network conductsOutput node at GND
Computer Architecture Fall 2008 ©
Switch Representations
Implementation of AND and OR Functions with Switches
A
False
T rue
output
B A
False
T rue
output
B
AND functionSeries connection to TRUE
OR functionParallel connection to TRUE
Computer Architecture Fall 2008 ©
Representations of a Digital Design
Truth Tables
tabulate all possible input combinations and their associated output values
Example: half adder adds two binary digits to form Sum and Carry
Example: full adder adds two binary digits and Carry in to form Sum and Carry Out
NOTE: 1 plus 1 is 0 with a carry of 1 in binary
A B
0 0 1 1
0 1 0 1
Sum Carry
0 1 1 0
0 0 0 1
A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
C in 0 1 0 1 0 1 0 1
S um 0 1 1 0 1 0 0 1
C out 0 0 0 1 0 1 1 1
Computer Architecture Fall 2008 ©
Representing Digital Design: Boolean Algebra
NOT X is written as XX AND Y is written as X & Y, or sometimes X YX OR Y is written as X + Y
values: 0, 1variables: A, B, C, . . ., X, Y, Zoperations: NOT, AND, OR, . . .
A
0011
B
0101
Sum
0110
Carry
0001
Sum = A B + A B
Carry = A B
OR'd together product terms for each truth table
row where the function is 1
if input variable is 0, it appears in complemented form;
if 1, it appears uncomplemented
Deriving Boolean equations from truth tables:
Computer Architecture Fall 2008 ©
Representing Digital Logic: Boolean Algebra
A
00001111
B
00110011
Cin
01010101
Sum
01101001
Cout
00010111
Another example:
Sum = A B Cin + A B Cin + A B Cin + A B Cin
Cout = A B Cin + A B Cin + A B Cin + A B Cin
Computer Architecture Fall 2008 ©
Gate Representations of a Digital Designmost widely used primitive building block in digital system design
StandardLogic Gate
RepresentationHalf Adder Schematic
Netlist: tabulation of gate inputs & outputs and the nets they are connected to
Net: electrically connected collection of wires
Inverter
AND
OR
A
B
CARR Y
SUM
Computer Architecture Fall 2008 ©
Representations of a Digital Design: Gates
Full Adder Schematic
Fan-in: number of inputs to a gateFan-out: number of gate inputs an output is connected to
Technology "Rules of Composition" place limits on fan-in/fan-out
Cin B A \Cin \ B \ A
A
B
Cin SUM
Cout
A B
B C in
A C in
C out
Computer Architecture Fall 2008 ©
Waveform Representationdynamic behavior of a circuitreal circuits have non-zero delays
Timing Diagram of the Half Adder
sumpropagation
delay
circuit hazard: 1 plus 0 is 1, not 0!
sumpropagation
delay
Output changes are delayed from input changes
The propagation delay is sensitive to paths in the circuit
Outputs may temporarily change from the correct value to the wrong value back again to the correct value: this is called a glitch or hazard
100 200
A B SUM CARR Y
Computer Architecture Fall 2008 ©
Routing Stuff Around – Multiplexors and Demultiplexors
Multi-point connections
MUX MUX
DEMUX
A B
Sum
A0 A1 B0 B1
Sa Sb
Ss
S0 S1
Multiple input sources
Multiple output destinations
Computer Architecture Fall 2008 ©
So far Combinatorial (or stateless) logic°Things don’t get really interesting until we have memory elements
• Think about a digital watch, or a vending machine (or a microprocessor!)
• This is called “Sequential Logic”
°Two questions:• How do we design memory elements?
- How do we create logic that remembers?
• How do we design sequential logic
Computer Architecture Fall 2008 ©
Memory Elements°The trick is to use feedback
Cascaded Inverters: Static Memory Cell
"0"
"1"
°Example: D-Latch
°Latch vs. Flip Flop• Flip flop: two latches in a row
• Allows you to read the old value and write a new value without a race condition
D Q
D
Clk
Q
Clk
Computer Architecture Fall 2008 ©
Sequential Logic Design
° State as part of the input
° Next state as part of the output
° State stored in flip flops (registers!)
° Clock controls everything (synchronous logic)
° Lets rethink our 8 segment display example to make it display a counter
inputs outputsCombinatorialLogic
State
Current state Next state
Computer Architecture Fall 2008 ©
Take home points°Logic built using switches (transistors)
°Boolean algebra and truth tables
°Translation to gates: sum of products
°Multiplexors, demultiplexors, ALU … all designed this way
°Sequential logic• Memory elements• Old state part of inputs, next state part of outputs
• Counters, registers, control all designed this way