Computer Design 2007 – Introduction 1 MAMAS – Computer Architecture PC Structure and Peripherals...
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Computer Des 1 MAMAS – Computer Architecture MAMAS – Computer Architecture PC Structure and PC Structure and Peripherals Peripherals Dr. Lihu Rappoport
Computer Design 2007 – Introduction 1 MAMAS – Computer Architecture PC Structure and Peripherals Dr. Lihu Rappoport
Computer Design 2007 Introduction 1 MAMAS Computer Architecture
PC Structure and Peripherals Dr. Lihu Rappoport
Slide 2
Computer Design 2007 Introduction 2 Memory
Slide 3
3 SRAM vs. DRAM u Random Access: access time is the same for
all locations DRAM Dynamic RAMSRAM Static RAM RefreshRegular
refresh (~1% time)No refresh needed AddressAddress muxed: row+
columnAddress not multiplexed AccessNot true Random AccessTrue
Random Access densityHigh (1 Transistor/bit)Low (6 Transistor/bit)
Powerlowhigh Speedslowfast Price/bitlowhigh Typical usageMain
memorycache
Slide 4
Computer Design 2007 Introduction 4 CapacitySpeed Logic2 in 3
years2 in 3 years DRAM4 in 3 years1.4 in 10 years Disk2 in 3
years1.4 in 10 years Technology Trends CPU-DRAM Memory Gap
(latency)
Slide 5
Computer Design 2007 Introduction 5 Basic DRAM chip Addressing
sequence Row address and then RAS# asserted RAS# to CAS# delay
Column address and then CAS# asserted DATA transfer Row latch Row
address decoder Column addr decoder Column latch CAS# RAS# Data
Memory array Memory address bus Addr
Slide 6
Computer Design 2007 Introduction 6 Addressing sequence Access
sequence Put row address on data bus and assert RAS# Wait for RAS#
to CAS# delay (t RCD ) Put column address on data bus and assert
CAS# DATA transfer Precharge t RAC Access time RAS/CAS delay
Precharge delay RAS# Data A[0:7] CAS# Data n Row iCol n Row j X CL
- CAS latency X
Slide 7
Computer Design 2007 Introduction 7 Basic SDRAM controller DRAM
address decoder Time delay gen. address mux RAS# CAS# R/W# A[20:23]
A[10:19] A[0:9] Memory address bus D[0:7] Select Chip select u DRAM
data must be periodically refreshed Needed to keep data correct
DRAM controller performs DRAM refresh, using refresh counter
Slide 8
Computer Design 2007 Introduction 8 Paged Mode DRAM Multiple
accesses to different columns from same row Saves RAS and RAS to
CAS delay Extended Data Output RAM (EDO RAM) A data output latch
enables to parallel next column address with current column data
Improved DRAM Schemes RAS# Data A[0:7] CAS# Data nD n+1 RowXCol n
XCol n+1 XCol n+2 X D n+2 X RAS# Data A[0:7] CAS# Data nData n+1
RowXCol n XCol n+1 XCol n+2 X Data n+2 X
Slide 9
Computer Design 2007 Introduction 9 Burst DRAM Generates
consecutive column address by itself Improved DRAM Schemes (cont)
RAS# Data A[0:7] CAS# Data nData n+1 RowXCol n X Data n+2 X
Slide 10
Computer Design 2007 Introduction 10 Synchronous DRAM SDRAM u
All signals are referenced to an external clock (100MHz-200MHz)
Makes timing more precise with other system devices u Multiple
Banks Multiple pages open simultaneously (one per bank) u Command
driven functionality instead of signal driven ACTIVE: selects both
the bank and the row to be activated ACTIVE to a new bank can be
issued while accessing current bank READ/WRITE: select column u
Read and write accesses to the SDRAM are burst oriented Successive
column locations accessed in the given row Burst length is
programmable: 1, 2, 4, 8, and full-page May end full-page burst by
BURST TERMINATE to get arbitrary burst length u A user programmable
Mode Register CAS latency, burst length, burst type u Auto
pre-charge: may close row at last read/write in burst u Auto
refresh: internal counters generate refresh address
Slide 11
Computer Design 2007 Introduction 11 SDRAM Timing u t RCD :
ACTIVE to READ/WRITE gap = t RCD (MIN) / clock period u t RC :
successive ACTIVE to a different row in the same bank u t RRD :
successive ACTIVE commands to different banks BL = 1
Slide 12
Computer Design 2007 Introduction 12 DDR-SDRAM u 2n-prefetch
architecture The DRAM cells are clocked at the same speed as SDR
SDRAM Internal data bus is twice the width of the external data bus
Data capture occurs twice per clock cycle Lower half of the bus
sampled at clock rise Upper half of the bus sampled at clock fall u
Uses 2.5V (vs. 3.3V in SDRAM) Reduced power consumption 0:n-1
n:2n-1 0:n-1 200MHz clock 0:2n-1 SDRAM Array
Slide 13
Computer Design 2007 Introduction 13 DDR SDRAM Timing 133MHz
clock cmd Bank Data Addr NOP X ACT Bank 0 Row iX RD Bank 0 Col j t
RCD >20ns ACT Bank 0 Row l t RC >70ns ACT Bank 1 Row m t RRD
>20ns CL=2 NOP X X X X X X RD Bank 1 Col n NOP X X X X X X X X j
+1 +2 +3 n +1 +2 +3
Slide 14
Computer Design 2007 Introduction 14 DIMMs u DIMM: Dual In-line
Memory Module A small circuit board that holds memory chips u
64-bit wide data path (72 bit with parity) Single sided: 9 chips,
each with 8 bit data bus 512 Mbit / chip 8 chips 512 Mbyte per DIMM
Dual sided: 18 chips, each with 4 bit data bus 256 Mbit / chip 16
chips 512 Mbyte per DIMM
Slide 15
Computer Design 2007 Introduction 15 DRAM Standards u SDR
SDRAM: PC66, PC100 and PC133 u DDR SDRAM u Total BW for DDR400
3200M Byte/sec = 64 bit 2 200MHz / 8 (bit/byte) u Dual channel DDR
SDRAM Uses 2 64 bit DIMM modules in parallel to get a 128 data bus
Total BW for DDR400 dual channel: 6400M Byte/sec = 128 bit 2 200MHz
/8 DDR200DDR266DDR333DDR400DDR533 Bus freq (MHz)100133167200266
Bit/pin (Mbps)200266333400533 Total bandwidth (M Byte/sec )
16002133266632004264
Computer Design 2007 Introduction 18 DDR2 u DDR2 achieves
high-speed using 4-bit prefetch architecture SDRAM cells read/write
4 the amount of data as the external bus DDR2-533 cell works at the
same frequency as a DDR266 SDRAM or a PC133 SDRAM cell u This
method comes at a price of increased latency DDR2-based systems may
perform worse than DDR1-based systems
Slide 19
Computer Design 2007 Introduction 19 DDR2 Other Features u
Shortened page size for reduced activation power Each time an
ACTIVATE command is given, all bits in the page are read A major
contributor to the active power A device with a shorter page size
has a significantly lower power 512Mb DDR2 page size is 1KByte vs.
2KB for 512Mb DDR1 u Eight banks in 1Gb densities and above
Increases flexibility in DRAM accesses Also increases the
power
Slide 20
Computer Design 2007 Introduction 20 DDR2 vs DDR1 SDRAM DDR1DDR
2 Data Bus64 bit Data Rate200/266/333/400 Mbps400/533/667/800 Mbps
Bus Frequency100/133/166/200 MHz200/266/333/400 MHz DRAM
Frequency100/133/166/200 MHz Operation Voltage2.5V1.8V
PackageTSOPFBGA Densities128Mb~1Gb256Mb~2Gb Prefetch size2 bits4
bits Burst length2/4/84/8 CAS Latency2, 2.5, 33, 4, 5 Data
Bandwidth3.2GBs6.4GBs Power Consumption399mW217mW
Slide 21
Computer Design 2007 Introduction 21 DDR2 Latency u Many
DDR2-533 modules have 4-4-4 timings (CAS Latency - RAS to CAS Delay
- RAS Precharge Time) 1.5 latency compared to DDR400 232 30% growth
of bandwidth does not compensates access time worsening u DDR2-533
latency improves considerably at 3-3-3 timings only 12% worse than
the latency of 2-3-2 DDR400 MemoryTimingsLatencydual-channel BW
DDR4002.5 3 312.5 ns6.4 GB/sec DDR40023223210 ns6.4 GB/sec
DDR53334434411.2 ns8.5 GB/sec DDR5332.5 3 39.4 ns8.5 GB/sec
DDR2-53355555518.8 ns8.5 GB/sec DDR2-53344444415 ns8.5 GB/sec
DDR2-53333333311.2 ns8.5 GB/sec DDR2-60055555516.6 ns9.6 GB/sec
DDR2-60044444413.3 ns9.6 GB/sec
Slide 22
Computer Design 2007 Introduction 22 DDR2 Latency (cont.) u
Performance tests DDR2-533 with 4-4-4 timings worse than DDR400 232
DDR2-533 with 3-3-3 timings better than DDR400 232 u DDR2-533
modules with 3-3-3 timings Supported by 925/915 best choice for
enthusiastic users significant improvement u Over-clocked
motherboards clock DDR2-533 at 600MHz realized through undocumented
memory frequency ratios available in i925/i915 u The performance of
DDR2-based systems is more sensitive to a lower latency than to a
higher frequency We get practically nothing from using DDR2-600
SDRAM with i925/i915
Slide 23
Computer Design 2007 Introduction 23 SRAM Static RAM u True
random access u High speed, low density, high power u No refresh u
Address not multiplexed u DDR SRAM 2 READs or 2 WRITEs per clock
Common or Separate I/O DDRII: 200MHz to 333MHz Operation; Density:
18/36/72Mb+ u QDR SRAM Two separate DDR ports: one read and one
write One DDR address bus: alternating between the read address and
the write address QDRII: 250MHz to 333MHz Operation; Density:
18/36/72Mb+
Slide 24
Computer Design 2007 Introduction 24 Read Only Memory (ROM) u
Random Access u Non volatile u ROM Types PROM Programmable ROM
Burnt once using special equipment EPROM Erasable PROM Can be
erased by exposure to UV, and then reprogrammed E 2 PROM
Electrically Erasable PROM Can be erased and reprogrammed on board
Write time (programming) much longer than RAM Limited number of
writes (thousands)
Slide 25
Computer Design 2007 Introduction 25 Flash Memory u
Non-volatile, rewritable memory limited lifespan of around 100,000
write cycles u Flash drives compared to HD drives: Smaller size,
faster, lighter, noiseless, consume less energy Withstanding shocks
up to 2000 Gs Equivalent to a 10 foot drop onto concrete - without
losing data Lower capacity (8GB), but going up Much more expensive
(cost/byte): currently ~20$/1GB u NOR Flash Supports per-byte
addressing Suitable for storing code (e.g. BIOS, cell phone SW) u
NAND Flash Supports page-mode addressing (e.g., 1KB blocks)
Suitable for storing large data (e.g. pictures, songs)
Slide 26
Computer Design 2007 Introduction 26 Hard Disks
Slide 27
Computer Design 2007 Introduction 27 Hard Disk Structure u
Direct access u Nonvolatile, Large, inexpensive, and slow Lowest
level in the memory hierarchy u Technology Rotating platters coated
with a magnetic surface Use a moveable read/write head to access
the disk Each platter is divided to tracks: concentric circles Each
track is divided to sectors Smallest unit that can be read or
written Disk outer parts have more space for sectors than the inner
parts Constant bit density: record more sectors on the outer tracks
speed varies with track location u Buffer Cache A temporary data
storage area used to enhance drive performance Platters Track
Sector
Slide 28
Computer Design 2007 Introduction 28 The IBM Ultrastar 36ZX u
Top view of a 36 GB, 10,000 RPM, IBM SCSI server hard disk u 10
stacked platters
Slide 29
Computer Design 2007 Introduction 29 Disk Access Read/write
data is a three-stage process u Seek time: position the arm over
the proper track Average: Sum of the time for all possible seek /
total # of possible seeks Due to locality of disk reference, actual
average seek is shorter: 4 to 12 ms u Rotational latency: wait for
desired sector to rotate under head The faster the drives spins,
the shorter the rotational latency time Most disks rotate at 5,400
to 15,000 RPM At 7200 RPM: 8 ms per revolution An average latency
to the desired information is halfway around the disk At 7200 RPM:
4 ms u Transfer block: read/write the data Transfer Time is a
function of: Sector size Rotation speed Recording density: bits per
inch on a track Typical values: 100 MB / sec u Disk Access Time =
Seek time + Rotational Latency + Transfer time + Controller Time +
Queuing Delay
Slide 30
Computer Design 2007 Introduction 30 The Disk Interface EIDE u
EIDE, ATA, UltraATA, ATA 100, ATAPI: all the same interface Uses
for connecting hard disk drives and CD-ROM drives 80-pin cable,
40-pin dual header connector 100 MB/s (ATA66 is only 66MB/s) EIDE
controller integrated with the motherboard (in the ICH) u EIDE
controller has two channels: primary and a secondary Work
independently Two devices per channel: master and slave, but equal
The 2 devices have to take turns controlling the bus A total of
four devices per cont If there are two device on the system (e.g.,
a hard disk and a CD-ROM) It is better to put them on different
channels Avoid mixing slower (CD) and faster devices (HDD) on the
same channel If doing a lot of copying from a CD-ROM drive to the
CD-RW Better performance by separating devices to separate
channels
Slide 31
Computer Design 2007 Introduction 31 The Disk Interface Serial
ATA (SATA) u Point-to-point connection Ensures dedicated 150 MB/s
per device (no sharing) u Dual controllers allow independent
operation of each device u Thinner (7 wires), flexible, longer
cables Easier routing and improved airflow 4 wires for signaling +
3 ground wires to minimize impedance and crosstalk u New 7-pin
connector design for easier installation and better device
reliability takes 1/6 the area on the system board u CRC error
checking on all data and control information u Increased BW
supports data intensive applications such as digital video
production, digital audio storage and recording, high-speed file
sharing u No configuration needed when a adding a 2 nd SATA drive
One cable for each drive eliminates the need for jumpers No more
figuring out which device is the master or slave u Today's hard
drives are clearly below 100 MB/s Do not benefit from UltraATA /
SATA
Slide 32
Computer Design 2007 Introduction 32 Some Disk Examples
sizeGB40 80 36.4 Platter Rotational SpeedRPM54007200 15K
InterfaceATA SATASCSI Average Latencyms5.64.2 4.72 Average Seek
Timems129993.6 Number of palters11112 Cache SizeMB22288 Max
Transfer RateMBps100 24086 Max Transfer Rate (Burst)MBps100 320
Sustained Lowest Transfer Rate MBps20 23 57 Sustained Highest
Transfer Rate MBps323542 76 Sizeinch3.5
Slide 33
Computer Design 2007 Introduction 33 RAID RAID 0 (Striping)RAID
1 (Data Mirror) Customer Sees: 2x120GB = 240GB120GB System:
Characteri- stics RAID controller breaks data to blocks;
distributes pieces to both drives RAID controller writes the same
data to both drives Customer Benefit Offers performance benefits
over a single hard drive configuration Offers data integrity: if
one drive fails, data is still intact on the other drive High
performance and capacity for storage intensive applications
Failsafe storage, while increasing read performance
Slide 34
Computer Design 2007 Introduction 34 CDROM / DVD Drive u Read
speed (max) Compared to the speed of an audio CD or a video DVD u
Write speed u Re-write speed u Capacity 700MB(CD), 4.7GB (DVD) u
Interface: EIDE/ATAPI u Data transfer rate (max): CD 48x : 7.2MB/s
= 153,600B/s x 48 DVD 16x: 21MB/s = 1,250,000B/s x 16 u CD-R
Recordable: can be written once u CD-RW ReWritable: can be
written/erased many times (upto 1000)
Slide 35
Computer Design 2007 Introduction 35 The Motherboard
Slide 36
Computer Design 2007 Introduction 36 Motherboard with PCI
Express Monitor L2 Cache CPU FSB 800MHz Graphics Adaptor Video Buff
North Bridge DRAM Ctrlr I/O Controller Floppy Disk Drive Key- board
Hard Disk Drive CD/ DVD ROM Drive South Bridge IDE Ctrlr PCI
Express 16 Memory Memory Bus Parallel PortSerial Port USB Ctrlr Hub
interface LCP SATA Ctrlr Hard Disk Drive PS2 mouse USB mouse PCI
Bus: 133MB/s = 32bit 33MHz Speakers Sound Card Modem Phone Line
Network card PCI express
Slide 37
Computer Design 2007 Introduction 37 The Motherboard IEEE-
1394a header audio header PCI add-in card connector PCI express x1
connector PCI express x16 connector Back panel connectors Processor
core power connector Rear chassis fan header LGA775 processor
socket GMCH: North Bridge + integ GFX Processor fan header DIMM
Channel A sockets Serial port header DIMM Channel B sockets
Diskette drive connector Main Power connector Battery ICH: South
Bridge + integ Audio 4 SATA connectors Front panel USB header
Speaker Parallel ATA IDE connector High Def. Audio header PCI
add-in card connector
Slide 38
Computer Design 2007 Introduction 38 How to get the most of
Memory ? u Single Channel DDR u Dual channel DDR Each DIMM pair
must be the same u Balance FSB and memory bandwidth 800MHz FSB
provides 800MHz 64bit / 8 = 6.4 G Byte/sec Dual Channel DDR400
SDRAM also provides 6.4 G Byte/sec L2 Cache CPU FSB Front Side Bus
Memory Memory Bus North Bridge DRAM Ctrlr CH A DDR DIMM DDR DIMM
DDR DIMM DDR DIMM CH B L2 Cache CPU FSB Front Side Bus North Bridge
DRAM Ctrlr
Slide 39
Computer Design 2007 Introduction 39 How to get the most of
Memory ? u Each DDR DIMM supports 4 open pages simultaneously The
more open pages, the more random access It is better to have more
DIMMs n DIMMs: 4n open pages u DIMMs can be single sided or dual
sided Dual sided DIMMs may have separate CS of each side In this
case the number of open pages is doubled (goes up to 8) This is not
a must dual sided DIMMs may also have a common CS for both sides,
in which case, there are only 4 open pages, as with single
side
Slide 40
Computer Design 2007 Introduction 40 USB Universal Serial Bus u
USB 2.0 providing 40 times the bandwidth of full-speed USB u
High-speed, full-speed, and low-speed USB devices u Enhanced Host
Controller Interface (EHCI) controller Supports high speed USB
signaling for data transfers up to 480 Mb/s u Universal Host
Controller Interface (UHCI) controllers Supports full-speed and
low-speed USB signaling u When a device is plugged in, ICHs port
routing logic differentiates whether a high-speed USB device or a
classic USB device is connected Configures the appropriate UHCI or
EHCI to control the device
Slide 41
Computer Design 2007 Introduction 41 PCI Express
Slide 42
Computer Design 2007 Introduction 42 Diverging I/O bus
Standards u Some I/O devices require higher bandwidth than PCI
delivers Higher bandwidth buses were defined for dedicated HW
Resulted in a variety of application-specific buses in the PC
platform u The processor system bus continues to scale in frequency
Memory bandwidths have increased to keep pace with the processor
The chipset is typically partitioned as a memory hub and an I/O hub
Isolates the ever-changing memory bus from the stable I/O CPU
Memory Bridge I/O Bridge MemoryGraphics HDD USB PCI ATA AGP
FSB
Slide 43
Computer Design 2007 Introduction 43 Interconnect Trends Device
1980s Device Bridge 1990s 2000s Bus vs. Switched Device CPU/Devic e
Device CPU/Devic e Device CPU/Devic e Switched Interconnect
Slide 44
Computer Design 2007 Introduction 44 PCI vs. PCI Express PCI u
Parallel Signaling 33MT/S to 266MT/S 32/64bit Bus Side band Control
Signals u Load-Store Architecture Memory, I/O, Config. u PCI Power
Management u Parity and ECC Parity PCI Express u Serial P2P
Differential Interface 2.5GT/S Scalable Width: 1X, 2X32X In-band
control u Load Store Architecture Memory, I/O, Config. &
Messages u Enhanced Configuration Mechanism u 100% compatible With
PCI SW u Advanced Power Management u Advanced RAS, Native Hot Plug
u Support for QoS PCI Express advanced features and scalable
performance enable it to become a unifying I/O solution across a
broad range of platforms
Slide 45
Computer Design 2007 Introduction 45 Chipset Example Intel
925XE
Slide 46
Computer Design 2007 Introduction 46 Intel 925XE u Optimized
for Hyper-Threading Technology u Front side bus 1066-and 800MHz FSB
Dual-channel DDR2 533 memory Up to 8.53 GB/s memory bandwidth Up to
a maximum of 4GB of RAM u PCI Express* Up to 4 GB/s per direction
for graphics bandwidth Up to 500 MB/s concurrent data transfers for
I/O u Intel Matrix Storage Technology Integrated Raid 0 and Raid 1
capabilities using the latest SATA interface u Intel High
Definition Audio Technology Eight independent DMA audio engines
Enable multiple separate, simultaneous audio streams Supports 7.1
surround sound, Dolby Digital, DTS
Slide 47
Computer Design 2007 Introduction 47 The BIOS
Slide 48
Computer Design 2007 Introduction 48 Starting Your System: How
the BIOS loads the OS When you turn on your computer, several
events occur automatically: 1. The CPU "wakes up" and sends a
message to activate the BIOS 2. BIOS runs the Power On Self Test
(POST): make sure system devices are working ok Initialize system
hardware and chipset registers Initialize power management Test RAM
Enable the keyboard Test serial and parallel ports Initialize
floppy disk drives and hard disk drive controllers Displays system
summary information 3. During POST, the BIOS compares the system
configuration data obtained from POST with the system information
stored on a memory chip located on the MB A CMOS chip, which is
updated whenever new system components are added Contains the
latest information about system components. 4. After the POST tasks
are completed the BIOS looks for the boot program responsible for
loading the operating system Usually, the BIOS looks on the floppy
disk drive A: followed by drive C: 5. After being loaded into
memory, the boot program then loads the system configuration
information contained in the registry in a Windows environment and
device drivers 6. Finally, the operating system is loaded
Slide 49
Computer Design 2007 Introduction 49 Monitors
Slide 50
Computer Design 2007 Introduction 50 CRT Monitors u Primary
light colors Red, Green and Blue (RGB) Added to create any other
color u Pixel a color dot on the screen Contains 3 phosphors RGB u
How it works An electrons gun produces an electron beam hits the
phosphor coated screen When the beam hits a phosphor it produces
light The beam scans all the pixels in the screen The intensity of
the beam is controlled for each phosphor in each pixel u There are
2 common types of tubes Invar shadow mask tube The mask is a thin
sheet of metal (Invar) perforated with holes Aperture grille tube
(Sony's Trinitron) An array of thinly stretched wires and phosphor
stripes Requires horizontal damping wires to hold the grille in
place
Slide 51
Computer Design 2007 Introduction 51 Monitor Parameters u Dot
Pitch Distance between a phosphor dot and the nearest dot of the
same color A smaller dot pitch means more closely spaced pixels
sharper picture Typical dot : 0.25mm u Resolution The number of
pixels in the screen Defined by common Standards VGA (Video
Graphics Array) 640 480 SVGA (Super Video Graphics array): 800 600
UVGA (Ultra Video Graphics Array). 1024 768 VESA (Video Electronic
Standards Association)1280 1024 1600 1200 u Viewable Area The
actual screen size (excluding dead area around the CRT outer edge)
Example: a 17" CRT the viewable area ranges from 15.8" to 16.1 In
LCD monitors, the Viewable Area equals the specified area
Slide 52
Computer Design 2007 Introduction 52 Monitor Parameters (cont.)
u Brightness Light output measured at the faceplate of the screen
Typically measured in foot-lamberts (Fl). A minimum brightness
level of 20Fl when viewing at full-page size is considered
acceptable u Vertical refresh rate Number of times the monitor
displays a complete image each second High refresh rate more stable
screen image that is easier on the eyes A low refresh rate means
you will see noticeable screen flicker A vertical refresh rate of
85Hz is acceptably ergonomic u Interlaced Scanning Vs.
Non-interlaced Mode Interlaced Scanning takes two passes to paint
an on screen image One scan for even lines and the other for odd
lines Non-interlaced Scanning takes one pass to paint an on screen
image Preferred, as it reduces flicker u Low Emission Special
shielding to lower emission (safety standard: MPRII and TCO)
Slide 53
Computer Design 2007 Introduction 53 LCD Monitors u Viewable
Screen Size = Monitor size u LCD Type TFT/Active Matrix one
transistor per pixel to retain image quality between scans u Pixel
pitch: 0.3 0.25 mm (better) u Horizontal Scan (KHz): 31 80 u
Vertical scan refresh (Hz): 55 85 u Horizontal Viewing Angle: +/-80
+/-85 Angle range at which minimum acceptable viewing parameters
(5:1 contrast ratio, good brightness, and front-of-screen
performance) is maintained u Vertical Viewing Angle: +/-80 +/-85 u
Response time (black white + white black): 8ms 2ms Fast response
time prevents "ghosting" as an image is moved Important when
viewing motion video u Brightness: 250 nits u Contrast ratio: 350:1
600:1
Computer Design 2007 Introduction 55 Printing Parameters u
Printing Speed Measured in pages per minute (p.p.m) Personal
Printers: 4 - 5 p.p.m. Office Printers: 8 - 12 p.p.m. Workgroup
Printers:15 - 30 p.p.m. Production Printers: 50 p.p.m - 200 p.p.m
Dependant on the complexity of the page Printing speed of complex
pages may be limited by processing time u Printing Resolution The
number of individual dots it can print within a specified area
Typical 600 x 600 dots per square inch (600 DPI)
Computer Design 2007 Introduction 57 Laser Printer Structure u
The Laser Scanning Assembly is comprised of Laser: emits a very
brief pulse of light for each dot to be printed No pulse for blank
areas Mirror: deflects the laser beam in the horizontal axis
Carefully synchronized with the laser to position dots along a line
Vertical movement is achieved by moving the photoreceptor Lens:
corrects the beam positioning Counteract the divergent effect
caused by the edges of the photoreceptor being further from the
mirror than the center u The drum (photoreceptor): a cylinder with
a very smooth surface Can accept an electrostatic charge, and is
discharged by light Before exposure to the laser beam the drum is
charged evenly all over by the charger corotron (a wire carrying a
very high voltage) The laser beam creates a pattern of discharged
dots The drum revolves continuously The laser scans the drum very
fast, so dots appear to be in a straight line As the drum revolves
it passes the developer unit Charged dots on the drum attract toner
from the charged developer roller
Slide 58
Computer Design 2007 Introduction 58 Laser Printer Structure
(cont) u Once the paper has passed the drum and attracted the toner
The detac corotron cancels the charge on the paper Prevent it from
sticking to the photoreceptor or other sheets of paper u The drum
passes the discharge lamp Exposes the whole width of the drum to
light to erase residual charge u Fuser Once the toner transferred
from the drum it lies on the paper in a very thin coating, with
nothing to hold it in place Paper is heated, by passing between a
pair of very hot rollers, so that the plastic toner melts around
the fibers of the paper and is "fused" into place Fixes the toner
to the paper permanently
Slide 59
Computer Design 2007 Introduction 59 Backup
Slide 60
Computer Design 2007 Introduction 60 The Disk Interface SCSI u
Small Computer System Interface u SCSI hard disks are more
expensive than EIDE hard disks u SCSI requires an extra controller,
connected to the PCI bus u In a standard environment, the
performance of single hard disk wont improve much from the SCSI
interface u The power of SCSI is that several devices can use the
bus at the same time, not using the bus while they dont need it u
The best benefit from SCSI is when several devices are all used on
the same bus
Slide 61
Computer Design 2007 Introduction 61 Motherboard with AGP PCI
Bus: 133MB/s = 32bit 33MHz Monitor L2 Cache CPU FSB 800MHz Graphics
Adaptor Video Buff North Bridge DRAM Ctrlr PCI Expan. Slots I/O
Controller Floppy Disk Drive Key- board Speakers Sound Card Hard
Disk Drive CD/DVD ROM Drive South Bridge IDE Ctrlr AGP8 Memory
Memory Bus Parallel PortSerial Port Modem Phone Line Network card
USB Ctrlr Hub interface LCP SATA Ctrlr Hard Disk Drive PS2 mouse
USB mouse
Slide 62
Computer Design 2007 Introduction 62 AGP - Accelerated Graphics
Port u A high performance, interconnect for 3D graphics adaptors
based on an enhanced 66 MHz PCI bus u Specification developed by
Intel u AGP Pro Primarily designed to deliver additional electrical
power to the graphics cards to meet the needs of advanced
workstation graphics AGP accepts AGP 1.0 and 2.0 cards depending on
the connector used u AGP3.0 offers also feature enhancements to
AGP2.0 BandwidthBus CycleAGP 1.0 AGP 2.0 AGP Pro AGP 3.0 1x266MB/s8
bytes per two clock cycles++++ 2x533MB/s8 bytes per clock cycle++++
4x1.07GB/s16 bytes per clock cycle+++ 8x2.1GbB/s32 bytes per clock
cycle+
Slide 63
Computer Design 2007 Introduction 63 Chipset Example Intel
875P
Slide 64
Computer Design 2007 Introduction 64 DRAM Standards
LabelNameEffective Clock RateData BusBandwidth PC66SDRAM66 MHz64
Bit0,5 GB/s PC100SDRAM100 MHz64 Bit0,8 GB/s PC133SDRAM133 MHz64
Bit1,06 GB/s PC1600DDR200100 MHz64 Bit1,6 GB/s PC1600DDR200 Dual100
MHz2 x 64 Bit3,2 GB/s PC2100DDR266133 MHz64 Bit2,1 GB/s
PC2100DDR266 Dual133 MHz2 x 64 Bit4,2 GB/s PC2700DDR333166 MHz64
Bit2,7 GB/s PC2700DDR333 Dual166 MHz2 x 64 Bit5,4 GB/s
PC3200DDR400200 MHz64 Bit3,2 GB/s PC3200DDR400 Dual200 MHz2 x 64
Bit6,4 GB/s PC4200DDR533266 MHz64 Bit4,2 GB/s PC4200DDR533 Dual266
MHz2 x 64 Bit8,4 GB/s PC800RDRAM Dual400 MHz2 x 16 Bit3,2 GB/s
PC1066RDRAM Dual533 MHz2 x 16 Bit4,2 GB/s PC1200RDRAM Dual600 MHz2
x 16 Bit4,8 GB/s PC800RDRAM Dual400 MHz2 x 32 Bit6,4 GB/s
PC1066RDRAM Dual533 MHz2 x 32 Bit8,4 GB/s PC1200RDRAM Dual600 MHz2
x 32 Bit9,6 GB/s
Slide 65
Computer Design 2007 Introduction 65 More On PCI Express
Slide 66
Computer Design 2007 Introduction 66 PCI Limitations vs.
Growing Needs u PCI is a multi-drop, parallel bus Close to its
practical limits of performance Cannot be easily scaled up in
frequency or down in voltage Pushing the limits result in large
cost increases for little performance gain u Buses Dont scale
number of connections scale physically scale bandwidth support
multiple traffic types support high availability u Todays software
applications are more demanding Streaming data from various video
and audio sources are now common Multiple concurrent transfers at
ever-increasing data rates It is no longer acceptable to treat all
data as equal Streaming data must be processed at real-time
Slide 67
Computer Design 2007 Introduction 67 3 rd Generation Local I/O
bus Requirements u Supports multiple market segments and emerging
applications: Unified I/O Architecture for Desktop, Mobile, Server,
Communications Platforms, Workstations and Embedded Devices u Low
cost and high volume Cost at or below PCI cost structure at the
system level u PCI Compatible software model Boot existing
operating systems without any change PCI compatible configuration
and device driver interfaces u Performance: Scalable performance
via frequency and additional lanes High Bandwidth per Pin. Low
overhead. Low latency. u Support multiple platform connection types
Chip-to-chip, board-to-board via connector, docking station and
enable new form factors u Advanced features Comprehend different
data types. Power Management. Quality Of Service. Hot Plug and Hot
Swap support. Data Integrity and Error Handling. Extensible. Base
mechanisms to enable Embedded and Communications applications. u
Non-Goals Coherent interconnect for processors, memory
interconnect, cable interconnect for cluster solutions.
Slide 68
Computer Design 2007 Introduction 68 PCI Express Architecture u
SW layers generate read and write requests Transported by the
transaction layer to the I/O devices Using a packet-based,
split-transaction protocol u The link layer adds sequence numbers
and CRC to these packets Create a highly reliable data transfer
mechanism u The basic physical layer consists of a dual-simplex
channel Implemented as a transmit pair and a receive pair u The
initial speed of 2.5 Giga transfers/second/direction provides a
200MB/s communications channel close to twice the classic PCI data
rate
Slide 69
Computer Design 2007 Introduction 69 PCI Express Layered
Architecture u Compatible with the PCI addressing model A
load-store architecture with a flat address space All existing
applications and drivers operate unchanged SW Physical Point to
point, serial, differential, hot-plug, inter-op form factors Data
Integrity Data Link 2.5Gb/s Transaction Packet Switching HW PCI
SW/Driver Model PCI PnP (init, enum, config) Operating System Use
standard mechanisms, as defined in PCI Plug-and-Play spec Adds Seq
num and CRC, Link Synchronization, Auto negotiation, Link status
Data routing, Credit based flow control, Event and error handling,
etc.
Slide 70
Computer Design 2007 Introduction 70 PCI Express Physical Layer
u Transport packets between the link layers of two PCI Express
agents u The fundamental PCI Express link Point to point Consists
of two, low-voltage, differentially driven pairs of signals A
transmit pair and a receive pair Clock is embedded on the data
using the 8b/10b encoding scheme Initial frequency is 2.5G
transfers/sec/direction Can be increased to 10G with silicon
technology advances The theoretical maximum for signals in copper u
PCI Express link bandwidth may be linearly scaled By adding signal
pairs to form multiple lanes The physical layer supports x1, x2,
x4, x8, x12, x16 and x32 lane widths u During initialization Each
PCI Express link is set up following a negotiation of lane widths
and frequency of operation by the two agents at each end of the
link No firmware or operating system software is involved u Future
speeds would only impact the physical layer
Slide 71
Computer Design 2007 Introduction 71 PCI Express Link Layer u
Ensure reliable delivery of packets across PCI Express link u
Responsible for data integrity Adds a sequence number and a CRC to
the transaction layer packet u A credit-based, flow control
protocol Ensures that packets are only transmitted when it is known
that a buffer is available to receive this packet at the other end
Eliminates packet retries saves waste of bus bandwidth u
Automatically retry a packet that is signaled as corrupted
Slide 72
Computer Design 2007 Introduction 72 Transaction Layer u
Receives read and write requests from the SW layer Creates request
packets for transmission to the link layer Some of the request
packets need a response packet u Receives response packets from the
link layer Matches them with the original SW requests according to
unique identifier u Packet format supports 32bit and extended 64bit
memory addressing u Packets have attributes (e.g., no-snoop,
relaxed-ordering, priority) Used to optimally route these packets
through the I/O subsystem u Supports four address spaces The three
PCI address spaces (memory, I/O and configuration) A Message Space:
can be thought of as virtual wires Eliminates the wide array of
sideband signals currently used in PCI u Uses Message Signaled
Interrupt (MSI) to propagate system interrupts PCI Express uses
Message Space to support all prior hard-wired side-band signals
Interrupts, power-management requests, resets
Slide 73
Computer Design 2007 Introduction 73 Software Layers u PCI
Express Software compatibility Initialization, or enumeration: PCI
has a robust initialization model: the OS can discover all add-in
HW devices present and then allocate system resources, such as
memory, I/O space and interrupts, to create an optimal system
environment PCI configuration space and the programmability of I/O
devices are key concepts that are unchanged within the PCI Express
Architecture; All operating systems will be able to boot without
modification on a PCI Express-based platform Run-time SW model PCI
uses a load-store, shared memory model Maintained by PCI Express
All existing software executes unchanged PCI Express is SW
compatible with all existing PCI-based SW Enable smooth integration
within future systems. u New software may use new capabilities
Slide 74
Computer Design 2007 Introduction 74 Mechanical Form Factors u
Evolutionary Design Replace AGP and PCI cards PCI Express add-in
cards co-exist with PCI-form factor boards Use a new connector
placed alongside the existing PCI or AGP connector in the area
previously occupied by those type of connectors u PCMCIA announced
the development of ExpressCard Integrated desktop and mobile
external expansion The next evolution of the PC Card Smaller form
factor Faster performance