Embed Size (px)
Citation preview
2
Welcome
• Office Hours: – Tuesdays 10:00 – 11:30 A.M.
• Office: Eng-Building, Last Floor, Room
344
• Tel: 0313 793 4533
• Course Web Site: eng.ui.ac.ir/~m.rezaei/architecture/index.html
3
Text book
Computer
Organization &
Design: The
Hardware/Software
Interface David A. Patterson and John
E. Hennessy
5th Edition, Morgan Kaufmann,
2013
http://booksite.elsevier.com/97
80124077263/
4
Overview
• Intro to Computer Architecture
• Administrative Matters
• Course Style, Philosophy and Structure
• High Level, Assembly, and Machine Language
• Anatomy of computer system
• Computer Architecture – realistic view
5
What is “Computer Architecture”
Computer Architecture = ?
6
What is “Computer Architecture”
Computer Architecture =
Instruction Set Architecture +
Machine Organization
7
Instruction Set Architecture
... the attributes of a [computing] system as seen by the
programmer, i.e. the conceptual structure and
functional behavior, as distinct from the organization
of the data flows and controls the logic design, and
the physical implementation. Amdahl, Blaaw, and
Brooks, 1964 SOFTWARESOFTWARE
-- Organization of Programmable Storage -- Data Types & Data Structures: Encodings & Representations -- Instruction Set -- Instruction Formats -- Modes of Addressing and Accessing Data Items and Instructions -- Exceptional Conditions
Slide from Dave Patterson
8
The Instruction Set: a Critical Interface
instruction set
software
hardware
Slide from Dave Patterson
9
Example ISAs (Instruction Set Architectures)
Alpha (v1, v3, … , ev8) 1992-2003
HP PA-RISC (v1.1, v2.0) 1986-2003
Sun Sparc (v8, v9) 1987-2003
SGI MIPS(MIPS I, …, IV, V) 1986-96
Intel 1971-2003 (4004, …, 8086, … 80486, Pentium, MMX, PII, …, PIV, Itanium, Xeon)
10
MIPS R3000 Instruction Set Architecture
• Instruction Categories
– Load/Store
– Computational
– Jump and Branch
– Floating Point
• coprocessor
– Memory Management
– Special
R0 - R31
PC
HI
LO
OP
OP
OP
rs rt rd sa funct
rs rt immediate
jump target
3 Instruction Formats: all 32 bits wide
Registers
11
Organization
• Capabilities & Performance Characteristics of Principal Functional Units (e.g., Registers, ALU, Shifters, Logic Units, ...)
• Ways in which these components are interconnected
• Information flows between components Data path
• Logic and means by which such information flow is controlled. Control unit
• Choreography of FUs to realize the ISA
12
What is “Computer Architecture”?
Coordination of many levels of abstraction
Under a rapidly changing set of forces
Design, Measurement, and Evaluation
I/O system Instr. Set Proc.
Compiler
Operating System
Application
Digital Design Circuit Design
Instruction Set Architecture
Firmware
Datapath & Control
Layout
Slide from Dave Patterson
13
Course Style (overview handout)
• Grade breakdown
– Midterm Exam: 30%
– Final Exam: 50%
– Projects 20%
– Homework Assignments: 10%
• No late homework
• Passing Grade
– Projects + Homework : necessary requirements
– Reasonable grades on exams (50% above)
14
Academic Honesty vs. Cheating
• Don’t cheat
– If you submit something, it should be your own work
– Scholarly work
• Give credit to whom you get the idea from
– Plagiarizing is forbidden
• What happens if you cheat
– I will inform
• Department
• Provost
• I will give you an F
• What I am trying to say is “Do not cheat”
15
Course Materials (Systematically)
• Instruction Set Architecture
• Measuring the performance of computer system
• CPU design, single cycle and pipelined CPU
• Memory Systems
• I/Os – We won’t have time, read on your own.
16
Where are we?
• Intro to Computer Architecture
• Administrative Matters
• Course Style, Philosophy and Structure
• High Level, Assembly, Machine Language
• Anatomy of computer system
• Computer Architecture – realistic view
17
High Level Language Program
Assembly Language Program
Machine Language Program
Control Signal Specification
Compiler
Assembler
Machine Interpretation
0000 1001 1100 0110 1010 1111 0101 1000
1010 1111 0101 1000 0000 1001 1100 0110
1100 0110 1010 1111 0101 1000 0000 1001
0101 1000 0000 1001 1100 0110 1010 1111
°
°
ALUOP[0:3] <= InstReg[9:11] & MASK
High Level, Assembly, Machine language, and
control signals
temp = v[k];
v[k] = v[k+1];
v[k+1] = temp;
lw $15, 0($2)
lw $16, 4($2)
sw $16, 0($2)
sw $15, 4($2)
Slide from Dave Patterson
18
Levels of Organization (computer Anatomy)
SPARCstation 20
Processor
Computer
Control
Datapath
Memory Devices
Input
Output
Workstation Design Target:
25% of cost on Processor
25% of cost on Memory
(minimum memory size)
Rest on I/O devices,
power supplies, box
Slide from Dave Patterson
19
Another view
System Bus
CPU
Cache
BIU
DRAM
Bridge
I/O Bus
Hard disk Controller
Video Controller
Keyboard Controller NIC
I/O Expa- nsion
Secondary Storage Video
Monitor Keyboard Network
Memory Controller
20
Example Organization
TI SuperSPARCtm TMS390Z50 in Sun SPARCstation20
Floating-point Unit
Integer Unit
Inst
Cache
Ref
MMU
Data
Cache
Store
Buffer
Bus Interface
SuperSPARC
L2
$ CC
MBus Module
MBus
L64852 MBus control
M-S Adapter
SBus
DRAM
Controller
SBus DMA
SCSI
Ethernet
STDIO
serial
kbd mouse
audio
RTC
Boot PROM
Floppy
SBus
Cards
21
Execution Cycle
Instruction
Fetch
Instruction
Decode
Operand
Fetch
Execute
Result
Store
Next
Instruction
Obtain instruction from program storage
Determine required actions and instruction size
Locate and obtain operand data
Compute result value or status
Deposit results in storage for later use
Determine successor instruction
DLQ
• Computer Architecture is?
22
23
(final thoughts) Forces on Computer
Architecture
Computer
Architecture
Technology Programming Languages
Operating
Systems
History
Applications
Why Technology Matters
25
A Prediction by Gordon Moore
0
2
4
6
8
10
12
14
16
18
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
year
Lo
g2 o
f N
um
ber
of
Co
mp
on
en
ts
per
Inte
gra
ted
Fu
ncti
on
Courtesy of the graph – Cramming more components
onto integrated circuits, Electronics, 38(8), April 1965
26
The Growth in CPU Speed (lately)
Sources: J. S. EmerJ. S. Emer. “Simultaneous Multithreading: Multiplying Alpha's
Performance”, 12 th Microprocessor Forum, October 1999.
R. E. KesslerR. E. Kessler. “The Alpha 21264 Microprocessor”, IEEE Micro,
19(2), pp. 2436, March/April 1999.
V. A. KlauserV. A. Klauser. “Trends in HighPerformance Microprocessor
Design”, Telematik, 7(1), pp. 1221, April 2001.
Chip's name 21064 - EV4 21164 - EV5 21264 - EV6 21364 - EV7 21464 - EV8
Introduced 1992 1995 1998 X X
Technology 0.75 - 0.5 mm 0.5 - 0.35 mm 0.35 mm 0.18 mm 0.125 mm
Transistors 1.68 M 9 M 15 M 152 M 250 M
Frequency 150 - 275 MHz 300 - 600 MHz 0.6 - 1 GHz 1.2 - 1.4 GHz 1.2 - 2 GHz
Architecture 2-Way In-Order 4-Way In-Order 4-Way Out-Of-Order 4-Way Out-Of-Order 8-Way Out-Of-Order
System on a Chip 4-Way SMT, SoC
27
Pace In Memory Speed
Column Access
Strobe (CAS)/
Year of Slowest Fastest data transfer Cycle
Introduction Chip Size DRAM (ns) DRAM (ns) time (ns) time (ns)
1980 64K bit 180 150 75 250
1983 256K bit 150 120 50 220
1986 1M bit 120 100 25 190
1989 4M bit 100 80 20 165
1992 16M bit 80 60 15 120
1996 64M bit 70 50 12 110
1998 128M bit 70 50 10 100
2000 256M bit 65 45 7 90
2002 512M bit 60 40 5 80
Row Access Strobe (RAS)
Courtesy of the table:JJ. L. Hennessy and D. A. Patterson. L. Hennessy and D. A. Patterson. ``Computer
Architecture: A Quantitative Approach'', Morgan Kaufmann Publishers, Third
Edition 2003.
28
CPU-Memory Speed Gap
1
10
100
1000
10000
100000
1980
1982
1984
1986
1988
1990
1992
1994
1996
1998
2000
2002
2004
Year
Performance
Memory CPU
Courtesy of the Graph:J. L. Hennessy and D. A. PattersonJ. L. Hennessy and D. A. Patterson. ``Computer
Architecture A Quantitative Approach'', Morgan Kaufmann Publishers, Third
Edition 2003.
Ever-increasing
CPU-Mem S-Gap
DLQ
• 5 Stages of Instruction Execution?
• 5 main Components of any computer
system?
29
