Computer Organization and Computer Organization and DesignDesign

Building a Computer!Building a Computer!

Montek SinghMontek Singh

Wed, April 20, 2011Wed, April 20, 2011

Lecture 15Lecture 15

Building a ComputerBuilding a ComputerTHIS IS IT!THIS IS IT!

We are now ready to We are now ready to build a computer.build a computer.

The ingredients are The ingredients are all in place, so let’s all in place, so let’s put them together…put them together…

I wonder wherethis goes?

Instruction

Memory

A

D

0

1

MIPS Kit

ALU

A

B

Review: The MIPS ISAReview: The MIPS ISA

Instruction classesdistinguished by types:1) 3-operand ALU2) ALU w/immediate3) Loads/Stores4) Branches5) Jumps

Instruction classesdistinguished by types:1) 3-operand ALU2) ALU w/immediate3) Loads/Stores4) Branches5) Jumps

The MIPS instruction set as seen from a Hardware Perspective

OP

6 5 5 5 5 616

26

000000 rs rt rd funcshamt

R-type: ALU with Register operands Reg[rd] Reg[rs] op Reg[rt]

001XXX rs rtimmediate

I-type: ALU with constant operandReg[rt] Reg[rs] op SEXT(immediate)

10X011 rs rtimmediate

I-type: Load and StoreReg[rt] Mem[Reg[rs] + SEXT(immediate)]Mem[Reg[rs] + SEXT(immediate)] Reg[rt]

I-type: Branch Instructionsif (Reg[rs] == Reg[rt]) PC PC + 4 + 4*SEXT(immediate) if (Reg[rs] != Reg[rt]) PC PC + 4 + 4*SEXT(immediate)

10X011immediate

rs rt

00001X 26-bit constant J-type: jump

PC (PC & 0xf0000000) | 4*(immediate)

Design ApproachDesign Approach““Incremental Featurism”Incremental Featurism”

We’ll implement circuits for each type of instruction We’ll implement circuits for each type of instruction individually, and merge them (using MUXes, etc).individually, and merge them (using MUXes, etc).

Our Bag of Components:

Registers

0 1 Muxes

ALUA B ALU & adders

DataMemory

WD

A

RD

R/W

RegisterFile

(3-port)

RA1 RA2

WA

WE

WD

RD1 RD2

InstructionMemory

A

D

Memories

+

Steps:Steps: 1. 3-Operand ALU instrs1. 3-Operand ALU instrs 2. ALU w/immediate instrs2. ALU w/immediate instrs 2. Loads & Stores2. Loads & Stores 3. Jumps & Branches 3. Jumps & Branches 4. Exceptions4. Exceptions

A Few ALU TweaksA Few ALU Tweaks Let’s review the ALU that we built a few Let’s review the ALU that we built a few

lectures ago.lectures ago.(With a few minor additions)(With a few minor additions)

FlagsV,C

A B

R

BidirectionalBarrelShifter

BooleanAdd/SubSub

Bool

Shft

Math

1 0

1 0 …

NFlag

ZFlag

Sub Bool Shft Math OP 0 XX 0 1 A+B 1 XX 0 1 A-B X X0 1 1 0 X X1 1 1 1 X 00 1 0 B<<A X 10 1 0 B>>A X 11 1 0 B>>>A X 00 0 0 A & B X 01 0 0 A | B X 10 0 0 A ^ B X 11 0 0 A | B

0 1

5-bit ALUFN

Instruction Fetch/DecodeInstruction Fetch/Decode Use a counter to FETCH Use a counter to FETCH

the next instruction:the next instruction: PROGRAM COUNTER (PC)PROGRAM COUNTER (PC)

use PC as memory addressuse PC as memory address add 4 to PC, load new value add 4 to PC, load new value

at end of cycleat end of cycle fetch instruction from fetch instruction from

memorymemory use some instruction fields use some instruction fields

directly (register numbers, directly (register numbers, 16-bit constant)16-bit constant)

use bits <31:26> and use bits <31:26> and <5:0> to generate controls<5:0> to generate controls

INSTRUCTIONWORDFIELDS

PC

+4

InstructionMemor

y

A

D

Control Logic

CONTROL SIGNALS

00

OP[31:26], FUNC[5:0]

32

32

32

3-Operand ALU Data Path3-Operand ALU Data Path

RegisterFile

RA1 RA2

RD1 RD2

WA WD

WE

Rd: <15:11>

PC

+4

InstructionMemory

A

D

Rt: <20:16>

ALUA B

ALUFN

Control Logic

WERF

ALUFN

WERF

00

32 32

32

Rs: <25:21>

000000 rs rt rd 100XXX00000

R-type: ALU with Register operands Reg[rd] Reg[rs] op Reg[rt]

WERF!

Shift InstructionsShift Instructions

RegisterFile

RA1 RA2

RD1 RD2

WA WD

WE

Rd: <15:11>

PC

+4

InstructionMemory

A

D

Rt: <20:16>

ALUA B

ALUFN

Control Logic

WERF

ALUFN

WERF

00

32

000000 rs rt rd 000XXXshamt

R-type: ALU with Register operands sll: Reg[rd] Reg[rt] (shift) shamtsllv: Reg[rd] Reg[rt] (shift) Reg[rs]

ASEL

Rs: <25:21>

ASEL10

shamt:<10:6>

ASEL!

ALU with ImmediateALU with Immediate

WA

PC

+4

InstructionMemory

A

D

Rt: <20:16>

RegisterFile

RA1 RA2

RD1 RD2

ALUA B

WA WD

WE

ALUFN

Control Logic

ALUFN

BSEL01

imm: <15:0>

BSEL

WERF

WERF

00

BSEL!

001XXX rs rtimmediat

e

I-type: ALU with constant operandReg[rt] Reg[rs] op SEXT(immediate)

Rd:<15:11>

Rt:<20:16>0

1

SEXTSEXT

SEXT

ASEL

BSEL

Rs: <25:21>

ASEL10

shamt:<10:6>

How do you build

SEXT?

Load InstructionLoad Instruction

WA

PC

+4

InstructionMemory

A

D

RegisterFile

RA1 RA2

RD1 RD2

ALUA B

WA WD

WE

ALUFN

Control Logic

Imm: <15:0>

Data Memory

RD

WD R/W

Adr

Wr

WDSEL0 1 2

BSELWDSELALUFNWr

WERF

WERF

00

32

32

Rd:<15:11>

Rt:<20:16>0

1

BSEL

SEXT

100011 rs rtimmediat

e

I-type: LoadReg[rt] Mem[Reg[rs] + SEXT(immediate)]

ASEL

Rt: <20:16>Rs: <25:21>

SEXT

BSEL01

SEXT

ASEL10

shamt:<10:6>

Store InstructionStore Instruction

WA

PC

+4

InstructionMemory

A

D

RegisterFile

RA1 RA2

RD1 RD2

ALUA B

WA WD

WE

ALUFN

Control Logic

Imm: <15:0>

Data Memory

RD

WD R/W

Adr

Wr

WDSEL0 1 2

BSELWDSELALUFNWr

WERF

WERF

00

32

Rd:<15:11>

Rt:<20:16>0

1

SEXT

ASEL

10X011 rs rtimmediat

e

I-type: StoreMem[Reg[rs] + SEXT(immediate)] Reg[rt]

Rt: <20:16>

BSEL

No WERF!

Rs: <25:21>

ASEL10

SEXT

BSEL01

SEXT

shamt:<10:6>

JMP InstructionsJMP Instructions

WA

PC

+4

InstructionMemory

A

D

RegisterFile

RA1 RA2

RD1 RD2

ALUA B

WA WD

WE

ALUFN

Control Logic

Data Memory

RD

WD R/W

Adr

Wr

WDSEL0 1 2

BSELWDSELALUFNWr

J:<25:0>

PCSEL

WERF

WERF

00

32

PC+4

Rt: <20:16>

Imm: <15:0>

ASEL

SEXT

00001X 26-bit constant

J-type: j: PC (PC & 0xf0000000) | 4*(immediate) jal: PC (PC & 0xf0000000) | 4*(immediate);

Reg[31] PC + 4

PC<31:29>:J<25:0>:00

WASEL

Rs: <25:21>

ASEL10

SEXT

BSEL01

SEXT

shamt:<10:6>

PCSEL 0123456

WASEL

Rd:<15:11>Rt:<20:16> 0

1231

BEQ/BNE InstructionsBEQ/BNE Instructions

WA

PC

+4

InstructionMemory

A

D

RegisterFile

RA1 RA2

RD1 RD2

ALUA B

WA WD

WE

ALUFN

Control Logic

Data Memory

RD

WD R/W

Adr

Wr

WDSEL0 1 2

BSELWDSELALUFNWr

J:<25:0>

PCSEL

WERF

WERF

00

32

PC+4

Rt: <20:16>

Imm: <15:0>

ASEL

SEXT

10X011immediat

ers rt

R-type: Branch Instructionsif (Reg[rs] == Reg[rt]) PC PC + 4 + 4*SEXT(immediate)if (Reg[rs] != Reg[rt]) PC PC + 4 + 4*SEXT(immediate)

+x4

BT

Z

Z

BT

PC<31:29>:J<25:0>:00

Why add, another adder? Couldn’t we reuse the one in the ALU? Nope, it needs to do a subtraction.

That “x4” unit is trivial. I’ll just wire the input shifted over 2–bit positions.

WASEL

Rs: <25:21>

ASEL10

SEXT

BSEL01

SEXT

shamt:<10:6>

PCSEL 0123456

WASEL

Rd:<15:11>Rt:<20:16>

31

012

Jump Indirect InstructionsJump Indirect Instructions

WA

PC

+4

InstructionMemory

A

D

RegisterFile

RA1 RA2

RD1 RD2

ALUA B

WA WD

WE

ALUFN

Control Logic

Data Memory

RD

WD R/W

Adr

Wr

WDSEL0 1 2

BSELWDSELALUFNWr

J:<25:0>

PCSEL

WERF

WERF

00

32

PC+4

Rt: <20:16>

Imm: <15:0>

ASEL

SEXT

R-type: Jump Indirect, Jump and Link Indirectjr: PC Reg[rs]jalr: PC Reg[rs], Reg[rd] PC + 4

Z

Z

BT

WASEL

PC<31:29>:J<25:0>:00

000000 rs rt rd 00100X00000

JT

JT

Rs: <25:21>

ASEL10

SEXT

BSEL01

SEXT

shamt:<10:6>

PCSEL 0123456

WASEL

Rd:<15:11>Rt:<20:16>

31

012

BT

+x4

Loose EndsLoose Ends

WA

PC

+4

InstructionMemory

A

D

RegisterFile

RA1 RA2

RD1 RD2

ALUA B

WA WD

WE

ALUFN

Control Logic

Data Memory

RD

WD R/W

Adr

Wr

WDSEL0 1 2

BSELWDSELALUFNWr

J:<25:0>

PCSEL

WERF

WERF

00

32

PC+4

Rt: <20:16>

Imm: <15:0>

ASEL

SEXT

I-type: set on less than & set on less than unsigned immediate slti: if (Reg[rs] < SEXT(imm)) Reg[rt] 1; else Reg[rt] 0 sltiu: if (Reg[rs] < SEXT(imm)) Reg[rt] 1; else Reg[rt] 0

Z

Z

BT

WASEL

PC<31:29>:J<25:0>:00

JT

JT

001XXXimmediat

ers rt

VN

N V

Reminder:To evaluate (A < B) we first compute A-B and look at the flags.

LT = N V LTU = C

C

C

Rs: <25:21>

ASEL10

SEXT

BSEL01

SEXT

shamt:<10:6>

PCSEL 0123456

Rd:<15:11>Rt:<20:16>

WASEL

31

012

BT

+x4

More Loose EndsMore Loose Ends

WA

PC

+4

InstructionMemory

A

D

RegisterFile

RA1 RA2

RD1 RD2

ALUA B

WA WD

WE

ALUFN

Control Logic

Data Memory

RD

WD R/W

Adr

Wr

WDSEL0 1 2

BSELWDSELALUFNWr

J:<25:0>

PCSEL

WERF

WERF

00

32

PC+4

Rt: <20:16>

Imm: <15:0>

ASEL

SEXT

R-type: set on less than & set on less than unsigned slt: if (Reg[rs] < Reg[rt]) Reg[rd] 1; else Reg[rd] 0 sltu: if (Reg[rs] < Reg[rt]) Reg[rd] 1; else Reg[rd] 0

Z

BT

WASEL

PC<31:29>:J<25:0>:00

JT

JT

000000 rs rt rd 10101X00000

N V C

ZVN C

Rs: <25:21>

ASEL10

SEXT

BSEL01

SEXT

shamt:<10:6>

PCSEL 0123456

Rd:<15:11>Rt:<20:16>

BT

+x4

WASEL

31

012

LUILUI

WA

PC

+4

InstructionMemory

A

D

RegisterFile

RA1 RA2

RD1 RD2

ALUA B

WA WD

WE

ALUFN

Control Logic

Data Memory

RD

WD R/W

Adr

Wr

WDSEL0 1 2

BSELWDSELALUFNWr

J:<25:0>

PCSEL

WERF

WERF

00

32

PC+4

Rt: <20:16>

Imm: <15:0>

ASEL

SEXT

I-type: Load upper immediate lui: Reg[rt] Immediate << 16

Z

BT

WASEL

PC<31:29>:J<25:0>:00

JT

JT

N V C

ZVN C

001XXXimmediat

e00000 rt

Rs: <25:21>

SEXT

BSEL01

SEXT

PCSEL 0123456

Rd:<15:11>Rt:<20:16>

ASEL20

shamt:<10:6>

“16”

1

WASEL

31

012

BT

+x4

Reset, Interrupts, and ExceptionsReset, Interrupts, and Exceptions Upon reset/reboot:Upon reset/reboot:

Need to set PC to where boot code resides in memoryNeed to set PC to where boot code resides in memory

Interrupts/Exceptions:Interrupts/Exceptions: any event that causes interruption in program flowany event that causes interruption in program flow

FAULTS: e.g., nonexistent opcode, divide-by-zeroFAULTS: e.g., nonexistent opcode, divide-by-zeroTRAPS & system calls: e.g., read-a-characterTRAPS & system calls: e.g., read-a-character I/O events: e.g., key pressedI/O events: e.g., key pressed

How to handle?How to handle? interrupt current running programinterrupt current running program invoke exception handlerinvoke exception handler return to program to continue execution.return to program to continue execution.

ExceptionsExceptions

WA

PC

+4

InstructionMemory

A

D

RegisterFile

RA1 RA2

RD1 RD2

ALUA B

WA WD

WE

ALUFN

Control Logic

Data Memory

RD

WD R/W

Adr

Wr

WDSEL0 1 2

BSELWDSELALUFNWr

J:<25:0>

PCSEL

WERF

WERF

00

32

PC+4

Rt: <20:16>

Imm: <15:0>

ASEL

SEXT

Z

BT

WASEL

PC<31:29>:J<25:0>:00

JT

JT

N V C

ZVN C

Rs: <25:21>

SEXT

BSEL01

SEXT

PCSEL 0123456

LSEL

IRQ

0x800000800x800000400x80000000

RESET

IRQ: Reg[27] PC+4; PC 0x80000080Bad Opcode: Reg[27] PC+4; PC 0x80000040

Reset: PC 0x80000000

ASEL20

shamt:<10:6>

“16”

1

WASEL

Rd:<15:11>Rt:<20:16>

0123

3127

BT

+x4

MIPS: Our Final VersionMIPS: Our Final VersionThis is a complete 32-bit processor.Although designed in “one” class lecture,it executes the majority of theMIPS R2000 instruction set.

Executes one instruction per clock

All that’s left is the controllogic design

WA

PC

+4

InstructionMemory

A

D

RegisterFile

RA1 RA2

RD1 RD2

ALUA B

WA WD

WE

ALUFN

Control Logic

Data Memory

RD

WD R/W

Adr

Wr

WDSEL0 1 2

BSELWDSELALUFNWr

J:<25:0>

PCSEL

WERF

WERF

00

PC+4

Rt: <20:16>

Imm: <15:0>

ASEL

SEXT

Z

BT

WASEL

PC<31:29>:J<25:0>:00

JT

JT

N V C

ZVN C

Rs: <25:21>

ASEL20

SEXT

BSEL01

SEXT

shamt:<10:6>

PCSEL 0123456

“16”

IRQ

0x800000800x800000400x80000000

RESET

1

BT

+x4

WASEL

Rd:<15:11>Rt:<20:16>

0123

3127

MIPS ControlMIPS Control The control unit can be built as a large ROMThe control unit can be built as a large ROM

Instruction

RESET

IRQ

Z N V C

PCSEL

SEXT

WASEL

WDSEL

ALUFN

Sub Bool Shft Math

WR

WERF

ASEL

BSEL

X 1 X X X X X 4 0 0 0 0 00 0 0 0 0 0 0

X 0 1 X X X X 6 0 3 0 0 00 0 0 0 0 0 0

add 0 0 X X X X 0 0 0 1 0 00 0 1 0 1 0 0

sll

andi

lw

sw

beq