COMPUTER ORGANIZATIONAND DESIGN

Third Edition

P. PAL CHAUDHURIProfessor Emeritus

Cellular Automata Research Lab (CARL), Kolkata(A Research Lab established by Alumnus Software, Salt Lake, Kolkata)

Formerly, ProfessorIndian Institute of Technology Kharagpur and

Bengal Engineering and Science University, Shibpur, Howrah

New Delhi-110001

20

COMPUTER ORGANIZATION AND DESIGN, Third EditionP. Pal Chaudhuri

© 2008 by PHI Learning Private Limited, New Delhi. All rights reserved. No part of this book may be reproduced in any form, by mimeograph or any other means, without permission in writing from the publisher.

ISBN-978-81-203-3511-0

The export rights of this book are vested solely with the publisher.

Seventeenth Printing (Third Edition) … … January, 2012

Published by Asoke K. Ghosh, PHI Learning Private Limited, Rimjhim House, 111, Patparganj In-dustrial Estate, Delhi-110092 and Printed by Rajkamal Electric Press, Plot No. 2, Phase IV, HSIDC, Kundli-131028, Sonepat, Haryana.

To

the Memory of My Parentsand to

Jayasree, Mitul and Tutul

for their excellent support throughout the periodof preparing the manuscript of this book

v

Preface .................................................................................................................................... xiiiPreface to the First Edition .................................................................................................... xvAcknowledgements ................................................................................................................. xvii

1 EVOLUTION OF COMPUTER SYSTEMS .......................................................... 1–37

1.0 INTRODUCTION ......................................................................................................... 11.1 THE DISCIPLINE OF COMPUTER SCIENCE AND ENGINEERING .................. 11.2 MANUAL VERSUS MACHINE COMPUTATION ................................................... 21.3 MECHANICAL AND ELECTROMECHANICAL MACHINES ............................... 31.4 EVOLUTION OF ELECTRONIC COMPUTER SYSTEMS .................................... 4

1.4.1 First Generation .............................................................................................. 51.4.2 Second Generation ........................................................................................ 111.4.3 The Third Generation ................................................................................... 151.4.4 Fourth Generation ......................................................................................... 21

1.5 DIFFERENT LAYERS OF A COMPUTER SYSTEMAND THEIR INTERFACES ...................................................................................... 28

1.6 COMPLEXITY OF COMPUTING............................................................................ 30SOURCES ............................................................................................................................... 33PROBLEMS ............................................................................................................................ 33SOLUTION TO SELECTED PROBLEMS .......................................................................... 35

2 COMPUTER SYSTEM DESIGN: HIERARCHICAL LEVELS ........................ 38–137

2.0 INTRODUCTION ....................................................................................................... 382.1 DESIGN OF A COMPUTER SYSTEM ................................................................... 38

2.1.1 Design Layers ............................................................................................... 382.2 RTL STRUCTURE REALIZING BEHAVIOUR

EXPRESSED IN AN ALGORITHM ......................................................................... 432.2.1 RTL Components .......................................................................................... 432.2.2 Features of a HDL ....................................................................................... 44

CONTENTS

vi Contents

2.3 LOGIC CIRCUIT LEVEL STRUCTURE OF RTL COMPONENTS ..................... 472.3.1 Combinational RTL Components ................................................................. 482.3.2 Programmable Logic Devices ...................................................................... 622.3.3 Programmable Logic Array (PLA) .............................................................. 662.3.4 PLA Folding .................................................................................................. 682.3.5 Sequential RTL Components ........................................................................ 712.3.6 Complex Functional/RTL Modules .............................................................. 802.3.7 Buses ............................................................................................................. 84

2.4 INTERFACING DEVICES OF DIFFERENT LOGIC FAMILIES .......................... 872.4.1 CMOS to TTL Interfacing ........................................................................... 882.4.2 TTL to CMOS Interfacing ........................................................................... 89

2.5 GATE ARRAY ............................................................................................................ 902.6 MOS TRANSISTOR SWITCH LEVEL NETWORK .............................................. 92

2.6.1 NMOS Inverter ............................................................................................. 932.6.2 CMOS Inverter ............................................................................................. 962.6.3 CMOS Transmission Gate/Pass Transistor .................................................. 972.6.4 NMOS Network ............................................................................................ 972.6.5 CMOS Networks ......................................................................................... 1022.6.6 Sequential Network ..................................................................................... 1052.6.7 Precharged Logic ........................................................................................ 1102.6.8 Clocked CMOS Network ............................................................................1112.6.9 Register Array ............................................................................................. 113

2.7 COMPUTER-AIDED DESIGN (CAD) TOOLS ..................................................... 114APPENDIX—VHDL ............................................................................................................ 115SOURCES ............................................................................................................................. 118PROBLEMS .......................................................................................................................... 119SOLUTION TO SELECTED PROBLEMS ........................................................................ 121

3 INFORMATION REPRESENTATION ............................................................ 138–183

3.0 INTRODUCTION ..................................................................................................... 1383.1 BUILT-IN DATA TYPES ......................................................................................... 139

3.1.1 Number Systems ......................................................................................... 1393.1.2 Fixed Point Binary Numbers (Integers or Fractions) ............................... 1403.1.3 Floating Point Binary Number Representation ......................................... 1473.1.4 Decimal Data Type ..................................................................................... 1533.1.5 Logical Data Type ...................................................................................... 1573.1.6 Alphanumeric (Character) Data Type ........................................................ 1573.1.7 Other Built-in Data Types .......................................................................... 157

3.2 COMPLEX DATA TYPES AND DATA STRUCTURES ...................................... 1583.2.1 Complex Data Types and Data Structures ................................................ 1583.2.2 Abstract Data Types—Data Object—Built-in Data Type ......................... 161

3.3 ERROR DETECTION AND CORRECTION ......................................................... 1633.3.1 Parity Generation and Detection ................................................................ 1643.3.2 Single Error Detection and Correction ...................................................... 1653.3.3 Single Error Corrector, and Double Error Detection Code ..................... 169

Contents vii

3.4 SEMANTIC GAP ..................................................................................................... 1703.4.1 Performance Degradation ........................................................................... 1713.4.2 Compiler Complexity .................................................................................. 172

3.5 SELF-DEFINING DATA TYPE ............................................................................... 1733.5.1 Tagged Storage ........................................................................................... 1733.5.2 Data Descriptor ........................................................................................... 1743.5.3 Object-Oriented/Capability/Addressing Scheme ........................................ 176

SOURCES ............................................................................................................................. 176PROBLEMS .......................................................................................................................... 177SOLUTION TO SELECTED PROBLEMS ........................................................................ 180

4 CENTRAL PROCESSING UNIT (CPU) ........................................................ 184–325

4.0 INTRODUCTION ..................................................................................................... 1844.1 DATA PATH AND CONTROL PATH TO SUPPORT DIFFERENT

OPERATIONS ON BUILT-IN DATA TYPES ........................................................ 1844.2 MICROOPERATIONS ON DATA PATH AND

THE ASSOCIATED CONTROL SIGNALS ........................................................... 1894.2.1 Memory Transfer ........................................................................................ 1894.2.2 Bus Transfer ................................................................................................ 1894.2.3 Inter-Register Transfer ................................................................................ 1894.2.4 Arithmetic Microoperations ........................................................................ 1914.2.5 Logic Microoperations ............................................................................... 193

4.3 MACHINE LANGUAGE INSTRUCTIONS ........................................................... 1954.3.1 Instruction Repertoires ................................................................................ 1964.3.2 Generic Instruction Types .......................................................................... 1984.3.3 Instruction Length of CPU ......................................................................... 2064.3.4 Operation Code ........................................................................................... 2084.3.5 Addressing Modes ...................................................................................... 212

4.4 EXECUTION OF INSTRUCTIONS ....................................................................... 2184.4.1 Fetch Cycle ................................................................................................. 2184.4.2 Execution Cycle .......................................................................................... 2184.4.3 Execution of Fixed Point Add/Subtract Instructions ................................ 2244.4.4 Execution of Fixed Point Multiplication Instruction ................................ 2354.4.5 Fixed Point Division ................................................................................... 2564.4.6 Floating Point Arithmetic Instruction ........................................................ 2714.4.7 Decimal Arithmetic Instructions ................................................................. 282

4.5 ARITHMETIC AND LOGIC UNIT (ALU) ............................................................ 2854.5.1 Bit-sliced ALU ............................................................................................ 288

4.6 ARITHMETIC PROCESSOR .................................................................................. 2934.6.1 Arithmetic Processor as a Coprocessor ..................................................... 2934.6.2 Arithmetic Processor as an Auxiliary Processor ....................................... 296

4.7 INTERRUPT CYCLE ............................................................................................... 2974.7.1 Interrupt Servicing ...................................................................................... 2984.7.2 Sources of Interrupts .................................................................................. 3004.7.3 Interrupt Identification and Priorities ........................................................ 302

viii Contents

SOURCES ............................................................................................................................. 303PROBLEMS .......................................................................................................................... 303SOLUTION TO SELECTED PROBLEMS ........................................................................ 311

5 CONTROLLER DESIGN ............................................................................... 326–403

5.0 INTRODUCTION ..................................................................................................... 3265.1 CONTROL TRANSFER ........................................................................................... 327

5.1.1 Instruction Control Transfer ....................................................................... 3275.1.2 Program Control Transfer .......................................................................... 329

5.2 FETCH CYCLE ........................................................................................................ 3305.3 INSTRUCTION INTERPRETATION AND EXECUTION ................................... 331

5.3.1 Hardwired Control ...................................................................................... 3325.3.2 Microprogrammed Control ......................................................................... 333

5.4 HARDWIRED CONTROL ...................................................................................... 3345.4.1 Sequence Counter Method ......................................................................... 3385.4.2 Delay Element Method ............................................................................... 3425.4.3 State Table Method ..................................................................................... 346

5.5 MICROPROGRAMMED CONTROL ..................................................................... 3485.5.1 Encoding of Control Signals ...................................................................... 3505.5.2 Next Address Generation ........................................................................... 3565.5.3 Microprogram Sequencer ........................................................................... 3595.5.4 Microinstruction Execution ........................................................................ 3625.5.5 Control Memory Optimization ................................................................... 3645.5.6 Two-Level Control ...................................................................................... 3735.5.7 User Microprogramming ............................................................................ 380

SOURCES ............................................................................................................................. 381PROBLEMS .......................................................................................................................... 382SOLUTION TO SELECTED PROBLEMS ........................................................................ 387

6 MEMORY SUBSYSTEM................................................................................ 404–557

6.0 INTRODUCTION ..................................................................................................... 4046.1 CPU—MEMORY INTERACTION ......................................................................... 404

6.1.1 Impact of Memory Speed on CPU’s Processing Power ........................... 4066.1.2 Processing Power of CPU .......................................................................... 4096.1.3 Main Storage Speed and Capacity versus CPU Power ............................ 4116.1.4 Access Mechanism ..................................................................................... 414

6.2 STORAGE TECHNOLOGY .................................................................................... 4156.2.1 Fundamental Requirements for Storing

and Retrieving Information ........................................................................ 4156.2.2 Ferrite Core Cell ......................................................................................... 4176.2.3 Thin Film Memory Cell ............................................................................. 4186.2.4 Semiconductor Memory Cell ..................................................................... 4206.2.5 Power Consumption versus Cell Area ....................................................... 423

Contents ix

6.3 MEMORY ARRAY ORGANIZATION AND TECHNOLOGY ............................. 4246.3.1 2D Organization .......................................................................................... 4256.3.2 3D Organization .......................................................................................... 4266.3.3 2.5D Memory Organization ....................................................................... 4296.3.4 Main Storage Bipolar Technology ............................................................. 4376.3.5 NMOS Technology ..................................................................................... 4406.3.6 Silicon Gate CMOS Technology ............................................................... 444

6.4 SEMICONDUCTOR MEMORY.............................................................................. 4466.4.1 Static Memory Cell .................................................................................... 4466.4.2 Dynamic Memory Cell ............................................................................... 4526.4.3 A Case Study—Intel 2116 DRAM Chip

of Capacity 16K ¥ 1-bit [Intel, 1977] ....................................................... 4606.4.4 Register File ................................................................................................ 4636.4.5 Read Only Memory (ROM) ....................................................................... 466

6.5 SOLUTION FOR THE SPEED MISMATCHBETWEEN MAIN STORAGE AND CPU ............................................................. 4736.5.1 Memory Hierarchy ...................................................................................... 4736.5.2 Working Principle of Cache Memory........................................................ 4746.5.3 Address Mapping ........................................................................................ 476

6.6 MULTIPLE MODULE MEMORY .......................................................................... 4836.7 ASSOCIATIVE MEMORY ...................................................................................... 485

6.7.1 Working Principle of CAM........................................................................ 4866.7.2 Associative Memory Cell and Array ......................................................... 4866.7.3 Priority Encoding for Multiple Responders .............................................. 4896.7.4 A Few Applications .................................................................................... 491

6.8 VIRTUAL MEMORY ............................................................................................... 4966.8.1 Logical versus Physical Address Space ..................................................... 4986.8.2 Working Principle ....................................................................................... 4986.8.3 Mapping Function ....................................................................................... 5016.8.4 Case Study .................................................................................................. 5096.8.5 Main Storage Allocation ............................................................................. 513

6.9 GAP FILLER MEMORIES ...................................................................................... 5236.9.1 Magnetic Bubble Memory ......................................................................... 5246.9.2 Charge Coupled Device (CCD) ................................................................. 531

SOURCES ............................................................................................................................. 538PROBLEMS .......................................................................................................................... 538SOLUTION TO SELECTED PROBLEMS ........................................................................ 542

7 SECONDARY STORAGE ............................................................................. 558–608

7.0 INTRODUCTION ..................................................................................................... 5587.1 MAGNETIC MEDIUM AND MAGNETIC HEAD ............................................... 5587.2 DIGITAL RECORDING METHODS ...................................................................... 5607.3 MAGNETIC TAPE DRIVE AND CONTROLLER................................................ 5677.4 DISK DRIVE AND CONTROLLER ...................................................................... 568

7.4.1 A Disk Pack ................................................................................................ 568

Computer Organization And Design

Publisher : PHI Learning ISBN : 9788120335110Author : CHAUDHURI, P.PAL

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