Computer Organization and Design Memories and State Machines Montek Singh Mon, April 13, 2011 Lecture 14

Computer Organization and Computer Organization and DesignDesign

Memories and State MachinesMemories and State Machines

Montek SinghMontek Singh

Mon, April 13, 2011Mon, April 13, 2011

Lecture 14Lecture 14

Memory, Latches, & RegistersMemory, Latches, & Registers

1) Structured Logic Arrays2) Memory Arrays3) Transparent Latches4) How to save a few bucks

at toll booths!5) Edge-triggered Registers6) Finite State Machines

Memory as a Lookup TableMemory as a Lookup Table

A multiplexer to implement a lookup table:A multiplexer to implement a lookup table: Remember that, in theory, we can build any 1-output Remember that, in theory, we can build any 1-output

combinational logic block with multiplexerscombinational logic block with multiplexers For an N-input function we need a 2For an N-input function we need a 2NN input multiplexer input multiplexer

BIG Multiplexers?BIG Multiplexers? How about 10-input function? 20-input?How about 10-input function? 20-input?

MUXLogic

A B

Fn(A,B)

AB Fn(A,B)

00 0 01 1 10 1 11 0

A Mux’s GutsA Mux’s Guts

Hmmm, by sharing the decoder part of the logic MUXs could be adapted to make lookup tables with any number of outputs

I 00

I 01

I 10

I 11

AB

AB

AB

AB

Y

Decoder Selector Multiplexerscan be

partitionedinto two sections.

A DECODER thatidentifies the

desired input,and

a SELECTOR that enables that

inputonto the output.

A decodergeneratesall possible

productterms fora set ofinputs

0

1

2

3

A New Combinational DeviceA New Combinational Device

k

D1D2

DN

DECODER:

k SELECT inputs,

N = 2k DATA OUTPUTs.

Selected Dj HIGH; all others LOW.

NOW, we are well on our way to building a general purpose table-lookup device.

We can build a 2-dimensional ARRAY of decoders and selectors as follows ...

Have Imentionedthat HIGH

is a synonym for ‘1’ andLOW means

the sameas ‘0’

Shared Decoding LogicShared Decoding Logic

0 2 3 4 5 6 71

AB

Cin

S

Cout

There’s anextra levelof inversion

that isn’tnecessary

in the logic.However,it reduces

the capacitiveload on the

module drivingthis one.

These are just“DeMorgan”ized

NOR gates

Made from PREWIRED connections , and CONFIGURABLEconnections that can be either connected or not connected

We can build a general purpose “table-lookup” device called a Read-Only Memory (ROM), from which we can implement any truth table and, thus, any combinational device

Decoder

Configurable Selector

This ROM stores 16 bitsin 8 words of 2 bits.

Logic According to ROMsLogic According to ROMs ROMs ignore the structure of combinational ROMs ignore the structure of combinational

functions ...functions ... Size, layout, and design are independent of functionSize, layout, and design are independent of function Any Truth table can be “programmed” by minor Any Truth table can be “programmed” by minor

reconfiguration:reconfiguration:Metal layer (masked ROMs)Metal layer (masked ROMs)Fuses (Field-programmable PROMs)Fuses (Field-programmable PROMs)Charge on floating gates (EPROMs)Charge on floating gates (EPROMs) ... etc.... etc.

Model: LOOK UP value of function in truth Model: LOOK UP value of function in truth table...table... Inputs: “ADDRESS” of a T.T. entryInputs: “ADDRESS” of a T.T. entry ROM SIZE = # TT entries...ROM SIZE = # TT entries...

... for an N-input boolean function, size = __________... for an N-input boolean function, size = __________

2N x #outputs

Analog Storage: Using CapacitorsAnalog Storage: Using Capacitors We’ve chosen to encode information using voltages We’ve chosen to encode information using voltages

and we know from physics that we can “store” a and we know from physics that we can “store” a voltage as “charge” on a capacitorvoltage as “charge” on a capacitor

Pros:Pros:compact!compact!

Cons:Cons: it leaks! refreshit leaks! refreshcomplex interfacecomplex interface reading a bit, destroys reading a bit, destroys

itit– (you have to rewrite (you have to rewrite

the value after each the value after each read)read)

it’s NOT a digital circuitit’s NOT a digital circuit

bit line

N-channel FET serves

as an access switch

VREF

To write: Drive bit line, turn on access fet, force storage cap to new voltageTo read: precharge bit line, turn on access fet, detect (small) change in bit line voltage

wordline

This storage circuit is the basis for commodity DRAMs

Y

S

B

A “Digital” Storage ElementA “Digital” Storage Element It’s also easy to build a settable DIGITAL It’s also easy to build a settable DIGITAL

storage element (called a latch) using a MUX storage element (called a latch) using a MUX and FEEDBACK:and FEEDBACK:

0

1

G

0011

D

----01

QIN

01----

QOUT

0101

Q follows D

Q stable

“state” signalappears as bothinput and output

A

D

G

Q

Here’s a feedback path,so it’s no longer acombinational circuit.

Looking Under the CoversLooking Under the Covers Let’s take a quick look at the equivalent circuit for our Let’s take a quick look at the equivalent circuit for our

MUX when the control is LOW (the feedback path is MUX when the control is LOW (the feedback path is active)active)

DG=0

QQ

G=0

D

0

1

11

Q

This storage circuit is the basis for commodity SRAMs

Advantages: 1) Maintains remembered state for as long as power is applied. 2) State is DIGITALDisadvantage: 1) Requires more transistors

Static D LatchStatic D Latch

G

D Q

D

G

Q stable

Q follows D

Positive latch

Q

“static” means latch will hold data (i.e., value of Q) while G is inactive, however long that may be.

G

D Q

Negative latch

Q

G

D

1

0

What is thedifference?

Latch TimingLatch Timing Circuits with memory must follow some rulesCircuits with memory must follow some rules

Guarantee that inputs to sequential devices are valid Guarantee that inputs to sequential devices are valid and stable during periods when they may influence and stable during periods when they may influence state changesstate changesThis is assured with additional timing specificationsThis is assured with additional timing specifications

G

D

>tPULSE

tPULSE (minimum pulse width): guarantee G is active for long enough for latch to capture data

>tSETUP

tSETUP (setup time): guarantee that D value has propagated through feedback path before latch becomes opaque

>tHOLD

tHOLD (hold time): guarantee latch is opaque and Q is stable before allowing D to change again

Flakey Control SystemsFlakey Control Systems

Here’s a strategy for saving 2 bucks the next time you find yourself at a toll booth!




WARNING:Professional Drivers Used!

DON’T try thisAt home!


Escapement StrategyEscapement Strategy

The Solution: Add two gates and only open one at a time.






The Solution: Add two gates and only open one at a time. (Psst… Don’t tell the toll folks)

























Key Idea: At no time is there an open path through both gates…

G

D Q

G

D Q

Edge-triggered Flip FlopEdge-triggered Flip Flop

Logical “escapement”:Logical “escapement”: Double-gated toll booth built using logic gatesDouble-gated toll booth built using logic gates

Observations:Observations: only one latch “transparent” at any time:only one latch “transparent” at any time:

master closed when slave is open (CLK is high)master closed when slave is open (CLK is high)slave closed when master is open (CLK is low)slave closed when master is open (CLK is low)no combinational path all the way through flip flopno combinational path all the way through flip flop

Q only changes shortly after 0 Q only changes shortly after 0 1 1 transition transition of CLK, so of CLK, so flip flop appears to be “triggered” by rising edge of flip flop appears to be “triggered” by rising edge of CLKCLK

D QD

CLK

Q D

CLK

Qmaster slav

e

Transitions mark instants, not

intervals

Flip Flop WaveformsFlip Flop Waveforms

G

D Q

G

D Q D QD

CLK

Q D

CLK

Qmaster slav

e

D

CLK

Q

master closedslave open

slave closedmaster open

Flip Flop TimingFlip Flop Timing

CLK

D

QD QD

CLK

Q<tPD

tPD: maximum propagation delay, CLK Q

>tSETUP

tSETUP: setup timeguarantee that D has propagated through feedback path before master closes

>tHOLD

tHOLD: hold timeguarantee master is closed and data is stable before allowing D to change

Synchronous SystemsSynchronous Systems

FlipflopCombinational

logicFlipflop

leading

edge

trailing

edge

On the leading edge of the clock, the input of a flipflop is transferred to the output and held.

We must be sure the output of the combinational logic has settled before the next leading clock edge.

Clock

data

Fetching Sequential InstructionsFetching Sequential Instructions

P

C

4

Read

Address Instruction

Instruction

Memory

How about branch?

flipflop

+

Datapath for R-type InstructionsDatapath for R-type Instructions

Read Reg. 1 (rs)5

5

5

32

Read Reg. 2 (rt)

Write Reg. (rd)

Write Data

data 1

data 2

3

ALU Operation

Inst Bits 25-21

Inst Bits 20-16

Inst Bits 15-11

RegWrite

32

32

MUX BlocksMUX Blocks

01234567

Out

2 1 0Select

Inp ut

8

3

Select

In Out

The select signal determines which of the inputs is connectedto the output

Inside there is a 32 way MUX per Inside there is a 32 way MUX per bitbit

Register 0

Register 1

Register 2

Register 3

Register 4

Register ...

Register 30

Register 31

32 to1 MUX

Read Reg 1

Data 1

For EACH bit in the 32 bit register

LOT’S OF CONNECTIONS!

And this is just one port! Remember, there’s data1 and data2 coming out of the register file!

5

Our Register File has 3 portsOur Register File has 3 ports

Read Reg. 15

5

5

32

Read Reg. 2

Write Reg.

Write Data

data 1

data 2

Inst Bits 25-21

Inst Bits 20-16

Inst Bits 15-11

RegWrite

32

32

2 Read Ports

1 Write Port

REALLY LOTS OF CONNECTIONS!

This is one reason we have only a small number of registers

What’s another reason?

Finite State MachinesFinite State Machines What is a State Machine?What is a State Machine?

Remember automata?Remember automata?

It is defined by the following:It is defined by the following:Set of STATESSet of STATESSet of INPUTSSet of INPUTSSet of OUTPUTSSet of OUTPUTSA mapping from (STATES, INPUTS) to …A mapping from (STATES, INPUTS) to …

… … the next STATE and an OUTPUTthe next STATE and an OUTPUT

STATE represents memory!STATE represents memory!

Implementing an FSMImplementing an FSM

State(flipflops)

Function

(comb. logic)

Inputs Outputs

Clock

SummarySummary Regular Arrays can be used to implement Regular Arrays can be used to implement

arbitrary logic functions arbitrary logic functions MemoriesMemories

ROMs are HARDWIRED memoriesROMs are HARDWIRED memories RAMs include storage elements that are read-writeRAMs include storage elements that are read-write

dynamic memory: compact, only reliable short-termdynamic memory: compact, only reliable short-termstatic memory: controlled use of positive feedbackstatic memory: controlled use of positive feedback

For static storage:For static storage: Level-sensitive D-latches; edge-triggered flipflopsLevel-sensitive D-latches; edge-triggered flipflops Timing issues: setup and hold timesTiming issues: setup and hold times

Finite State Machines (FSM)Finite State Machines (FSM) With just a register and some logic, we can implement With just a register and some logic, we can implement

a state machinea state machine

Documents

Computer Organization and Design Memories and State Machines Montek Singh Mon, April 13, 2011 Lecture 14