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Computer Organization and Design Transistors & Logic - II Montek Singh Oct {21,28}, 2015 Lecture 10

Computer Organization and Design Transistors & Logic - II Montek Singh Oct {21,28}, 2015 Lecture 10

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Computer Organization and Design

Transistors & Logic - II

Montek Singh

Oct {21,28}, 2015

Lecture 10

Today’s Topics Basic gates Boolean algebra Synthesis using standard gates

Truth tablesUniversal gates: NAND and NORGates with more than 2 inputsSum-of-ProductsDeMorgan’s Law

2

Single-Input Logic Gates

NOT

Y = A

A Y0 11 0

A Y

BUF

Y = A

A Y0 01 1

A Y

3

Two-Input Logic Gates

AND

Y = AB

A B Y0 0 00 1 01 0 01 1 1

AB

Y

OR

Y = A + B

A B Y0 0 00 1 11 0 11 1 1

AB

Y

4

More Two-Input Logic Gates

XNOR

Y = A + B

A B Y0 00 11 01 1

AB

Y

XOR NAND NOR

Y = A + B Y = AB Y = A + B

A B Y0 0 00 1 11 0 11 1 0

A B Y0 0 10 1 11 0 11 1 0

A B Y0 0 10 1 01 0 01 1 0

AB

Y AB

Y AB

Y

1001

5

XNOR

Y = A + B

A B Y0 00 11 01 1

AB

Y

XOR NAND NOR

Y = A + B Y = AB Y = A + B

A B Y0 0 00 1 11 0 11 1 0

A B Y0 0 10 1 11 0 11 1 0

A B Y0 0 10 1 01 0 01 1 0

AB

Y AB

Y AB

Y

1001

Multiple-Input Logic Gates

NOR3

Y = A+B+C

B C Y0 00 11 01 1

AB YC

A0000

0 00 11 01 1

1111

10000000

6

Multiple-Input Logic Gates

NOR3

Y = A+B+C

B C Y0 00 11 01 1

AB YC

A0000

0 00 11 01 1

1111

10000000

7

Boolean Algebra

Algebra of 1s and 0s

9

Table of Identities

10

Duals Left and right columns are duals Replace ANDs and ORs, 0s and 1s

11

Single Variable Identities

12

Commutativity Operation is independent of order of variables

13

Associativity Independent of order in which we group

So can also be written asand

ZYX XYZ

14

Distributivity

Substitution Can substitute arbitrarily large algebraic

expressions for the variablesDistribute an operation over the entire expressionExample:

X + YZ = (X+Y)(X+Z)

Substitute ABC for X

ABC + YZ = (ABC + Y)(ABC + Z)

15

16

DeMorgan’s Theorem Used a lot

NOR invert, then AND

NAND invert, then OR

17

Truth Tables for DeMorgan’s

18

Algebraic/Boolean Manipulation Apply algebraic and Boolean identities to

simplify expressionExample: XZZYX YZ X F

19

Simplification Example

XZZYX YZ X F

XZZ Z YX F )(

XZYX F 1

XZYX F

Apply

Apply

Apply

20

Fewer Gates

XZYX F

From Truth Table to Gate-Level Circuit

Now We’re Ready to Design Stuff! We need to start somewhere

usually it’s the functional specification

A

B YIf C is 1 thencopy B to Y,

otherwise copyA to YC

First step is to translate a verbal description into a tabular form. Any combinational function can be represented as a “truth table.”

A truth table lists the output(s) for each combination of inputs.

C B A Y

0 0 0 00 0 1 10 1 0 00 1 1 11 0 0 01 0 1 01 1 0 11 1 1 1

Truth Table

We Can Make Most Gates Out of Others Example 1: B > A

Output Y is 1 if and only if B is 1 AND A is 0

Y = B AND (NOT(A))

AB Y

00 001 110 011 0

B>A

AB

y

We Can Make Most Gates Out of Others Example 2: A XOR B

Output Y is 1 if and only if …B is 1 AND A is 0 --OR—B is 0 AND A is 1

Y = B AND (NOT(A)) OR A AND (NOT(B))

AB Y

00 0 01 1 10 1 11 0

XOR

AB

Y

AB

Y

Symbol for XOR

How many gates do we really need?

One Will Do! NANDs and NORs are universal

one can make any circuit out of just NANDs, or out of just NORs!

Ah! But what if we want more than 2-inputs?

=

=

=

=

=

=

Gate Trees: Multi-input gates

Suppose we have some 2-input XOR gates:(same idea holds for AND and OR gates)

And we want an N-input XOR:

XOR(A1, A2, A3 … AN) =XOR … (XOR(XOR(A1, A2), A3) … AN)

A1

A3 A4 AN

A2

A

BC

A0011

B0101

C0110

tpd = 1(latency)

tpd (latency)= O( ___ ) in the WORST CASE.

output = 1 iff number of 1s in input is ODD (“ODD PARITY”)

Can we compute N-input XOR faster?

N

Gate Trees

A1

A2

A4

A3

AN

N-input TREE has O( ______ ) levels...

InputOutput propagation takes O( _______ ) gate delays.

log N

log N

21222

log2N

Design Approach: Sum-of-ProductsThree steps:

1. Write functional spec as a truth table

2. Write down a Boolean expression for every ‘1’ in the output

3. Wire up the gates!

This approach will always give us logic expressions in a particular form:

SUM-OF-PRODUCTS (“SOP”) “SUM” actually means OR “PRODUCT” actually means AND

C B A Y

0 0 0 00 0 1 10 1 0 00 1 1 11 0 0 01 0 1 01 1 0 11 1 1 1

Truth Table

CBAACBBACABCY

Straightforward Synthesis We can implement SUM-OF-PRODUCTS…

…with just three levels of logic: INVERTERS/AND/OR

ABC

ABC

ABC

ABC

Y

CBAACBBACABCY

Notations Symbols and Boolean operators:

DeMorgan’s Laws Change ANDs into ORs and vice-versa

AB=A+B

Useful Gate Structures NAND-NAND

NOR-NOR

C

A

B

Y

C

A

BY

C

A

B

Y

zyxxyz

C

A

BY

yxyx

C

A

B

Y

C

A

BY

AB=A+B “Pushing Bubbles”

DeMorgan’s Laws

An Interesting 3-Input Gate: Multiplexer Based on C, select the A or B input to be

copied to the output Y.

C B A Y

0 0 0 00 0 1 10 1 0 00 1 1 11 0 0 01 0 1 01 1 0 11 1 1 1

Truth Table

A

BY

C

If C is 1 thencopy B to Y,

otherwise copyA to Y

2-input Multiplexer

A

B

C

0

1

Gatesymbol

Multiplexer (MUX) Shortcuts

0101S

0101S

0101S

I0I1

I2I3

Y

S0 S1

A 4-input Mux(implemented as a

tree)

0101S

0101S

A2

B2

A3

B3

Y0

S

0101S

0101S

A0

B0

A1

B1

Y1

Y2

Y3

A 4-bit wide 2-input Mux

ABCDS

0123

YA0-3

B0-3

S

Y0-3

Next Class Arithmetic circuits