Computer Organization Lecture 12

Fall 2006

Lillevik 333f06-l12 1University of Portland School of Engineering

EE 333

Computer OrganizationLecture 12

Branch controlJump control

Controller FSM

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Datapath and controller

Controller Input

ck1

ck2

ck3

ck4

ck5

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Datapath timing overview

• Clocks vary from 3 – 5

• Clocks 1 and 2 the same for all instructions• R-type: 2 more

• Memory reference– Store: 2 more– Load: 3 more

• Branch, Jump: 1 more

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R-type instruction timing

Inst

ruct

ion

Fet

ch

Dec

ode,

Reg

Rea

d

Fun

ctio

n

Reg

iste

r W

rite

Clock

Inst

ruct

ion

Fet

ch

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Complete R-type

001000

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Store instruction timing

Inst

ruct

ion

Fet

ch

Dec

ode,

Reg

Rea

d

Add

ress

Cal

cula

tion

Mem

ory

Wri

te

Clock

Inst

ruct

ion

Fet

ch

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Complete store word

000000

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Load instruction timing

Inst

ruct

ion

Fet

ch

Dec

ode,

Reg

Rea

d

Add

ress

Cal

cula

tion

Mem

ory

Rea

d

Reg

Wri

te

Clock

Inst

ruct

ion

Fet

ch

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Complete load word

000000

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Branch (beq) execution

• Operation– If (A = = B), PC = ALUout– ALUout = branch address from clock 2

• Functional units– ALU must sub, A-B– ALUout contains optimistic branch address– Zero flag controls write to PC

Clock 3

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Control for branch (beq)?

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Complete beq

000001

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Beq Instruction Timing

Inst

ruct

ion

Fet

ch

Dec

ode,

Reg

Rea

d

AL

U S

ubtr

act

Clock

Inst

ruct

ion

Fet

ch

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Jump execution

• Operation– PC = PC[31-28] || (IR[25-0]<<2)– PC always written

• Functional units– Instruction register– Upper 4 bits of PC

Clock 3

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Control for jump?

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Jump instruction timing

Inst

ruct

ion

Fet

ch

Dec

ode,

Reg

Rea

d

Wri

te P

C

Clock

Inst

ruct

ion

Fet

ch

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Complete jump

0000

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Controller and datapath

InputsIR(31:25)

Outputs

Outputs

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FSM architecture

Present

State

NS

Decoder

Output

Decoder

Inputs Outputs

Combo logic

ROM

MUX

Combo logic

ROM

MUX

Decoder

Flip Flops

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Ten one-bit outputs

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Three two-bit outputs

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State diagram overview

All instructions require IF, ID (2 clk’s)

2 Clk

1-3 Clk

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State diagram notation

Previous States Next States

Current State

Signal1

Signal3 = 00

Signals not listed are “don’t cares”

Signal2 = 0

condition

condition

condition

condition

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Full FSM state diagram

Inputs:Op

Outputs: 13 signals

States: 10

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Add state diagram

Inputs:Op

Outputs: 13 signals

States: 10

S0 S1 S6 S7 S0

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Add instruction timing

Inst

ruct

ion

Fet

ch

Dec

ode,

Reg

Rea

d

Add

Ope

rand

s

Reg

iste

r W

rite

Clock

Inst

ruct

ion

Fet

ch

S0 S1 S6 S7

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Find the state transitions?

Inst Clk 1 Clk 2 Clk 3 Clk 4 Clk 5

add $1, $2, $3 0 1

sw $4, 64($5) 0 1

beq $1, $4, label 0 1

sub $1, $5, $2 0 1

lw $8, 256($12) 0 1

beq $7, $2, label 0 1

j jumpAdr 0 1

or $7, $4, $5 0 1

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Control for branch (beq)? Clock 3

Optimistic branch address

01

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Control for jump? Clock 3

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Find the state transitions?

Inst Clk 1 Clk 2 Clk 3 Clk 4 Clk 5

add $1, $2, $3 S0 S1 S6 S7

sw $4, 64($5) S0 S1 S2 S5

beq $1, $4, label S0 S1 S8

sub $1, $5, $2 S0 S1 S6 S7

lw $8, 256($12) S0 S1 S2 S3 S4

beq $7, $2, label S0 S1 S8

j jumpAdr S0 S1 S9

or $7, $4, $5 S0 S1 S6 S7

Documents

Computer Organization Lecture 12