Computer Organization

Rabie A. Ramadan

Lecture 3

2

Instruction Set Architecture (ISA)

MIPS Processor

3

MIPS Processor CPU:

• 64-bit program counter – PC;

• two 64-bit registers – Hi & Lo, hold results of integer multiply and divide

• 32 64-bit general purpose registers – GPRs (s0 – s31);

Floating Point Processor – FPU (Coprocessor 1 – CP1):• 32 64-bit floating point registers – FPRs (f0 – f31);

• five control registers;

• Coprocessor 0 – CP0 is incorporated on the MIPS CPU chip and it provides functions necessary to support operating system: exception handling, memory management scheduling and control of critical resources.

MIPS Processor Coprocessor 0 (CP0) registers (partial list):

• Status register (CP0reg12) – processor status and control;

• Cause register (CP0reg13) – cause of the most recent exception;

• EPC register (CP0reg14) – program counter at the last exception;

• BadVAddr register (CP0reg08) – the address for the most recent address related exception;

• Count register (CP0reg09) – acts as a timer, incrementing at a constant rate that is a function of the pipeline clock;

• Compare register (CP0reg11) – used in conjunction with Count register;

• Performance Counter register (CP0reg25);

Registers vs. Memory Arithmetic instruction operands must be registers,

— only 32 registers provided Compiler associates variables with registers

CPU Memory

IO

register file

Main Memory Model (Cont.)

7

Main Memory Model

8

Millions of cells

Word

• An entity that can be written to or read from the memory.

• Each word requires an address.

Word Addressing

9

Given M words , how many bits l are required to address them?

Example: to address 64 MB, we need

Ml 2log

bitsl 26)2*64(log 202

Memory Organization Viewed as a large, single-dimension array, with an address A memory address is an index into the array "Byte addressing" means that successive addresses are one byte apart

0

1

2

3

4

5

6

...

8 bits of data

8 bits of data

8 bits of data

8 bits of data

8 bits of data

8 bits of data

8 bits of data

MIPS Memory Organization Bytes are nice, but most data items use larger

"words" For MIPS, a word is 32 bits or 4 bytes.

...

0

4

8

12

32 bits of data

32 bits of data

32 bits of data

32 bits of data

Registers hold 32 bits of data

Main Types of Instructions Arithmetic

• Integer

• Floating Point

Memory access instructions

• Load & Store

Control flow

• Jump

• Conditional Branch

• Call & Return

MIPS arithmetic Most instructions have 3 operands Operand order is fixed (destination first)

Example 1: Java code: A = B + CMIPS code: add $s0, $s1, $s2

Example 2: Java code: A = B + C + D;

E = F - A;MIPS code: add $t0, $s1, $s2

add $s0, $t0, $s3sub $s4, $s5, $s0

Instructions: load and store

Example:

Java code: A[8] = h + A[8];

MIPS code: lw $t0, 32($s3)add $t0, $s2, $t0sw $t0, 32($s3)

$s3 is the base register + 32 offset A[8] Remember arithmetic operands are registers, not memory!

0

4

8

12

32 bits of data

32 bits of data

32 bits of data

32 bits of data

Instructions Format Instructions, like registers and words of data, are also 32 bits long

• Example: add $t0, $s1, $s2

• Registers have numbers: $t0=9, $s1=17, $s2=18

Instruction Format:

6 bits 5 bits 5 bits 5 bits 6 bits5 bits

000000 10001 10010 01000 00000 100000

op rs rt rd shamt funct

Can you guess what the field names stand for?

Instructions Format

R format -- arithmetic and logic instructions op -- operation of the instructions rs -- first source register number rt -- second source register rd -- destination register shamt -- shift amount (This field is set to 0 in all but the shift instructions.) funct -- additional specification of operation (add , sub,..)

6 bits 5 bits 5 bits 5 bits 6 bits5 bits

000000 10001 10010 01000 00000 100000

op rs rt rd shamt funct

Why two fields (op

and funct)?

Instructions: Control FlowDecision making instructions

alter the control flow,i.e., change the "next" instruction to be executed

MIPS conditional branch instructions:

bne $t0, $t1, Label beq $t0, $t1, Label

Example: if (i==j) h = i + j;

bne $s0, $s1, Labeladd $s3, $s0, $s1

Label: ....

Instructions Format Consider the load-word and store-word instructions, Introduce a new type of instruction format

• I-type for register – Load and control

• Example: lw $t0, 32($s2)

• op -- operation code

• rs -- register source

• rt -- used as destination register in this format

• address -- 16-bit constant for addressing instructions in this class use at most two registers this is how to get constants into the registers

Only one field for the operation (op).

Therefore, All formats are consistent.

Example

Mapping is straightforward addi uses the I format (immediate) Generally one to one correspondence Straightforward translation

Instructions: Unconditional Branch

MIPS unconditional branch instructions:j label

Example:

if (i!=j) beq $s4, $s5, Lab1 h=i+j; add $s3, $s4, $s5else j Lab2 h=i-j; Lab1: sub $s3, $s4, $s5

Lab2: ... Is there any Operands in the Jump instructions ?

• J Instructions Format:

MIPS Instruction Formats Summary

Instructions, like registers and words of data, are also 32 bits long R format -- arithmetic and logic instructions I format -- transfer and branch instructions J format -- jump instructions

OP

OP

OP

rs rt rd sa funct

rs rt immediate

target

6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

R format

I format

J format

MIPS assembly language

Category Instruction Example Meaning Commentsadd add $s1, $s2, $s3 $s1 = $s2 + $s3 Three operands; data in registers

Arithmetic subtract sub $s1, $s2, $s3 $s1 = $s2 - $s3 Three operands; data in registers

add immediate addi $s1, $s2, 100 $s1 = $s2 + 100 Used to add constants

load word lw $s1, 100($s2) $s1 = Memory[$s2 + 100] Word from memory to register

store word sw $s1, 100($s2) Memory[$s2 + 100] = $s1 Word from register to memory

Data transfer load byte lb $s1, 100($s2) $s1 = Memory[$s2 + 100] Byte from memory to register

store byte sb $s1, 100($s2) Memory[$s2 + 100] = $s1 Byte from register to memory

load upper immediate lui $s1, 100 $s1 = 100 * 216 Loads constant in upper 16 bits

branch on equal beq $s1, $s2, 25 if ($s1 == $s2) go to PC + 4 + 100

Equal test; PC-relative branch

Conditional

branch on not equal bne $s1, $s2, 25 if ($s1 != $s2) go to PC + 4 + 100

Not equal test; PC-relative

branch set on less than slt $s1, $s2, $s3 if ($s2 < $s3) $s1 = 1; else $s1 = 0

Compare less than; for beq, bne

set less than immediate

slti $s1, $s2, 100 if ($s2 < 100) $s1 = 1; else $s1 = 0

Compare less than constant

jump j 2500 go to 10000 Jump to target address

Uncondi- jump register jr $ra go to $ra For switch, procedure return

tional jump jump and link jal 2500 $ra = PC + 4; go to 10000 For procedure call

23

Byte Halfword Word

Registers

Memory

Memory

Word

Memory

Word

Register

Register

1. Immediate addressing

2. Register addressing

3. Base addressing

4. PC-relative addressing

5. Pseudodirect addressing

op rs rt

op rs rt

op rs rt

op

op

rs rt

Address

Address

Address

rd . . . funct

Immediate

PC

PC

+

+

MIPS addressing modes

The operand is constant within the instruction itself

Operand is a register

The operand is at the memory location whose address is the sum of a register and a constant in the instruction

The address is the sum of the Pc and constant in the instructionJump Address is 26 bits (inst) concatenated with upper PC bits