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– 1 –! CS:APP!
Alvin R. Lebeck!
CS:APP!
Computer Science 104:!Y86 & Single Cycle Processor Design!
Slides based on those from Randy Bryant
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Administrative!
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Instruction Set Architecture!
ISA!
Compiler! OS!
CPU!Design!
Circuit!Design!
Chip!Layout!
Application!Program!
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Y86: A simpler Instruction Set!
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%eax %ecx %edx %ebx
%esi %edi %esp %ebp
Y86 Processor State!
Program Registers! Same 8 as with IA32. Each 32 bits!
Condition Codes! Single-bit flags set by arithmetic or logical instructions!
» OF: Overflow !ZF: Zero !SF:Negative! Program Counter!
Indicates address of instruction! Memory!
Byte-addressable storage array! Words stored in little-endian byte order!
Program registers! Condition
codes!
PC!
Memory!
OF ZF SF
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Y86 Instructions!
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Encoding Registers!
%eax %ecx %edx %ebx
%esi %edi %esp %ebp
0 1 2 3
6 7 4 5
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Instruction Example!
addl rA, rB! 6 0 rA!rB!
Encoded Representation!
Generic Form!
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Arithmetic and Logical Operations! Refer to generically as
“OPl”! Encodings differ only by
“function code”! Low-order 4 bytes in first
instruction word! Set condition codes as
side effect!
addl rA, rB! 6 0 rA!rB!
subl rA, rB! 6 1 rA!rB!
andl rA, rB! 6 2 rA!rB!
xorl rA, rB! 6 3 rA!rB!
Add!
Subtract (rA from rB)!
And!
Exclusive-Or!
Instruction Code! Function Code!
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Move Operations!
Like the IA32 movl instruction! Simpler format for memory addresses! Give different names to keep them distinct!
rrmovl rA, rB! 2 0 rA!rB! Register --> Register!
Immediate --> Register!irmovl V, rB! 3 0 8 rB! V!
Register --> Memory!rmmovl rA, D(rB)! 4 0 rA!rB! D!
Memory --> Register!mrmovl D(rB), rA 5 0 rA!rB! D!
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Move Instruction Examples!
irmovl $0xabcd, %edx !movl $0xabcd, %edx! 30 82 cd ab 00 00!IA32! Y86! Encoding!
rrmovl %esp, %ebx !movl %esp, %ebx! 20 43!
mrmovl -12(%ebp),%ecx movl -12(%ebp),%ecx! 50 15 f4 ff ff ff!
rmmovl %esi,0x41c(%esp) movl %esi,0x41c(%esp)!
!—!movl $0xabcd, (%eax)!
!—!movl %eax, 12(%eax,%edx)!
!—!movl (%ebp,%eax,4),%ecx!
40 64 1c 04 00 00!
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Jump Instructions! Refer to generically as
“jXX”! Encodings differ only by
“function code”! Based on values of
condition codes! Same as IA32 counterparts! Encode full destination
address! Unlike PC-relative
addressing seen in IA32!
jmp Dest! 7 0
Jump Unconditionally!
Dest!
jle Dest! 7 1
Jump When Less or Equal!
Dest!
jl Dest! 7 2
Jump When Less!
Dest!
je Dest! 7 3
Jump When Equal!
Dest!
jne Dest! 7 4
Jump When Not Equal!
Dest!
jge Dest! 7 5
Jump When Greater or Equal!
Dest!
jg Dest! 7 6
Jump When Greater!
Dest!
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Y86 Program Stack! Region of memory holding
program data! Used in Y86 (and IA32) for
supporting procedure calls! Stack top indicated by %esp
Address of top stack element! Stack grows toward lower
addresses! Top element is at highest
address in the stack! When pushing, must first
decrement stack pointer! When popping, increment stack
pointer!%esp
•
•
•
Increasing!Addresses!
Stack “Top”!
Stack “Bottom”!
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Stack Operations!
Decrement %esp by 4! Store word from rA to memory at %esp Like IA32!
Read word from memory at %esp Save in rA! Increment %esp by 4! Like IA32!
pushl rA! a 0 rA! 8
popl rA! b 0 rA! 8
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Subroutine Call and Return!
Push address of next instruction onto stack! Start executing instructions at Dest! Like IA32!
Pop value from stack! Use as address for next instruction! Like IA32!
call Dest! 8 0 Dest!
ret! 9 0
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Miscellaneous Instructions!
Donʼt do anything!
Stop executing instructions! IA32 has comparable instruction, but canʼt execute it in
user mode!
nop! 0 0
halt! 1 0
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Y86 Instruction Set!Byte! 0 1 2 3 4 5
pushl rA! A 0 rA! 8
jXX Dest! 7 fn! Dest!
popl rA! B 0 rA! 8
call Dest! 8 0 Dest!
rrmovl rA, rB! 2 0 rA! rB!
irmovl V, rB! 3 0 8 rB! V!
rmmovl rA, D(rB) 4 0 rA! rB! D!
mrmovl D(rB), rA! 5 0 rA! rB! D!
OPl rA, rB! 6 fn! rA! rB!
ret 9 0
nop 0 0
halt 1 0
addl 6 0
subl 6 1
andl 6 2
xorl 6 3
jmp 7 0
jle 7 1
jl 7 2
je 7 3
jne 7 4
jge 7 5
jg 7 6
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Building Blocks!
Register!file!
A!
B!
W! dstW!
srcA!
valA!
srcB!
valB!
valW!
Clock!
A!L!U!
fun!
A!
B!
MUX!0!
1!
=!
Clock!
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SEQ Hardware Structure (Abstract)!
Instruction!memory!Instruction!memory! PC!
increment!PC!increment!
CC!CC!ALU!ALU!
Data!memory!Data!memory!
Fetch!
Decode!
Execute!
Memory!
Write back!
icode!, !ifun!rA! , !rB!
valC!
Register!file!Register!file!
A! B!M!E!
Register!file!Register!file!
A! B!M!E!
PC!
valP!
srcA!, !srcB!dstA!, !dstB!
valA!, !valB!
aluA!, !aluB!Bch!
valE!
Addr!, Data!
valM!
PC!valE!, !valM!
newPC!
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SEQ Stages!
Instruction!memory!Instruction!memory! PC!
increment!PC!increment!
CC!CC!ALU!ALU!
Data!memory!Data!memory!
Fetch!
Decode!
Execute!
Memory!
Write back!
icode!, !ifun!rA! , !rB!
valC!
Register!file!Register!file!
A! B!M!E!
Register!file!Register!file!
A! B!M!E!
PC!
valP!
srcA!, !srcB!dstA!, !dstB!
valA!, !valB!
aluA!, !aluB!Bch!
valE!
Addr!, Data!
valM!
PC!valE!, !valM!
newPC!
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Instruction Decoding!
5 0 rA! rB! D!
icode!ifun!
rA!rB!
valC!
Optional! Optional!
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Executing Arith./Logical Operation!OPl rA, rB! 6 fn! rA!rB!
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Stage Computation: Arith/Log. Ops!
Formulate instruction execution as sequence of simple steps!
Use same general form for all instructions; often called Register Transfer Language (RTL)!
OPl rA, rB!icode:ifun ← M1[PC]!rA:rB ← M1[PC+1]!
valP ← PC+2!
Fetch!
Read instruction byte!Read register byte!
Compute next PC!valA ← R[rA]!valB ← R[rB]!
Decode!Read operand A!Read operand B!
valE ← valB OP valA!Set CC!
Execute!Perform ALU operation!Set condition code register!
Memory!R[rB] ← valE!Write!
back!Write back result!
PC ← valP!PC update! Update PC!
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Executing rmmovl rmmovl rA, D(rB)! 4 0 rA!rB! D!
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Stage Computation: rmmovl
Use ALU for address computation!
rmmovl rA, D(rB)!icode:ifun ← M1[PC]!rA:rB ← M1[PC+1]!valC ← M4[PC+2]!valP ← PC+6!
Fetch!
Read instruction byte!Read register byte!Read displacement D!Compute next PC!
valA ← R[rA]!valB ← R[rB]!
Decode!Read operand A!Read operand B!
valE ← valB + valC!Execute!
Compute effective address!
M4[valE] ← valA!Memory! Write value to memory !Write!back!
PC ← valP!PC update! Update PC!
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Executing popl popl rA! b 0 rA! 8
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Stage Computation: popl
Use ALU to increment stack pointer! Must update two registers!
Popped value! New stack pointer!
popl rA!icode:ifun ← M1[PC]!rA:rB ← M1[PC+1]!
valP ← PC+2!
Fetch!
Read instruction byte!Read register byte!
Compute next PC!valA ← R[%esp]!valB ← R [%esp]!
Decode!Read stack pointer!Read stack pointer!
valE ← valB + 4!Execute!
Increment stack pointer!
valM ← M4[valA]!Memory! Read from stack !R[%esp] ← valE!R[rA] ← valM!
Write!back!
Update stack pointer!Write back result!
PC ← valP!PC update! Update PC!
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Executing Jumps!jXX Dest! 7 fn! Dest!
XX XX fall thru:!
XX XX target:!
Not taken!
Taken!
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Stage Computation: Jumps!
Compute both addresses! Choose based on setting of condition codes and branch
condition!
jXX Dest!icode:ifun ← M1[PC]!
valC ← M4[PC+1]!valP ← PC+5!
Fetch!
Read instruction byte!
Read destination address!Fall through address!
Decode!
Bch ← Cond(CC,ifun)!Execute!
Take branch?!Memory!Write!back!
PC ← Bch ? valC : valP!PC update! Update PC!
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Executing call call Dest! 8 0 Dest!
XX XX return:!
XX XX target:!
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Stage Computation: call
Use ALU to decrement stack pointer! Store incremented PC!
call Dest!icode:ifun ← M1[PC]!
valC ← M4[PC+1]!valP ← PC+5!
Fetch!
Read instruction byte!
Read destination address !Compute return point!
valB ← R[%esp]!Decode!
Read stack pointer!valE ← valB + –4!
Execute!Decrement stack pointer!
M4[valE] ← valP !Memory! Write return value on stack !R[%esp] ← valE!Write!
back!Update stack pointer!
PC ← valC!PC update! Set PC to destination!
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Executing ret ret! 9 0
XX XX return:!
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Stage Computation: ret
Use ALU to increment stack pointer! Read return address from memory!
ret
icode:ifun ← M1[PC]!
Fetch!
Read instruction byte!
valA ← R[%esp]!valB ← R[%esp]!
Decode!Read operand stack pointer!Read operand stack pointer!
valE ← valB + 4!Execute!
Increment stack pointer!
valM ← M4[valA] !Memory! Read return address!R[%esp] ← valE!Write!
back!Update stack pointer!
PC ← valM!PC update! Set PC to return address!
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Computation Steps!
All instructions follow same general pattern! Differ in what gets computed on each step!
OPl rA, rB!icode:ifun ← M1[PC]!rA:rB ← M1[PC+1]!
valP ← PC+2!
Fetch!
Read instruction byte!Read register byte![Read constant word]!Compute next PC!
valA ← R[rA]!valB ← R[rB]!
Decode!Read operand A!Read operand B!
valE ← valB OP valA!Set CC!
Execute!Perform ALU operation!Set condition code register!
Memory! [Memory read/write] !R[rB] ← valE!Write!
back!Write back ALU result![Write back memory result] !
PC ← valP!PC update! Update PC!
icode,ifun!rA,rB!valC!valP!valA, srcA!valB, srcB!valE!Cond code!valM!dstE!dstM!PC!
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Computation Steps!
All instructions follow same general pattern! Differ in what gets computed on each step!
call Dest!
Fetch!
Decode!
Execute!
Memory!Write!back!PC update!
icode,ifun!rA,rB!valC!valP!valA, srcA!valB, srcB!valE!Cond code!valM!dstE!dstM!PC!
icode:ifun ← M1[PC]!
valC ← M4[PC+1]!valP ← PC+5!
valB ← R[%esp]!valE ← valB + –4!
M4[valE] ← valP !R[%esp] ← valE!
PC ← valC!
Read instruction byte![Read register byte]!Read constant word!Compute next PC![Read operand A]!Read operand B!Perform ALU operation![Set condition code reg.]![Memory read/write] ![Write back ALU result]!Write back memory result!Update PC!
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Computed Values!
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Summary!
