Computing Devices Switching

15-398 lecture 5

© 2004 Seth Copen Goldstein 1

lecture 8 15-398 © 2004 Seth Copen Goldstein 1

NanotechnologyAnd

Computer Architecture

Seth Copen [email protected]

CMU

15-398 Introduction to Nanotechnology


Today

Device requirementsManufacturing requirementsFabricationMicro-nano scale matchingReconfigurable computingArchitectures


Computing Devices

CompletenessLogic RestorationFan-outInput/Output IsolationPower GainInexpensiveLow power (zero static power)Dense packingReliable


Switching

Devices must have some non-linear characteristic that supports logical computation

VoutVin

Vdd

Vout

VihVil

Voh

Vol

Vin

15-398 lecture 5



Completeness

Must be able to generate all functions

01

10

aa

a x

ax

NOT AND OR NAND XOR

010

001

1

0

b

11

00

a ba

110

101

1

0

b

11

00

a ba

110

101

1

0

b

01

10

(a b)

a

ab a b

ab

a b

110

101

1

0

b

01

00

a ba

ab


Is AND sufficient?

AND

010

001

1

0

b

11

00

a ba


Logic Restoration

Why?

VoutVin

Vdd

Vout

VihVil

Voh

Vol

Vin


Fan-out

The ability to drive more than one output.Why?

NOT

halfaddersum

carry

a

b

a

b

sum

15-398 lecture 5



I/O Isolation

A change in the output does not affect the value of the input.Why?


Power gain

Is it strictly necessary?

SirM modelSwitchingIsolationRestorationMemory


Necessary Device Abstraction

Transistor provides it allSwitchFan-outI/O isolationSignal restoration

Replace single abstraction with multiple abstractions: SIRMEnables an incremental path to direct nano-circuits

Necessary for logic

Necessary for large designs


SIRM

SIRM decomposes the abstraction into its fundumental components.

SwitchI solationRestorationMemory

SIRM already in useAllows circuit designers to explicitly manage the different components of a scalable circuit technology

Necessary for logic

Necessary for large designs

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SIRM Example

Breaks up transistor abstraction into its components

Allows creation of library of composable components

Increases freedom of design

A

A

B

B

A&B

Old Way

A

B

A&B

New Way

Nano-switchNano-restorer

Nano-isolator


Manufacturing Requirements

InexpensiveReliableHigh yieldDense packingScalable

Top-Down: Photolithography-Combines manufacturing and assembly into one step!Bottom-up: ?


(scalable) Bottom-up assembly

Many different techniques:Langmuir-Blodgett filesFlow-based alignmentEM alignmentSelf-assembled monolayersChemical synthesisDNA-based assemblyNano-imprinting

Separates manufacturing and assembly!Often, no precise placement control


Fabrication Is Different

Devices & wires alone are not usefulKey to nanoscale computing is bottom-up assembly

Con

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15-398 lecture 5



Fabrication PrimitivesParallel wires2-D grids


Fabrication PrimitivesParallel wires2-D gridsSelf-assembled monolayers


Fabrication PrimitivesParallel wires2-D gridsSelf-assembled monolayersConnections between orthogonal wires


Fabrication PrimitivesParallel wires2-D gridsSelf-assembled monolayersConnections between orthogonal wiresConnections to CMOS

15-398 lecture 5



Fabrication PrimitivesParallel wires2-D gridsSelf-assembled monolayersConnections betweenorthogonal wiresConnections to CMOSNon-deterministic placement


Fabrication PrimitivesParallel wires2-D gridsSelf-assembled monolayersConnections betweenorthogonal wiresConnections to CMOSNon-deterministic placementSelective variability on a lithographic scale


Building a Computing Crystal



15-398 lecture 5




Assembly Computing CrystalsWith defects


Scale Matching

1.2nm >40nm40x differenceOverhead?

Input

A2

A2A2

A1

A1A1

A0

A0A0

O0O1O2O3O4O5O6O7


Harnessing RandomnessFab primitives prefer low information content structures

Can we design circuits that can exploit this?

Example: Scale Matching

Address 1 nanoscale wire with 5log(N) micronscalewires

Based on random placement of molecules

Address lines

Nanoscale wireslecture 8 15-398 © 2004 Seth Copen Goldstein 28

Reconfigurable!

Implications

Prefer devices at cross-points(only 2 terminal devices?)Only regular structuresDefect-tolerance requiredFunctionality must be added post-fabricationReduce nano-micro overhead

15-398 lecture 5



FPGA

Universal gates and/or

storage elements

Interconnectionnetwork

Programmable Switches


Reconfigurable Computing

Compiler

General-Purpose Custom Hardwareint reverse(int x){

int k,r=0;for (k=0; k<64; k++)

r |= x&1;x = x >> 1;r = r << 1;

}}int func(int* a,int *b){

int j,sum=0;for (j=0; *a>0; j++)

sum+=reverse(*b

General-PurposeCustom Hardware

Logic Blocks

Routing Resources


Aides defect tolerance

Reconfigurability & DFT

FPGA computing fabricRegularperiodic Fine-grainedHomogenous

programs circuits

Place& Route

Place& Route


Sample Proposals

Can be evaluated on determinism required at fab time

Nanocell: purely randomArray-based: quasi-regularNanoscale silicon: determinisitc

15-398 lecture 5



Nanocell

Summer


Using the Nanocell

Summer


Array-Based approaches

This is the general trendCreate meshes, glue them togetherEach Mesh is reconfigurable

Dehon

+Vdd

Gro

und

C

CGnd

+Vdd

Gro

und

C

CGnd


NanoBlock

+Vdd

Gro

und

C

CGnd

Stripped regions indicate connections from the CMOS layer.

Diode-matrix Molecular-latches

15-398 lecture 5



Diode-resistor Logic

A * B

V AND

BA

A ^ B

VVV AND

A

BA

B

A * B

Nano-implementation

Configured ON

Configured OFF


Diode-resistor Logic

VDD

A * BA

B

A * B

Nano-implementation Electrical equivalent

Configured ON

Configured OFFV AND

BA

A ^ B

VVV AND

A

BA

B

A * B

Problems?


V

BAA

B

V V V

S = A B

V V

CS

C = A ^ B

Half adder


Abstract

+Vdd

Gro

und

C

CGnd

SE

15-398 lecture 5



SE

SE

Nearest Neighbor Routing


SE

SE

NW

NW



SE

SE

NW

NW


Switch block


2-D Mesh

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2-D Mesh


2-D Mesh


Cluster of NanoBlocks


The NanoFabric

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Nanoscale layer put deterministically ontop of CMOS

Highly regular

~108 long lines

~106 clusters

Cluster has 128 blocks

15-398 lecture 5



NanoFabric Attributes

Hierarchical fabrication1. Manufacture devices2. Non-deterministically align wires3. Self-assemble monolayers onto wires

4. Create meshes5. Deterministically align w/CMOS

ReconfigurableDefect tolerant


Trade-offs

Ease of Manufacturing Vs. ?Device capabilities Vs. ?Device reliability Vs ?Information content in design Vs ?


Next Time

Take a closer look at nano-devicesRead chapter 5Recommended Ratner 1973

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Computing Devices Switching