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Field-Programmable Gate Arrays (FPGAs)
Fine-grained reconfigurable hardware
Gate-Array: regular structure of logic cells, connectedthrough
an interconnection network
Configuration stored in SRAM, must be loaded on startup
EPROM
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FPGA toolflow
HDL
(VHDL /Verilog)
Synthesize
Netlist
Map
Place
Route
Bitstream
Hardware design is traditionally done by
modeling the system in a hardware
description language
An FPGA compiler (synthesis tool)
generates a netlist,
which is then mapped to the FPGA
technology,
the inferred components are placed on thechip,
and the connecting signals are routed
through the interconnection network.
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HDL Synthesis
Register
a
boutput
clk
reset
clear
D Q
process(clk, reset)
beginif reset = 1 then
output
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Technology Mapping
HDL
(VHDL /Verilog)
Synthesize
Netlist
Map
Place
Route
Bitstream
Register
a
b
output
clk
reset
clear
D Q
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Place & Route
HDL
(VHDL /Verilog)
Synthesize
Netlist
Map
Place
Route
Bitstream
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Xilinx ISE
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Traditional Embedded System
Power Supply
CLKCLK
CLKcustomIF-logic
SDRAM SDRAMSRAM SRAMSRAM
MemoryController
UARTLC
DisplayController
Interrupt
Controller
Timer
AudioCodec
CPU(uP / DSP) Co-
Proc.
GP I/O
AddressDecode
Unit
EthernetMAC
Images by H.Walder
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Traditional Embedded System
FPGACLKCLK
CLKcustomIF-logic
SDRAM SDRAMSRAM SRAMSRAM
MemoryController
UART
DisplayController
Timer
Power Supply
LC
AudioCodec
CPU(uP / DSP) Co-
Proc.
GP I/O
AddressDecode
Unit
EthernetMAC
Interrupt
Controller
Images by H.Walder
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Configurable System on Chip (CSoC)
Power Supply
SDRAM SDRAMSRAM SRAMSRAM
LC
AudioCodec EPROM
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Advantages
Fewer physical components
Shorter development cycles
Field-programmable (updates, new features...)
Possibly higher performance through on-chip integration
Signals on a chip can typically be clocked higher than signals
across
board traces
Optimization between modules possible
Partial reconfigurability
Exchange peripherals while the rest of the system keeps
running
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Embedded CPUs
PowerPC 405 (hard core) 32 bit embedded PowerPC RISC
architecture
Up to 450 MHz 2x 16 kB instruction and data caches
Memory management unit (MMU)
Hardware multiply and divide
Coprocessor interface (APU)
Embedded in Virtex-II Pro and Virtex-4
PLB and OCM bus interfaces
MicroBlaze (soft core) 32 bit RISC architecture
2-64 kB instruction and data caches
Barrel Shifter
Hardware multiply and divide
OPB and LMB bus interfaces
Others NIOS (Altera), ARM, PicoBlaze (Xilinx), ...
Images by Xilinx
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CoreConnect Bus Architecture
Flexible bus architecture for embedded Systems and SoCs
Developed by IBM
Used by Xilinx EDK
Processor Local Bus (PLB)
On-Chip Peripheral Bus (OPB)
Device Control Register Bus
(DCR)
Alternatives:
AMBA (Altera)
Wishbone (OpenCores)
Proprietary bus architectures
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Bus Configurations
Images by H.Walder
LMB: Local Memory Bus (for on-chip memory)OPB: On-Chip
Peripheral Bus
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CSoC Design Flow (Hardware)
HDL
(VHDL /Verilog)
Synthesize
Netlist
Map
Place
Route
Bitstream
Platform description is
translated/assembled into netlist,
which in turn is either
mapped, placed and routed onto
FPGA, or
Platform
Description
NetlistGeneration
Netlist
Bitstream
Xilinx ISE
(VHDL Edit, Map,Place & Route)
XST(Map, Place & Route)
VHDL
imported into ISE and used ina larger FPGA design
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Demonstration
Platform
Description
NetlistGeneration
Netlist
Bitstream
Xilinx ISE
(VHDL Edit, Map,Place & Route)
XST(Map, Place & Route)
VHDL
CSoC Design Flow (Hardware)
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CSoC Design Flow (Software)
Platform
Description
NetlistGeneration
Netlist
Bitstream
XST or ISE(Map, Place & Route)
Compile &Link
UpdateBitstream
Bitstreamwith
executableCode
Program
*.elf
*.aLibrary
Generation *.h *.h *.c
User sources
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CSoC Design Flow (Software)
Platform
Description
NetlistGeneration
Netlist
Bitstream
XST or ISE(Map, Place & Route)
Compile &Link
UpdateBitstream
Bitstreamwith
executableCode
Program
*.elf
*.aLibrary
Generation*.h *.h *.c
User sources
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Demonstration
Simple System: LED Counter
Bus Configuration:
MicroBlaze CPU
Instruction- and data memories
attached to local memory buses
General Purpose I/O (GPIO)
attached to data-side OPB
Target: Xilinx Spartan-III (XC3S200)
200000 gates (4320 logic cells)
480 CLBs (24 x 20)
216 Kbits Block RAM
173 User I/O pins
12 18x18 bit multipliers
MicroBlaze CPU Core
DOPB
DLMBILMB
GP I/O
BRAM
Image by H.Walder
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Demonstration
Spartan III FPGA
50 MHz clock(back side)
7-segment display
E14
G13F13N16
N15
P16
P15
R16
Reset button
CLK
RST LED0
LED7
Image by H.Walder
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Any
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