Concepts in VLSI Design

5/28/2018 Concepts in VLSI Design

1/59

Concepts in VLSI Design

Presented byNiket Agrawal(MTech VLSI)

IIT Guwahati


2/59

VGS

VT

Ro n

S D

A Switch!

|VGS|

An MOS Transistor

What is a transistor (Digital Definition)


3/59

The NMOS Transistor


4/59

Threshol Voltage Concept

n+n+

p-substrate

DS

G

B

VGS

+

-

Depletion

Region

n-channel


5/59

Transistor in Linear

n"n"

p#s$%strate

D

S

G

B

VGS

xL

V(x)"&

VDS

ID

MOS transistor an its %ias conitions


6/59

Transistor in Sat$ration

n+n+

S

G

VGS

D

VDS> VGS- VT

VGS

- VT

+-

Pinch-off


7/59

C$rrent#Voltage 'elations

Long#Channel Deice


8/59

C$rrent#Voltage 'elations

Quadratic

Relationship

0 0.5 1 1.5 2 2.50

1

2

3

4

5

6x 10

-4

VDS

(V)

ID(A)

VGS= !" V

VGS= !# V

VGS= $!" V

VGS= $!# V

Resisti%e Saturation

VDS= VGS- VT


9/59

Velocit Sat$ration( Deep s$% *icron +ra)

(V/m)c= 1.5

n(

m/s)

sat= 105

Constant mobility (slope = )

Constant velocity


10/59

,erspectie

ID

Long-channel device

Short-channel device

VDSVDSAT VGS- VT

VGS = VDD


11/59

ID ers$s V-S

0 0.5 1 1.5 2 2.50

1

2

3

4

5

6x 10

-4

VGS(V)

ID(A)

0 0.5 1 1.5 2 2.50

0.5

1

1.5

2

2.5x 10

-4

VGS(V)

ID(A)

&uadratic

&uadratic

linear

'ong (hannel Short (hannel


12/59

A $nifie *oel

for *an$al analsis


13/59

A ,MOS Transistor

-2.5 -2 -1.5 -1 -0.5 0-1

-0.8

-0.6

-0.4

-0.2

0x 10

-4

VDS(V)

ID(A)

)ssu*e all %ariables

negati%e+

VGS = -$!#V

VGS = -$!"V

VGS = -!#V

VGS = -!"V


14/59

MOS Capacitances

DS

G

B

CGDCGS

CSB CDBCGB


15/59

The -ate Capacitance

tox

n" n"

Cross section

L

-ate o.ie

xd xd

L d

,ol silicongate

Top view

-ate#%$l/oerlap

So$rce

n"

Drain

n"W


16/59

-ate Capacitance

S D

G

CGC

S D

G

CGC

S D

G

CGC

(ut-off Resisti%e Saturation

Most i*portant regions in igital esign sat$ration an c$t#off


17/59

Diff$sion Capacitance

Bottom

Side wall

Side wall

Channel

Source

ND

Channel-stop implant NA1

Substrate NA

W

xj

LS


18/59

S$%#Threshol 'egion (MOS now a 01T)

0 0.5 1 1.5 2 2.510

-12

10-10

10-8

10-6

10-4

10-2

VGS

(V)

ID(A)

VT

'inear

,ponential

Quadratic ox

DnkT

qV

D C

C

neII

GS

+=

$./ #


19/59

2a%rication

Fr a great tur thrugh the I!"anu#acturing $rcessand its di##erent ste$s% check

htt$&''www#ull"anc"'se"icnductrs'se"icnductrsht"l


20/59

CMOS ,rocess at a -lance

Define active areas

Etch and fill trenches

Implant well regions

Deposit and patternpolysilicon layer

Implant source and drainregions and substrate contacts

Create contact and via windowsDeposit and pattern metal layers


21/59

OutIn

VDD

PMOS

NMOS

p s$%strate

Metal

Thic/ fiel o.ie

n well

n"n" n"p"p"p"

Inerter Lao$t


22/59

2a%rication Steps

Start with blank wa#er (ty$ically $ty$e whereNM*S is created)

First ste$ will be t #r" the nwell (where

PM*S wuld reside) !+er wa#er with $rtecti+e layer # Si*, (-ide) .e"+e -ide layer where nwell shuld be built I"$lant r di##use n d$ants int e-$sed wa#er t

#r" nwell Stri$ ## Si*,

p s$%strate


23/59

O.iation

Grw Si*, n t$ # Si wa#er /00 1 2,00 ! with 3,* r *, in -idatin

#urnace

p s$%strate

SiO3


24/59

,hotoresist

Pht resist Phtresist is a lightsensiti+e rganic

$ly"er Pr$erty changes where e-$sed t light

Tw ty$es # $ht resists ($siti+e rnegati+e) Psiti+e resists can be re"+ed i# e-$sed

t 4V light Negati+e resists cannt be re"+ed i#e-$sed t 4V light

p s$%strate

SiO3

,hotoresist


25/59

Lithograph

5-$se $htresist t 4ltra+ilate(4V) light thrugh the nwell "ask

Stri$ ## e-$sed $ht resist with

che"icals

p s$%strate

SiO3

,hotoresist


26/59

+tch

5tch -ide with hydr#luric acid (3F) *nly attacks -ide where resist has been

e-$sed

Nwell $attern is trans#erred #r" the "ask tsilicndi-ide sur#ace6 creates an $ening tthe silicn sur#ace

p s$%strate

SiO3

,hotoresist


27/59

Strip ,hotoresist

Stri$ ## re"aining $htresist4se "i-ture # acids called $iranah etch

Necessary s resist desn7t "elt in

ne-t ste$

p s$%strate

SiO3


28/59

N#well

Nwell is #r"ed with di##usin r in i"$lantatin 8i##usin

Place wa#er in #urnace with arsenicrich gas 3eat until As at"s di##use int e-$sed Si

In I"$lanatatin 9last wa#er with bea" # As ins Ins blcked by Si*,% nly enter e-$sed Si

Si*, shields (r "asks) areas which re"ain $ty$e

n well

SiO3


29/59

Strip O.ie

Stri$ ## the re"aining -ide using 3F Subse:uent ste$s in+l+e si"ilar

series # ste$s

p s$%strate

n well


30/59

,ol silicon

(self#aligne gate technolog)

8e$sit +ery thin layer # gate -ide; ,0 < (=> at"ic layers)

!he"ical Va$r 8e$sitin (!V8) # silicnlayer Place wa#er in #urnace with Silane gas

(Si3?) Fr"s "any s"all crystals called $lysilicn

3ea+ily d$ed t be gd cnductrThin gate o.ie

,olsilicon

p s$%straten well


31/59

Self#Aligne ,rocess

4se gate-ide'$ly silicn and"asking t e-$se where n@ d$antsshuld be di##used r i"$lanted

Ndi##usin #r"s nM*S surce% drain%and nwell cntact

p s$%straten well


32/59

N#iff$sion4i*plantation

Pattern -ide and #r" n@ regins Self-aligned processwhere gate blcks n

d$ants Plysilicn is better than "etal #r sel#aligned

gates because it desn7t "elt during later$rcessing

p s$%straten well

n" Diff$sion


33/59

N#iff$sion4i*plantation cont5

3istrically d$ants were di##used 4sually high energy ini"$lantatin

used tday 9ut n@ regins are still called di##usin

n wellp s$%strate

n"n" n"


34/59

,#Diff$sion4i*plantation

Si"ilar set # ste$s #r" $@di##usinB regins #r PM*S surceand drain and substrate cntact

p" Diff$sion

p s$%straten well

n"n" n"p"p"p"


35/59

Contacts

Nw we need t wire tgether thede+ices

!+er chi$ with thick #ield -ide (F*) 5tch -ide where cntact cuts are

needed

p s$%strate

Thic/ fiel o.ie

n well

n"n" n"p"p"p"

Contact


36/59

Metali6ation

S$utter n alu"inu" +er whle wa#er Gld is used in newer technlgy Pattern t re"+e e-cess "etal% lea+ing wires

p s$%strate

Metal

Thic/ fiel o.ie

n well

n"n" n"p"p"p"

Metal


37/59

CMOS INV+'T+'

OutIn

VDD

PMOS

NMOS

VDD VDD

Vin 5 VDD Vin 5 0

VoutVout

Rn

Rp


38/59

CMOS Inerter VTC

Vout

Vin# ! " $ $ ! " ! "

#!

"

$

$!

"

!

"

012S res

P12S off

012S sat

P12S sat

012S off

P12S res

012S sat

P12S res

012S res

P12S sat

OutIn

VDD

PMOS

NMOS


39/59

CMOS Inerter ,ropagation Dela

VDD

Vout

Vin= VDD

Ron

CL

tpHL= f(on!CL"

= #!$% onCL

t

Vo$t

VDD

'onCL

7

859

ln(859)

85:;


40/59

0 0.5 1 1.5 2 2.5

x 10-10

-0.5

0

0.5

1

1.5

2

2.5

3

t (sec)

Vout(

V)

Transient 'esponse

tp= 0.69 CL(Reqn+Reqp)/2

3

tp'4tp4'


41/59

Design for ,erfor*ance

Cee$ ca$acitances s"all Increase transistr siDes

watch ut #r sel#ladingE Increase V88 ()


42/59

Dela as a f$nction of VDD

0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.41

1.5

2

2.5

3

3.5

4

4.5

5

5.5

VDD(V)

t p(normalized)


43/59

2 4 6 8 10 12 142

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

3.8x 10

-11

S

t p(sec)

Dela as a f$nction of Deice Si6ing

5for fied load6

Self-loading effect7

8ntrinsic capacitances

do*inate


44/59

Where Does ,ower -o in CMOSInN)

In7

In3

InN

In7

In3

InN

,?N

,DN

,MOS onl

NMOS onl

,?N an ,DN are $allogic networ/s

9

9


52/59

Threshol Drops

VDD

VDD8,DN

8 VDD

CL

CL

,?N

VDD

8 VDD# VTn

CL

VDD

VDD

VDD@VTp@

CL

S

D S

D

V-S

S

SD

D

V-S


53/59

+.a*ple -ate NAND


54/59

Co*ple. CMOS -ate

O?T D " A B (0 " C)

D

A

0 C

D

A

0

C


55/59

CMOS ,roperties

Full railtrail swing6 high nise "argins Lgic le+els nt de$endent u$n the relati+e

de+ice siDes6 ratiless

Always a $ath t Vdd r Gnd in steady state6lw ut$ut i"$edance 5-tre"ely high in$ut resistance6 nearly Der

steadystate in$ut current

N direct $ath steady state between $werand grund6 n static $wer dissi$atin Pr$agatin delay #unctin # lad ca$acitance

and resistance # transistrs


56/59

Dela Depenence on Inp$t ,atterns

-0.5

0

0.5

1

1.5

2

2.5

3

0 100 200 300 400

A078

A7= 078

A7 8= 07

ti*e ps

V

oltage

CVD

Input Data

Pattern

Delay

(psec)

A902 =>

A2%902

=?

A 02%92

=2

A920 ?J

A2%920

K0

A 20%92

K2


57/59

2ast Co*ple. -ates

Design TechniE$e 7

Transistr siDing as lng as #anut ca$acitance d"inates

Prgressi+e siDing

InN CL

C:

C3

C7

In7

In3

In:

M7

M3

M:

MNDistri%$te 'C line

M7 F M3 F M: F > F MN

(the fet closest to the o$tp$t is the s*allest)

Can re$ce ela % *ore than

38GH ecreasing gains as

technolog shrin/s


58/59

2ast Co*ple. -ates

Design TechniE$e 3

Transistr rdering

C3

C7In7

In3

In:

M7

M3

M: CL

C3

C7In:

In3

In7

M7

M3

M: CL

critical path critical path

charge7

87 charge

charge7

ela eter*ine % ti*e to

ischarge CL= C7an C3

ela eter*ine % ti*e to

ischarge CL

7

7

87 charge

ischarge

ischarge


59/59

S$**ar

It was a big talk At last it #inished

Nw I Hant t eny Sunday

Documents

Concepts in VLSI Design