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Confidential Date : Approval Signature Accepted by : Date : Proposed by : JDG01-E-01E Specifications Product Name LPM025M475A To :

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Page 1: Confidential Tozb.16rd.com/data/uploads/2019/09/02/8457858165d6d15a38d635.pdf · Ambient temperature : Ta=25°C Backlight current : I LED =9.5mA Notes (1) Definition of Brightness

仕様書パターン2 CAS表紙

Confidential

Date :

Approval Signature

Accepted by :

Date :

Proposed by :

JDG01-E-01E

Specifications

Product Name LPM025M475A

To :

Page 2: Confidential Tozb.16rd.com/data/uploads/2019/09/02/8457858165d6d15a38d635.pdf · Ambient temperature : Ta=25°C Backlight current : I LED =9.5mA Notes (1) Definition of Brightness

Confidential

No. Item Page

1 COVER 1 / 35

CONTENTS 2 / 35

2 RECORD OF REVISIONS 3 / 35

3 GENERAL DATA 4 / 35

4 ABSOLUTE MAXIMUM RATINGS 5 / 35

4.1 ELECTRICAL ABSOLUTE MAXIMUM RATINGS OF LCD 5 / 35

4.2 ENVIRONMENTAL ABSOLUTE MAXIMUM RATINGS 5 / 35

5 ELECTRICAL CHARACTERISTICS 6 / 35

6 OPTICAL CHARACTERISTICS 7~8 / 35

7 BLOCK DIAGRAM 9 / 35

8 INTERFACE 10 / 35

8.1 INTERNAL PIN CONNECTION 10 / 35

8.2 TIMING CHARACTERISTICS 11~15 / 35

8.3 POWER ON/OFF SEQUENCE 16 / 35

8.4 SEQUENCE 17~19 / 35

9 DIMENSIONAL OUTLINE (LCD) 20 / 35

LPM025M475A-01 2 / 35Japan Display Inc. Page

CONTENTS

Sh.

No.Date Mar. 12, 2019

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RECORD OF REVISIONS Confidential

LPM025M475A-01 3 / 35

SummaryPage

PageSh.

No.Japan Display Inc. Date Mar. 12, 2019

Sheet No.Date

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3. GENERAL DATA Confidential

(1) Part Name LPM025M475A

(2) Module Dimensions 39.19 (W) mm × 64.46 (H) mm × 1.9 (t) mm *Except FPC

(3) Active Area Dimensions 31.59 (W) mm × 56.16 (H) mm

(4) Pixel Pitch 0.00975 (W) mm × 0.02925 (H) mm (868ppi)

(5) Resolution 1080 × 3 (R,G,B) (W) × 1920 (H) dots

(6) Color Pixel Arrangement RGB Vertical Stripes

(7) Display Mode Transmissive Type, Normally Black Mode, In-Plane Switching Mode

(8) Number of Colors 16,777,216 Colors

(9) Viewing Direction -

(10) Backlight Light Emitting Diode (LED), 5 LEDs (2in1) ;

Backlight current : 9.5mA / LED (typ)

LED NS2W266G-HG (Nichia)

(11) Weight Around 9.45g

(12) Power Supply Voltage VSP +5.7V+/-0.1 V, VSN -5.7V+/-0.1 V

(13) Interface I/O power supply IOVCC = 1.8 +/-0.1 V

Note (1) The same voltage as "H" level of a customer's interface signal

must be supplied to VDDI.

(14) LCD Driver IC JD35596S(cut3)

(15) Interface MIPI-DSI 4Lanes x 1 Port

(16) Methode of Inversion Column Inversion

(17) Surface Treatment HC-Polarizer

Note (1) IOVCC is the reference voltage for adjusting the I/O signal level of JD35596S

IOVCC voltage must be determined according to a customer's system.

(2) VSP=AVDD, VSN=AVEE, IOVCC=VDDI=VDDIO=IOVDD=LCD_VDDIO

LPM025M475A-01 4 / 35Sh.

No.Japan Display Inc. Date Mar. 12, 2019 Page

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4. ABSOLUTE MAXIMUM RATINGS Confidential

4.1 ELECTRICAL ABSOLUTE MAXIMUM RATINGS OF LCD Ta=25°C

Item Symbol Min Max Unit Note

Power Supply for Interface

Power Supply for LCD

Power Supply for LCD

Input Voltage

LED Reverse Voltage VR - V

LED Forward Current ILED - Note (2) mA per LED

Notes (1) Applies to the RESET pin.

(2) LED Ambient Temperatures vs. Allowable Forward Current.

4.2 ENVIRONMENTAL ABSOLUTE MAXIMUM RATINGS

Operating Non-Operating (Note3)

Min Max Min Max

Ambient Temperature -10°C 50°C -30°C 60°C Note (2)

Humidity No condensation,Note (1)

Corrosive Gas Not Acceptable Not Acceptable

Notes (1) Ta < 40°C 85%RH max.

Ta > 40°C Absolute humidity must be lower than the humidity of 85%RH at 40°C.

(2) Background color slightly changes depending on ambient temperature and viewing angle.

The temperature for operating in the table above apply to operation only.

Visual qualities, such as contrast ratio and response time, to be evaluated at Ta=25°C Operating.

(3) This is not for storing condition. When storing LCM for long term, please follow the condition

mentioned in "11.5 STORAGE".

LPM025M475A-01 5 / 35Sh.

No.Japan Display Inc. Date Mar. 12, 2019 Page

Item Remarks

5% 85% 5% 85%

Vt -0.3 IOVCC+0.3 V (1),(2)

VSN -6.5 0.3 V (2)

VSP -0.3 6.5 V (2)

IOVCC -0.3 4.0 V (2)

8.5mA (85°C)

30mA (39°C)

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5. ELECTRICAL CHARACTERISTICS Confidential

LCD MODULE Ta=25°C

Item Symbol Condition Min Typ Max Unit Note

-

-

-

Input Voltage for Logic VIH - IOVCC V (1),(2)

Circuits VIL 0 -

Output Voltage for Logic VOH1 IOH=-0.1mA - - V (1),(3)

Circuits VOL1 IOL=0.1mA - -

All White mA (4)

Power Supply Current Deep standby uA (4)

All White mA (4)

Deep standby uA (4)

All White mA (4)

Deep standby uA (4)

LED Forward Voltage VLED - - 5.65 V (5)

LED Forward Current ILED - - 9.5 mA (5)(6)

LED Reverse Current IR - - - μA

Frame Frequency fFLM - - 60 - Hz

Notes (1) IOVCC = 1.7V to 1.9V

(2) Input : RESET

(3) Output : LEDPWM, TE

(4) IOVCC=1.8V, VSP=5.7V, VSN=-5.7V, fFLM=60Hz

The current is time averaged value even for Maximum criteria.

(5) Each value is the characteristics of one LED. @If=9.5mA

(6) The operating current of LED and the duty ratio should be determined within

the maximum rating of the temperature environmental condition.

LPM025M475A-01 6 / 35

V

Power Supply Voltage for

LCDVSP - 5.6 5.7 5.8 V

Power Supply Voltage for

LCDIOVCC - 1.7 1.8 1.9

0.8×IOVCC

Power Supply Voltage for

LCDVSN - -5.8 V

- 0.8×IOVCC

- 0.2×IOVCC

-5.7 -5.6

0.2×IOVCC

I_IOVCC- 27 37

- 0.2 50.0

I_VSP- 4.4 7.0

- 2.1 50.0

-4 -7

- -3.2 -50.0

Japan Display Inc. Date Mar. 12, 2019

I_VSN-

Page

-

-

-

Sh.

No.

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6. OPTICAL CHARACTERISTICS Confidential

LCD (BACKLIGHT ON)

Item Symbol Condition Min Typ Max Unit Note

Brightness B φ=0°, θ=0° - cd/m2 (1),(2)

Brightness Uniformity - φ=0°, θ=0° - %

Viewing Angle θ φ=0°, CR>10 - - deg (4),(6),(7)

φ=90°, CR>10 - -

φ=180°, CR>10 - -

φ=270°, CR>10 - -

Contrast Ratio CR φ=0°, θ=0° - - (6)

Response Time G to G φ=0°, θ=0° ms (8)

x

y

x

Color Tone y

(Primary Color) x φ=0°, θ=0° - -

y

x

y

NTSC Ratio - - - % -

Gamma - - 2.1 2.2 2.3 % (10)

Cross Talk - - (9)

Flicker - - (9)

Measurement Conditions

Measurement environment : Dark room with illluminance < 0.1lux

Ambient temperature : Ta=25°C

Backlight current : ILED=9.5mA

Notes (1) Definition of Brightness "B"

Sensor : KONICA MINOLTA CS-2000A or CA310 equivalent

Measurement point : Center of LCD's active area

(2) Display image for measurement : All White

LPM025M475A-01 7 / 35Japan Display Inc. Date Mar. 12, 2019 Page

White0.293 0.313 0.333

0.309 0.329 0.349

90 95

No visible problem on practical use

No visible problem on practical use

Sh.

No.

Blue0.122 0.152 0.182

0.020 0.050 0.080

0.311 0.341

Green0.237 0.267 0.297

0.653 0.683 0.713

Red0.650 0.680 0.710

0.281

180 200

80 85

80

950

- 7.3 10

750

500 mm

Sensor

LCD Module

Page 8: Confidential Tozb.16rd.com/data/uploads/2019/09/02/8457858165d6d15a38d635.pdf · Ambient temperature : Ta=25°C Backlight current : I LED =9.5mA Notes (1) Definition of Brightness

Notes (3) Measurement point (4) Definition of θ and φ Confidential

(5) Definition of brightness uniformity

(6) Definition of Contrast "CR"

(7) Definition of Viewing Angle θ1 and θ2

(8) Definition of Optical Response Time

(9) If a nonconformance is found, both parties will have a discussion to solve it.

(10) Gray 0~16,Gray 236~255 gamma 2.2±0.2 is acceptable.

LPM025M475A-01 8 / 35Sh.

No.Japan Display Inc. Date Mar. 12, 2019 Page

Brightness when displaying White raster

Brightness when displaying Black raster CR =

10

θ1 θ2

θ1 < 0°< θ2

Contr

ast C

R

Viewing angle θ

Sensor

θ=0°

θ

Sensor : TOPCON's BM-5A or equivalent

Gary

tr : Rise time tf : Fall time

Optical response time

Gray Gray Display data

100 90

10 0

%

Rel

ativ

e

Bri

gh

tnes

s

× 100 (%) Brightness (min)

Brightness (max) Brightness uniformity =

x' x

z

y

y' φ

θ θ

Viewing direction

(φ=0°) (φ=180°)

(φ=90°)

(φ=270°)

θ=0°

P1 P2 P3

P4 P5 P6

P7 P8 P9

180 540 900

320 (V/6)

960 (V/2)

1600 (V5/6)

(Pixel) (1080) (1)

(1)

(1920)

(H/6) (H/2) (H5/6)

H: A.A horizontal dimension

V: A.A vertical dimension

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7.BLOCK DIAGRAM Confidential

2

3

17

2

2

6

LPM025M475A-01 9 / 35Sh.

No.Japan Display Inc. Date Mar. 12, 2019 Page

1080xRGB(H)x1920(V)

JD35596S

R G B

CN001

Note 1 LED Backlight Circuit Diagram

LED Backlight (5LEDs are series and

1pallarel strings connection)

G1

G1920

1 1080

GND

LCD_RST

D0P,D0N

IOVCC,VSP,VSN

PWM

LEDA,LEDK

CLKP,CLKN

D1P,D1N,D2P,

D2N,D3P,D3N

TE

LCD_ID

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8.INTERFACE Confidential

8.1 INTERNAL PIN CONNECTION

I/O

Ground

Ground

LCD Power

MIPI DSI data-3 signal line(-)

Ground

MIPI DSI data-3 signal line(+)

LCD Power

Ground

Ground

MIPI DSI data-0 signal line(-)

I/O power (for LCDIC& TPIC)

MIPI DSI data-0 signal line(+)

Ground

Ground

Ground

MIPI DSI Clock signal line(-)

Ground

MIPI DSI Clock signal line(+)

Ground

Ground

Ground

MIPI DSI data-1 signal line(-)

LCD Reset signal

MIPI DSI data-1 signal line(+)

Ground

Ground

LCD TE signal output

MIPI DSI data-2 signal line(-)

Ground

MIPI DSI data-2 signal line(+)

Backlight control PWM signal output

Ground

Ground

Ground

No connection

Ground

LED Anode

LED Cathode

No connection

Ground

Notes (1) P : Power supply, I : Input, O: Output, I/O: Input/Output

(2) LCM Connector : (Panasonic) AXQ2401HB1 (40pin) (Plug)

LPM025M475A-01 10 / 35

2 GND P GND

3 VSP P VSP

Pin No. Signal Function Remarks

1 GND P GND

6 D3P I D3P

7 VSN P VSN

4 D3N I D3N

5 GND P GND

10 D0N I/O D0N

11 IOVCC P IOVCC

8 GND P GND

9 GND P GND

14 GND P GND

15 LCD_ID(GND) O LCD_ID

12 D0P I/O D0P

13 GND P GND

18 CLKP I CLKP

19 GND P GND

16 CLKN I CLKN

17 GND P GND

22 D1N I D1N

23 RESET I LCD_RST

20 GND P GND

21 GND P GND

26 GND P GND

27 TE O TE

24 D1P I D1P

25 GND P GND

30 D2P I D2P

31 LEDPWM O PWM

28 D2N I D2N

29 GND P GND

34 GND P GND

35 NC - NC

32 GND P GND

33 GND P GND

38 LED- P LEDK

39 NC - NC

36 GND P GND

37 LED+ P LEDA

40 GND P GND

Sh.

No.Japan Display Inc. Date Mar. 12, 2019 Page

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8.2 TIMING CHARACTERISTICS Confidential

(1)MIPI DSI Characteristics

Item Symbol Unit Condition Min Typ Max Note

Differential input

high threshold

Differential input

low threshold

Single-ended

input low voltage

Single-ended

input high voltage

Common-mode voltage

HS receive mode

Differential input

impedance

Logic 0 input voltage

not in ULP State

Thevenin output

low level

Thevenin output

high level

Output impedance of

LP transmitter

Logic 0

contention threshold

Logic 1

contention threshold

LPM025M475A-01 11 / 35Sh.

No.Japan Display Inc. Date Mar. 12, 2019 Page

70

VIDTL mV IOVCC=1.65~1.95V -70 - -

VIDTH mV IOVCC=1.65~1.95V - -

- -

VIHHS mV IOVCC=1.65~1.95V - - 460

VILHS mV IOVCC=1.65~1.95V -40

LP-RX

VIL mV IOVCC=1.65~1.95V 0 -

ZID Ω IOVCC=1.65~1.95V 80 100 125

VCMRX(DC) mV IOVCC=1.65~1.95V 70 - 330

HS-RX

550

Logic 1 input voltage VIH mV IOVCC=1.65~1.95V 880 - IOVCC

CD-RX

VILCD mV IOVCC=1.65~1.95V 0 - 200

50

VOH V IOVCC=1.65~1.95V 1.1 1.2 1.3LP-TX

VOL mV IOVCC=1.65~1.95V -50 -

ZOLP Ω

VIHCD mV IOVCC=1.65~1.95V 450 - IOVCC

100 125IOVCC=1.65~1.95V 80

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MIPI DSI HS-RX Clock and Data-Clock Specifications Confidential

Item Symbol Unit Condition Min Typ Max Note

Notes 1. This value corresponds to a minimum 80 Mbps data rate.

2. The minimum UI shall not be violated for any single bit period, i.e.,any DDR half cycle within a data burst.

3. Total silicon and package delay budget of 0.3* UIINST when D-PHY is supporting maximum data rate = 1Gbps.

4. Total setup and hole window for receiver of 0.3* UIINST when D-PHY is supporting maximum data rate = 1Gbps.

5. Applicable when operating at HS bit rates ≤ 1 Gbps (UI ≥ 1 ns).

6. Applicable for all HS bit rates. However, to avoid excessive radiation, bit rates ≤ 1 Gbps (UI ≥ 1 ns), should not use values below 150 ps.

7. For MIPI speed limitation:

[1] Per lane bandwidth is 1Gbps,

[2] Total Bit Rate: 4.8Gbps for 8-8-8; 3.6 Gbps for 6-6-6; and 3.2Gbps for5-6-5.

MIPI DSI LP-RX/TX Clock and Data-Clock Specifications

Item Symbol Unit Condition Min Typ Max Note

Time to drive LP-00 to prepare

for HS transmission

Time to drive flipped differential

state after last payload data bit of

a HS transmission burst

Time to drive LP-11

after HS burst

Time to drive LP-00

after Turnaround Request

Time-out before new TX side

starts driving

Length of any Low-Power state

period

Ratio of TLPX(MASTER)/TLPX(SLAVE)

between Master and Slave side

Time that the transmitter shall

continue sending HS clock after

the last associated Data Lane

has transitioned to LP mode

TCLK-PREPARE + Time for lead HS-0

drive period before starting Clock

LPM025M475A-01 12 / 35Sh.

No.Japan Display Inc. Date Mar. 12, 2019 Page

12.5 1, 2, 7

Data to Clock Skew

[measured at transmitter]T SKEW [TX] UIINST IOVCC=1.65~1.95V -0.15 - 0.15 3

UI instantaneous UIINST ns IOVCC=1.65~1.95V 0.833 -

0.15 4

Data to Clock Hold Time

[measured at receiver]T HOLD [RX] UIINST IOVCC=1.65~1.95V 0.15 - 0.15 4

Data to Clock Setup Time

[measured at receiver]T SETUP [RX] UIINST IOVCC=1.65~1.95V 0.15 -

- 6

UIINST IOVCC=1.65~1.95V - - 0.3 5

20% - 80% rise time

and fall timetR / tF

ps IOVCC=1.65~1.95V 150 -

THS-TRAIL - IOVCC=1.65~1.95V60ns

+4*UI- -

THS-PREPARE - IOVCC=1.65~1.95V40ns

+4*UI-

85ns

+6*UI

TTA-GO - IOVCC=1.65~1.95V

THS-EXIT ns IOVCC=1.65~1.95V 100 - -

- 4*TLPTX -

Time to drive LP-00 by new TX TTA-GET - IOVCC=1.65~1.95V

TTA-SURE - IOVCC=1.65~1.95V 1*TLPTX - 2*TLPTX

- 5*TLPTX -

Ratio TLPX - IOVCC=1.65~1.95V 2/3 - 3/2

TLPX ns IOVCC=1.65~1.95V 50 - 75

TCLK-PREPARE

+ TCLK-ZERO

ns IOVCC=1.65~1.95V 300 - -

TCLK-POST - IOVCC=1.65~1.95V60ns

+52UI- -

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Confidential

Item Symbol Unit Condition Min Typ Max Note

Time that the HS clock shall be

driven prior to any associated

Data Lane beginning the transition

from LP to HS mode

Time to drive LP-00 to prepare

for HS clock transmission

Time to drive HS differential state

after last payload clock bit

of an HS transmission burst

Time from start of THS-TRAIL

period to start of LP-11 state

Data to Clock Timing Definitions

D-PHY Signaling Levels

LPM025M475A-01 13 / 35Sh.

No.Japan Display Inc. Date Mar. 12, 2019 Page

-

95

-

TCLK-TRAIL nsIOVCC=DPHYVCC

=1.65~1.95V60 -

TCLK-PRE UIIOVCC=DPHYVCC

=1.65~1.95V8 -

TCLK-PREPARE nsIOVCC=DPHYVCC

=1.65~1.95V38 -

105ns

+12*UITEOT -

IOVCC=DPHYVCC

=1.65~1.95V- -

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Confidential

HS Data Transmission in Bursts

Switching the clock lane between clock Transmission and LP mode

DSI LP Mode

LPM025M475A-01 14 / 35Sh.

No.Japan Display Inc. Date Mar. 12, 2019 Page

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Confidential

LPM025M475A-01 15 / 35Sh.

No.Japan Display Inc. Date Mar. 12, 2019 Page

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8.3 POWER ON/OFF SEQUENCE Confidential

LPM025M475A-01 16 / 35Sh.

No.Japan Display Inc. Date Mar. 12, 2019 Page

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8.4 SEQUENCE Confidential

LPM025M475A-01 17 / 35Sh.

No.Japan Display Inc. Date Mar. 12, 2019 Page

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Initial setting & Exit sleep mode sequence for non-compression mode Confidential

LPM025M475A-01 18 / 35Sh.

No.Japan Display Inc. Date Mar. 12, 2019 Page

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Confidential

LPM025M475A-01 19 / 35Sh.

No.Japan Display Inc. Date Mar. 12, 2019 Page

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9. DIMENSIONAL OUTLINE Confidential

LPM025M475A-01 20 / 35Sh.

No.Japan Display Inc. Date Mar. 12, 2019 Page