Copyright © 2008 Intel Corporation. All rights reserved. FROM SINGLE- TO MANY-CORE COMPUTING 14 April 2008 Dr Herbert Cornelius Intel EMEA

Copyright © 2008 Intel Corporation. All rights reserved.

FROM SINGLE- TO MANY-CORE COMPUTINGFROM SINGLE- TO MANY-CORE COMPUTING

14 April 200814 April 2008Dr Herbert CorneliusDr Herbert CorneliusIntel EMEAIntel EMEA


Risk FactorsRisk Factors

This presentation contains forward-looking statements that involve a number of risks and uncertainties. These statements do not reflect the potential impact of any mergers, acquisitions, divestitures, investments or other similar transactions that may be completed in the future, with the exception of the Numonyx transaction. Our forward-looking statements for 2008 reflect the expectation that the Numonyx transaction will close during the first quarter. The information presented is accurate only as of today’s date and will not be updated. In addition to any factors discussed in the presentation, the important factors that could cause actual results to differ materially include the following: Factors that could cause demand to be different from Intel's expectations include changes in business and economic conditions, including conditions in the credit market that could affect consumer confidence; customer acceptance of Intel’s and competitors’ products; changes in customer order patterns, including order cancellations; and changes in the level of inventory at customers. Intel’s results could be affected by the timing of closing of acquisitions and divestitures. Intel operates in intensely competitive industries that are characterized by a high percentage of costs that are fixed or difficult to reduce in the short term and product demand that is highly variable and difficult to forecast. Additionally, Intel is in the process of transitioning to its next generation of products on 45 nm process technology, and there could be execution issues associated with these changes, including product defects and errata along with lower than anticipated manufacturing yields. Revenue and the gross margin percentage are affected by the timing of new Intel product introductions and the demand for and market acceptance of Intel's products; actions taken by Intel's competitors, including product offerings and introductions, marketing programs and pricing pressures and Intel’s response to such actions; Intel’s ability to respond quickly to technological developments and to incorporate new features into its products; and the availability of sufficient components from suppliers to meet demand. The gross margin percentage could vary significantly from expectations based on changes in revenue levels; product mix and pricing; capacity utilization; variations in inventory valuation, including variations related to the timing of qualifying products for sale; excess or obsolete inventory; manufacturing yields; changes in unit costs; impairments of long-lived assets, including manufacturing, assembly/test and intangible assets; and the timing and execution of the manufacturing ramp and associated costs, including start-up costs. Expenses, particularly certain marketing and compensation expenses, vary depending on the level of demand for Intel's products, the level of revenue and profits, and impairments of long-lived assets. Intel is in the midst of a structure and efficiency program that is resulting in several actions that could have an impact on expected expense levels and gross margin. We expect to complete the divestiture of our NOR flash memory assets to Numonyx. A delay or failure of the transaction to close, or a change in the financial performance of the contributed businesses could have a negative impact on our financial statements. Intel’s equity proportion of the new company’s results will be reflected on its financial statements below operating income and with a one quarter lag. The tax rate expectation is based on current tax law and current expected income. The tax rate may be affected by the jurisdictions in which profits are determined to be earned and taxed; changes in the estimates of credits, benefits and deductions; the resolution of issues arising from tax audits with various tax authorities , including payment of interest and penalties; and the ability to realize deferred tax assets. Gains or losses from equity securities and interest and other could vary from expectations depending on fixed income and equity market volatility; gains or losses realized on the sale or exchange of securities; gains or losses from equity method investments; impairment charges related to marketable, non-marketable and other investments; interest rates; cash balances; and changes in fair value of derivative instruments. Intel’s results could be affected by the amount, type, and valuation of share-based awards granted as well as the amount of awards cancelled due to employee turnover and the timing of award exercises by employees. Intel's results could be impacted by adverse economic, social, political and physical/infrastructure conditions in the countries in which Intel, its customers or its suppliers operate, including security concerns, natural disasters, infrastructure disruptions, health concerns and fluctuations in currency exchange rates. Intel's results could be affected by adverse effects associated with product defects and errata (deviations from published specifications), and by litigation or regulatory matters involving intellectual property, stockholder, consumer, antitrust and other issues, such as the litigation and regulatory matters described in Intel's SEC reports. A detailed discussion of these and other risk factors that could affect Intel’s results is included in Intel’s SEC filings, including the report on Form 10-K for the fiscal year ended December 29, 2007.


Computing …Computing …

*Other names and brands may be claimed as the property of others.


NEED FOR SPEED & DENSITYNEED FOR SPEED & DENSITY

TERAOPSTERAOPS Performance PerformanceTERABYTESTERABYTES Memory Bandwidth Memory BandwidthTERABITSTERABITS I/O Throughput I/O Throughput

Tera-Scale ComputingTera-Scale Computing


NEED FOR SPEED & DENSITYNEED FOR SPEED & DENSITY

TERAOPSTERAOPS Performance PerformanceTERABYTESTERABYTES Memory Bandwidth Memory BandwidthTERABITSTERABITS I/O Throughput I/O Throughput

Tera-Scale ComputingTera-Scale Computing


Some Observations Regarding Benefits vs. Some Observations Regarding Benefits vs. EffortsEfforts

The number of transistors on a chip doubles every 24 month Processor architectures changed from area limited to power limited

ILP useful for ~4 parallel instructions Instruction pipeline useful if 30 stages Power consumption grows about cubically with frequency Processing capability grows faster than memory speed

Single core performance is growing slower than it used to be

SMT/HT can mitigate the situation for certain workloads CMP/Multi-Core seems to be a reasonable “compromise” Opportunity for performance to increase faster than Moore’s Law


1 TFLOPS on a Chip

62WExperimental Research Test ChipExperimental Research Test Chip

100M Transistors – 80 Tiles – 275mm100M Transistors – 80 Tiles – 275mm22


Industry Trend to Multi/Many-CoreIndustry Trend to Multi/Many-Core

Multi ProcessorMulti Processor

Hyper-ThreadingHyper-Threading

Dual-CoreDual-Core

Multi-CoreMulti-Core

Many-CoreMany-Core

Energy Efficient Petascale with Multi-threaded Cores

Intel Intel Tera-ScaleTera-Scale Computing Research Computing Research Program:Program:

www.intel.com/go/terascale www.intel.com/go/terascale

QUAD-CORE

All products, dates, and figures are preliminary and are subject to change without any notice.


On-Time 2 Year CyclesOn-Time 2 Year CyclesMoore´s Law is (still) leading the Chip Industry

Future options subject to change; Source: Intel


IntelArchitecture

Core

New Materials and DesignsNew Materials and Designs

Core EnhancementsCore Enhancements

Platform EnhancementsPlatform Enhancements

Going ForwardGoing Forward

Multi to Many-Core Multi to Many-Core


IntelArchitecture

Core

Tri-Gate, Nanotubes Tri-Gate, Nanotubes

MMX SSE AVX MMX SSE AVX

PCIe, IMC, QPI, SOC PCIe, IMC, QPI, SOC

Going ForwardGoing Forward

Dual Quad Octo Dual Quad Octo


Memory and CPU package architectures forMemory and CPU package architectures foraddressing bandwidth challengesaddressing bandwidth challenges

Future Vision, does not represent real Intel product

Package Technology to Address the Memory Bandwidth Challenge for Tera-scale Computing, Intel Technology Journal, Volume 11, Issue 3, 2007



The Magic of 45 nmThe Magic of 45 nm(Spectrum of Intel Architecture)(Spectrum of Intel Architecture)

Source: Intel Internal

Ultra-low Cost andPower Optimized

Architecture

Intel® Core™ 2 and NehalemArchitecture

Notebook, Desktop and Server

POWER

PE

RFO

RM

AN

CE

SYSTEMON A CHIP

Visual Computingand HPC Optimized

Architecture

Integration Options

Example: GraphicsIntegration Options

Example: Graphics

All plans, products, dates, and figures are preliminary and are subject to change without any notice.


Bringing IA Programmability and ParallelismBringing IA Programmability and Parallelismto High Performance & Throughput Computingto High Performance & Throughput Computing

Highly parallel, IA programmable architecture in development

Ease of scaling for software ecosystem Array of enhanced IA cores New Cache Architecture New Vector Processing Unit Scalable to TFLOPS performance

Cache

SpecialFunction

& I/O

… IA++

…

…… … …

… IA++

IA++

IA++

IA++

IA++

IA++

IA++

IA++

IA++

IA++

IA++

Future options subject to change without notice.


20102007 2008 2009

PenrynPenryn NehaleNehalemm

Sandy Sandy BridgeBridge

WestmereWestmere

NEWMicroarchitecture

45nm


32nm

Compaction/Derivative

45nm45nm

Compaction/Derivative

32nm32nm

Tick/Tock: Our Model for Sustained Tick/Tock: Our Model for Sustained Microprocessor Leadership Microprocessor Leadership

2006

IntelIntel®® Core™Core™


65nm

Forecast

Future options subject to change without notice.

e.g. Intel® QuickPath Architecture


Parallel Programming ConsiderationsParallel Programming Considerations

Finding or Introducing Parallelism Serial vs. Parallel Algorithm Partitioning

– Data-Parallelism– Functional-Parallelism– Manager/Worker Approach

Implementing Parallelism Correctness Speed-Up Scalability Overhead Communication/Synchronization Load-Imbalance Granularity Platform Related


Intel’s Software Tools and SupportIntel’s Software Tools and Support

ISN & ISC ISS

Performance | Compatibility | Support | Productivity | Cross-Platform

Cluster Tools

www.intel.com/software

Intel® Threading ToolsIntel® Threading Tools


INTEL® ARCHITECTUREINTEL® ARCHITECTURE

Continuous Innovation and sustained Leadership

Moving ahead to Multi/Many-Core Processors

45nm Production since 2007

2nd Generation Quad-Core – 100 GFLOPS/Processor today

Advanced Next Generation Nehalem Architecture in 2008

High Density Platforms

Energy Efficient

Leading (Parallel) Software Tools

Performance Easy to Use


Industry’s First 45nm High-KIndustry’s First 45nm High-K

*Codenames*Codenames

DualDualCoreCore

QuadQuadCoreCore

MobileDesktopServer

100 GFLOPS/PROCESSOR100 GFLOPS/PROCESSOR


What about Amdahl’s LawWhat about Amdahl’s Law

nppp nS

11max )( S = (max.) speed-up

n = number of processors/cores/threadsp = parallel portion of the application

Gene Amdahl, "Validity of the Single Processor Approach to Achieving Large-Scale Computing Capabilities", AFIPS Conference Proceedings, (30), pp. 483-485, 1967.

p | n 1 2 4 8 16

0.00 1.00 1.00 1.00 1.00 1.00

0.05 1.00 1.03 1.04 1.05 1.05

0.10 1.00 1.05 1.08 1.10 1.10

0.15 1.00 1.08 1.13 1.15 1.16

0.20 1.00 1.11 1.18 1.21 1.23

0.25 1.00 1.14 1.23 1.28 1.31

0.30 1.00 1.18 1.29 1.36 1.39

0.35 1.00 1.21 1.36 1.44 1.49

0.40 1.00 1.25 1.43 1.54 1.60

0.45 1.00 1.29 1.51 1.65 1.73

0.50 1.00 1.33 1.60 1.78 1.88

0.55 1.00 1.38 1.70 1.93 2.06

0.60 1.00 1.43 1.82 2.11 2.29

0.65 1.00 1.48 1.95 2.32 2.56

0.70 1.00 1.54 2.11 2.58 2.91

0.75 1.00 1.60 2.29 2.91 3.37

0.80 1.00 1.67 2.50 3.33 4.00

0.85 1.00 1.74 2.76 3.90 4.92

0.90 1.00 1.82 3.08 4.71 6.40

0.95 1.00 1.90 3.48 5.93 9.14

1.00 1.00 2.00 4.00 8.00 16.00

Amdahl's Law for Parallelism

0.002.004.006.008.00

10.0012.0014.0016.0018.00

0.00

0.10

0.20

0.30

0.40

0.50

0.60

0.70

0.80

0.90

1.00

% parallel

Ma

x. S

pe

ed

up 1

2

4

8

16

Documents

Copyright © 2008 Intel Corporation. All rights reserved. FROM SINGLE- TO MANY-CORE COMPUTING 14 April 2008 Dr Herbert Cornelius Intel EMEA