Copyright Agarwal & Srivaths, 2007 Low-Power Design and Test, Lecture 8 Test Power

Copyright Agarwal & Srivaths, 2007 Low-Power Design and Test, Lecture 8

Test Power

2Copyright Agarwal & Srivaths, 2007 Low-Power Design and Test, Lecture 8

Outline

Test Power Problem: Background and Basics

Increasing Test Power Concerns

Aspects of Test Power Dissipation

DFT techniques targeting test power

Power-aware ATPG

Power Analysis Methodologies and Issues


Test Power Problem*

A circuit is designed for certain function. Its design must allow the power

consumption necessary to execute that function/application.

Power buses are laid out to carry the maximum current necessary for the

function.

Heat dissipation of package conforms to the average power consumption

during the intended function.

Manufacturing test mode can be/should be viewed as another mode of operation for the circuit with respect to power dissipation.

* See [Ravi-VDAT07,Ravi-ITC07] for more information on test power


Testing Differs from Function: Functional Mode

VLSI chip

system

Systeminputs

Systemoutputs

Functional inputs Functional outputs

Other chips


Testing Differs from Function: Test Mode

VLSI chipTest vectors:

Pre-generated and stored in

ATE

DUT output for comparison with expected response stored in ATE

Automatic Test Equipment (ATE):Control processor, vector memory,timing generators, power module,

response comparator

PowerClock

Packaged or unpackaged device under test (DUT)


Scan Testing

Combinational logic

Scan flip-

flops

Primary inputs

Primary outputs

Scan-inSI

Scan-outSO

Scan enableSE

DQ

DFFmux

SE

SD

DQ

SO1

0

Scan flip-flop

Sequential Circuit with ScanScan Flip-Flop

An example scan based test

During response shift-out, next pattern can be concurrently shifted in.

Shift-In Shift-OutCapture

• time


Testing Differs from Function: Functional Inputs vs. Test Vectors

Functional inputs:■ Functionally meaningful

signals■ Generated by circuitry

■ Restricted set of inputs

■ May have been optimized to reduce logic activity and power

Test vectors:■ Functionally irrelevant signals■ Generated by software to test

faults■ Can be random or

pseudorandom■ May be optimized to reduce

test time; can have high logic activity

■ May use testability logic for test application


Terminology*

Design-for-test (DFT): Modifications to the circuit for facilitating test. e.g.

scan flip-flop insertion

Automatic Test Pattern Generation (ATPG): Process of automatically

generating test patterns that can be applied to the chip■ Pattern generation happens on the gate-level netlist of the circuit

assuming a certain set of eventual defects/faults

Fault Models: Abstraction of potential defects to ease the task of ATPG■ E.g., stuck-at faults, transition faults

Compression: Technology for reduced test data volume/test application

time. Compressed patterns are stored on the tester, while on-chip de-

compression logic ensures that uncompressed patterns can be applied.

* See [Agarwal00] for more information on basics/advanced concepts in testing


Outline





Power-aware ATPG




■ Conflicting requirements of test data volume reduction practices

● Compression and compaction techniques elevate circuit switching

■ Tests are run at various stress conditions (voltage and temperature)

■ Redundant switching in circuit logic during scan shift

0

2

4

6

8

10

12

Raw Compacted CompressedN

orm

aliz

ed P

ow

er

3.5X

4.1X

Pattern type

Example circuit in 65nm technology

Test power is several times higher than normal mode power ■ Conflicting requirements of test time reduction practices

● Increasing test concurrency Test multiple modules simultaneously

● Increasing frequency of scan shift


Peak test power can affect circuit yield■ Example: Ti/Siemens 130nm ASIC design with 1M gates + 300kbits SRAM,

150 MHz clock frequency [Saxena-ITC03]■ Some transition fault patterns passed only on or near 1.55V■ Failure identified to be due to significant IR drop, caused by increased

switching in the launch to capture time window.■ Example: Power supply voltage drops during scan shift operations

[Matsushita-ITC03]


Test power is a determining factor for packaging and power grid design

Power dissipation constraints can also come from a tester standpoint■ Power availability during wafer

testing smaller [Intel-ITC04]

Am

per

es0

50

100

150

200

0.25μm 0.18μm 0.13μm 0.09μmAllowable current during test of unpackaged die

Allowable current during normal o/p of packagedchip

(source: Intel)


Outline





Power-aware ATPG



Aspects of Test Power

Average vs peak power■ Average Power Dissipation = (Total Energy Consumed / Total time)

● Relevant for reliability issues – temperature effects, EM■ Peak Power Dissipation

● Max power consumed in a cycle, Instantaneous peak power● Tester implications, packaging implications for field test, IR drop issues can

have impact on power grid design

Dynamic power vs Static power■ Depends on the PTV corner

At burn-in corner, static power can dominate with low frequency circuit operation!

■ Leakage power implications An increasingly major component of static power, that is dependent on

the state of the circuit■ Glitch power neglected

Arise due to non-zero cell and interconnect delays, imbalance in logic paths

■ As good as your power analysis flow!


Aspects of Test Power

Shift power versus Capture power■ Low Frequency Shifts: Average Shift power may be a concern■ High Frequency Shifts: Peak and Average power becomes a concern■ Capture power: Fast capture pulses in transition patterns cause Peak power (IR drop) issues

Structural Breakdown: Memories, Scan FF vs Combinational logic

■ Memory power consumption can be dominant ■ Must be aware of this while scheduling test of

multiple memories ■ Scan FF vs Combinational logic

● 78% of the energy dissipated in the combinational logic [Wunderlich99]

● 29%-53% of power dissipation seen in combinational logic for industrial designs

Power Analysis Times and Logic Simulation Dump Sizes!■ Ideally, you need the toggle activity in every test related cycle■ Size of VCD dump file (for the TI/Siemens Design) to infer toggle activity in the launch-to-capture time

window is 2M !

0

20

40

60

80

100

Ckt1 Ckt2 Ckt3 Ckt4

Seq comb

PE

RC

EN

TA

GE

PO

WE

R


Outline





Power-aware ATPG



DFT for test power reduction (1) –Blocking Circuitry

Basic Concept: Prevent switching in the comb. logic during shift■ Use of blocking circuitry (NOR, MUX) at Q outputs connected

to combinational logic● Can manifest as part of special scan cells

■ Use of First Level Power Supply Gating [Bhunia05]

+ Structured Tech (minimal ATPG impact)- Normal Mode Overheads

EN

SD

D QSQ

ScanFF

EN

SD

QD

EN

SD

QD

EN

SD

QD

Combinational Circuit

ScanEn

ScanIn ScanOutSQ SQ SQ

Enhanced Scan CellsUsage in an Sequential Circuit

Q

Q


First Level Power Supply Gating [Bhunia05]

(a) Simplest Version: GND Gating

(b) GND Gating with Floating output fixup


DFT for test power reduction (2) – Scan Segmentation [Whetsel-ITC00]

+ Does not add delay to the normal path + No significant change to ATPG + Test application time (TAT) impact negligible - Scan segment control implementation needed, routing implications - Delay test considerations (LOC ok)

Basic Concept: Divide a scan chain into multiple segments, and shift them one at at time, while the other segments have their clocks gated.■ Clock gating and by pass multiplexors added to provide acccess

SI1 SO1

SI2 SO2

SIn SOn

Gated_clk1 Gated_clk2

CHAIN1, SEGMENT 1

CHAIN2, SEGMENT 1

CHAINn, SEGMENT 1

CHAIN1, SEGMENT 2

CHAIN2, SEGMENT 2

CHAINn, SEGMENT 2

SC

AN

INS

SC

AN

OU

TS

SEGMENT1 SEGMENT2


DFT for test power reduction (3) – Scan chain disable [Sankaralingam02]

If a scan chain is disabled,■ It is not clocked, scan chain does not shift/capture

Issue: Deciding on the granularity of scan chain disabling■ Inter-core (coarse-grained) versus Intra-core (fine-grained)

Basic Concept: Operate one scan chain at a time (differs from scan segmentation (how?)


Example: Scan Chain Disable in CELL processor [IBM-ITC06]

CELL Processor SPE■ Each SPE has

● 150k latches● 24 scan chains in LBIST

mode■ Thold signal: When active, it

will stop the clock to the latch element


Something to think about ….

Can you think of DFT options

that can help reduce test power?

What trade-offs will you usually

worry about?


Outline





Power-aware ATPG



Power-aware ATPG: Significance of Care Bits

Test patterns consist of care bits and don’t care bits■ E.g., a pattern (0XXX1XX) has 5 don’t care bits and 2 care bits

The way the care bits are populated will affect ATPG quality and also have an impact on power■ For e. g., Random Fill (randomly filling care bits) may help in fortuitous detection of faults,

but at higher power consumption costs.

Fra

cti

on

of

care

bit

s p

rese

nt

Percentage of Patterns ATPG pattern # (as APTG progresses)

Fra

cti

on

of

care

bit

s p

rese

nt

[source: Butler-ITC04]


Power-aware ATPG: Fill Techniques Different kinds of fill techniques can be used

■ Random fill: Fill in randomly■ Zero fill: Fill in don’t care bits with ‘0’■ One fill: Fill in don’t care bits with ‘1’■ Adjacent fill: Fill in don’t care bits with the value of the nearest care bit. (Example: 0XXX1XX will be

0000111)

Module D: 600k gates, 8 scan chains, scan chain length 2970

Module M: 600k gates, 8 scan chains, scan chain length 3271

Fill adjacent performs better than other heuristics along various dimensions [Butler-ITC04].

Fraction of cells switching in 3 of the first 1000 patterns during launch-to-capture cycle

Fraction of cells switching in 11 from all patterns during launch-to-capture cycle


Power-aware ATPG: Fill Techniques

Earlier Example: IR drop issue with TI/Siemens ASIC■ Transition pattern caused increased switching during launch-to-capture time

window

Increasing No. of0s placed

in “non-essential”Scan cells

Source: [Saxena-ITC03]


Inadequacy of Existing Low-Power ATPG Techniques [Ravi-ICCAD07]

10.2

10.3

10.4

10.5

10.6

10.7

Random Fill Adjacent Fill Zero Fill

319

320

321

322

323

324

325

Design A Design B

Des

ign

AP

ow

er (

mW

)

Desig

n B

Po

wer (m

W)

0.9%

Random Fill 0-Fill1-Fill Adj-Fill

Random Fill 0-Fill 1-fill Adj-Fill

0

5

10

15

20D

ynam

ic P

ow

er(m

illiW

atts

)

12%

First 5 patterns Last 5 patterns

Ineffectiveness of fill techniques for compressed and compacted patterns■ Compaction increases bit

utilization in a pattern for testing more faults

■ Compression reduces control over don’t care bits due to requirement for driving multiple scan chains Variation of Power with Fill Techniques

for Two Designs Supporting Compression

Variation of Power with fill techniques for compacted patterns for an example module from a TI design


Low Power ATPG Using Activity Threshold Controls [Ravi-ICCAD07]

Goals:■ To come up with low power ATPG techniques which are better than fill techniques■ No modification to ATPG tool should be required■ Benefit the generation of low power patterns even in compressed and compacted

scenarios

0

1

2

3

4

5

6

7

8

9

10

0.44 0.54 0.64 0.74 0.84 0.94

Normalized Toggles

Num

ber

of P

atte

rns

Random Fill

Adjacent Fill

PeakToggle

0

1

2

3

4

5

6

7

8

9

10

0.44 0.54 0.64 0.74 0.84 0.94

Normalized Toggles

Num

ber

of P

atte

rns

Random Fill

Adjacent Fill

80% of Peak

Toggle Distribution usingFill Techniques for an Example

Circuit

Reduced Activity Toggle Distribution for an Example Circuit Using the

Proposed Framework


General Observations

Power constraints are simple mathematical computations. Example: Thresholded transition count for a scan out operation

Power constraints can be encapsulated as a circuit themselves (aka Power Constraint Circuits or PCC)

Force ATPG tool to generate patterns on a circuit that includes target circuit+PCC

SF1

SF2

SF3

SFN

+

+

+

+<=

τ

transitioncount

adder tree

tc_out

Target Circuit

INPUTS

OUTPUTS

PowerConstraint

Circuit

MonitoredSignals

POWERTHRESHOLD

Meet Constraint (Y/N)? [Constrained as Y for ATPG tool]

POWER CONSTRAINT CIRCUIT

ENHANCED NETLIST FOR ATPG


Low Power ATPG Methodology

Exploits the capabilities of

the power constraint circuit

(PCC) to perform both

pattern filtering and pattern

generation

Target Circuit

Generate Power Constraint Circuit (PCC) using a partitioned

and LUT based architecture

Integrate with Target Circuit

Enhanced netlist

Perform unconstrained ATPG with

PCC logic no-faulted

TestPatterns

Apply constraint checks using ATPG tool during

fault simulation

Identify faults not detected by the good

patterns

GoodPatterns

Discardedviolatingpatterns

Perform constrained ATPG to generate power-

constrained patterns

Power-constrained

patterns

1

2

3

4

5

6

List ofMonitored

Signals

ActivityThreshold

PCC PCC I/O Constraints


Outline





Power-aware ATPG



Background: Status of Test Power Analysis Flows

Several power estimation

choices available for

functional use cases

Gaps in test power

analysis flows■ RTL option not

available yet■ Architecture-level

test power calculators way off

Current Status:■ Gate-level power

estimators remain the best bet.

Architecture Level

RTL

Gate-Level

EstimationTime

AccuracyGap

Power Estimation options

Usability for Test Power Estimation

Yes

Yes

No (at present)


Gate-level Test Power Estimation Flow (Conventional)

Conventional flow adopted to perform gate-level test power estimation is simulation-based■ Four main steps as shown in the

figure■ Step 3 (dump format conversion)

is optional For average test power consumption,

shift power due to a scanout operation is calculated■ The time interval of interest can

be specified as an input in Steps 1/2/3

Estimation is performed at various PVT corners

Challenges for multi-million gate SoCs:■ Time-consuming■ Dump sizes can be very large

Test Pattern Generation

Simulation

Dump Format Conversion

Gate-LevelPower Estimator

Gate-Level Netlist

TDL

Power Report

Step 1

Step 2

Step 3

Step 4


Summary

Test power consumption is a very important aspect of chip design cycle

Four facets of test power consumption■ Test preparation/planning: Understanding the requirements■ Power-aware DFT■ Low-Power ATPG■ Test Power Analysis

What we did not cover today?■ Test implications of power management circuitry


References

Books on Testing■ [Agarwal00] Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits by Bushnell and

Agrawal, Springer, 2000

Survey Papers/Articles■ [Ravi-VDAT07] S. Ravi, “Addressing Test Power Issues in Digitial CMOS Design”, to appear in Proc. VLSI Design and Test

Symposium (VDAT), 2007.

■ [Ravi-ITC07] S. Ravi, “Power-aware Testing: Challenges and Solutions”, (invited lecture series), to appear in Proc. International Test Conference (ITC), 2007.

■ [Jackson-07] T. Jackson, “Design-with-test for low-power devices”, EE Times-Asia, Jan 2007.■ [Butler-ITC04] K. M. Butler, J. Saxena, T. Fryars, G. Hetherington, A. Jain, and J. Lewis, “Minimizing Power Consumption

in Scan Testing: Pattern Generation and DFT Techniques”, Proc. International Test Conference, pp. 355-364, 2004.

DFT■ [Wunderlich99] S. Gerstendorfer and H. –J Wunderlich, "Minimized power consumption for scan-based BIST," Proc.

International Test Conference, pp.77-84, 1999.■ [Whetsel-ITC00] L. Whetsel, Adapting scan architectures for low power operation, Proc. International Test Conference,

pp. 863-872, 2000.■ [IBM-ITC06] C. Zoellin, H. -J Wunderlich, N. Maeding and J. Leenstraa, “BIST Power Reduction Using Scan-Chain Disable

in the Cell Processor,” Proc. International Test Conference, 2006.■ [Bhunia05] S. Bhunia, H. Mahmoodi, D. Ghosh, S. Mukhopadhyay, and K. Roy, “Low Power Scan Design Using First Level

Supply Gating”, IEEE Trans. onVLSI Systems, March 2005.■ [Sankaralingam02] R. Sankaralingam and N. Touba, “Reducing Test Power During Test Using Programmable Scan Chain

Disable”, Proc. DELTA, pp. 159-166, 2002.■ [Yoshida-ITC03]T. Yoshida and M. Watati, "A new approach for low-power scan testing," Proc. International Test

Conference, pp. 480- 487, 2003.


References

Low-Power ATPG■ [Saxena-ITC03] J. Saxena et al, “A Case Study of IR-Drop in Structured At-Speed Testing”, Proc.

International Test Conference, pp. 1098-1104, 2003. ■ [Ravi-ICCAD07] S. Ravi, V. Devanathan, and R. Parekhji, “Methodology for Low Power Test Pattern

Generation Using Activity Threshold Control Logic”, to appear in Proc. International Conference on Computer-Aided Design (ICCAD), 2007.

Misc■ [Intel-ITC04] S. Kundu, T. M. Mak, and R. Galivanche, "Trends in manufacturing test methods and their

implications," Proc. International Test Conference, pp. 679- 687, Oct. 2004.

Documents

Copyright Agarwal & Srivaths, 2007 Low-Power Design and Test, Lecture 8 Test Power