CpE 252

Computer Organization & Design

Computer Arithmetic

Dr. T. Eldos 2

Computer Arithmetic

Introduction

Addition and Subtraction

Multiplication Algorithms

Division Algorithms

Floating-Point Algorithms

Decimal Arithmetic Unit

Decimal Arithmetic Operations

Dr. T. Eldos 3

Introduction

Solving problems require data manipulation through arithmetic

operations

Four basic arithmetic operations:

Addition

Subtraction

Multiplication

Division

Other functions can be formulated from those, like floating-point

Arithmetic processor is the part of the processor that performs the

arithmetic operations

In this chapter, we will study few types; fixed-point signed and

unsigned binary, floating-point binary and BCD formats

Dr. T. Eldos 4

Addition & Subtraction

Three ways to represent negative fixed-point numbers:

Signed magnitude

Signed 1’s complement

Signed 2’s complement

Addition and Subtraction with signed magnitude

Addition of Signed-Magnitude Numbers

Operation Add Magnitudes Subtract Magnitudes

A < B A = B A > B

(+A) + (+B) +(A + B)

(+A) + (- B) - (B - A) +(A - B) +(A - B)

(- A) + (+B) +(B - A) +(A - B) - (A - B)

(- A) + (- B) - (A + B)

Subtraction of Signed-Magnitude Numbers

Operation Add Magnitudes Subtract Magnitudes

A < B A = B A > B

(+A) - (+B) - (B - A) +(A - B) +(A - B)

(+A) - (- B) +(A + B)

(- A) - (+B) - (A + B)

(- A) - (- B) + (B - A) +(A - B) - (A - B)

Dr. T. Eldos 5

Add/Subtract Signed-Magnitude Numbers

Hardware Implementation requires

Two registers to hold the arguments A and B

An adder to produce A+B

Two subtractors to produce A-B and B-A

Comparator to check if AB to take proper action

Flags comparator (XOR) to decide if the numbers are of opposite or

same sign

Clearly

Using other formats, like 2’s complement signed format, is more

efficient as it requires only a single adder to perform add and subtract

Only one zero is available as opposed to +0 and -0

Dr. T. Eldos 6

2’s Complement Signed Format

Need Two registers to hold data

AC to hold Augend for addition, Minuend for subtraction

B to hold Addend for addition, Subtrahend for subtraction

Complementer

Produce 1’s complement to perform subtraction by addition

Adder

Addition: AC AC + B , V Overflow

Subtraction: AC AC+B’+1 , V Overflow

AC

B

V Add/SubAdder

Dr. T. Eldos 7

Multiplication Hardware

Signed-Magnitude numbers are multiplied by successive shift and

add operations

Least significant bit of the multiplier is tested, and if one the

multiplicand is added and shifted left, else only shifted left

Multiplier is then shifted right and the process is repeated

Sequence Counter (SC) is initially equal to the number of bits in the

multiplier

A

B

E

Add/SubAdder

Bs

As

0

Qs

Q Rightmost Bit

SC

Dr. T. Eldos 8

Multiplication Algorithm

B Multiplicand

Q Multiplier

Qn ?

SC ?

EA A+B

Shr EAQ, SC SC-1

=0

START

STOP

As Qs BsQs Qs Bs

A 0, E0, SCn-1

=1

Product: AQ

=0

Dr. T. Eldos 9

Booth Multiplication Algorithm

Booth algorithm multiplies two numbers in the 2’s complement

signed formats

It operates on the facts that

String of 0’s in the multiplier require shifting only (no addition)

String of 1’s in the multiplier bits k through m can be treated as 2k+1-2m

The algorithms works for both –ve and +ve numbers

Example

Multiplicand M and Multiplier 001110 (+14); string of 1’s from 3 to 1

Multiplication Mx14 can be done as Mx(24-21) = Mx24 - Mx21

Mx21 and Mx24 are M shifted left once and 4 times, respectively

Multiplicand M and Multiplier 10010 (-14)

Multiplication Mx(-14) can be done as Mx(-24+ 22-21) = -Mx24 + Mx22 -

Mx21

Mx21 , Mx22 and Mx24 are M shifted left once, twice and 4 times,

respectively

Add up; Mx(24-21)+Mx(-24+ 22-21) =Mx(24-21 -24+ 22-21)=M

Dr. T. Eldos 10

Booth Rules and Hardware

Multiplicand is either subtracted from the partial product, added to

the partial product or left unchanged

Rules:

Multiplicand subtracted from partial product upon encountering first

least significant 1 in a string of 1’s in the multiplier

Multiplicand is added to the partial product upon encountering the first 0

in a string of 0’s in the multiplies (provided there was a previous 1)

Partial product does not change when multiplier bit is identical to the

previous one

A

B

Add/SubAdder

Qn

Q

SC

Qn+1

Dr. T. Eldos 11

Booth Algorithm

B Multiplicand

Q Multiplier

QnQn+1?

SC ?

A A+B

shr A & Q

SC SC-1

=0

START

STOP

A 0, Qn+1 0

SC n

11 00

A A+B’+1

0110

Dr. T. Eldos 12

Booth Algorithm Example

B = 10111, B’+1 = 01001, Q = 10011

QnQn+1 A Q Qn+1 SC

Initial 00000 10011 0 101

1 0 Sub B 01001

01001

ashr 00100 11001 1 100

1 1 ashr 00010 01100 1 011

0 1 Add B 10111

11001

ashr 11100 10110 0 010

0 0 ashr 11110 01011 0 001

1 0 Sub B 01001

00111

ashr 00011 10101 1 000

Dr. T. Eldos 13

Array Multiplier

Multiplication by reparative addition takes time proportional to the

number of bits in the multiplier

An alternative is to use combinational logic to implement the input-

output relationship

This way, the time is only due to the propagation delay of the gates,

which is relatively small, but need large number of gates

A j-bit multiplier & k-bit multiplicand requires j x k 2-input AND gates

and (j-1) x k Adders to produce (j+k) bit products

Dr. T. Eldos 14

Array Multiplier Hardware

B0

HA

C S

C

0

C1

HA

C S

C3 C2

B1A1 A0

B1 B0A1 A0_______

A0B1 A0B0A1B1 A1B0

__________________

C3 C2 C1 C0

Dr. T. Eldos 15

3-bit by 4-bit Array Multiplier

C

0

C1C3 C2C4C6 C5

4-bit Adder

B3

A2

B2 B1 B0 4-bit Adder

B3

A1

B2 B1 B0

B3

A0

B2 B1 B0

0

Dr. T. Eldos 16

Division Algorithms

Paper and Pencil: successive compare, shift and subtract

Binary division is simpler than decimal one because the quotients

are either 0 or 1

On computers, instead of shifting the divisor to the right, the

dividend or partial remainder is shifted to the left, thus leaving the

two numbers in the required relative position

Hardware required is that used for multiplication

Dr. T. Eldos 17

Binary Division with Digital Hardware

Dividend A=01110, Divisor B=10001 and Divisor 2’s complement B’+1=01111

E A Q SC

Dividend 01110 00000 5

shl EAQ 0 11100 00000

add B’+1 01111

E=1 1 01011

set Qn = 1 1 01011 00001 4

shl EAQ 0 10110 00010

add B’+1 01111

E=1 1 00101

set Qn = 1 1 00101 00011 3

shl EAQ 0 01010 00110

add B’+1 01111

E=0, Leave Qn=0 0 11001 00110

add B 10001

Restore remainder 1 01010 2

shl EAQ 0 10100 01100

sdd B’+1 01111

E=1 1 00011

set Qn = 1 1 00110 11010 1

shl EAQ 0 00110 11010

sdd B’+1 01111

E=0, Leave Qn=0 0 10101 11010

sdd B 10001

Restore remainder 1 00110 11010 0

Dr. T. Eldos 18

Divide Overflow

Division may result in a quotient with an overflow,; quotient larger

than register size

This is critical when division is implemented in hardware, because

we have finite register length

Typically, a flag is set upon having such condition

In some computers, it is the programmer’s responsibility to check

then divide overflow flag after each divide, to call a subroutine for

corrective measure like data scaling

Older computers used to stop (divide stop)

Most computers provide traps (software interrupt) based on such

condition

Dr. T. Eldos 19

Hardware Algorithm

AQ Dividend

B Divisor

E ?

START

Qs As BsSC n-1

EA A+B’+1

1 0

EA A +B

DVF 1

EA A +B

DVF 0

AB AB

shl EAQ

E ?0 1

EA A+B’+1 A A+B’+1

E ?

0

1

EA A+B Qn 1

ABAB

Sc SC-1

SC ?

0

STOP

Division of Magnitude

Quotient in Q

Remainder in A

Divide

Overflow

Error

Dr. T. Eldos 20

Floating-Point Arithmetic Operations

Computer or/and their programming languages must have provision

for floating-point number arithmetic

FP computations can be done in hardware or software

Hardware FP is expensive but so much more efficient

To represent extremely small and large numbers both negative and

positive, three fields are used

s , sign bit

m, mantissa bits

e, exponent bits

Using binary system, radix r, then the value m x re

Dr. T. Eldos 21

Single & Double Precision Formats

Integers:

32-bit represents: -2147483648 to +2147483647

64-bit represents: -9223372036854775808 to +9223372036854775807

Fractions

32-bit: 1-bit sign, 8-bit exponent and 23-bit mantissa (actually 24)

64-bit: 1-bit sign, 11-bit exponent and 53-bit mantissa (actually 54)

In the past, computers used proprietary formats

Today’s computers use the IEEE single and double formats for compatibility

IEEE standard floating point formats have cases

A way to represent 0 and 1 exactly

A way to represent Infinity (plus and minus)

Dr. T. Eldos 22

Addition & Subtraction

The sum or difference of two FP numbers is computed through the

following steps:

Check for zeros

If one is zero, sum or difference is equal the other

Zeros can not be normalized, that’s why

Align mantissas

Add or subtract mantissa

Normalize the result

Dr. T. Eldos 23

Multiplication

The product of two FP numbers is computed through the following

steps:

Check for zeros

If one is zero, sum or difference is equal the other

Zeros can not be normalized, that’s why

Add exponents

Multiply the mantissa

Normalize the product

Dr. T. Eldos 24

Division

The product of two FP numbers is computed through the following

steps:

Check for zeros

If one is zero, sum or difference is equal the other

Zeros can not be normalized, that’s why

Initialize registers and evaluate the signs

Align the dividend

Subtract the exponents

Divide the mantissas

Dr. T. Eldos 25

Decimal Arithmetic Unit

Mostly, users use input/output devices with decimals formats

Internally, decimal numbers converted into binary for binary

calculation

Some computers employ extra logic to perform the computations in

BCD formats to reduce the burden of decimal-to-Binary conversion

Ordinary binary adders can be modified to support this kind of

computation

When sum of two digits (groups of 4 bits) is more than 1001, then an

invalid BCD is to be corrected, adding 6 will do that

The condition for correction is C=K+Z8Z4+Z8Z2

Dr. T. Eldos 26

BCD Adder

Binary Sum BCD Sum

K Z8 Z4 Z2 Z1 C S8 S4 S2 S1 Decimal

0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 1 0 0 0 0 1 1

0 0 0 1 0 0 0 0 1 0 2

0 0 0 1 1 0 0 0 1 1 3

0 0 1 0 0 0 0 1 0 0 4

0 0 1 0 1 0 0 1 0 1 5

0 0 1 1 0 0 0 1 1 0 6

0 0 1 1 1 0 0 1 1 1 7

0 1 0 0 0 0 1 0 0 0 8

0 1 0 0 1 0 1 0 0 1 9

0 1 0 1 0 1 0 0 0 0 10

0 1 0 1 1 1 0 0 0 1 11

0 1 1 0 0 1 0 0 1 0 12

0 1 1 0 1 1 0 0 1 1 13

0 1 1 1 0 1 0 1 0 0 14

0 1 1 1 1 1 0 1 0 1 15

1 0 0 0 0 1 0 1 1 0 16

1 0 0 0 1 1 0 1 1 1 17

1 0 0 1 0 1 1 0 0 0 18

1 0 0 1 1 1 1 0 0 1 19

Condition for adding corrective 6

C=K+Z8Z4+Z8Z2

Dr. T. Eldos 27

BCD Adder Hardware

S0S1S3 S2

4-bit Binary Adder

E Cin

Z8 Z4 Z2 Z1

Addend Augend

4-bit Binary Adder

Z8 Z4 Z2 Z1

0

Carry inCarry out

Sum

B0B1B3 B2 A0A1A3 A2

Dr. T. Eldos 28

Decimal Arithmetic Operations

Need to add and subtract BCD numbers

The BCD adder is used to subtract by adding the BCD 9’s

complement of the subtrahend

BCD 9‘s complement can be generated by:

Taking 1’s complement and adding 10 (1010)

Adding 6 (0110) and taking 1’s complement

We can use a MUX to pass either the BCD numbers or its 9’s

complement, or directly extract from the table

Dr. T. Eldos 29

Decimal Arithmetic Unit

S0S1S3 S2

BCD Adder

Z8 Z4 Z2 Z1

CinCout

B0B1B3 B2 A0A1A3 A2

BCD 9’s

Complementer

X8 X4 X2 X1

M

BCD 9’s Complement

B3 B2 B1 B0 X3 X2 X1 X0

0 0 0 0 1 0 0 1

0 0 0 1 1 0 0 0

0 0 1 0 0 1 1 1

0 0 1 1 0 1 1 0

0 1 0 0 0 1 0 1

0 1 0 1 0 1 0 0

0 1 1 0 0 0 1 1

0 1 1 1 0 0 1 0

1 0 0 0 0 0 0 1

1 0 0 1 0 0 0 0

1 0 1 0 x x x x

1 0 1 1 x x x x

1 1 0 0 x x x x

1 1 0 1 x x x x

1 1 1 0 x x x x

1 1 1 1 x x x x

Logic Expressions

X0=M’B0+MB’0X1=B1X2=M’B2+M(B’1B2+B1B’2)

X3=M’B3+MB’1B’2B’3

Dr. T. Eldos 30

Decimal Addition: Parallel Decimal Adder

Each BDC digit has its own hardware to perform addition

They all work at the same time

Delay is proportional to the number of stages because we have to

propagate the carry

Expensive, but fast

Cout BCD Adder Cin

X3 Y3

Cout BCD Adder Cin

X2 Y2

Cout BCD Adder Cin

X1 Y1

Cout BCD Adder Cin

X0 Y0

Z3 Z3 Z3 Z3

Dr. T. Eldos 31

Decimal Addition: Digit-Serial Bit-Parallel Adder

Digit based addition uses o1-digit adder

Passes digit one at a time and saves the carry for the next digit

processing

Less expensive than the parallel

Of course slower

Cout BCD Adder Cin

Addend Augend

Sum

X0 Y0

X1 Y1

X2 Y2

X3 Y3

Carry

Z0

Z1

Z2

Z3

Dr. T. Eldos 32

Decimal Addition: All-Serial Adder

Digits are added bit by bit

If most recent digits, BCD packet, the correction circuit adds 6

Fully serial and fully parallel schemes trade speed of completion and

cost of implementation, while the digit-serial sets somewhere in the

middle

S

1-bit Full

Adder

Cin Cout

Addend

Augend

Sum

X0X1X2

Y0Y1Y2CorrectionCarry

Z0Z1Z2