CPLD Development/Programmer Kit User Guideww1.microchip.com/downloads/en/DeviceDoc/doc3300.pdf · Programmer Kit The Atmel CPLD Development/Programmer Kit ... ATF1502AS/ASL ATF1508AS/ASL

CPLD Development/Programmer Kit..............................................................................................

User Guide

-2 CPLD Development/Programmer Kit User Guide

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CPLD Development/Programmer K

Table of Contents

Section 1Introduction ........................................................................................... 1-1

1.1 CPLD Development/Programmer Kit ........................................................1-11.3 Kit Features...............................................................................................1-2

1.3.1 CPLD Development/Programmer Board ............................................1-2

1.3.2 Logic Doubling CPLDs .......................................................................1-2

1.3.3 CPLD ISP Download Cable ................................................................1-2

1.3.4 PLD Software CD-ROM......................................................................1-2

1.3.5 Atmel CD-ROM Data Books ...............................................................1-3

1.4 Device Support .........................................................................................1-31.5 System Requirements...............................................................................1-31.7 Technical Support .....................................................................................1-4

1.8.1 ProChip Designer ...............................................................................1-5

1.8.2 Atmel-WinCUPL .................................................................................1-5

1.8.3 ATMISP ..............................................................................................1-5

1.8.4 POF2JED ...........................................................................................1-5

Section 2Hardware Description ........................................................................... 2-1

2.1 Atmel CPLD Development/Programmer Board.........................................2-1

2.1.1 8-segment Display LEDs ....................................................................2-2

2.1.2 Push-button Switches.........................................................................2-6

2.1.3 Clock Select Jumper...........................................................................2-6

2.1.4 VCC Select Jumper ............................................................................2-7

2.1.5 JTAG Port Header ..............................................................................2-7

2.1.6 Power Connectors ..............................................................................2-8

2.2.1 Expansion Terminal Holes..................................................................2-9

2.3 Atmel CPLD ISP Cable .............................................................................2-9

Section 3CPLD Design Flow Tutorial .................................................................. 3-1

3.1 Overview ...................................................................................................3-13.2 Create a Project Using the “New Project Wizard” .....................................3-13.3 Add a Design File......................................................................................3-6

Section 4Schematic Diagrams............................................................................. 4-1

it User Guide i

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Table of Contents

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CPLD Development/Programmer Kit User Guide

Section 1

Introduction

1.1 CPLDDevelopment/Programmer Kit

The Atmel CPLD Development/Programmer Kit (P/N: ATF15xx-DK2) is a completedevelopment system and an In-System Programming (ISP) programmer for theATF15xx family of industry-standard pin-compatible Complex Programmable LogicDevices (CPLDs) with Logic Doubling™ features. This kit provides designers a veryquick and easy way to develop, prototype and evaluate new designs with an ATF15xxCPLD. With the availability of the different Socket Adapter Boards to support all thepackage types offered in the ATF15xx family of ISP CPLDs, this CPLD Develop-ment/Programmer Board can be used as an ISP programmer to program the ATF15xxISP CPLDs in all the available package types through the industry-standard JTAG inter-face (IEEE 1149.1a-1993).

Figure 1-1. Contents of the ATF15xx-DK2

CPLD Development/Programmer Kit User Guide 1-1

Rev. 3300A–PLD–08/02

Introduction

1.2 Kit Contents � CPLD Development/Programmer Board

� 84-lead PLCC Socket Adapter Board (P/N: ATF15xx-SAJ84)(1)

� Atmel CPLD ISP Download Cable

� Atmel PLD Software CD-ROM (includes ProChip Designer™, Atmel-WinCUPL™ andother EPLD software)

� Atmel CD-ROM Data Books

� One ATF1508AS 5V 84-lead PLCC Sample Device

� One ATF1508ASVL 3.3V, low-power, 84-lead PLCC Sample Device

� Atmel CPLD Development/Programmer Kit User Guide

Note: 1. Only the 84-lead PLCC Socket Adapter Board is included in this kit. Other SocketAdapter Boards are sold separately. Please refer to Section 1.6 for ordering informa-tion of the Socket Adapter Boards.

1.3 Kit Features

1.3.1 CPLD Development/Programmer Board

� 10-lead JTAG-ISP Port

� Regulated Power Supply Circuitry for 9V DC Power Source

� 5V or 3.3V VCC Operation

� 84-lead PLCC Socket Adapter Board

� Socket Adapter Board Headers

� Expansion Terminal Holes for all Input and I/O pins of the ATF15xx Device

� 2 MHz Crystal Oscillator

� Eight 8-segment LED Displays

� Global Clear and Output Enable Push Button Switches

1.3.2 Logic DoublingCPLDs

� ATF1508AS-15JC84, 5V 128-Macrocell ISP CPLD with Logic Doubling Architecture

� ATF1508ASVL-20JC84, 3.3V Low-power 128-Macrocell ISP CPLD with LogicDoubling Architecture

1.3.3 CPLD ISP DownloadCable

� 5V/3.3V ISP Download Cable for PC Parallel Printer (LPT) Port

1.3.4 PLD SoftwareCD-ROM

� Free Atmel-WinCUPL™ Design Software

� 30-day Trial Version of Atmel ProChip Designer™ Software

� Full Licensed Version of Atmel ProChip Designer Software (permanent licenserequired)

� Atmel CPLD ISP Software (ATMISP)

� POF2JED Conversion Utility

� Logic Doubling Support and Documentation

1-2 CPLD Development/Programmer Kit User Guide

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Introduction

1.3.5 Atmel CD-ROMData Books

� Data Sheets

� Application Notes

� Manuals and User Guides

1.4 Device Support The Atmel CPLD Development/Programmer Board supports the following devices in allspeed grades and packages:

1.5 SystemRequirements

The minimum hardware and software requirements to program an ATF15xx ISP CPLDon the CPLD Development/Programmer Board through the Atmel CPLD ISP Software(ATMISP) V4.0 or later are:

� Pentium® or Pentium-compatible microprocessor based computer

� Windows® 98, Windows NT® 4.0, Windows ME, or Windows 2000

� 16-MByte RAM

� 10-MByte free hard disk space

� Windows-supported mouse

� Available parallel printer (LPT) port

� 9V DC power supply with 500 mA of supply current

� SVGA monitor (800 x 600 resolution)

ATF1502AS/ASL ATF1508AS/ASL

ATF1502ASV ATF1508ASV/ASVL

ATF1502SE/SEL ATF1508SE/SEL

ATF1502AE/AEL ATF1508AE/AEL

ATF1504AS/ASL ATF1516SE/SEL (Future)

ATF1504ASV/ASVL ATF1516AE/AEL (Future)

ATF1504SE/SEL ATF1532AE/AEL (Future)

ATF1504AE/AEL


3300A–PLD–08/02

Introduction

1.6 OrderingInformation

1.7 TechnicalSupport

For technical support on any Atmel PLD related issues, please contact the Atmel PLDApplications Group at:

Hotline: 1-408-436-4333

Email: [email protected]

URL: www.atmel.com/atmel

Part Number Description

ATF15xx-DK2 Atmel CPLD Development/Programmer Kit

ATF15xx-SAA44 44-lead TQFP Socket Adapter Board

ATF15xx-SAJ44 44-lead PLCC Socket Adapter Board

ATF15xx-SAC49 49-lead BGA Socket Adapter Board




ATF15xx-SAQ100 100-lead PQFP Socket Adapter Board

ATF15xx-SACT100 100-lead BGA Socket Adapter Board



ATF15xx-SAC169 169-lead BGA Socket Adapter Board


ATF15xx-SACT256 256-lead BGA Socket Adapter Board


3300A–PLD–08/02

Introduction

1.8 References To help PLD designers use the different Atmel PLD software, documentation such asHelp Files, Tutorials, Application Notes/Briefs, and User Guides are available.

1.8.1 ProChip Designer

1.8.2 Atmel-WinCUPL

1.8.3 ATMISP

1.8.4 POF2JED

ProChip DesignerHelp Files

From the ProChip Designer main window, click on HELP and thenselect PROCHIP DESIGNER HELP.

Tutorials From the ProChip Designer main window, click on HELP and thenselect TUTORIALS.

Known Problems &Solutions

From the ProChip Designer main window, click on HELP and thenselect REVIEW KPS.

Help Files From the Atmel-WinCUPL main window, click on HELP and thenselect CONTENTS.

CUPL ProgrammersReference Guide

From the Atmel-WinCUPL main window, click on HELP and thenselect CUPL PROGRAMMERS REFERENCE.

Tutorial From the Atmel-WinCUPL main window, click on HELP, select ATMELINFO and then select TUTORIAL1.PDF.


From the Atmel-WinCUPL main window, click on HELP, select ATMELINFO and then select CUPL_BUG.PDF.

Help Files From the ATMISP main window, click on HELP and then select ISPHELP.

Tutorial From the ATMISP main window, click on HELP, and then selectATMISP TUTORIAL.


Using Windows Explorer, go to the directory where ATMISP isinstalled and open the README.TXT file through any ASCII texteditor.

ATF15xx ConversionApplication Brief

From the POF2JED main window, click on HELP and then selectCONVERSION OPTIONS.


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Introduction


3300A–PLD–08/02

Section 2

Hardware Description

2.1 Atmel CPLDDevelopment/ProgrammerBoard

The Atmel CPLD Development/Programmer Board, along with the Socket AdapterBoard as shown in Figure 2-1, contains many features that designers will find very use-ful when developing, prototyping, or evaluating their ATF15xx CPLD design. Featuressuch as push-button switches, 8-segment display LEDs, 2 MHz crystal oscillator,5V/3.3V VCC selector, JTAG-ISP port, and expansion terminal holes make this a veryversatile starter/development kit and an ISP programmer for the ATF15xx family ofJTAG-ISP CPLDs.

Figure 2-1. CPLD Development/Programmer Board with 84-lead PLCC Socket Adapter Board

8-segmentDisplay LEDs

Clock SelectJumper

84-pin PLCCSocket

JTAG PortHeader

ExpansionTerminal Holes

GOEPush-buttonSwitch

GCLRPush-buttonSwitch

VCC SelectJumper

2 MHz CrystalOscillator

Power Switch

Power LED

Power SupplyJack

Power SupplyHeader


Rev. 3300A–PLD–08/02


2.1.1 8-segment DisplayLEDs

The Atmel CPLD Development/Programmer Board contains eight 8-segment LEDs toallow the designer to observe the outputs of the ATF15xx. These eight LEDs are labeledDSP1 to DSP8 on the board. These eight display LEDs are common anode LEDs withthe common anode lines connected to VCC and the individual cathode lines connectedto the I/O pins of the ATF15xx CPLD on the CPLD Development/Programmer Board. Toturn on a particular segment of an LED, the corresponding ATF15xx I/O pin connectedto this LED segment must be in a logical-0 state. Hence, the outputs of the ATF15xxneed to be configured as active-low outputs in the design file.

Figure 2-2. 8-segment Display LED

Each segment of the display LED is hard-wired to one specific I/O pin of the ATF15xx.For the higher pin count devices (100-lead and larger), all eight segments of the eightLEDs are connected to the I/O pins of the ATF15xx. However, for the lower pin countdevices (84-lead and smaller), only a subset of the LED segments are connected to theATF15xx's I/O pins. Table 2-1 to Table 2-8 below show the connections of the LEDs tothe ATF15xx in all the different package types.

Dot

A

B

CE

FG

D

Table 2-1. Connections of LEDs to ATF15xx 44-lead PLCC

DSP/Sgt PLD Pin # DSP/Sgt PLD Pin # DSP/Sgt PLD Pin # DSP/Sgt PLD Pin #

1/A NC 3/A 28 5/A 6 7/A NC

1/B NC 3/B 26 5/B 4 7/B NC

1/C NC 3/C 24 5/C 5 7/C NC

1/D NC 3/D 25 5/D 8 7/D NC

1/E NC 3/E 27 5/E 11 7/E NC

1/F NC 3/F 29 5/F 9 7/F NC

1/G NC 3/G 31 5/G 12 7/G NC

1/DOT NC 3/DOT NC 5/DOT NC 7/DOT NC

2/A NC 4/A 36 6/A 18 8/A NC

2/B NC 4/B 33 6/B 16 8/B NC

2/C NC 4/C 34 6/C 14 8/C NC

2/D NC 4/D 40 6/D 17 8/D NC

2/E NC 4/E 37 6/E 19 8/E NC

2/F NC 4/F 39 6/F 20 8/F NC

2/G NC 4/G 41 6/G 21 8/G NC



3300A–PLD–08/02


Table 2-2. Connections of LEDs to ATF15xx 44-lead TQFP


1/A NC 3/A 21 5/A 44 7/A NC

1/B NC 3/B 19 5/B 42 7/B NC

1/C NC 3/C 18 5/C 43 7/C NC

1/D NC 3/D 20 5/D 2 7/D NC

1/E NC 3/E 22 5/E 5 7/E NC

1/F NC 3/F 23 5/F 3 7/F NC

1/G NC 3/G 25 5/G 6 7/G NC


2/A NC 4/A 30 6/A 12 8/A NC

2/B NC 4/B 27 6/B 10 8/B NC

2/C NC 4/C 28 6/C 8 8/C NC

2/D NC 4/D 34 6/D 11 8/D NC

2/E NC 4/E 31 6/E 13 8/E NC

2/F NC 4/F 33 6/F 14 8/F NC

2/G NC 4/G 35 6/G 15 8/G NC




1/A NC 3/A 47 5/A 5 7/A 25

1/B NC 3/B 45 5/B 4 7/B 24

1/C NC 3/C 44 5/C 7 7/C 27

1/D NC 3/D 46 5/D 9 7/D 29

1/E NC 3/E 49 5/E 13 7/E 32

1/F NC 3/F 51 5/F 8 7/F 28

1/G NC 3/G 52 5/G 10 7/G 30


2/A 37 4/A 56 6/A 17 8/A NC

2/B 33 4/B 54 6/B 14 8/B NC

2/C 36 4/C 55 6/C 15 8/C NC

2/D 39 4/D 61 6/D 18 8/D NC

2/E 41 4/E 59 6/E 22 8/E NC

2/F 40 4/F 60 6/F 20 8/F NC

2/G 42 4/G 64 6/G 23 8/G NC



3300A–PLD–08/02




1/A 49 3/A 67 5/A 6 7/A 25

1/B 46 3/B 64 5/B 4 7/B 22

1/C 48 3/C 65 5/C 5 7/C 24

1/D 50 3/D 68 5/D 8 7/D 27

1/E 52 3/E 70 5/E 10 7/E 29

1/F 51 3/F 69 5/F 9 7/F 28

1/G 54 3/G 73 5/G 11 7/G 30

1/DOT NC 3/DOT NC 5/DOT 45 7/DOT 41

2/A 57 4/A 76 6/A 16 8/A 34

2/B 55 4/B 74 6/B 12 8/B 31

2/C 56 4/C 75 6/C 15 8/C 33

2/D 58 4/D 77 6/D 17 8/D 35

2/E 61 4/E 80 6/E 20 8/E 37

2/F 60 4/F 79 6/F 18 8/F 36

2/G 63 4/G 81 6/G 21 8/G 39

2/DOT NC 4/DOT NC 6/DOT 44 8/DOT 40



1/A 47 3/A 67 5/A 96 7/A 20

1/B 52 3/B 64 5/B 93 7/B 17

1/C 48 3/C 63 5/C 94 7/C 19

1/D 46 3/D 65 5/D 97 7/D 21

1/E 44 3/E 68 5/E 99 7/E 25

1/F 45 3/F 69 5/F 98 7/F 23

1/G 42 3/G 71 5/G 100 7/G 29

1/DOT 49 3/DOT 61 5/DOT 92 7/DOT 22

2/A 54 4/A 80 6/A 12 8/A 32

2/B 41 4/B 76 6/B 9 8/B 30

2/C 40 4/C 78 6/C 8 8/C 31

2/D 56 4/D 84 6/D 10 8/D 33

2/E 58 4/E 81 6/E 13 8/E 36

2/F 57 4/F 83 6/F 14 8/F 35

2/G 60 4/G 85 6/G 16 8/G 37

2/DOT 55 4/DOT 75 6/DOT 6 8/DOT 28


3300A–PLD–08/02


Table 2-6. Connections of LEDs to ATF15xx 100-lead PQFP


1/A 48 3/A 69 5/A 98 7/A 22

1/B 50 3/B 66 5/B 95 7/B 19

1/C 49 3/C 65 5/C 96 7/C 21

1/D 47 3/D 67 5/D 99 7/D 23

1/E 44 3/E 70 5/E 3 7/E 27

1/F 46 3/F 71 5/F 100 7/F 25

1/G 43 3/G 73 5/G 4 7/G 39

1/DOT 51 3/DOT 63 5/DOT 94 7/DOT 24

2/A 56 4/A 82 6/A 14 8/A 37

2/B 54 4/B 78 6/B 11 8/B 38

2/C 42 4/C 81 6/C 10 8/C 35

2/D 58 4/D 86 6/D 12 8/D 33

2/E 60 4/E 83 6/E 15 8/E 31

2/F 59 4/F 85 6/F 16 8/F 34

2/G 62 4/G 87 6/G 18 8/G 32

2/DOT 52 4/DOT 77 6/DOT 8 8/DOT 30



1/A 79 3/A 100 5/A 134 7/A 25

1/B 78 3/B 98 5/B 137 7/B 22

1/C 74 3/C 99 5/C 136 7/C 23

1/D 80 3/D 101 5/D 133 7/D 26

1/E 82 3/E 106 5/E 138 7/E 28

1/F 81 3/F 102 5/F 132 7/F 27

1/G 83 3/G 107 5/G 131 7/G 29

1/DOT 77 3/DOT 97 5/DOT 139 7/DOT 21

2/A 88 4/A 118 6/A 9 8/A 41

2/B 86 4/B 119 6/B 7 8/B 31

2/C 87 4/C 117 6/C 6 8/C 32

2/D 91 4/D 114 6/D 8 8/D 38

2/E 93 4/E 112 6/E 10 8/E 37

2/F 92 4/F 116 6/F 11 8/F 40

2/G 94 4/G 113 6/G 15 8/G 39

2/DOT 84 4/DOT 111 6/DOT 5 8/DOT 30


3300A–PLD–08/02


2.1.2 Push-buttonSwitches

Two push-button switches are provided to allow the user to control the logic states of theOE1 and GCLR inputs of the ATF15xx. These two switches are labeled GOE and GCLRon the board. The GCLR push-button switch is a momentary Single-Pole Single-Throw(SPST) normally open switch while the GOE push-button switch is a snap-actingmomentary SPST normally open switch. As shown in the CPLD Development/Program-mer Board schematic in Figure 4-1, these two switches are normally open and theGCLR and GOE signals are pulled-up to VCC when they are not depressed. When theswitches are depressed, the GCLR and GOE signals are connected to GND.

The output of the GCLR switch is connected to the GCLR dedicated input pin of theATF15xx, and it is intended to be used as an active-low reset signal to reset the regis-ters in the ATF15xx. The output of the GOE switch is connected to the OE1 dedicatedinput pin of the ATF15xx. It is intended to be used as an active-high or active-low outputenable signal to control the enabling/disabling of the tri-state output buffers in theATF15xx. However, these two switches can also be used to generate general logic inputsignals to the GCLR and OE1 input pins of the ATF15xx.

2.1.3 Clock Select Jumper The Clock Select Jumper, labeled JPCLK, on the CPLD Development/ProgrammerBoard is a two-position jumper that allows the user to select which GCLK dedicatedinput pin (either GCLK1 or GCLK2) of the ATF15xx should be connected to the output ofthe 2 MHz crystal oscillator. In addition, the jumper can be removed to allow an externalclock source to be connected to GCLK1 and/or GCLK2 of the ATF15xx.

Table 2-9 shows the pin numbers for the GCLR, OE1, GCLK1 and GCLK2 dedicatedinput pins of the ATF15xx in all the available package types.

Table 2-8. Connections of LEDs to ATF15xx 160-lead PQFP


1/A 91 3/A 102 5/A 11 7/A 29

1/B 89 3/B 100 5/B 159 7/B 27

1/C 90 3/C 98 5/C 160 7/C 28

1/D 80 3/D 101 5/D 10 7/D 52

1/E 73 3/E 103 5/E 12 7/E 50

1/F 78 3/F 105 5/F 13 7/F 53

1/G 72 3/G 106 5/G 14 7/G 51

1/DOT 88 3/DOT 97 5/DOT 158 7/DOT 25

2/A 69 4/A 110 6/A 20 8/A 43

2/B 71 4/B 108 6/B 18 8/B 49

2/C 68 4/C 109 6/C 16 8/C 30

2/D 92 4/D 123 6/D 19 8/D 31

2/E 94 4/E 111 6/E 21 8/E 32

2/F 93 4/F 121 6/F 23 8/F 41

2/G 96 4/G 122 6/G 24 8/G 33

2/DOT 70 4/DOT 107 6/DOT 15 8/DOT 48


3300A–PLD–08/02


2.1.4 VCC Select Jumper The VCC Select Jumper, labeled VCC Select, on the CPLD Development/ProgrammerBoard is a two-position jumper that allows the users to select the VCC voltage level(either 3.3V or 5.0V) used by various components on the CPLD Development/Program-mer Board. This voltage generated by the on-board voltage regulation circuitry isapplied to the VCC input pins (both VccINT and VccIO) of the ATF15xx, the commonanode lines of the eight 8-segment LEDs, the VCC input of the 2 MHz crystal oscillator,the two push-button switches, and the VCC pin (Pin 4) of the 10-pin JTAG port headerlabeled JTAG.

Therefore, when a 3.3V device (ATF15xxASV/ASVL/AE/AEL) is used on this board, theVCC Select Jumper must be in the 3.3V position. On the other hand, when a 5V device(ATF15xxAS/ASL/SE/SEL) is used on this board, the VCC Select Jumper must be in the5.0V position. This is also true when the ATF15xx is being programmed through ISP onthis board.

2.1.5 JTAG Port Header The JTAG Port Header, labeled JTAG, on the CPLD Development/Programmer Boardis used to connect the ATF15xx's JTAG port pins (TCK, TDI, TMS and TDO) through theISP download cable to the parallel printer (LPT) port of a PC for ISP programming of theATF15xx. Table 2-10 shows the pin numbers for the four JTAG port pins of the ATF15xxin all the available package types.

The ISP algorithm is controlled by the ATMISP software, which runs on the PC. Thefour JTAG signals are generated by the LPT port and they are buffered by the ISPdownload cable before going into the ATF15xx on the CPLD Development/ProgrammerBoard. The pinout for the 10-pin JTAG Port Header on the CPLD Development/Pro-grammer Board is shown in Figure 2-3 and the dimensions of this 10-pin male JTAGheader are shown in Figure 2-4.

Table 2-9. Pin Numbers of GCLR, OE1, GCLK1 and GCLK2

Signal44-leadTQFP

44-leadPLCC

68-leadPLCC

84-leadPLCC

100-leadPQFP

100-leadTQFP

144-leadTQFP

160-leadPQFP

GCLR 39 1 1 1 91 89 127 141

OE1 38 44 68 84 90 88 126 140

GCLK1 37 43 67 83 89 87 125 139

GCLK2 40 2 2 2 92 90 128 142

Table 2-10. Pin Numbers of JTAG Port Signals

Signal44-leadTQFP

44-leadPLCC

68-leadPLCC

84-leadPLCC

100-leadPQFP

100-leadTQFP

144-leadTQFP

160-leadPQFP

TDI 1 7 12 14 6 4 4 9

TDO 32 38 57 71 75 73 104 112

TMS 7 13 19 23 17 15 20 22

TCK 26 32 50 62 64 62 89 99


3300A–PLD–08/02


Figure 2-3. Pinout Diagram of 10-pin JTAG Port Header (Top-view)

Figure 2-4. 10-pin Male Header Dimensions

The pinout of this 10-pin JTAG Port Header is compatible with the Altera® ByteBlaster™

and ByteBlasterMV™ cables. In addition, the ATMISP software allows users to chooseeither the Atmel CPLD ISP Cable or the ByteBlaster/ByteBlasterMV cable to implementISP.

2.1.6 Power Connectors The Atmel CPLD Development/Programmer Board contains two different types of powerconnectors, and either one can be used to connect to a 9V DC power source to powerthe board. The first power connector, labeled JPower, is a barrel power jack with a2.1 mm diameter post and it mates to a 2.1 mm (inner diameter) x 5.5 mm (outer diame-ter) female plug. The second power connector, labeled JP Power, is a 4-pin male 0.1"header with 0.025" square posts. The availability of these two types of power connec-tors allows the users to choose the type of power supply equipment to use for the CPLDDevelopment/Programmer Board.

1

3 4

5

8

9 10

6

TCK GND

TDO VCC

TMS

NCNC

NC

TDI GND

2

7

0.100 0.025 Sq.

0.235

Top View Side View

0.100

All dimensions are in inches


3300A–PLD–08/02


2.2 Socket AdapterBoard

Atmel CPLD Development/Programmer Socket Adapter Boards are circuit boards thatinterface with the Atmel CPLD Development/Programmer Board. They are used in con-junction with the CPLD Development/Programmer Board to evaluate/program Atmel ISPCPLDs in different package types. Currently, there are nine Socket Adapter Boardsavailable covering all the package types offered in the ATF15xx family of CPLDs. Theyinclude 44-lead PLCC, 44-lead TQFP, 68-lead PLCC, 84-lead PLCC, 100-lead TQFP,100-lead PQFP, 144-lead TQFP and 160-lead PQFP. New Socket Adapter Boards willbecome available when new packages are offered.

Each socket adapter board contains a socket for the Atmel ATF15xx device on the topside and male headers on the bottom side. The headers on the bottom side mate withthe female headers, labeled JPLEFT and JPRIGHT, on the CPLD Development/Pro-grammer Board. The eight 8-segment LEDs, push-button switches, JTAG port signals,crystal oscillator, VCC, and GND on the CPLD Development/Programmer Board are con-nected to the ATF15xx device on the Socket Adapter Board through these two rows ofconnectors.

2.2.1 Expansion TerminalHoles

Rows of expansion terminal holes suitable for 0.1" headers with 0.025" square posts areavailable on each of the Socket Adapter Boards to allow users to interface the ATF15xxto an external circuit board. All input and I/O pins except the four JTAG port pins of theATF15xx are routed to these expansion terminal holes, and the corresponding pin num-bers are marked next to the terminal holes. Please refer to the Socket Adapter Boardschematics in Section 4 for the pinouts of the expansion terminal holes.

On the bottom side of the Socket Adapter Boards, traces connecting the pairs of expan-sion terminal holes can be cut to isolate the LEDs, push-button switches and crystaloscillator from the ATF15xx on the Socket Adapter Board. This allows the users to gaincomplete control and access to all input and I/O pins of the ATF15xx.

2.3 Atmel CPLD ISPCable

The Atmel CPLD ISP Cable connects the parallel printer (LPT) port of the user’s PC tothe 10-pin JTAG header on the Atmel CPLD Development/Programmer Board or a cus-tom circuit board. This is shown in Figure 2-5. This ISP cable acts as a buffer to bufferthe JTAG signals between the PC's LPT port and the ATF15xx on the circuit board. Thecircuit schematic of the Atmel CPLD ISP Cable is shown in Figure 4-10 and Figure 4-11.The Power-On LED on the back of the 25-pin male connector housing indicates that thecable is connected properly. Make sure this LED is turned on before using the AtmelCPLD ISP Software (ATMISP).

This ISP cable consists of a 25-pin (DB25) male connector, which is connected to theLPT port of a PC. The 10-pin female plug connects to the 10-pin male JTAG header onthe ISP circuit board. The red color stripe on the ribbon cable indicates the orientation ofPin 1 of the female plug. The 10-pin male JTAG header on the CPLD Development/Pro-grammer Board is polarized to prevent users from inserting the female plug in the wrongorientation.

If the user is attempting to program low voltage (3.3V) devices, the user needs to useRev. 4 or later of the Atmel CPLD ISP Cable. This and later revisions will support boththe 3.3V and 5V ATF15xx ISP CPLDs. Earlier revisions of the cable only supported 5Vdevices.

When programming 3.3V devices, the VCC supplied to the ISP cable should also be3.3V. Similarly, the VCC supplied to the ISP cable should be 5.0V when programming5V devices.


3300A–PLD–08/02


Figure 2-5. Atmel ISP Cable Connection to ISP Hardware Board/Circuit Board

Figure 2-6 shows the pinout for the 10-pin Female header on the Atmel-ISP Cable. Thepinout on the 10-pin male header on the PC board (if used for ISP) must match thispinout.

Figure 2-6. Atmel ISP Download Cable 10-pin Female Header Pinout

Note: The user’s circuit board must supply VCC and GND to the Atmel CPLD ISPCable through the 10-pin male header (See Figure 2-3).


3300A–PLD–08/02

Section 3

CPLD Design Flow Tutorial

3.1 Overview This tutorial will guide the user through a complete design cycle for the Atmel ATF15xxCPLD with Logic Doubling architecture. It will go through each phase of the design cyclestep-by-step from design entry, logic synthesis, device fitting, in-system programming,and finally verifying the design on the Atmel CPLD Development/Programming Board.

Note: To complete this tutorial, ProChip Designer V4.0 or later and Atmel-ISP Soft-ware (ATMISP) V4.0 or later are required.

3.2 Create a ProjectUsing the “NewProject Wizard”

Before starting the design process, a Project File must be created within ProChipDesigner. ProChip Designer's New Project Wizard provides a very easy way to createa new Project File.

1. Click on the START .... PROGRAMS .... PROCHIP Icon to launch ProChipDesigner. Or double-click on the PROCHIP icon on the desktop.

(1) Click to launch ProChip Designer


Rev. 3300A–PLD–08/02


2. Click on PROJECT .... NEW or double-click on the NEW PROJECT shortcut but-ton to launch the New Project Wizard.

3. Click on the NEXT button to start the project file creation process.

4. Click on the BROWSE button to open the browser window.

5. Use C:\PROCHIP\DESIGNS\CUPL as the directory of the project.

6. Enter DEV_KIT.APJ as the project filename. The extension of a project file mustbe .APJ.

Note: The name and directory of the design project is specified in this window. Alldesign, simulation and other project files must be placed in this project direc-tory.

Click to create New Project

(2)

(3) Click Next to Start

(4) Click onBrowse

(5) Select theProject Directory

(6) Enter theProject Filename


3300A–PLD–08/02


7. Choose [ATF1508AS-10JC84] as the target device type for the project. Alsoreview the Filters that allow for selection of a specific Speed Grade or PackageType.

8. Select CUPL – ALTIUM as the software tool for this design flow.

With ProChip Designer V4.0 and later, the five possible design flows and their corre-sponding design entry types supported are listed in the table below:

Note: 1. Design flow require Mentor Graphics® Leonardo Spectrum software with Atmel CPLDsupport.

Design Flow Design Entry Type

CUPL – Altium™ CUPL design entry through Altium Protel™ 99SE

Verilog – Exemplar™(1) Verilog® design entry through Exemplar Leonardo Spectrum™

VHDL – Altium VHDL design entry through the Altium PeakFPGA

VHDL – Exemplar(1) VHDL design entry through Exemplar Leonardo Spectrum

Schematic – Altium Schematic design entry through Altium Protel 99SE

(7) Select theDevice Type

(8)Select theDesign Flow


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9. Select DONE WITH PARTS so that there will be only one device in this project.

On the other hand, users can select ADD MORE PARTS to include more parts to thecurrent Project Directory.

10. Click the FINISH button to finish the New Project Wizard and the project creationprocess.

This closes the New Project Wizard and opens the ProChip Designer window. TheSources in the project are shown in the Left window.

(9) Select Donewith Parts

(10)Click Finish to End New Project Wizard


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11. Click on the Device Icon [ATF1508AS-10JC84] to view the Design Flowwindow.

Project Sources Window Information Dialog Box

Message Window (11) Click on the Device Icon

Project File Window Design Flow Window


3300A–PLD–08/02


3.3 Add a DesignFile

Once the Project File is created, the next step is to add the design source file(s) into theuser’s project. For this tutorial, a single CUPL design file will be added into the project.

1. Click on the ADD/EDIT button from Source Manager to open the Source Man-ager Window. The user can view the Source Manager Help File by clicking onthe Help button within the Source Manager Window to view the description forthe different processes.

2. In the Source Manager Window, click on the ADD button to add a CUPL designfile to the project.

3. In the File Manager Window, select LOGIC_D8.PLD from theC:\PROCHIP\DESIGNS\CUPL directory as the source design file for this project.

This "LOGIC_D8.PLD" is a CUPL design that uses the eight 8-segment LED displaysand the 2 MHz oscillator on the Atmel CPLD Development/Programmer Board to gener-ate a scrolling message that displays the words "logic doubling" on the LEDs. The GOEpush-button switch is used to control the direction that the message scrolls in (left orright). The GCLR push-button switch is used to reset the counter registers. When theGCLR push-button switch is depressed, the message will stop scrolling. This CUPLdesign can be compiled using either the ProChip Designer or the Atmel-WinCUPLsoftware.

The first section of the LOGIC_D8.PLD as shown below pre-defines which segments ofthe LED should be asserted in order to display the desired letter or number. For exam-ple, to display the upper case letter "C", segments A, D, E, and F need to be set to low(active low) and the remaining segments need to be set to high.

Click Add/Editto Open Source

Manager Window

(1)

Select CUPLSource File

(3)

Click ADD toadd Design File(2)

$define Font0 'b'1000000 /* = ( _f_e_d_c_b_a ); 0 */$define Font1 'b'1111001 /* = ( _c_b ); 1 */

:$define FontA 'b'0001000 /* = (_g_f_e _c_b_a ); A */


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The next section of this CPLD design as shown below illustrates how to declare andassign pin numbers in the CUPL language to the input and output signals. The input andoutput pin assignments are assigned according to the connections between the CPLDand the eight 8-segment LED's as shown in the connection tables (Table 2-1 to Table 2-8) in Section 2.

Next, the buried signals for the counter and state machine are declared as PINNODE'sas shown below. The feedback and/or the foldback paths available in each macrocellimplement these buried signals. For the listing of the pinnode numbers, please refer tothe "ATF15xx Device Help" section of the ProChip Designer Help File.

After assigning the input, output and buried signals, the related signals (i.e. the LEDsegments and buried counter) are grouped together as shown below to make the designsource code more readable and manageable. In CUPL, the "Field" declaration can beused to group a specific set of signals.

Next, a 21-bit buried up-counter implemented using D-type Flip-flops is shown belowand it is used to divide the 2.0 MHz clock into a 0.954 Hz (2 MHz ÷ 221 = 0.954 Hz) sig-nal that can be used to display the text messages. The last bit of this counter is used asthe clock for the state machine that controls the display sequence of the messages onthe LEDs.

/* Inputs */pin 1 = GCLR; /* Global Clear input */pin 83 = MCLK; /* Global Clock input */pin 84 = GOE; /* GOE1 button used as direction control */

/* Outputs *//* DSP1 */pin 49 = LED1A; /* LED1 segment A */pin 46 = LED1B; /* LED1 segment B */pin 48 = LED1C; /* LED1 segment C */pin 50 = LED1D; /* LED1 segment D */pin 52 = LED1E; /* LED1 segment E */pin 51 = LED1F; /* LED1 segment F */pin 54 = LED1G; /* LED1 segment G */

pinnode [618,634,650,687]= [CA20..CA17];pinnode = [CA16..CA0];pinnode = [SM7..SM0];

Field DSP1 = [LED1G,LED1F,LED1E,LED1D,LED1C,LED1B,LED1A];Field DSP2 = [LED2G,LED2F,LED2E,LED2D,LED2C,LED2B,LED2A];

:Field CNT_A = [CA20..CA0];Field SM = [SM7..SM0];

CA0.d = !CA0;CA1.d = CA0 $ CA1;

:CA7.d = (CA6 & CA5 & CA4 & CA3 & CA2 & CA1 & CA0) $ CA7;

:CNT_A.ck = MCLK;CNT_A.ar = !GCLR;


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The next section of this PLD design is a state machine with 15 states to control the dis-play sequence of the text messages on the LEDs. The GOE push-button switch on theCPLD Development/Programmer Board controls the flow of this state machine. Whenthis switch is in the "up" position, the state machine will go from RESET to State-0 toState-1 to State-2 and so on until it reaches State-14 and then it will go back to State-0.On the other hand, if the GOE switch is in the "down" position, the state machine will goin the opposite direction (i.e. State-14 to State13 .. etc).

Finally, the last section of the PLD design will assign the appropriate letters or numbersto the eight 8-segment LEDs to be displayed during the different states of the statemachine. The user can easily change the letters/numbers to be displayed by changingthis section of the code to the appropriate pre-defined letters/numbers.

SM.ck = COUNTER_1;sequence SM{

present RESET next S0;

present S0if SM_DIR next S1;

if !SM_DIR next S14;:

present S14 if SM_DIR next S0; if !SM_DIR next S13;}

LED1 = FontBK & SM:[RESET] # FontBK & SM:[S0]

# FontLl & SM:[S1] # FontLo & SM:[S2] # FontLg & SM:[S3] # FontLi & SM:[S4] # FontLc & SM:[S5] # FontBK & SM:[S6] # FontLd & SM:[S7] # FontLo & SM:[S8] # FontLu & SM:[S9] # FontLb & SM:[S10] # FontLl & SM:[S11] # FontLi & SM:[S12] # FontLn & SM:[S13] # FontLg & SM:[S14];


3300A–PLD–08/02


3.4 Compile theCUPL Design

In this part of the tutorial, the CUPL design will be compiled through the Logic Synthesisprocess into a set of optimized/minimized logic equations.

1. Click on the CUPL – Design Ex. button in the Design Flow Window to open theLogic Synthesis Window.

2. Make sure all of the options in the Optimization section are unchecked.

3. Make sure the Minimization setting is set to Quick.

4. Click on the Compile button to start the CUPL compile process.

The user can click on the Set Defaults button and it will automatically specify the Syn-thesis tool in the Tool Text box.

If the user clicks on the CUPL Tab, it shows the various Synthesis options. Please referto the HELP file for further description.

(1) Open LogicSynthesis

(2) Make sure theseOptions are Not Checked

(3) Set toQuick

(4) Start theCompileProcess


3300A–PLD–08/02


3.5 Fit theSynthesizedDesign File

In Section 3.4, the Logic Synthesis portion of the CPLD Design Flow was completed. Onsuccessful compilation, the CUPL compiler tool produces a PLA output file (with exten-sion .pla). A PLA file contains the netlist of the optimized and minimized logic equations.It is now necessary to map this netlist into a specific Atmel PLD architecture using theAtmel Fitter.

1. The user can now proceed to the Device Fitter portion of the Design Flow byclicking on the Atmel Fitter button.

The user can either use the Default options or specify Fitter properties. ProChipDesigner will automatically select the PLA file associated to the current design projectand the tool type. In this example, since the target device is an ATF1508AS, thefit1508.exe device fitter will be selected.

The fitter creates the important JEDEC and FIT REPORT output files. They contain thedata for programming the Device (using In-System Programming or on a third partydevice programmer) and the pin assignments required for board layout respectively.

Please review the Global Device Parameters and Pin/Node Options as well. The HelpFiles also show the Device Pin_Node lists for each of the ATMEL CPLDs.

2. Make sure the JTAG box is checked. This enables the JTAG port for ISPprogramming.

3. Make sure the PIN FIT CONTROL setting is set to Keep. This will ensure that thepin assignments in the PLD file will be kept during the Place-and-Route process.

4. When all the fitter options are set, click on the Run Fitter button to fit the design.

(1) Open the AtmelFitter Window

(2)Check theJTAG box

(3)Set the Pin FitControl setting

to KEEP

(4) Start the Fitting Process


3300A–PLD–08/02


The Fitter Report (.FIT) File generated for this design is shown below.

The ATF15xx Family devices Logic Doubling features provide extra I/O connectivity andlogic reusability. Some of the Logic Doubling features available in the ATF15xx family ofCPLDs are:

� Bury either Register or Combinatorial signal while using the other for output

� Dual independent feedback allows multiple latch functions per macrocell

� 5 product terms per macrocell, expandable to 40 per macrocell with cascade logic,plus 15 more with foldback logic

� D/T/Latch configurable flip-flops plus transparent latches

� Global and/or per macrocell Output Enable

� Single level Switch Matrix

� Up to 40 inputs per Logic Block

In the LOGIC_D8.PLD example given in this tutorial, Logic Blocks B, C D, and F have37 or more signal inputs (Fan-In's) as shown in the Universal-Interconnect-Multiplexerassignments section of the .FIT file. The availability of wide Fan-In's to the Logic Blocksis one of the many Logic Doubling features. This feature improves the possibility of rout-ing all the necessary signals from the Global Bus to the Logic Blocks.

In addition, macrocells 37 and 59 of the ATF1508 are able to implement both combina-torial outputs (LED1G and LED8D) and buried registered signals (CA0 and RST) withinthe same macrocells. This is shown in the Resource Usage section of the .FIT file.

For more examples of design techniques that utilize the Logic Doubling features of theATF15xx Family, refer to Atmel's Logic Doubling White Paper and Reference Designsavailable on the Atmel website. These examples show how to apply Logic Doublingtechniques to new product designs, to obtain the benefits of more features in a smallerand possibly less expensive chip, or spare logic resources for future revisions andreduce the risk of PCB re-spin.

Logic Array Block Logic Cells I/O Pins Foldbacks TotalPT FanINCascadesA: LC1 - LC16 16/16(100%) 8/16(50%) 5/16(31%) 46/80(57%) (19) 0B: LC17 - LC32 16/16(100%) 8/16(50%) 3/16(18%) 51/80(63%) (38) 0C: LC33 - LC48 16/16(100%) 8/16(50%) 2/16(12%) 48/80(60%) (38) 0D: LC49 - LC64 16/16(100%) 6/16(37%) 2/16(12%) 40/80(50%) (38) 0E: LC65 - LC80 16/16(100%) 6/16(37%) 6/16(37%) 55/80(68%) (32) 0F: LC81 - LC96 16/16(100%) 8/16(50%) 2/16(12%) 47/80(58%) (38) 0G: LC97 - LC112 16/16(100%) 8/16(50%) 3/16(18%) 43/80(53%) (25) 0H: LC113- LC128 16/16(100%) 8/16(50%) 2/16(12%) 42/80(52%) (34) 0

Total dedicated input used: 3/4 (75%)Total I/O pins used 60/64 (93%)Total Logic cells used 128/128 (100%)Total Flip-Flop used 31/128 (24%)Total Foldback logic used 25/128 (19%)Total Nodes+FB/MCells 153/128 (119%)Total cascade used 0Total input pins 7Total output pins 56Total Pts 372:


3300A–PLD–08/02


3.6 Program andVerify Design

In this step of the tutorial, the user will program an ATF1508AS 84-pin PLCC device onthe Atmel CPLD Development/Programmer Board through ISP and then verify thedesign by observing the text messages displayed on the eight 8-segment LED displaysof the CPLD Development/Programmer Board.

The user will need to follow the steps below to setup the ATMISP software in order toprogram the ATF1508AS 84-pin PLCC on the CPLD Development/Programmer Board.

1. To create a new chain file, the ATMISP Software first needs to be launchedeither through the PROGRAM CHIP button in the ProChip Designer window, theATMISP desktop icon or the Start ... Programs .. Atmel ISP menu.

If ATMISP is launched through ProChip Designer, steps 2 to 6 below can be skippedsince ProChip Designer will automatically setup the appropriate chain file for the ISPoperation.

2. To create a new chain file, select the New command under the File menu or clickon the New Shortcut Button.

3. The first piece of information that the software asks for when creating a newchain is the number of devices in the JTAG chain. Therefore, enter 1 and thenclick OK since a 1-device JTAG chain will be programmed.

4. Next the user will need to specify the properties of each JTAG device in theDevice Properties window. First, select the target device type of the first device inthe JTAG chain. For this tutorial, please select ATF1508AS as the target devicetype.

5. In the JTAG Instruction field, the user can specify the appropriate JTAG instruc-tion to be executed on this device in the chain. Please select Program/Verify toprogram and verify the ATF1508AS.

LaunchATMISP

(1)

(2)Create NewChain File

(3)Enter the number of

devices


3300A–PLD–08/02


6. The next step is to specify the JEDEC file to be programmed into the targetdevice in the JEDEC File field. Click on the Browse button, change the directoryto [..\PROCHIP\DESIGNS\CUPL"] and then select LOGIC_D8.JED as the tar-get JEDEC file. Click OK to close the JTAG Device Properties window when allproperties are specified.

The next few steps require the user to setup the Atmel CPLD Development/ProgrammerBoard to program the ATF1508AS through ISP.

7. Connect the 25-DB side of the Atmel-ISP Cable to the PC's parallel port and the10-pin header side of the Atmel-ISP Cable to the Atmel CPLD DevelopmentBoard as shown Figure 2-5.

8. Connect a 9V AC/DC power adapter to the power connector (JPower) of theAtmel CPLD Development/Programmer Board.

9. Set the 5V/3.3V jumper to 5V. This will set the system board VCC to 5V.

10. Set the JPCLK jumper to GCLK1 so that the output of the crystal oscillator willbe connected to Pin 83 of the ATF1508AS.

11. Connect the 84-pin PLCC Socket Adapter Board onto the main Develop-ment/Programmer Board.

Note: If a device in a different package type is to be programmed, then the appropriate SocketAdapter Board must be used.

12. Switch the Power Switch to the ON position.

13. Select the appropriate LPT port in the Port Setting field. LPT 1 is the default port.

14. Select the ISP download cable type in the Cable Types field. The default cabletype is the Atmel ISP Cable but it can be changed to the Altera ByteBlaster cableif the ByteBlaster cable is being used.

Now both the user’s software and hardware are setup for ISP programming, and theuser can execute the PROGRAM/VERIFY instruction to program the ATF1508AS onthe Atmel CPLD Development/Programmer Board.

(5) SpecifyJTAG

Instruction

(4) SpecifyTarget

Device Type

(6) SelectJEDEC

File


3300A–PLD–08/02


15. Click on the Run button in the ATMISP main window to execute the JTAGinstruction to program the ATF1508AS on the CPLD Development/ProgrammerBoard.

After successfully programming the ATF1508AS with the LOGIC_D8.JED file, the eight8-segment LED's will display the words "Logic Doubling".

If these two text messages are correctly displayed on the CPLD Development/Program-mer Board, then the user has successfully completed this tutorial.

(13)SelectLPT PortNumber

(14)SelectCableType

(15) Click on theRUN Button


3300A–PLD–08/02

Section 4

Schematic Diagrams


Rev. 3300A–PLD–08/02

Schematic Diagrams

Figure 4-1. Schematic Diagram of the Atmel CPLD Development/Programmer Board

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RD

OT3

RD

OT4

RD

OT4

RD

OT5

RD

OT5

RD

OT6

RD

OT6

RD

OT7

RD

OT7

RD

OT8

RD

OT8

D1AD1AD1BD1BD1CD1CD1DD1DD1ED1ED1FD1FD1GD1G









3300A–PLD–08/02

s

CP

LD

Dev

elo

pm

ent/

Pro

gra

mm

erK

itU

ser

Gu

ide

4-3

3300

A–

PLD

–08

/02

P29

P31

P33P34

P36P37

P39

GND

VCC

TDO

TCK

D4F

D4ED4A

D4CD4B

D3G

D3F2930313233343536373839

U1

PLCC44

Sch

emat

icD

iag

ram

Fig

ure

4-2.

Sch

emat

icD

iagr

amo

f44-

pin

PLC

CS

ock

etA

dapt

er

Boa

rd

c10.1uF

c20.1uF

c30.1uF

c40.1uF

VCC

1 23 45 67 89 1011 1213 1415 1617 1819 2021 2223 2425 2627 2829 3031 3233 3435 3637 3839 40

JPLEFT

HEADER 20X2

1 23 45 67 89 1011 1213 1415 1617 1819 2021 2223 2425 2627 2829 3031 3233 3435 3637 3839 40

JPRIGHT

HEADER 20X2

VCC

GND

GCLK1

TCKD3BD3AD3F

D4BD4AD4FD4G

D3GD3E

VCC

GNDGCLK2

TDO

D3CD3D

D4C

D4DD4E

VCC

D5BD5AD5FD5G

D6AD6FD6G

GOE

D6B

GCLR

TDI

GND

TMS

D5CD5DD5E

D6CD6DD6E

P8P9

P11P12

P14

P16P17

P1

8P

19

P2

0P

21

P2

4P

25

P2

6P

27

P2

8P

40

P4

1

P4

3P

44

P1

P2

P4

P5

P6

GO

EG

CL

K1

GN

D

GND

GN

D

VCC

VC

C

VC

C

TDI

TMSGND VCC

D5

BD

5C

D5

A

D5DD5F

D5ED5G

D6C

D6BD6D

D6

AD

6E

D6F

D6

GG

CL

K2

GC

LR

D4

GD

4D

D3

ED

3A

D3

DD

3B

D3C

ATMEL PLCC44

TDI7

I/O8

I/O9

GND10

I/O11

TMS13

I/O14

VCC15

I/O16

I/O17

I/O12

I/O

18

I/O

19

I/O

20

I/O

21

GN

D2

2

VC

C2

3

I/O

24

I/O

25

I/O

26

I/O

27

I/O

28

I/OGND

I/OTCKI/OI/O

VCCI/OI/O

TDOI/OI/

O4

0G

CLK

34

1G

ND

42

GC

LK1

43

OE

14

4G

CLR

1I/

OE

2/G

CLK

22

VC

C3

I/O

4I/

O5

I/O

6

4-4

CP

LD

Dev

elo

pm

ent/

Pro

gra

mm

erK

itU

ser

Gu

ide

3300

A–P

LD

–08/

02

P23

P25

P27P28

P30P31

P33

2324252627282930313233

U1

TQFP44

GND

VCC

TDO

TCK

D4F

D4ED4A

D4CD4B

D3G

D3F

Sch

emat

icD

iag

ram

s

Fig

ure

4-3.

Sch

emat

icD

iagr

amo

f44-

pin

TQ

FP

So

cket

Ada

pte

rB

oard

c10.1uF

c20.1uF

c30.1uF

c40.1uF

VCC

1 23 45 67 89 1011 1213 1415 1617 1819 2021 2223 2425 2627 2829 3031 3233 3435 3637 3839 40

JPLEFT

HEADER 20X2

1 23 45 67 89 1011 1213 1415 1617 1819 2021 2223 2425 2627 2829 3031 3233 3435 3637 3839 40

JPRIGHT

HEADER 20X2

VCC

GND

GCLK1

TCKD3BD3AD3F

D4BD4AD4FD4G

D3GD3E

VCC

GNDGCLK2

TDO

D3CD3D

D4C

D4DD4E

VCC

D5BD5AD5FD5G

D6AD6FD6G

GOE

D6B

GCLR

TDI

GND

TMS

D5CD5DD5E

D6CD6DD6E

P2P3

P5P6

P8

P10P11

P1

2P

13

P1

4P

15

P1

8P

19

P2

0P

21

P2

2P

34

P3

5

P3

7P

38

P3

9P

40

P4

2P

43

P4

4

ATMEL TQFP44

TDI1

I/O2

I/O3

GND4

I/O5

TMS7

I/O8

VCC9

I/O10

I/O11

I/O6

I/O

12

I/O

13

I/O

14

I/O

15

GN

D1

6

VC

C1

7

I/O

18

I/O

19

I/O

20

I/O

21

I/O

22

I/OGND

I/OTCKI/OI/O

VCCI/OI/O

TDOI/OI/

O3

4G

CLK

33

5G

ND

36

GC

LK1

37

OE

13

8G

CLR

39

I/O

E2/

GC

LK2

40

VC

C4

1I/

O4

2I/

O4

3I/

O4

4

GO

EG

CL

K1

GN

D

GND

GN

D

VCC

VC

C

VC

C

TDI

TMSGND VCC

D5

BD

5C

D5

A

D5DD5F

D5ED5G

D6C

D6BD6D

D6

AD

6E

D6F

D6

GG

CL

K2

GC

LR

D4

GD

4D

D3

ED

3A

D3

DD

3BD

3C

s

CP

LD

Dev

elo

pm

ent/

Pro

gra

mm

erK

itU

ser

Gu

ide

4-5

3300

A–

PLD

–08

/02

O 44O 45O 46O 47D 48O 49K 50O 51O 52C 53O 54O 55O 56O 57D 58O 59O 60

U1

P44P45P46P47

P49

P51P52

P54P55P56

P59P60

GND

GND

VCC

TCK

TDO

D4FD4E

D4AD4CD4B

D3GD3F

D3E

D3AD3DD3BD3C

Sch

emat

icD

iag

ram

Fig

ure

4-4.

Sch

emat

icD

iagr

amo

f68-

pin

PLC

CS

ock

etA

dapt

er

Boa

rd

c10.1uF

c20.1uF

c30.1uF

c40.1uF

VCC

ATMEL PLCC68

I/O10

VCC11

TDI12

I/O13

I/O14

I/O15

GND16

I/O17

I/O18

TMS19

I/O20

VCC21

I/O22

I/O23

I/O24

I/O25

GND26

I/O

27

I/O

28

I/O

29

I/O

30

VCC

31

I/O

32

I/O

33

GN

D3

4

VCC

35

I/O

36

I/O

37

GN

D3

8

I/O

39

I/O

40

I/O

41

I/O

42

VCC

43

I/I/I/I/

GNI/

TCI/I/

VCI/I/I/

TDGN

I/I/I/

O6

1T

CK

62

VC

C6

3I/

O6

4G

CL

K3

65

GN

D6

6G

CL

K1

67

OE

16

8G

CLR

1G

CL

K2

2V

CC

3I/

O4

I/O

5G

ND

6I/

O7

I/O

8I/

O9

P1

P2

P4

P5

P7

P8

P9

P10

P13P14P15

P17P18

P20

P22P23P24P25

P2

7P

28

P2

9P

30

P3

2P

33

P3

6P

37

P3

9P

40

P4

1P

42

P6

1

P6

4P

65

P6

7P

68

GND

GND

GN

D

GN

DG

ND

GN

D

VC

C

VC

C

VC

C

VC

C

VC

C

VCC

VCC

TDI

TMS

GC

LRG

OE

GC

LK

1

GC

LK

2

1 23 45 67 89 1011 1213 1415 1617 1819 2021 2223 2425 2627 2829 3031 3233 3435 3637 3839 40

JPLEFT

HEADER 20X2

1 23 45 67 89 1011 1213 1415 1617 1819 2021 2223 2425 2627 2829 3031 3233 3435 3637 3839 40

JPRIGHT

HEADER 20X2

VCC

GND

GCLK1

TCK

D2BD2AD2F

D3BD3AD3F

D4BD4AD4FD4G

D2G

D3GD3E

VCC

GNDGCLK2

TDO

D2CD2DD2E

D3CD3D

D4C

D4DD4E

VCC

GND

D5BD5AD5FD5G

D6AD6FD6G

D7AD7FD7G

GOE

D6B

D7B

GCLR

TDI

D7C

VCC

GND

TMS

D5CD5DD5E

D6CD6DD6E

D7DD7E

P6

2

D5

BD

5A

D5

CD

5F

D5

D

D5G

D5ED6BD6C

D6AD6D

D6F

D6ED6GD7BD7A

D7

CD

7F

D7

DD

7G

D7

E

D4

G

D4

DD

2G

D2

ED

2F

D2

D

D2

AD

2C

D2

B

4-6

CP

LD

Dev

elo

pm

ent/

Pro

gra

mm

erK

itU

ser

Gu

ide

3300

A–P

LD

–08/

02

JR2JR4

JR32

JR6

JR30

JR8

JR28

JR10

JR26

JR13

JR24

JR16

JR22

JR17

JR21JR19

JL2JL4JL6JL8JL10

JL13JL15JL17

JL20JL22JL24JL26JL28JL30JL32

PIN2

PIN1

PIN5PIN8PIN10

PIN15PIN17PIN20

PIN24PIN27PIN29

PIN33PIN35

PIN48PIN50PIN52

PIN56PIN58PIN61

PIN65PIN68PIN70

PIN75PIN80PIN77

JR34

JL34 PIN37

PIN40

PIN45

PIN41

CDE

E

C

DLK2

O

CDE

CD

C

DE

5R

8

7

Sch

emat

icD

iag

ram

s

Fig

ure

4-5.

Sch

emat

icD

iagr

amo

f84-

pin

PLC

CS

ock

etA

dapt

er

Boa

rd

INP

UT

/GC

LRn

1IN

PU

T/O

E2/

GC

LK2

2V

CC

_IN

T3

I/O

4I/

O5

I/O

6G

ND

7I/

O8

I/O

9I/

O10

I/O

11

I/O12

VCC_IO13

I/O / TDI14

I/O15

I/O16

I/O17

I/O18

GND19

I/O20

I/O21

I/O22

I/O / TMS23

I/O24

I/O25

VCC_IO26

I/O27

I/O28

I/O29

I/O30

I/O31

GND32

I/O33

I/O34

I/O35

I/O36

I/O37

VC

C_I

O38

I/O39

I/O40

I/O41

GN

D42

VC

C_I

NT

43

I/O44

I/O45

I/O46

GN

D47

I/O48

I/O49

I/O50

I/O51

I/O52

VC

C_I

O53

I/O54

I/O 55I/O

56I/O 57I/O

58GND 59

I/O60

I/O 61I/O / TCK

62I/O 63I/O

64I/O 65

VCC_IO66

I/O 67I/O

68I/O 69I/O

70I/O / TDO 71

GND72

I/O 73I/O

74

I/O

75I/

O76

I/O

77V

CC

_IO

78I/

O79

I/O

80I/

O81

GN

D82

INP

UT

/GC

LK

183

INP

UT

/OE

184

ATMEL

ATF1508AS-15JC84

U1

1 23 45 67 89 1011 1213 1415 1617 1819 2021 2223 2425 2627 2829 3031 3233 3435 3637 3839 40

JPLEFT

HEADER 20X2

1 23 45 67 89 1011 1213 1415 1617 1819 2021 2223 2425 2627 2829 3031 3233 3435 3637 3839 40

JPRIGHT

HEADER 20X2

PIN

1

GND

GND

GN

D

GN

D

GND

GND

GN

D

GN

DV

CC

VC

C

VCC

VCC

VCC

VC

C

VC

C

VC

CP

IN8

4P

IN8

3

PIN

2

TDI

TMS

TDO

TCK

c10.1uF

c20.1uF

c30.1uF

c40.1uF

VCC

SMALLATMELMARKP

IN4

PIN

5P

IN6

PIN

8P

IN9

PIN

10

PIN

11

PIN12

PIN15PIN16PIN17PIN18

PIN20PIN21PIN22

PIN24PIN25

PIN27PIN28PIN29PIN30PIN31

PIN

33

PIN

34

PIN

35

PIN

36

PIN

37

PIN

39

PIN

40

PIN

41

PIN

44

PIN

45

PIN

46

PIN

48

PIN

49

PIN

50

PIN

51

PIN

52


PIN60PIN61

PIN63PIN64PIN65

PIN67PIN68PIN69PIN70

PIN73PIN74

PIN

75

PIN

76

PIN

77

PIN

79

PIN

80

PIN

81

JR1JR3JR5JR7JR9JR11JR12JR14JR15

JR18

JR31

JR20

JR29JR27JR25JR23

JL1JL3JL5JL7JL9JL11JL12JL14JL16JL18JL19JL21JL23JL25JL27JL29JL31

PIN83


PIN12PIN16PIN18

PIN49

PIN21

PIN51

PIN22PIN25

PIN54PIN55

PIN28

PIN57

PIN30

PIN60

PIN31PIN34

PIN63

PIN36

PIN64PIN67PIN69PIN73PIN74PIN76PIN79PIN81

JR33

JL33

PIN46

PIN44

PIN39

VCC

GND

GCLK1

TCK

D2BD2AD2F

D3BD3AD3F

D4BD4AD4FD4G

D1BD1AD1FD1G

D2G

D3G

D1D1D1

D3

VC

GNGC

TD

D2D2D2

D3D3

D4

D4D4

DOT6

VCC

GND

D5BD5AD5FD5G

D6AD6FD6G

D7AD7FD7G

GOE

D6B

D7B

D8BD8AD8FD8G

DOTGCL

TDI

D7C

D8CD8DD8E

DOT

VCC

GND

TMS

D5CD5DD5E

D6CD6DD6E

D7DD7E

DOT

s

CP

LD

Dev

elo

pm

ent/

Pro

gra

mm

erK

itU

ser

Gu

ide

4-7

3300

A–

PLD

–08

/02

1 23 45 67 89 1011 1213 1415 1617 1819 2021 2223 2425 2627 2829 3031 3233 3435 3637 3839 40

PLEFT

EADER 20X2

1 23 45 67 89 1011 1213 1415 1617 1819 2021 2223 2425 2627 2829 3031 3233 3435 3637 3839 40

PRIGHT

EADER 20X2

D1CD1DD1E

D3E

VCC

GNDGCLK2

TDO

D2CD2DD2E

D3CD3D

D4C

D4DD4E

DOT1

DOT2

DOT3

DOT4

DOT5GCLR

TDI

D7C

D8CD8DD8E

DOT8

VCC

GND

TMS

D5CD5DD5E

D6CD6DD6E

D7DD7E

DOT7

Sch

emat

icD

iag

ram

Fig

ure

4-6.

Sch

emat

icD

iagr

amo

f100

-pin

PQ

FP

Soc

ketA

dapt

erB

oard

c10.1uF

c20.1uF

c30.1uF

c40.1uF

VCC

J

H

J

H

VCC

GND

GCLK1

TCK

D2BD2AD2F

D3BD3AD3F

D4BD4AD4FD4G

D1BD1AD1FD1G

D2G

D3G

DOT6

VCC

GND

D5BD5AD5FD5G

D6AD6FD6G

D7AD7FD7G

GOE

D6B

D7B

D8BD8AD8FD8G

I/On1

I/On2

I/O3

I/O4

VCCIO5

TDI6

I/On7

I/O8

I/On9

I/O10

I/O11

I/O12

GND13

I/O14

I/O15

I/O16

TMS17

I/O18

I/O19

VCCIO20

I/O21

I/O22

I/O23

I/On24

I/O25

I/On26

I/O27

GND28

I/On29

I/On30

I/O3

1

I/O3

2

I/O3

3

I/O3

4

I/O3

5

VC

CIO

36

I/O3

7

I/O3

8

I/O3

9

GN

D4

0

VC

CIN

T4

1

I/O4

2

I/O4

3

I/O4

4

GN

D4

5

I/O4

6

I/O4

7

I/O4

8

I/O4

9

I/O5

0

I/On 51I/On 52VCCIO 53I/O 54I/On 55I/O 56I/On 57I/O 58I/O 59I/O 60GND 61I/O 62I/O 63TCK 64I/O 65I/O 66I/O 67VCCIO 68I/O 69I/O 70I/O 71I/On 72I/O 73I/On 74TDO 75GND 76I/O 77I/O 78I/On 79I/On 80I/O8

1I/O

82

I/O8

3V

CC

IO8

4I/O

85

I/O8

6I/

O/G

CL

K3

87

GN

D8

8G

CL

K1

89

OE

19

0G

CLR

91

GC

LK

29

2V

CC

INT

93

I/O9

4I/O

95

I/O9

6G

ND

97

I/O9

8I/O

99

I/O1

00

ATMEL PQFP100

U1

P1P2P3P4

P7P8P9P10P11P12

P14P15P16

P18P19

P21P22P23P24P25P26P27

P29P30

P3

1P

32

P3

3P

34

P3

5

P3

7P

38

P3

9

P4

2P

43

P4

4

P4

6P

47

P4

8P

49

P5

0

P51P52

P54P55P56P57P58P59P60

P62P63

P65P66P67

P69P70P71P72P73P74

P77P78P79P80

P8

1P

82

P8

3

P8

5P

86

P8

7

P8

9P

90

P9

1P

92

P9

4P

95

P9

8P

99

P9

6

P1

00

GN

D

GN

D

GND

GND

GN

D

GN

D

GND

GND

VCC

VCC

VC

C

VC

C

VCC

VCC

VC

C

VC

C

GC

LK

1

GC

LK

2

GO

EG

CLR

TDO

TCKTMS

TDI

DO

T5

D5B

D5C

D5

A

D5F

D5ED5G

DOT6

D5

D

D6CD6BD6D

D6AD6ED6F

D6GD7B

D7CD7AD7DDOT7D7F

D7E

D7

G

DOT8

D8

B

D8

C

D8

A

D8

DD

8F

D8

ED

8G

D4

GD

4D

D4F

D4

ED

4A

D4C

D4BDOT4

D3G

D3FD3ED3A

D3DD3BD3C

DOT3D2G

D2ED2FD2D

DOT2

D2A

D1

B

DOT1

D1

CD

1A

D1

DD

1F

D1

ED

1G

D2B

D2

C

4-8

CP

LD

Dev

elo

pm

ent/

Pro

gra

mm

erK

itU

ser

Gu

ide

3300

A–P

LD

–08/

02

51525354555657585960616263646566676869707172737475

U1

TQFP100

VCC

VCC

GND

GND

TCK

TDO

D2A

D2F

D3B

D3A

D3F

D1B

D2G

D3G

D3E

D2D

D2E

D3C

D3D

DOT2

DOT3

DOT4

P52P53P54P55P56P57P58

P60P61

P63P64P65

P67P68P69P70P71P72

P75

Sch

emat

icD

iag

ram

s

Fig

ure

4-7.

Sch

emat

icD

iagr

amo

f100

-pin

TQ

FP

Soc

ketA

dap

ter

Boa

rd

I/On1

I/On2

VCCIO3

TDI4

I/On5

I/O6

I/On7

I/O8

I/O9

I/O10

GND11

I/O12

I/O13

I/O14

TMS15

I/O16

I/O17

VCCIO18

I/O19

I/O20

I/O21

I/On22

I/O23

I/On24

I/O25

GN

D2

6

I/On

27

I/On

28

I/O

29

I/O

30

I/O

31

I/O

32

I/O

33

VC

CIO

34

I/O

35

I/O

36

I/O

37

GN

D3

8

VC

CIN

T3

9

I/O

40

I/O

41

I/O

42

GN

D4

3

I/O

44

I/O

45

I/O

46

I/O

47

I/O

48

I/On

49

I/On

50

VCCIOI/O

I/OnI/O

I/OnI/OI/OI/O

GNDI/OI/O

TCKI/OI/OI/O

VCCIOI/OI/OI/O

I/OnI/O

I/OnTDOGND

I/O

ATMEL TQFP100

I/O

76

I/On

77

I/O

78

I/On

79

I/O

80

I/O

81

VC

CIO

82

I/O

83

I/O

84

I/O

GC

LK

38

5G

ND

86

GC

LK1

87

OE

18

8G

CLR

89

GC

LK2

90

VC

CIN

T9

1I/

O9

2I/

O9

3I/

O9

4G

ND

95

I/O

96

I/O

97

I/O

98

I/O

99

I/O

10

0

1 23 45 67 89 1011 1213 1415 1617 1819 2021 2223 2425 2627 2829 3031 3233 3435 3637 3839 40

JPLEFT

HEADER 20X2

1 23 45 67 89 1011 1213 1415 1617 1819 2021 2223 2425 2627 2829 3031 3233 3435 3637 3839 40

JPRIGHT

HEADER 20X2

c10.1uF

c20.1uF

c30.1uF

c40.1uF

VCC

P1P2

P5P6P7

VCC

GND

GCLK1

TCK

D2BD2AD2F

D3BD3AD3F

D4BD4AD4FD4G

D1BD1AD1FD1G

D2G

D3G

D1CD1DD1E

D3E

VCC

GNDGCLK2

TDO

D2CD2DD2E

D3CD3D

D4C

D4DD4E

DOT1

DOT2

DOT3

DOT4

DOT6

VCC

GND

D5BD5AD5FD5G

D6AD6FD6G

D7AD7FD7G

GOE

D6B

D7B

D8BD8AD8FD8G

DOT5GCLR

TDI

D7C

D8CD8DD8E

DOT8

VCC

GND

TMS

D5CD5DD5E

D6CD6DD6E

D7DD7E

DOT7

TMS

VCC

VCC

VC

C

VC

C

VC

C

VC

C

GN

D

GN

D

GN

D

GN

D

GN

D

GND

TDI

GC

LK

1G

OE

GC

LRG

CL

K2

D2

B

D4

B

D4

A

D4

F

D4

G

D1

A

D1

F

D1

G

D1

C

D1

D

D1

E

D2

C

D4

C

D4

D

D4

E

DO

T1

DOT6

D5

B

D5

A

D5

F

D5

G

D6A

D6F

D6G

D7A

D7F

D7

G

D6B

D7B

D8

B

D8

A

D8

F

D8

G

DO

T5

D7C

D8

C

D8

D

D8

E

DO

T8

D5

C

D5

D

D5

E

D6C

D6D

D6E

D7D

D7E

DOT7

P8P9P10

P12P13P14

P16P17

P19P20P21P22P23P24P25

P2

7P

28

P2

9P

30

P3

1P

32

P3

3

P3

5P

36

P3

7

P4

0P

41

P4

2

P4

4P

45

P4

6P

47

P4

8P

49

P5

0P

76

P7

7P

78

P7

9P

80

P8

1

P8

3P

84

P8

5

P8

7P

88

P8

9P

90

P9

2P

93

P9

4

P9

6P

97

P9

8P

99

P1

00

Schematic Diagrams

Figure 4-8. Schematic Diagram of 144-pin TQFP Socket Adapter Board

c10.1uFc20.1uF

c30.1uFc

40.1uF

VCC

12

34

56

78

910

11

121

314

15

161

718

19

202

122

23

242

526

27

282

930

31

323

334

35

363

738

39

40

JPLEFT

HE

AD

ER

20X2

12

34

56

78

910

11

121

314

15

161

718

19

202

122

23

242

526

27

282

930

31

323

334

35

363

738

39

40

JPRIG

HT

HE

AD

ER

20X2

VC

C

GN

D

GC

LK1

TCK

D2B

D2A

D2F

D3B

D3A

D3F

D4B

D4A

D4F

D4G

D1B

D1A

D1F

D1G

D2G

D3G

D1C

D1D

D1E

D3E

VCC

GN

DG

CLK2

TDO

D2C

D2D

D2E

D3C

D3D

D4C

D4D

D4E

DOT1

DOT2

DOT3

DOT4

DOT6

VCC

GN

D

D5B

D5A

D5FD

5G

D6A

D6FD

6G

D7A

D7FD

7G

GO

E

D6B

D7B

D8B

D8A

D8FD

8G

DO

T5G

CLR

TDI

D7C

D8C

D8D

D8E

DO

T8

VCC

GN

D

TMS

D5C

D5D

D5E

D6C

D6D

D6E

D7D

D7E

DO

T7

I/On

1

I/On

2

GN

D3

TDI

4

I/O5

I/O6

I/O7

I/O8

I/O9

I/O1

0

I/O1

1

I/On

12

GN

D1

3

I/O1

4

I/O1

5

I/O1

6

GN

D1

7

I/O1

8

I/On

19

TMS

20

I/O2

1

I/O2

2

I/O2

3

VC

CIO

24

I/O2

5

I/O2

6

I/O2

7

I/O2

8

I/O2

9

I/O3

0

I/O3

1

I/O3

2

GN

D3

3

I/On

34

I/On

35

I/On

36

I /O41

I/O42

I/On43

I/O44

I/O45

I/On46

I/On47

I/On48

I/On49

VCCIO50

VCCINT51

GND52

I/O53

I/O54

I/O55

I/O56

GND57

VCCINT58

GND59

I/O60

I/O61

I/O62

I/O63

GND64

I/O65

I/On66

I/O67

I/O68

I/O69

I/O70

I/O71

I/O81

I/O82

I/O83

I/O84

GN

D85

I/O86

I/O87

I/O88

TCK89

I/On

90I/O

91I/O

92I/O

93I/O

94VC

CIO

95I/O

96I/O

97I/O

98I/O

99I/O

100I/O

101I/O

102I/O

n103

TDO

104G

ND

105I/O

106I/O

107I/O

n108

I/O 109I/O 110I/O 111I/O 112I/O 113I/O 114VCCIO 115I/O 116I/O 117I/O 118I/O 119I/On 120I/On 121I/On 122VCINT 123GND 124GCLK 125GOE 126GCLR 127GCLK2 128GND 129VCCINT 130I/O 131I/O 132I/O 133I/O 134GND 135I/O 136I/O 137I/O 138I/O 139I/O 140I/O 141I/O 142I/O 143VCCIO 144

ATM

EL TQ

FP144

VCC

IO76

I/O77

I/O78

I/O79

I/O80

VCC

IO73

I/O74

I/On

75

I /O72

I/O37

I/O38

I/O39

I/O40

U1

TQFP

144

P5

P6

P7

P8

P9

P10

P11

P14

P15

P16

P18

P21

P22

P23

P25

P26

P27

P28

P29

P30

P31

P32

P37P38P39P40P41P42

P44P45

P53P54P55P56

P60P61P62P63

P65

P67P68P69P70P71P72

P74

P77

P78

P79

P80

P81

P82

P83

P84

P86

P87

P88

P91

P92

P93

P94

P96

P97

P98

P99

P100

P101

P102

P106

P107

P109P110P111P112P113P114

P116P117P118

P119

P125P126P127P128

P131P132P133P134

P136P137P138P139P140P141P142P143

GND

GND

GND

GND

GND

GND

GND

GN

D

GN

D

GND

GND

GND

GND

VCC

VCCVCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

TDO

TCK

TMS

TDI

GCLK1GOEGCLRGCLK2

DOT5

D5BD5C

D5AD5DD5F

D5E

D5GD

OT6

D6C

D6B

D6D

D6A

D6E

D6F

D6G

DO

T7D

7BD

7C

D7A

D7D

D7FD

7ED

7GD

OT8

D8B

D8C

D8A

D8D

D8F

D8E

D8G

D4DD4GD4E

D4FD4CD4AD4B

DOT4

D3G

D3E

D3F

D3D

D3A

D3C

D3B

DO

T3

D2G

D2E

D2F

D2D

D2A

D2C

D2B

DO

T2D

1GD

1ED

1FD

1DD

1A

D1C

D1B

DO

T1


3300A–PLD–08/02

Schematic Diagrams

Figure 4-9. Schematic Diagram of 160-pin PQFP Socket Adapter Board

NC

1

NC

2

NC

3

NC

4

NC

5

NC

6

NC

7

VC

CIO

8

TDI

9

I/O10

I/O11

I/O12

I/O13

I/O14

I/O15

I/O16

GN

D17

I/O18

I/O19

I/O20

I/O21

TMS

22

I/O23

I/O24

I/O25

VC

CIO

26

I/O27

I/O28

I/O29

I/O30

I/O31

I/O32

I/O33

NC

34

NC

35

NC

36

NC

37

NC

38

NC

39

NC

40

I/O41

GND42

I/O43

NC44

NC45

NC46

NC47

I/O48

I/O49

I/O50

I/O51

I/O52

I/O53

I/O54

VCCIO55

I/O56

I/O57

I/O58

I/O59

GND60

VCCINT61

I/O62

I/O63

I/O64

I/O65

GND66

I/O67

I/O68

I/O69

I/O70

I/O71

I/O72

I/O73

NC74

NC75

NC76

NC77

I/O78

VCCIO79

I/O80

NC

81

NC

82

NC

83

NC

84

NC

85

NC

86

NC

87

I/O8

8I/O

89

I/O9

0I/O

91

I/O9

2I/O

93

I/O9

4G

ND

95

I/O9

6I/O

97

I/O9

8TC

K9

9I/O

100I/O

101I/O

102I/O

103V

CC

IO104

I/O105

I/O106

I/O107

I/O108

I/O109

I/O110

I/O111

TDO

112G

ND

113N

C114

NC

115N

C116

NC

117N

C118

NC

119N

C120

I/O 121I/O 122I/O 123NC 124NC 125NC 126NC 127I/O 128I/O 129I/O 130I/O 131I/O 132VCCIO 133I/O 134I/O 135I/O 136I/O/GCLK3 137GND 138GCLK1 139OE1 140GCLR 141GCLK2 142VCCINT 143I/O 144I/O 145I/O 146I/O 147GND 148I/O 149I/O 150I/O 151I/O 152I/O 153NC 154NC 155NC 156NC 157I/O 158I/O 159I/O 160

ATM

EL P

QFP

160

U1

c1

0.1uFc

20.1uF

c3

0.1uFc

40.1uF

VCC

12

34

56

78

910

1112

1314

1516

1718

1920

2122

2324

2526

2728

2930

3132

3334

3536

3738

3940

JPLEFT

HE

AD

ER

20X2

12

34

56

78

910

1112

1314

1516

1718

1920

2122

2324

2526

2728

2930

3132

3334

3536

3738

3940

JPR

IGH

T

HE

AD

ER

20X2

VCC

GN

D

GC

LK1

TCK

D2B

D2A

D2F

D3B

D3A

D3F

D4B

D4A

D4F

D4G

D1B

D1A

D1F

D1G

D2G

D3G

D1C

D1D

D1

E

D3

E

VCC

GN

DG

CLK

2

TDO

D2C

D2D

D2

E

D3C

D3D

D4C

D4D

D4

E

DO

T1

DO

T2

DO

T3

DO

T4

DO

T6

VCC

GN

D

D5B

D5A

D5F

D5G

D6A

D6F

D6G

D7A

D7F

D7G

GO

E

D6B

D7B

D8B

D8A

D8F

D8G

DO

T5G

CLR

TDI

D7C

D8C

D8D

D8

E

DO

T8

VCC

GN

D

TMS

D5C

D5D

D5

E

D6C

D6D

D6

E

D7D

D7

E

DO

T7

P11

P10

P12

P13

P14

P15

P16

P18

P19

P20

P21

P23

P24

P25

P27

P28

P29

P30

P31

P32

P33

P41

P43

P48P49P50P51P52P53P54

P56P57P58P59

P62P63P64P65

P67P68P69P70P71P72P73

P78

P80P88P89P90P91P92P93P94

P96P97P98

P100P101P102P103

P105P106P107P108P109P110P111

P121P122P123

P128P129P130P131P132

P134P135P136P137

P139P140P141P142

P144P145P146P147

P149P150P151P152P153

P158P159P160

VCC

VCC

VCC

VCC

VCC

VCC

VC

C

VC

C

GN

D

GND

GND

GND

GND

GND

GND

GND

GOEGCLRGCLK2

GCLK1

TMS

TD

ITD

O

TCK

DOT5D5BD5C

D5A

D5D

D5F

D5E

D5G

DO

T6D

6C

D6B

D6D

D6A

D6E

D6F

D6G

D7B

D7C

D7A

D7D

DO

T7

D7F

D7ED7G

DOT8D8B

D8C

D8A

D8D

D8F

D8E

D8G

D4GD4D

D4F

D4E

D4A

D4C

D4B

DO

T4D

3GD3F

D3E

D3A

D3D

D3B

D3C

DO

T3D

2G

D2E

D2FD

2D

D2AD2C

DOT2

D1GD1E

D1F

D1D

D1A

D1C

D1B

DO

T1

D2B


3300A–PLD–08/02

s

CP

LD

Dev

elo

pm

ent/

Pro

gra

mm

erK

itU

ser

Gu

ide

4-11

3300

A–

PLD

–08

/02

Sch

emat

icD

iag

ram

Fig

ure

4-10

.S

che

mat

icD

iagr

amof

Atm

elC

PLD

ISP

Cab

le

R16 100

1 23 45 67 89 10

JP1

HEADER 5X2

R224.7k

R214.7k

R264.7k

1A12

1Y118

1A24 1Y2 16

1A36

1Y314

1A48 1Y4 12

2A111

2Y19

2A213

2Y27

2A315 2Y3 5

2A417

2Y43

1G1

VCC20

2G19 GND 10

U1

74VHC244

R17 100

R1330ohm

R18 100

R19 100

R234.7k

R20 100

D1

1N4148R244.7k

C10.1uF

L1

LED

R254.7k

INI

TCK

AF

TMS

TDI

INITSEL_IN

AUTOSTROBE

nACK

BUSY

TDO

TDOINIAF

TCK

TMS

TDI

D7

D0

GND

GND

GND

VCC

VCC

GND

VCC

20-SOIC

Buffer/Line Driver

10 Pin Header to ISP Board

4-12

CP

LD

Dev

elo

pm

ent/

Pro

gra

mm

erK

itU

ser

Gu

ide

3300

A–P

LD

–08/

02

+

5

8

U2B

VCC

Sch

emat

icD

iag

ram

s

Fig

ure

4-11

.S

che

mat

icD

iagr

amof

Atm

elC

PLD

ISP

Cab

le,C

ontin

ued

R15 30K

R11 4.7K

R3 100

R13 4.7K

R14 3.3K

R10 4.7K

D4 1N4148

R4 100

D3 1N4148

D2 1N4148

R2 100

R7 100

R6 100

13251224112310229218207196185174163152141

P1

DB25

-

67

4

LM393

R8 100

R5 100

R9 100

- +

321

84

U2ALM393

R12 10K

STROBE

AUTO

INIT

SEL_IN

ERROR

D0

ERROR

D7

BUSY

nACK

GND

VCC

GND

VCC

GND

VCC

Parallel Port Section

Vref1.5V - 1.6V

Voltage Detection

8-SOP 8-SOP

3V = 05V = 1

1.36V at VCC = 3.32.06V at VCC = 5.0

Printed on recycled paper.

3300A–PLD–08/02 /1M

© Atmel Corporation 2002.Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warrantywhich is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errorswhich may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and doesnot make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are grantedby the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as criticalcomponents in life support devices or systems.

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Altera® is the registered trademark of Altera Corporation; ByteBlaster™ and ByteBlasterMV™ are the trade-marks of Altera Corporation. Pentium® is the registered trademark of Intel Corporation. Windows® and Win-dows NT® are the registered trademarks of Microsoft Corporation. Verilog® is a registered trademark ofCadence Design Systems, Inc. Mentor Graphics® is a registered trademark of Mentor Graphics Corporation;Exemplar™ and Leonardo Spectrum™ are trademarks of Mentor Graphics Corporation. Altium®, PeakFPGA™

and Protel™ are trademarks and registered trademarks of Altium Limited. Other terms and product namesmay be the trademarks of others.

Documents

CPLD Development/Programmer Kit User Guideww1.microchip.com/downloads/en/DeviceDoc/doc3300.pdf · Programmer Kit The Atmel CPLD Development/Programmer Kit ... ATF1502AS/ASL ATF1508AS/ASL