Cross-layer Optimized Placement and Routing for FPGA Soft Error Mitigation Keheng Huang 1,2, Yu Hu 1, and Xiaowei Li 1 1 Key Laboratory of Computer System

Cross-layer Optimized Placement and Routing for FPGA Soft Error Mitigation

Keheng Huang1,2, Yu Hu1, and Xiaowei Li1

1Key Laboratory of Computer System and Architecture

Institute of Computing Technology

Chinese Academy of Sciences

2Graduate University of Chinese Academy of Sciences

2

Outline• Background

• Motivation

• Cross-layer optimized placement and routing

• Experimental results

• Conclusions

3

Background• Architecture of SRAM-based FPGAs

4


Segments

(a) An overview of FPGA structure

5


Segments


W1

Wi

E1

Ei

S1 Sj

N1 Nj

(b) Switching block

.

.

.

CB

CB

CB

CB

CB

CB

CB

CB

CB

CB

.

.

.

CB

CB

. . .

. . .

S

S Switching block

6


• Configuration bits (>98% of all SRAM bits)–Routing resources (80% of configuration bits)

• User bits (<2% of all SRAM bits)

CLB CLB

CLB CLB


W1

Wi

E1

Ei

S1 Sj

N1 Nj

(b) Switching block

.

.

.

MUXsANDFFs Output

(c) Configurable logic block

.

.

.

CB

CB

CB

CB

CB

CB

CB

CB

CB

CB

.

.

.

CB

CB

. . .

. . .

LUTentry0: CBentry1: CB

entry14: CBentry15: CB

S

S Switching block

CLB Configurable logic blockThe reliability of routing resources needs to be seriously considered during placement and routing

Segments

7

Reliability Oriented EDA Flow

Synthesis and mapping

Design specification

Gate-level netlist

Bit Stream

Placement and routing

Application design level

Physical design level

• RoRA [TC’06]

TMR designs only

• SEU-Aware P & R[ISQED’07]

Dimensions of bounding box

• Reliability-aware P & R[ITC’10] Dimensions of bounding box

• SEU-Aware Router [DAC’07] Number of configuration bits

8

Soft Error Rate (SER)

Input Output

CBCBCBCB

CB

OutputInput

Propagation probability

Occurrence probability

SER evaluation criterion

Application level factor(EPP)

Physical level factor(Node error rate)

+

9

Key Observation

Application level factor(EPP)

Physical level factor(Node error rate)

Prior P & R guidance criterion

All EPPs are equal?

Physical level factor(Bounding boxes,

Configuration bits)

Estimated SER+

SER evaluation criterion

10

Key Observation• Application level factor (EPPs) varies significantly

Gini coefficient Inequality degree<0.2 Absolutely equal0.2-0.3 Relatively equal0.3-0.4 Moderately unequal0.4-0.5 The gap is relatively large>0.6 Quite unequal

0.0

0.2

0.4

0.6

0.8

1.0

avera

getse

ngseq

s385

84.1

s384

17frisc

ellipt

icdif

feqdes

dsip

clma

bigke

yap

ex2

ex5p

ex10

10spla

s298pd

c

misex3

apex

4

Gin

i coe

ffic

ient

of

EP

Ps Gini coefficient of EPPs

alu4

avg.=0.646

Circuit name

11

Key Observation• Application level factor (EPPs) varies significantly

Gini coefficient Inequality degree<0.2 Absolutely equal0.2-0.3 Relatively equal0.3-0.4 Moderately unequal0.4-0.5 The gap is relatively large>0.6 Quite unequal

0.0

0.2

0.4

0.6

0.8

1.0

avera

getse

ngseq

s385

84.1

s384

17frisc

ellipt

icdif

feqdes

dsip

clma

bigke

yap

ex2

ex5p

ex10

10spla

s298pd

c

misex3

apex

4

Gin

i coe

ffic

ient

of

EP

Ps Gini coefficient of EPPs

alu4

avg.=0.646

Circuit name

12

Cross-layer Optimized Placement and Routing

• Overview

Cross-layer optimized placement

Placer

Physicallevel factor

Cross-layer optimized routing

Router

Physical level

Cube-basedEPP analysis

SER

Application level factor

Applicationlevel factor

Logic synthesis Application level

Cross-layer optimization


SER

High Low

SER

13


• Overview


Placer



Router

Physical level


SER






SER

High Low

SER

14


• Overview

Cross-layer optimized routingCross-layer optimized placement

Placer


Router

Physical level


SER






SER

High Low

SER

15


• Overview


Placer


Router

Physical level


SER






SER

High Low

SER

16


• Overview


Placer


Router

Physical level


SER






SER

High Low

SER

17


• Overview


Placer


Router

Physical level


SER






SER

High Low

SER

18

Cube-based EPP Analysis• Error propagation probability (EPP)

• Monte Carlo simulation–Test vectors (high accuracy)–Traverse the design N times (high complexity)

• Static analysis–Signal probability and error propagation rules (lower accuracy)–Traverse the design twice per fault (lower complexity)

19

Cube-based EPP Analysis• Error propagation probability (EPP)

• Monte Carlo simulation–Test vectors (high accuracy)–Traverse the design N times (high complexity)

• Static analysis–Signal probability and error propagation rules (lower accuracy)–Traverse the design twice per fault (lower complexity)

A method with high accuracy and low complexity?

20

Cube-based EPP Analysis• Besides 0 and 1, “X” bit is introduced

• Introduce the cube and cover in logic synthesis

• Covers adjoin V:(set union: )∪ • Covers interface I:(set intersection: ∩)

0XX = {000,001,010,011}

cover ={0XX, 1XX}

cube

adjoin :{00X} V {01X} = {0XX}

interface: {00X} I {001} = {001}

21

Cube-based EPP Analysis• Forward traverse: compute the vectors that set

the logic of the wire as 0 and 1 respectively

0

0

0

1

Input0

Input1

control-cover 0 {X0}control-cover 1 {X1}

control-cover 0 {0X}control-cover 1 {1X} Output

LUTi

control-cover 0 {0X,10}control-cover 1 {11}

22



0

0

0

1

Input0

Input1



LUTi


23



• Backward traverse: compute the vectors that can propagate the fault to outputs

Output

LUTi

care-cover 0 {01,10}care-cover 1 {11}

care-cover 0 {0X}care-cover 1 {11}

0

0

0

1care-cover 0 {0X,10}care-cover 1 {11}

Fanout0

Fanout1

0

0

0

1

Input0

Input1



LUTi


24



• Backward traverse: compute the vectors that can propagate the fault to outputs

Output

LUTi

care-cover 0 {01,10}care-cover 1 {11}

care-cover 0 {0X}care-cover 1 {11}

0

0

0

1care-cover 0 {0X,10}care-cover 1 {11}

Fanout0

Fanout1

0

0

0

1

Input0

Input1



LUTi


25

Application level factor• Error propagation probability (EPP)

• Compare with traditional Monte Carlo simulation• For each fault, traverse the design N times

care-cover

inputs

NEPP

N

0

0

0

1Logic 0:

0

0

0

1

1

0

1

1

Input vectors

V0V1V2V3

Logic 1: 00

01

10

11

LUTi

11

00 01 10

Ncare-cover: number of vectors stored in care-cover

Ninputs: total number of input vectors

26

Application level factor• Comparison of computational complexity

• N: number of input vectors• V: number of LUTs• E: number of interconnecting wires• g: number of configuration bits per LUT or wire• Cavg: average compression ratio of all covers

Algorithm Computational complexity

Monte Carlo Simulation O(N*V*g*(V+E))

Static Analysis O(V2*(V +E))

Cube-based EPP Analysis O((N/Cavg)2*(V+E))

27

Cross-layer Optimized Placement Total cost=a*timing cost + b*congestion cost + c*SER cost

SER cost= Phy cost * App cost

placer

bby

bbx

SER costCube-based

EPP AnalysisEPPi

NETi

bbx+bby

cbby

cbbx

cbbx+cbby

Cross-layer optimizationEPPi+EPPj

NETj


Placer



Router


SER



Logic synthesis


SER

SER

28



placer

bby

bbx

SER costCube-based

EPP AnalysisEPPi

NETi

bbx+bby

cbby

cbbx

cbbx+cbby


NETj

open0

[ ( ) ( )]*netsi N

x y ii

SER cost bb i bb i EPP


Placer



Router


SER



Logic synthesis


SER

SER

29



bby

placerbbx

SER costCube-based

EPP AnalysisEPPi

NETi

bbx+bby

cbby

cbbx

cbbx+cbby


NETj


Placer



Router


SER



Logic synthesis


SER

SER

open0

[ ( ( ]) *)netsi N

ii

x ybb i bbSER cost Pi E P

30



bby

placerbbx

SER costCube-based

EPP AnalysisEPPi

NETi

bbx+bby

cbby

cbbx

cbbx+cbby


NETj

open0

[ ( ( ]) *)netsi

x y i

N

i

bb i bbSER cost i EPP


Placer



Router


SER



Logic synthesis


SER

SER

31



placer

bby

bbx

SER costCube-based

EPP AnalysisEPPi

NETi

bbx+bby

cbby

cbbx

cbbx+cbby


NETj

open0

[ ( ) ( )]*netsi N

x y ii


short0 0,

{[ ( ) ( )]*( )}nets netsi N j N

x y i ji j j i

SER cost cbb i cbb i EPP EPP


Placer



Router


SER



Logic synthesis


SER

SER

32



cbby

placer

bby

bbx

SER costCube-based

EPP AnalysisEPPi

NETi

bbx+bby

cbbx

cbbx+cbby


NETj

open0

[ ( ) ( )]*netsi N

x y ii


short0 0,

( {[ ]*() )}( )nets netsi N j N

i ji j

x yj i

cbb i cbSER cost EPP EPi Pb


Placer



Router


SER



Logic synthesis


SER

SER

33



cbby

placer

bby

bbx

SER costCube-based

EPP AnalysisEPPi

NETi

bbx+bby

cbbx

cbbx+cbby


NETj

open0

[ ( ) ( )]*netsi N

x y ii


short0 0,

( {[ ]*() )}( )nets netsi N j N

ix y i

j j ijcbb i cbSER cost b i EPP EPP


Placer



Router


SER



Logic synthesis


SER

SER

34

Cross-layer Optimized Routing• Finer granularity estimate of SER

router

SER costCube-based

EPP Analysis

NCBk

EPPi+EPPk_net Cross-layer optimizationEPPi

CB

CBCB

CB

CLB

CLB

CLB

CLB

CLB

CLB

Bridgek

SEGjNETi

NETk_net

open0 0

( * )segsnets

j Ni N

j ji j

SER cost NCB EPP


Placer


Router


SER



Logic synthesis


SER

SER

35


router

SER costCube-based

EPP Analysis

NCBk


CB

CBCB

CB

CLB

CLB

CLB

CLB

CLB

CLB

Bridgek

SEGjNETi

NETk_net

open0 0

( * )segsnets

ji

ij

NN

jj

SER cost NCB EPP


Placer


Router


SER



Logic synthesis


SER

SER

36


router

SER costCube-based

EPP Analysis

NCBk


CB

CBCB

CB

CLB

CLB

CLB

CLB

CLB

CLB

Bridgek

SEGjNETi

NETk_net

open0 0

( * )segsnets

ji

ij j

NN

j

SER cost NCB EPP


Placer


Router


SER



Logic synthesis


SER

SER

37


router

SER costCube-based

EPP Analysis

NCBk


CB

CBCB

CB

CLB

CLB

CLB

CLB

CLB

CLB

Bridgek

SEGjNETi

NETk_net

open0 0

( * )segsnets

j Ni N

j ji j

SER cost NCB EPP

short _0 0 0

[ *( )]segs bridgenets

j N k Ni N

k i k neti j k

SER cost NCB EPP EPP


Placer


Router


SER



Logic synthesis


SER

SER

38


router

SER costCube-based

EPP Analysis

NCBk


CB

CBCB

CB

CLB

CLB

CLB

CLB

CLB

CLB

Bridgek

SEGjNETi

NETk_net

open0 0

( * )segsnets

j Ni N

j ji j

SER cost NCB EPP

short _0 0 0

[ *( )]segs bridgenets

j N k Ni N

i k neti

kj k

SER cost EP EN B P PPC


Placer


Router


SER



Logic synthesis


SER

SER

39


router

SER costCube-based

EPP Analysis

NCBk


CB

CBCB

CB

CLB

CLB

CLB

CLB

CLB

CLB

Bridgek

SEGjNETi

NETk_net

open0 0

( * )segsnets

j Ni N

j ji j

SER cost NCB EPP

short0 0 0

_ [ *( )]segs bridgenets

j N k Ni N

i j kk i k netSER co NCB EP Est P PP


Placer


Router


SER



Logic synthesis


SER

SER

40

Experimental Setup

MCNC benchmark set

Berkeley ABC mapper

Gate-level netlist

Bit Stream

VPR: Academic FPGA placement and routing tool

Logic resources: 4 6-input LUTs per CLBRouting channel width: 30% increase

41

Experimental results• Comparison of EPP accuracy and run time

• Monte Carlo simulation• DCOW: partial Monte Carlo simulation• Cube-based EPP analysis

• Comparison of SER mitigation• Original VPR• Guided by physical level factor only (PPL)• Cross-layer optimized placement and routing

algorithm (COPAR)

42

Comparison of EPP Accuracy and Run Time

• Monte Carlo simulation (golden model)

• DCOW: partial Monte Carlo simulation (DAC’10)

• Cube-based analysis (our method)

faultscube sim

0 inputs

( )N

i

N NGap

N

Ncube: number of test vectors computed by cube-based analysis

Nsim: number of test vectors computed by Monte Carlo simulation

Ninputs: total number of input vectors

43

CircuitMonte Carlo simulation Cube-based analysis Gap(10-4)†

Nsim(105) Time(s) Ncube(105) Time(s) Gcube GDCOW

alu4 20.46 3314 20.45 186 0.212 0apex2 122.85 N/A 122.69 42/itr 0.257 1052apex4 2.89 461 2.89 54 0 0clma 126.79 N/A 126.89 35/itr 0.0529 1336

misex3 31.27 98528 31.23 78 0.604 0pdc 533.11 647142 533.27 4230 0.195 0s298 36.70 1055 36.70 1 0 0

s38417 2724.22 N/A 2725.37 395/itr 0.533 344s38584.1 2385.31 N/A 2385.50 252/itr 0.095 122

seq 689.72 N/A 689.41 13/itr 0.236 516spla 698.48 569302 698.48 1440 0.00013 0

bigkey 876.46 N/A 876.46 14/itr 0 14des 868.03 N/A 868.03 12/itr 0 0

diffeq 432.85 N/A 432.85 9/itr 0 379dsip 1158.63 N/A 1158.63 24/itr 0 0

elliptic 240.35 N/A 240.35 3/itr 0 192ex1010 2.50 109325 2.50 69 0 0

ex5p 0.47 305 0.47 16 0.024 0frisc 1706.43 N/A 1706.44 107/itr 0.00585 472

tseng 1436.15 N/A 1436.24 13/itr 0.0786 247

Geomean 704.68 178679 704.74 759 0.115 234


44




misex3 31.27 98528 31.23 78 0.604 0pdc 533.11 647142 533.27 4230 0.195 0s298 36.70 1055 36.70 1 0 0

s38417 2724.22 N/A 2725.37 395/itr 0.533 344s38584.1 2385.31 N/A 2385.50 252/itr 0.095 122

seq 689.72 N/A 689.41 13/itr 0.236 516spla 698.48 569302 698.48 1440 0.00013 0




ex5p 0.47 305 0.47 16 0.024 0frisc 1706.43 N/A 1706.44 107/itr 0.00585 472

tseng 1436.15 N/A 1436.24 13/itr 0.0786 247

Geomean 704.68 178679 704.74 759 0.115 234


45




misex3 31.27 98528 31.23 78 0.604 0pdc 533.11 647142 533.27 4230 0.195 0s298 36.70 1055 36.70 1 0 0

s38417 2724.22 N/A 2725.37 395/itr 0.533 344s38584.1 2385.31 N/A 2385.50 252/itr 0.095 122

seq 689.72 N/A 689.41 13/itr 0.236 516spla 698.48 569302 698.48 1440 0.00013 0




ex5p 0.47 305 0.47 16 0.024 0frisc 1706.43 N/A 1706.44 107/itr 0.00585 472

tseng 1436.15 N/A 1436.24 13/itr 0.0786 247

Geomean 704.68 178679 704.74 759 0.115 234


46

Comparison of SER Mitigation Circuit

VPR(baseline) PPL COPAR

SER(FIT†) SER(FIT) Ratio SER(FIT) Ratio

alu4 17.05 17.08 100.17% 14.25 83.58%

apex2 18.40 18.07 98.21% 14.04 76.30%

apex4 118.40 105.98 89.52% 98.08 82.84%

clma 23.31 20.12 86.33% 19.78 84.85%

misex3 24.76 30.05 121.33% 21.56 87.05%

pdc 175.04 212.12 121.18% 141.09 80.60%

s298 2.68 1.92 71.52% 1.69 63.11%

s38417 547.02 503.30 92.01% 524.95 95.96%

s38584.1 620.70 586.47 94.49% 567.22 91.38%

seq 49.23 46.07 93.56% 38.64 78.48%

spla 269.48 247.18 91.72% 200.03 74.23%

bigkey 159.87 151.56 94.80% 130.09 81.38%

des 130.70 118.60 90.75% 123.79 94.72%

diffeq 91.08 82.81 90.92% 81.81 89.83%

dsip 208.98 168.53 80.65% 207.93 99.50%

elliptic 42.66 39.51 92.63% 39.90 93.55%

ex1010 122.41 117.97 96.37% 96.01 78.44%

ex5p 32.02 29.23 91.29% 28.76 89.84%

frisc 488.89 431.86 88.33% 455.16 93.10%

tseng 125.74 106.53 84.72% 117.58 93.51%

Geomean 163.42 151.75 93.53% 146.12 85.61%

47

Comparison of SER Mitigation

0%

20%

40%

60%

80%

100%

120%

140% VPR (baseline)PPLCOPAR

100% 93.53% 85.61%

48

Conclusions• Observe the gap between the SER evaluation

criterion and guidance criterion for soft error mitigation (gini coefficient=0.646)

• Introduce cube-based EPP analysis to compute the application level factor (gap<1%)

• Propose a cross-layer optimized placement and routing algorithm (SER mitigation>14%)

49

• Thank You for Your Attention

• Question?

Documents

Cross-layer Optimized Placement and Routing for FPGA Soft Error Mitigation Keheng Huang 1,2, Yu Hu 1, and Xiaowei Li 1 1 Key Laboratory of Computer System